74HC237D-Q100118

74HC237-Q100 3-to-8 line decoder, demultiplexer with address latches Rev. 2 — 26 October 2021 Product data sheet 1. General description The 74HC237-Q100 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237-Q100 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237-Q100 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237-Q100 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Combines 3-to-8 decoder with 3-bit latch Multiple input enable for easy expansion or independent controls Active HIGH mutually exclusive outputs Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) 3. Ordering information Table 1. Ordering information Type number Package 74HC237D-Q100 Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches 4. Functional diagram 4 LE Y0 15 Y1 14 Y2 13 1 A0 2 A1 INPUT LATCHES 3 A2 Y3 12 3 TO 8 DECODER Y4 11 Y5 10 Y6 9 Y7 7 5 E1 6 E2 001aab871 Fig. 1. Functional diagram DX 4 1 2 3 C8 0 0 0 8D,G 7 2 1 2 3 4 5 4 6 5 & 6 7 LE Y0 Y1 1 2 3 A0 A1 A2 Y2 INPUT LATCHES Y3 3 TO 8 DECODER Y4 Y5 Y6 Y7 5 6 14 4 12 1 11 2 10 3 9 C8 0 8D,1 1 8D,2 2 8D,4 3 4 7 5 6 5 & 001aab869 74HC237_Q100 Product data sheet 13 12 11 10 9 7 X/Y 13 E1 Logic symbol 14 15 6 7 15 14 13 12 11 10 9 7 EN E2 Fig. 2. 15 001aab870 Fig. 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 2 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches A0 A0 LATCH LE A1 Y0 A0 LE Y1 A1 LATCH A1 LE LE Y2 A2 A2 LATCH Y3 A2 LE LE Y4 LE Y5 Y6 Y7 E1 001aab872 E2 Fig. 4. Logic diagram 5. Pinning information 5.1. Pinning 74HC237 A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 LE 4 13 Y2 E1 5 12 Y3 E2 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 001aab868 Fig. 5. Pin configuration SOT109-1 (SO16) 74HC237_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 3 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches 5.2. Pin description Table 2. Pin description Symbol Pin Description A0 to A2 1, 2, 3 data input LE 4 latch enable input (active LOW) E1 5 data enable input 1 (active LOW) E2 6 data enable input 2 (active HIGH) Y0 to Y7 15, 14, 13, 12, 11, 10, 9, 7 output GND 8 ground (0 V) VCC 16 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Enable Input Output LE E1 E2 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H L H X X X stable X H X X X X L L L L L L L L X X L X X L L H L L X L L L L L L L L L H L L L L L L L L L H H L L L H L L L L L L L L H L H L L L H L L L L L L L H H H L L L L H L L L L L L L H L L H L L L L H L L L L H H L H L L L L L H L L L L H L H H L L L L L L H L L L H H H H L L L L L L L H 74HC237_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 4 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +7 V VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current VO = -0.5 V to (VCC + 0.5 V) - ±25 mA ICC supply current - +50 mA IGND ground current - -50 mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Min Typ Max Unit 2.0 5.0 6.0 V input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC supply voltage VI 74HC237_Q100 Product data sheet Conditions VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 5 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V LOW-level input VCC = 2.0 V voltage VCC = 4.5 V - 0.8 0.5 - 0.5 - 0.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V HIGH-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 μA CI input capacitance - 3.5 - - - - - pF 74HC237_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 6 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 9. Symbol Parameter tpd propagation delay Conditions 25 °C Typ Max Min Max Min Max VCC = 2.0 V - 52 160 - 200 - 240 ns VCC = 4.5 V - 19 32 - 40 - 48 ns VCC = 5 V; CL = 15 pF - 16 - - - - - ns VCC = 6.0 V - 15 27 - 34 - 41 ns VCC = 2.0 V - 61 190 - 240 - 285 ns VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5 V; CL = 15 pF - 19 - - - - - ns VCC = 6.0 V - 18 32 - 41 - 48 ns VCC = 2.0 V - 47 145 - 180 - 220 ns VCC = 4.5 V - 17 29 - 36 - 44 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 25 - 31 - 38 ns VCC = 2.0 V - 47 145 - 180 - 220 ns VCC = 4.5 V - 17 29 - 36 - 44 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 25 - 31 - 38 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 50 11 - 65 - 75 - ns VCC = 4.5 V 10 4 - 13 - 15 - ns VCC = 6.0 V 9 3 - 11 - 13 - ns VCC = 2.0 V 50 6 - 65 - 75 - ns VCC = 4.5 V 10 2 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns An to Yn; see Fig. 6 [1] [1] E1to Yn; see Fig. 7 [1] E2 to Yn; see Fig. 6 tW tsu transition time pulse width set-up time 74HC237_Q100 Product data sheet -40 °C to +125 °C Unit Min LE to Yn; see Fig. 6 tt -40 °C to +85 °C Yn; see Fig. 6 and Fig. 7 [1] [2] LE HIGH; see Fig. 8 An to LE; see Fig. 8 All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 7 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches Symbol Parameter Conditions 25 °C Min th hold time CPD [1] [2] [3] power dissipation capacitance Typ -40 °C to +85 °C Max Min Max An to LE; see Fig. 8 -40 °C to +125 °C Unit Min Max - VCC = 2.0 V 30 3 - 40 - 45 - ns VCC = 4.5 V 6 1 - 8 - 9 - ns VCC = 6.0 V 5 1 - 7 - 8 - ns - 60 - - - - - pF CL = 50 pF; f = 1 MHz; VI = GND to VCC [3] tpd is the same as tPLH and tPHL. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 10.1. Waveforms and test circuit An, E2, LE input VM tPHL tPLH 90 % Yn output 90 % VM 10 % 10 % tTHL tTLH 001aab873 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. Propagation delay input (An) and enable inputs (E2, LE) to output (Yn) and output transition time E1 input VM tPHL Yn output tPLH 90 % 90 % VM 10 % 10 % tTHL tTLH 001aab874 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Propagation enable inputs (E1) to output (Yn) and output transition time 74HC237_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 8 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches An input VM th tsu VM latched LE input transparant th tsu transparant latched tW 001aab875 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. The data input (An) to latch enable input (LE) set-up times, latch enable input (LE) to data input (An) hold times and latch enable input (LE) pulse width Table 8. Measurement points Input Output VM VM 0.5VCC 0.5VCC VI negative pulse VM tf tr tr VI GND VM 10 % GND positive pulse tW 90 % tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig. 9. Test circuit for measuring switching times Table 9. Test data Input Load VI tr, tf CL VCC 6.0 ns 15 pF, 50 pF 74HC237_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 Test tPLH, tPHL © Nexperia B.V. 2021. All rights reserved 9 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches 11. Application information strobe decoder enable X0 X1 X2 LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 1 2 3 4 5 6 7 input address to five other decoders X3 X4 X5 LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 1 2 3 4 5 6 7 outputs LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 8 9 10 11 12 13 14 15 LE A2 A1 A0 237 E2 E1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 16 17 18 19 20 21 22 23 outputs outputs 001aab876 Fig. 10. 6-to-64 line decoder with input address storage 74HC237_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 10 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 11. Package outline SOT109-1 (SO16) 74HC237_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 11 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC237_Q100 v.2 20211026 Product data sheet - Modifications: • • • • 74HC237_Q100 v.1 74HC237_Q100 Product data sheet 74HC237_Q100 v.1 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Section 7: Derating values for Ptot total power dissipation updated. 20130114 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 - © Nexperia B.V. 2021. All rights reserved 12 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. 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Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. 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Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 13 / 14 74HC237-Q100 Nexperia 3-to-8 line decoder, demultiplexer with address latches Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 4 6. Functional description................................................. 4 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................5 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 8 11. Application information............................................10 12. Package outline........................................................ 11 13. Abbreviations............................................................ 12 14. Revision history........................................................12 15. Legal information......................................................13 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 26 October 2021 74HC237_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 October 2021 © Nexperia B.V. 2021. All rights reserved 14 / 14