74HC3GU04GD

74HC3GU04 Inverter Rev. 04. — 11 January 2010 Product data sheet 1. General description The 74HC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates with unbuffered outputs. The 74HC3GU04 has CMOS input switching levels and supply voltage range 2 V to 6 V. 2. Features Wide supply voltage range from 2.0 V to 6.0 V Symmetrical output impedance High noise immunity Low-power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74HC3GU04DP 74HC3GU04DC 74HC3GU04GD −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name TSSOP8 VSSOP8 XSON8U Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm 4. Marking Table 2. Marking Marking code HU4 HU4 HU4 Type number 74HC3GU04DP 74HC3GU04DC 74HC3GU04GD NXP Semiconductors 74HC3GU04 Inverter 5. Functional diagram 1 1 7 1 1A 1Y 7 3 1 5 3 2A 2Y 5 1 6 3A 3Y 2 6 2 mna720 mna721 Fig 1. Logic symbol Fig 2. IEC logic symbol 6. Pinning information 6.1 Pinning 74HC3GU04 1A 1 2 3 4 8 7 6 5 VCC 1Y 3A 2Y 74HC3GU04 1A 3Y 2A GND 1 2 3 4 001aak022 3Y 8 7 6 5 VCC 1Y 3A 2Y 2A GND 001aak023 Transparent top view Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT996-2 (XSON8U) 6.2 Pin description Table 3. Symbol 1A, 2A, 3A 1Y, 2Y, 3Y GND VCC Pin description Pin 1, 3, 6 7, 5, 2 4 8 Description data input data output ground (0 V) supply voltage 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 2 of 16 NXP Semiconductors 74HC3GU04 Inverter 7. Functional description Table 4. Input nA L H [1] H = HIGH voltage level; L = LOW voltage level. Function table [1] Output nY H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current output clamping current output current quiescent supply current ground current storage temperature total power dissipation Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to (VCC + 0.5 V) [1] [1] [1] [1] [1] Min −0.5 −50 −65 - Max +7.0 ±20 ±20 ±25 50 +150 300 Unit V mA mA mA mA mA °C mW Tamb = −40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO Tamb Δt/ΔV Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions Min 2.0 0 0 −40 Typ 5.0 +25 1.67 Max 6.0 VCC VCC +125 625 139 83 Unit V V V °C ns/V ns/V ns/V 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 3 of 16 NXP Semiconductors 74HC3GU04 Inverter 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 μA; VCC = 2.0 V IO = −20 μA; VCC = 4.5 V IO = −20 μA; VCC = 6.0 V IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 μA; VCC = 2.0 V IO = 20 μA; VCC = 4.5 V IO = 20 μA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI [1] −40 °C to +85 °C Min 1.7 3.6 4.8 1.9 4.4 5.9 4.13 5.63 Typ[1] 1.1 2.4 3.1 0.9 2.1 2.9 2.0 4.5 6.0 4.32 5.81 0 0 0 0.15 0.16 3.0 Max 0.3 0.9 1.2 0.1 0.1 0.1 0.33 0.33 ±1.0 10 - −40 °C to +125 °C Min 1.7 3.6 4.8 1.9 4.4 5.9 3.7 5.2 Max 0.3 0.9 1.2 0.1 0.1 0.1 0.4 0.4 ±1.0 20 - Unit V V V V V V V V V V V V V V V V μA μA pF input leakage current supply current input capacitance VI = VCC or GND; VCC = 6.0 V per input pin; VI = VCC or GND; IO = 0 A; VCC = 6.0 V All typical values are measured at Tamb = 25 °C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 13 6 5 Max 75 15 13 −40 °C to +125 °C Unit Min Max 90 18 15 ns ns ns propagation delay nA to nY; see Figure 5 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V - 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 4 of 16 NXP Semiconductors 74HC3GU04 Inverter Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6. Symbol Parameter tt transition time Conditions nY; see Figure 5 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation VI = GND to VCC capacitance All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. tt is the same as tTLH and tTHL. CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. [4] [3] −40 °C to +85 °C Min Typ[1] 18 6 5 5 Max 95 19 16 - −40 °C to +125 °C Unit Min Max 125 25 20 ns ns ns pF [1] [2] [3] [4] 12. Waveforms VI nA input GND t PHL VOH nY output VOL t THL VM VM 10 % VM VM t PLH 90 % t TLH mna722 Measurement points are given in Table 9. Fig 5. Table 9. Type Propagation delay data input (nA) to data output (nY) and transition time output (nY) Measurement points Input VM 0.5 × VCC Output VM 0.5 × VCC 74HC3GU04 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 5 of 16 NXP Semiconductors 74HC3GU04 Inverter VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 6. Table 10. Type Test circuit for measuring switching times Test data Input VI tr, tf ≤ 6 ns GND to VCC Load CL 50 pF RL 1 kΩ S1 position tPHL, tPLH open 74HC3GU04 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 6 of 16 NXP Semiconductors 74HC3GU04 Inverter 12.1 Additional characteristics Rbias = 560 kΩ VCC 0.47 μF input output 100 μF VI (f = 1 kHz) A IO GND mna050 ΔI o g fs = -------ΔV i VO is constant. Fig 7. Test set-up for measuring forward transconductance 30 gfs (mA/V) 20 mnb124 10 0 0 2 4 6 VCC (V) 8 Tamb = 25 °C. Fig 8. Typical forward transconductance as a function of supply voltage 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 7 of 16 NXP Semiconductors 74HC3GU04 Inverter 13. Typical transfer characteristics mnb122 150 ICC (μA) 120 mnb121 2 VO (V) 1.6 10 I CC (mA) 8 5 VO (V) 4 90 1.2 6 3 60 0.8 4 2 30 0.4 2 1 0 0 0.4 0.8 1.2 1.6 VI (V) 2 0 0 0 1 2 3 4 VI (V) 5 0 VCC = 2.0 V; IO = 0 A. VCC = 4.5 V; IO = 0 A. Fig 9. Typical transfer characteristics VCC = 2.0 V Fig 10. Typical transfer characteristics VCC = 4.5 V 20 I CC (mA) 16 mnb123 6 VO (V) 12 3 8 4 0 0 2 4 VI (V) 6 0 VCC = 6.0 V; IO = 0 A. Fig 11. Typical transfer characteristics VCC = 6.0 V 14. Application information Some applications for the 74HC3GU04 are: • Linear amplifier (see Figure 12) • Crystal oscillator (see Figure 14). 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 8 of 16 NXP Semiconductors 74HC3GU04 Inverter Remark: All values given are typical values unless otherwise specified. R2 VCC 1 μF R1 U04 ZL mna052 ZL > 10 kΩ. R1 ≥ 3 kΩ. R2 ≤ 1 MΩ. Open loop amplification: AOL = 20 (typical). Voltage amplification: A V = – ---------------------------------------- . R1 1 + ------ ( 1 + AOL ) R2 Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC. Unity gain bandwidth product is 5 MHz (typical). Input capacitance see Figure 13. A OL Fig 12. Linear amplifier application 80 input capacitance (pF) 60 mna054 (1) (2) 40 (3) 20 0 0 2 4 6 VI (V) 8 (1) VCC = 2.0 V. (2) VCC = 4.5 V. (3) VCC = 6.0 V. Fig 13. Typical input capacitance as a function of the input voltage 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 9 of 16 NXP Semiconductors 74HC3GU04 Inverter R1 R2 U04 C1 C2 out mna053 Test data is given in Table 11 and Table 12. C1 = 47 pF (typical). C2 = 22 pF (typical). R1 = 1 MΩ to 10 MΩ (typical). R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC = 2 mA at VCC = 3.0 V and f = 1 MHz) Fig 14. Crystal oscillator application Table 11. Frequency 10 kHz to 15.9 kHz 16 kHz to 24.9 kHz 25 kHz to 54.9 kHz 55 kHz to 129.9 kHz 130 kHz to 199.9 kHz 200 kHz to 349.9 kHz 350 kHz to 600 kHz Table 12. Frequency 3 kHz 6 kHz 10 kHz 14 kHz > 14 kHz External components for resonator (f < 1 MHz) R1 2.2 MΩ 2.2 MΩ 2.2 MΩ 2.2 MΩ 2.2 MΩ 2.2 MΩ 2.2 MΩ R2 220 kΩ 220 kΩ 100 kΩ 100 kΩ 47 kΩ 47 kΩ 47 kΩ C1 56 pF 56 pF 56 pF 47 pF 47 pF 47 pF 47 pF C2 20 pF 10 pF 10 pF 5 pF 5 pF 5 pF 5 pF Optimum value for R2 R2 2.0 kΩ 8.0 kΩ 1.0 kΩ 4.7 kΩ 0.5 kΩ 2.0 kΩ 0.5 kΩ 2.0 kΩ Optimum minimum required ICC minimum influence due to change in VCC minimum required ICC minimum influence by VCC minimum required ICC minimum influence by VCC minimum required ICC minimum influence by VCC replace R2 by C3 = 35 pF (typical) 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 10 of 16 NXP Semiconductors 74HC3GU04 Inverter 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 15. Package outline SOT505-2 (TSSOP8) 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 11 of 16 NXP Semiconductors 74HC3GU04 Inverter VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 16. Package outline SOT765-1 (VSSOP8) 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 12 of 16 NXP Semiconductors 74HC3GU04 Inverter XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 17. Package outline SOT996-2 (XSON8U) 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 13 of 16 NXP Semiconductors 74HC3GU04 Inverter 16. Abbreviations Table 13. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 17. Revision history Table 14. Revision history Release date 20100111 Data sheet status Product data sheet Product data sheet Product specification Product specification Change notice Supersedes 74HC3GU04_3 74HC3GU04_2 74HC3GU04_1 Document ID 74HC3GU04_4 Modifications: 74HC3GU04_3 74HC3GU04_2 74HC3GU04_1 • Marking code for 74HC3GU04DP package changed from HU04 to HU4 20090511 20031126 20030818 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 14 of 16 NXP Semiconductors 74HC3GU04 Inverter 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 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Export might require a prior authorization from national authorities. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC3GU04_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 11 January 2010 15 of 16 NXP Semiconductors 74HC3GU04 Inverter 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 12.1 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional characteristics . . . . . . . . . . . . . . . . . 7 Typical transfer characteristics . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 January 2010 Document identifier: 74HC3GU04_4