74HC73D

74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 04 — 19 March 2008 Product data sheet 1. General description The 74HC73 is a high-speed Si-gate CMOS device that complies with JEDEC standard no. 7A. It is pin compatible with Low-power Schottky TTL (LSTTL). The 74HC73 is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features I Low-power dissipation I Complies with JEDEC standard no. 7A I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Multiple package options I Specified from −40 °C to +80 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74HC73N 74HC73D 74HC73DB 74HC73PW −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C DIP14 SO14 SSOP14 Description plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm Version SOT27-1 SOT108-1 SOT337-1 SOT402-1 Type number TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 4. Functional diagram 14 1J J FF1 CP Q 1Q 12 1 1CP 3 1K K R Q 1Q 13 2 1R 7 2J J FF2 CP Q 2Q 9 5 2CP 10 2K K R Q 2Q 8 6 2R 001aab981 Fig 1. Functional diagram 14 1 14 7 1J 2J J FF CP 7 3 10 1K 2K K R 1R 2R 26 Q 1Q 13 2Q 8 5 10 6 001aab979 1J 12 C1 1K R 13 Q 1Q 12 2Q 9 3 2 1 1CP 5 2CP 1J 9 C1 1K R 001aab980 8 Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 2 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger C K C C C Q J C R C C C Q CP C C 001aab982 Fig 4. Logic diagram (one flip-flop) 5. Pinning information 5.1 Pinning 74HC73 1CP 1R 1K VCC 2CP 2R 2J 1 2 3 4 5 6 7 001aab978 14 1J 13 1Q 12 1Q 11 GND 10 2K 9 8 2Q 2Q Fig 5. Pin configuration 5.2 Pin description Table 2. Symbol 1CP, 2CP 1R, 2R 1K, 2K VCC GND 1Q, 2Q 1Q, 2Q 1J, 2J Pin description Pin 1, 5 2, 6 3, 10 4 11 12, 9 13, 8 14, 7 Description clock input (HIGH-to-LOW edge-triggered); also referred to as nCP asynchronous reset input (active LOW); also referred to as nR synchronous K input; also referred to as nK positive supply voltage ground (0 V) true output; also referred to as nQ complement output; also referred to as nQ synchronous J input; also referred to as nJ 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 3 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 6. Functional description Table 3. Input nR L H H H H [1] Function table[1] Output nCP X ↓ ↓ ↓ ↓ nJ X h l h l nK X h h l l nQ L q L H q nQ H q H L q asynchronous reset toggle load 0 (reset) load 1 (set) hold (no change) Operating mode H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition; X = don’t care; ↓ = HIGH-to-LOW clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C DIP14 package SO14 package (T)SSOP14 package [1] [2] [3] [4] [2] [3] [4] Conditions VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to VCC + 0.5 V [1] [1] Min −0.5 −50 −65 - Max +7.0 ±20 ±20 ±25 50 +150 750 500 500 Unit V mA mA mA mA mA °C mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 12 mW/K above 70 °C. Ptot derates linearly with 8 mW/K above 70 °C. Ptot derates linearly with 5.5 mW/K above 60 °C. 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 4 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 8. Recommended operating conditions Table 5. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions Min 2.0 0 0 −40 Typ 5.0 1.67 Max 6.0 VCC VCC +125 625 139 83 Unit V V V °C ns ns ns 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions Min VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −4 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI input leakage current VI = VCC or GND; VCC = 6.0 V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.33 0.33 ±1.0 40.0 0.1 0.1 0.1 0.4 0.4 ±1.0 80.0 V V V V V µA µA pF 1.9 4.4 5.9 2.0 4.5 6.0 1.9 4.4 5.9 3.84 5.34 1.9 4.4 5.9 3.7 5.2 V V V V V 1.5 3.15 4.2 25 °C Typ Max 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 −40 °C to +85 °C Min 1.5 3.15 4.2 Max 0.5 1.35 1.8 −40 °C to +125 °C Unit Min 1.5 3.15 4.2 Max 0.5 1.35 1.8 V V V V V V 3.98 4.32 5.48 5.81 0.15 0.26 0.16 0.26 3.5 ±0.1 4.0 - supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V input capacitance 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 5 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8 Symbol Parameter tpd propagation delay Conditions nCP to nQ; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF nCP to nQ; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF nR to nQ, nQ; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF tt transition time nQ, nQ; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width nCP input, HIGH or LOW; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nR input, HIGH or LOW; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trec recovery time nR to nCP; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time nJ, nK to nCP; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 80 16 14 22 8 6 100 20 17 120 24 20 ns ns ns 80 16 14 22 8 6 100 20 17 120 24 20 ns ns ns 80 16 14 22 8 6 100 20 17 120 24 20 ns ns ns 80 16 14 22 8 6 100 20 17 120 24 20 ns ns ns [2] [1] 25 °C Min Typ Max 52 19 15 16 52 19 15 16 50 18 14 15 19 7 6 160 32 27 160 32 27 145 29 25 75 15 13 −40 °C to +85 °C −40 °C to +125 °C Unit Min 180 36 31 95 19 16 220 44 38 110 22 19 Max 200 40 34 200 40 34 Min Max 240 48 41 240 48 41 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 6 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8 Symbol Parameter th hold time Conditions nJ, nK to nCP; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum frequency nCP input; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance per flip-flop; VI = GND to VCC [3] 25 °C Min Typ Max 3 3 3 6.0 30 35 −8 −3 −2 23 70 83 77 30 - −40 °C to +85 °C −40 °C to +125 °C Unit Min 3 3 3 4.8 24 28 Max Min 3 3 3 4.0 20 24 Max ns ns ns MHz MHz MHz MHz pF [1] [2] [3] tpd is the same as tPHL, tPLH. tt is the same as tTHL, tTLH. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 7 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 11. Waveforms VI nJ, nK input GND VM th 1/f max VM th tsu VI nCP input GND tsu tW tPHL VOH nQ output VOL VOH nQ output VOL 10 % tTLH tPLH tPHL 001aab983 tPLH 90 % VM 10 % tTHL 10 % tTLH 90 % VM 10 % tTHL 90 % 90 % The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J and K to nCP set-up and hold times, the output transition times and the maximum clock frequency VI nCP input GND trec tW VI nR input GND VOH nQ output VOL VOH nQ output VOL 001aab984 VM VM tPHL tPLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width and the nR to nCP removal time 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 8 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger Table 8. Type 74HC73 Measurement points Input VI VCC VM 0.5VCC Output VM 0.5VCC VI negative pulse GND tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VCC G VI VO VM VI positive pulse GND VM DUT RT CL 001aah768 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 8. Table 9. Type 74HC73 Test circuit for measuring switching times Test data Input VI VCC tr, tf 6 ns Load CL 15 pF, 50 pF 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 9 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D seating plane ME A2 A L A1 c Z e b1 b 14 8 MH wM (e 1) pin 1 index E 1 7 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 9. 74HC73_4 Package outline SOT27-1 (DIP14) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 10 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT108-1 (SO14) 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 11 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE vM A Z 14 8 Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT337-1 (SSOP14) 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 12 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 12. Package outline SOT402-1 (TSSOP14) 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 13 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. 74HC73_4 Modifications: Revision history Release date 20080319 Data sheet status Product data sheet Change notice Supersedes 74HC73_3 Document ID • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Quick reference data incorporated into Section 9 and 10. Section 8 “Recommended operating conditions” tr, tf converted to ∆t/∆V. Product data sheet Product specification 74HC_HCT73_CNV_2 - 74HC73_3 74HC_HCT73_CNV_2 20041112 December 1990 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 14 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC73_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 19 March 2008 15 of 16 NXP Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 March 2008 Document identifier: 74HC73_4