HEF40175BTT

HEF40175B Quad D-type flip-flop Rev. 7 — 3 May 2011 Product data sheet 1. General description The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 on the LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to Q3 = LOW; Q0 to Q3 = HIGH), independent of CP and D0 to D3. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. The device is suitable for use over both the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range from −40 °C to +125 °C Complies with JEDEC standard JESD 13-B 3. Applications Industrial Shift registers Buffer/storage register Pattern generator 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +125 °C. Type number HEF40175BP HEF40175BT HEF40175BTT Package Name DIP16 SO16 TSSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT38-4 SOT109-1 SOT403-1 NXP Semiconductors HEF40175B Quad D-type flip-flop 5. Functional diagram 4 D0 D Q FF 1 CP Q CD 9 1 3 CP MR Q0 Q0 2 6 Q1 Q1 7 Q2 Q2 11 10 Q3 Q3 14 15 5 D1 D Q FF 2 CP Q CD 12 D2 D Q FF 3 CP Q CD 13 D3 D Q FF 4 CP Q CD 001aae569 Fig 1. Functional diagram D0 D1 D2 D3 D Q FF 1 CP Q CD CP D Q FF 2 CP Q CD D Q FF 3 CP Q CD D Q FF 4 CP Q CD MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 001aae571 Fig 2. Logic diagram HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 2 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop 6. Pinning information 6.1 Pinning HEF40175B MR Q0 Q0 D0 D1 Q1 Q1 VSS 1 2 3 4 5 6 7 8 001aae570 16 VDD 15 Q3 14 Q3 13 D3 12 D2 11 Q2 10 Q2 9 CP 1 2 3 4 5 6 7 8 001aan211 HEF40175B MR Q0 Q0 D0 D1 Q1 Q1 VSS 16 VDD 15 Q3 14 Q3 13 D3 12 D2 11 Q2 10 Q2 9 CP Fig 3. Pin configuration SOT38-4 and SOT109-1 Fig 4. Pin configuration SOT403-1 6.2 Pin description Table 2. Symbol MR Q0 to Q3 Q0 to Q3 D0 to D3 VSS CP VDD Pin description Pin 1 2, 7, 10, 15 3, 6, 11, 14 4, 5, 12, 13 8 9 16 Description master reset input (active LOW) buffered output complementary buffered output data input ground supply voltage clock input (LOW-to-HIGH edge-triggered) supply voltage 7. Functional description Table 3. Input CP ↑ ↑ ↓ X [1] Function table [1] Output Dn H L X X MR H H H L Qn H L no change L Qn L H no change H H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition. HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 3 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation Tamb = −40 °C to +125 °C DIP16 package SO16 package TSSOP16 package P [1] [2] [3] [1] [2] [3] Conditions VI < −0.5 V or VI > VDD + 0.5 V VO < −0.5 V or VO > VDD + 0.5 V Min −0.5 −0.5 −65 −40 - Max +18 ±10 VDD + 0.5 ±10 ±10 50 +150 +125 750 500 500 100 Unit V mA V mA mA mA °C °C mW mW mW mW power dissipation per output For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 °C. 9. Recommended operating conditions Table 5. Symbol VDD VI Tamb Δt/ΔV Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 −40 Typ Max 15 VDD +125 3.75 0.5 0.08 Unit V V °C μs/V μs/V μs/V HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 4 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 μA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 μA 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 μA 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 μA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current all valid input combinations; |IO| = 0 A 5V 5V 10 V 5V 10 V 15 V 15 V 5V 10 V 15 V Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 0.64 1.6 4.2 Max 1.5 3.0 4.0 0.05 0.05 0.05 −1.7 −0.64 −1.6 −4.2 ±0.1 1.0 2.0 4.0 Min 3.5 7.0 11.0 4.95 9.95 14.95 0.5 1.3 3.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 −1.4 −0.5 −1.3 −3.4 ±0.1 1.0 2.0 4.0 7.5 Min 3.5 7.0 11.0 4.95 9.95 14.95 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 −1.1 −0.36 −0.9 −2.4 ±1.0 30 60 120 Min 3.5 7.0 11.0 4.95 9.95 14.95 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 −1.1 −0.36 −0.9 −2.4 ±1.0 30 60 120 V V V V V V V V V V V V mA mA mA mA mA mA mA μA μA μA μA pF VO = 13.5 V 15 V CI input capacitance 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 6; unless otherwise specified. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions CP to Qn or Qn; see Figure 5 VDD 5V 10 V 15 V MR to Qn; see Figure 5 5V 10 V 15 V HEF40175B Extrapolation formula 53 ns + (0.55 ns/pF) CL 24 ns + (0.23 ns/pF) CL 17 ns + (0.16 ns/pF) CL 48 ns + (0.55 ns/pF) CL 19 ns + (0.23 ns/pF) CL 17 ns + (0.16 ns/pF) CL Min - Typ 80 35 25 75 30 25 Max 160 70 50 155 65 50 Unit ns ns ns ns ns ns All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 5 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 6; unless otherwise specified. Symbol Parameter tPLH LOW to HIGH propagation delay Conditions CP to Qn or Qn; see Figure 5 VDD 5V 10 V 15 V MR to Qn; see Figure 5 5V 10 V 15 V tt transition time see Figure 5 5V 10 V 15 V tsu set-up time Dn to CP; see Figure 5 5V 10 V 15 V th hold time Dn to CP; see Figure 5 5V 10 V 15 V tW pulse width; CP input LOW; minimum pulse width see Figure 5 MR input LOW; minimum pulse width see Figure 5 trec recovery time MR input; see Figure 5 5V 10 V 15 V 5V 10 V 15 V 5V 10 V 15 V fmax maximum frequency 5V 10 V 15 V [1] [1] [1] Extrapolation formula 43 ns + (0.55 ns/pF) CL 19 ns + (0.23 ns/pF) CL 17 ns + (0.16 ns/pF) CL 43 ns + (0.55 ns/pF) CL 19 ns + (0.23 ns/pF) CL 17 ns + (0.16 ns/pF) CL 10 ns + (1.00 ns/pF) CL 9 ns + (0.42 ns/pF) CL 6 ns + (0.28 ns/pF) CL Min 60 20 15 +25 10 10 90 35 25 80 30 20 0 0 0 5 15 20 Typ 70 30 25 70 30 25 60 30 20 30 10 5 −5 0 0 45 15 10 40 15 10 −30 −20 −15 11 30 45 Max 140 65 45 140 65 50 120 60 40 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formula shown (CL in pF). Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (μW) PD = 2000 × fi + Σ(fo × CL) × VDD PD = 8400 × fi + Σ(fo × CL) × VDD 2 2 2 where: fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, Σ(fo × CL) = sum of the outputs. PD = 22500 × fi + Σ(fo × CL) × VDD HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 6 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop 12. Waveforms VI MR input 0V VI CP input 0V VM VI Dn input 0V tPLH VOH Qn output VOL VM 10 % 90 % tPHL tPHL tTLH tTHL 001aak039 a. CP and MR to Qn Propagation delays and Qn transition times 1/fmax VI CP input 0V tsu VI Dn input 0V trec VI MR input 0V tW 001aae568 VM th tW VM VM b. Minimum pulse widths for CP and MR, MR to CP recovery time, and set-up and hold time for Dn to CP VOH and VOL are typical output voltage levels that occur with the output load. Set-up and hold times are shown as positive values but may be specified as negative values. The shaded area are where input changes result in predicable output performance. Measurement points are given in Table 9. Fig 5. Waveforms showing switching times HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 7 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop VI negative pulse 0V tW 90 % VM 10 % tf tr 10 % tr tf 90 % VM 10 % tW 90 % VM 10 % 001aaj781 90 % VM VI positive pulse 0V a. Input waveforms VDD VI G RT VO DUT CL 001aag182 b. Test circuit Test and measurement data is given in Table 9 Definitions test circuit: DUT = Device Under Test; RT = Termination resistance should be equal to output impedance Zo of the pulse generator; CL = Load capacitance including jig and probe capacitance. Fig 6. Table 9. VDD Test circuit for measuring switching times Measurement points and test data Input VI VSS or VDD tr, tf ≤ 20 ns Load CL 50 pF Supply voltage 5 V to 15 V HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 8 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 7. HEF40175B Package outline SOT38-4 (DIP16) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 9 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 8 A1 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ o 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. HEF40175B Package outline SOT109-1 (SO16) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 10 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 9. HEF40175B Package outline SOT403-1 (TSSOP16) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 11 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop 14. Revision history Table 10. Revision history Release date 20110503 Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet Product specification Product specification Change notice Supersedes HEF40175B v.6 HEF40175B v.5 HEF40175B v.4 HEF40175B_CNV v.3 HEF40175B_CNV v.2 Document ID HEF40175B v.7 Modifications: HEF40175B v.6 HEF40175B v.5 HEF40175B v.4 HEF40175B_CNV v.3 HEF40175B_CNV v.2 • Temperature range (maximum) increased from 85 °C to 125 °C throughout the data sheet. 20101214 20100105 20090813 19950101 19950101 HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 12 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 13 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF40175B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 3 May 2011 14 of 15 NXP Semiconductors HEF40175B Quad D-type flip-flop 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 May 2011 Document identifier: HEF40175B