HEF4052BTT,112

HEF4052B Dual 4-channel analog multiplexer/demultiplexer Rev. 8 — 17 November 2011 Product data sheet 1. General description The HEF4052B is a dual 4-channel analog multiplexer/demultiplexer with common channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logic includes two select inputs (S1 and S2) and an active LOW enable input (E). Both multiplexers/demultiplexers contain four bidirectional analog switches, each with one side connected to an independent input/output (nY0 to nY3) and the other side connected to a common input/output (nZ). With E LOW, one of the four switches is selected (low-impedance ON-state) by S1 and S2. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 and S2. If break before make is needed, then it is necessary to use the enable input. VDD and VSS are the supply voltage connections for the digital control inputs (S1 and S2, and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0 to nY3, and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD  VEE may not exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches. 2. Features and benefits      Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications  Analog multiplexing and demultiplexing  Digital multiplexing and demultiplexing  Signal gating HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4052BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4052BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4052BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 5. Functional diagram VDD 16 13 12 14 15 S1 10 11 S2 9 LOGIC LEVEL CONVERSION 1 - OF - 4 DECODER 1 5 E 1Z 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 6 2 4 3 8 7 VSS VEE 2Y2 2Y3 2Z mnb042 Fig 1. Functional diagram HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer nYn VDD VDD nZ VEE 001aak604 Fig 2. Schematic diagram (one switch) 10 9 13 6 0 1 4× 0 3 G4 1Z 1Y0 12 10 S1 1Y1 14 9 S2 1Y2 15 1Y3 11 2 2Y0 1 3 6 E 2Y1 5 2Y2 2 2Y3 4 MDX 3 0 1 Fig 3. Logic symbol HEF4052B Product data sheet 5 2 4 12 14 13 15 2Z 3 1 11 001aak605 mnb041 Fig 4. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 1Z 1Y0 S1 LEVEL CONVERTER 1Y1 S2 LEVEL CONVERTER 1Y2 E LEVEL CONVERTER 1Y3 2Y0 2Y1 2Y2 2Y3 2Z 001aak634 Fig 5. Logic diagram HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning HEF4052B 2Y0 1 16 VDD 2Y2 2 15 1Y2 2Z 3 14 1Y1 HEF4052B 2Y3 4 13 1Z 2Y1 5 12 1Y0 E VEE VSS 6 11 1Y3 7 10 S1 9 8 S2 2Y0 1 2Y2 2 16 VDD 15 1Y2 2Z 3 14 1Y1 2Y3 4 13 1Z 2Y1 5 12 1Y0 E 6 11 1Y3 VEE 7 10 S1 VSS 8 S2 001aak606 001aag215 Fig 6. 9 Pin configuration SOT38-4 and SOT109-1 Fig 7. Pin configuration SOT338-1 and SOT403-1 6.2 Pin description Table 2. Pin description Symbol Pin Description E 6 enable input (active LOW) VEE 7 supply voltage VSS 8 ground supply voltage S1, S2 10, 9 select input 1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 12, 14, 15, 11, 1, 5, 2, 4 independent input or output 1Z, 2Z 13, 3 common output or input VDD 16 supply voltage HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 7. Functional description 7.1 Function table Table 3. Function table[1] Input Channel on E S2 S1 L L L nY0 to nZ L L H nY1 to nZ L H L nY2 to nZ L H H nY3 to nZ H X X switches off [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage Conditions [1] Min Max Unit 0.5 +18 V 18 +0.5 V - 10 mA VEE supply voltage referenced to VDD IIK input clamping current pins Sn and E; VI < 0.5 V or VI > VDD + 0.5 V VI input voltage 0.5 VDD + 0.5 V II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C total power dissipation Ptot P [1] [2] power dissipation Tamb = 40 C to +125 C [2] DIP16 package - 750 mW SO16 package - 500 mW TSSOP16 package - 500 mW - 100 mW per output To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE. For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage see Figure 8 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 001aac285 15 VDD − VSS (V) 10 operating area 5 0 0 Fig 8. 5 10 VDD − VEE (V) 15 Operating area as a function of the supply voltages 10. Static characteristics Table 6. Static characteristics VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL II HIGH-level input voltage LOW-level input voltage input leakage current HEF4052B Product data sheet Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit Conditions VDD Min Max Min Max Min Max Min Max IO < 1 A 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V IO < 1 A 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 15 V - 0.1 - 0.1 - 1.0 - 1.0 A All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 6. Static characteristics …continued VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter IS(OFF) OFF-state leakage current Conditions CI Max Min Max Min Max Min Max Z port; 15 V all channels OFF; see Figure 9 - - - 1000 - - - - nA 15 V - - - 200 - - - - nA 5V - 5 - 5 - 150 - 150 A 10 V - 10 - 10 - 300 - 300 A 15 V - 20 - 20 - 600 - 600 A - - - - 7.5 - - - - pF supply current IO = 0 A input capacitance Tamb = 85 C Tamb = 125 C Unit Min Y port; per channel; see Figure 10 IDD Tamb = 40 C Tamb = 25 C VDD Sn, E inputs 10.1 Test circuits VDD S1 and S2 VDD or VSS nYn nZ E IS VSS = VEE VDD VI VO 001aak635 Fig 9. Test circuit for measuring OFF-state leakage current Z port VDD VDD or VSS S1 and S2 nY0 1 nZ nYn 2 switch IS E VSS = VEE VSS VO VI 001aak636 Fig 10. Test circuit for measuring OFF-state leakage current nYn port HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 10.2 On resistance Table 7. ON resistance Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V. Symbol Parameter Conditions VDD  VEE Typ Max Unit RON(peak) ON resistance (peak) VI = 0 V to VDD  VEE; see Figure 11 and Figure 12 5V 350 2500  10 V 80 245  15 V 60 175  5V 115 340  10 V 50 160  15 V 40 115  5V 120 365  10 V 65 200  15 V 50 155  RON(rail) ON resistance (rail) VI = 0 V; see Figure 11 and Figure 12 VI = VDD  VEE; see Figure 11 and Figure 12 RON ON resistance mismatch between channels VI = 0 V to VDD  VEE; see Figure 11 5V 25 -  10 V 10 -  15 V 5 -  10.2.1 On resistance waveform and test circuit V VSW VDD VDD or VSS S1 and S2 nYn nZ E VSS = VEE VSS ISW VI 001aak637 RON = VSW / ISW. Fig 11. Test circuit for measuring RON HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 001aae648 400 RON (Ω) VDD = 5 V 300 200 10 V 100 15 V 0 0 5 10 15 VI (V) Fig 12. Typical RON as a function of input voltage 11. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16. Symbol Parameter tPHL HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Figure 13 Conditions Sn to nYn, nZ; see Figure 14 tPLH LOW to HIGH propagation delay Yn, nZ to nZ, nYn; see Figure 13 Sn to nYn, nZ; see Figure 14 tPHZ tPZH tPLZ HIGH to OFF-state propagation delay OFF-state to HIGH propagation delay LOW to OFF-state propagation delay HEF4052B Product data sheet E to nYn, nZ; see Figure 15 E to nYn, nZ; see Figure 15 E to nYn, nZ; see Figure 15 All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 VDD Typ Max Unit 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 150 305 ns 10 V 65 135 ns 15 V 50 100 ns 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 150 300 ns 10 V 75 150 ns 15 V 50 100 ns 5V 95 190 ns 10 V 90 180 ns 15 V 85 180 ns 5V 130 260 ns 10 V 55 115 ns 15 V 45 85 ns 5V 100 205 ns 10 V 90 180 ns 15 V 90 180 ns © NXP B.V. 2011. All rights reserved. 10 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Table 8. Dynamic characteristics …continued Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16. Symbol Parameter Conditions VDD Typ Max Unit tPZL OFF-state to LOW propagation delay E to nYn, nZ; see Figure 15 5V 120 240 ns 10 V 50 100 ns 15 V 35 75 ns 11.1 Waveforms and test circuit VDD nYn or nZ input VM VDD Sn input VEE tPLH tPLH VO nZ or nYn output VM VSS tPHL tPHL VO 90 % nYn or nZ output VM 10 % VEE VEE switch OFF switch ON 001aac290 switch OFF 001aac291 Measurement points are given in Table 9. Measurement points are given in Table 9. Fig 13. nYn, nZ to nZ, nYn propagation delays Fig 14. Sn to nYn, nZ propagation delays VDD E input VM VSS tPLZ nYn or nZ output LOW-to-OFF OFF-to-LOW tPZL VO 90 % 10 % VEE tPHZ VO tPZH 90 % nYn or nZ output HIGH-to-OFF OFF-to-HIGH 10 % VEE switch ON switch OFF switch ON 001aac292 Measurement points are given in Table 9. Fig 15. Enable and disable times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer tW VI negative pulse 0V 90 % VM 10 % tf tr tr tf VI positive pulse 0V VM 10 % 90 % VM VM tW VDD VDD VI PULSE GENERATOR VI VO RL S1 open DUT RT CL VSS VEE 001aaj903 Test data is given in Table 10. Definitions: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including test jig and probe. RL = Load resistance. Fig 16. Test circuit for measuring switching times Table 10. Test data Input nYn, nZ Load Sn and E tr, tf VDD or VEE VDD or VSS  20 ns [1] S1 position VM CL RL tPHL[1] 0.5VDD 50 pF 10 k VDD or VEE VEE tPLH tPZH, tPHZ tPZL, tPLZ other VEE VDD VEE For nYn to nZ propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD. HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 11.2 Additional dynamic parameters Table 11. Additional dynamic characteristics VSS = VEE = 0 V; Tamb = 25 C. Symbol THD Parameter Conditions total harmonic distortion 3 dB frequency response f(3dB) VDD Typ Max Unit see Figure 17; RL = 10 k; CL = 15 pF; 5 V channel ON; VI = 0.5VDD (p-p); 10 V fi = 1 kHz 15 V [1] 0.25 - % [1] 0.04 - % [1] 0.04 - % see Figure 18; RL = 1 k; CL = 5 pF; channel ON; VI = 0.5VDD (p-p) 5V [1] 13 - MHz 10 V [1] 40 - MHz 70 - 50 15 V [1] iso isolation (OFF-state) see Figure 19; fi = 1 MHz; RL = 1 k; CL = 5 pF; channel OFF; VI = 0.5VDD (p-p) 10 V [1] Vct crosstalk voltage digital inputs to switch; see Figure 20; RL = 10 k; CL = 15 pF; E or Sn = VDD (square-wave) 10 V Xtalk crosstalk between switches; see Figure 21; fi = 1 MHz; RL = 1 k; VI = 0.5VDD (p-p) 10 V [1] 50 [1] MHz - dB - mV 50 - dB fi is biased at 0.5 VDD; VI = 0.5VDD (p-p). Table 12. Dynamic power dissipation PD PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (W) 5V where: PD = 1300  fi + (fo  CL)  VDD 2 fi = input frequency in MHz; 10 V PD = 6100  fi + (fo  CL)  VDD 2 fo = output frequency in MHz; 15 V PD = 15600  fi + (fo  CL)  VDD2 CL = output load capacitance in pF; VDD = supply voltage in V; (CL  fo) = sum of the outputs. 11.2.1 Test circuits VDD VDD or VSS VDD S1 and S2 VDD or VSS nYn nZ S1 and S2 E VSS = VEE VSS RL CL D RL CL dB fi 001aak638 Fig 17. Test circuit for measuring total harmonic distortion Product data sheet VSS = VEE VSS fi HEF4052B nYn nZ E 001aak639 Fig 18. Test circuit for measuring frequency response All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer VDD VDD or VSS S1 and S2 nY0 1 nZ nYn 2 switch E VSS = VEE VSS RL CL dB fi 001aak657 Fig 19. Test circuit for measuring isolation (OFF-state) 0.5VDD VDD RL S1 and S2 nY0 1 nZ nYn 2 switch E G VSS = VEE VDD or VSS RL CL V VO 001aak658 a. Test circuit logic input (Sn, E) off on off Vct VO 001aaj908 b. Input and output pulse definitions Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer VDD VDD VDD or VSS S1 and S2 nY0 nZ nYn VDD or VSS S1 and S2 nY0 nZ nYn E E VSS = VEE VSS RL VO RL VSS = VEE VSS VI RL VI VO 001aak659 a. Switch closed condition RL 001aak660 b. Switch open condition Fig 21. Test circuit for measuring crosstalk between switches HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 22. Package outline SOT38-4 (DIP16) HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 16 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 23. Package outline SOT109-1 (SO16) HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 17 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 24. Package outline SOT403-1 (TSSOP16) HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 18 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 13. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4052B v.8 20111117 Product data sheet - HEF4052B v.7 Modifications: • • Legal pages updated. Changes in “General description”, “Features and benefits” and “Applications”. HEF4052B v.7 20100326 Product data sheet - HEF4052B v.6 HEF4052B v.6 20100308 Product data sheet - HEF4052B v.5 HEF4052B v.5 20091127 Product data sheet - HEF4052B v.4 HEF4052B v.4 20090924 Product data sheet - HEF4052B_CNV v.3 HEF4052B_CNV v.3 19950101 Product specification - HEF4052B_CNV v.2 HEF4052B_CNV v.2 19950101 Product specification - - HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 19 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 20 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 17 November 2011 © NXP B.V. 2011. All rights reserved. 21 of 22 HEF4052B NXP Semiconductors Dual 4-channel analog multiplexer/demultiplexer 16. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 10.1 10.2 10.2.1 11 11.1 11.2 11.2.1 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 On resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 9 On resistance waveform and test circuit. . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms and test circuit . . . . . . . . . . . . . . . 11 Additional dynamic parameters . . . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 November 2011 Document identifier: HEF4052B