MC908QL3VDTE

MC68HC908QL4 MC68HC908QL3 MC68HC908QL2 Data Sheet M68HC08 Microcontrollers MC68HC908QL4 Rev. 6 09/2005 freescale.com MC68HC908QL4 MC68HC908QL3 MC68HC908QL2 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History (Sheet 1 of 2) Date Revision Level September, 2003 N/A November, 2003 1.0 Description Page Number(s) Initial release N/A 17.3 Functional Operating Range — Corrected operating voltage range 226 17.6 Control Timing — Corrected values for internal operating frequency and internal clock period 228 17.14 5.0-Volt ADC Characteristics — Replaced ADC characteristic table found in initial release 236 17.15 3.3-Volt ADC Characteristics — Added 237 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 3 Revision History Revision History (Sheet 2 of 2) Date March, 2004 June, 2004 December, 2004 August, 2005 September, 2005 Revision Level 2.0 3.0 4.0 5.0 6.0 Page Number(s) Description Figure 2-2. Control, Status, and Data Registers Corrected reset state for the FLASH Block Protect Register. Corrected reset value for the Internal Oscillator Time Value 33 34 Table 7-1. Instruction Set Summary — Added WAIT instruction 83 11.8.1 Oscillator Status and Control Register — Revised description of ECGON bit for clarity 117 Table 13-3. Interrupt Sources — Corrected address locations for SLIC, KBI, and ADC 140 14.3.5 SLIC Wait (Core Specific) — Revised description for clarity 144 14.3.7 SLIC Stop (Core Specific) — Revised description for clarity 144 14.6.6.2 Byte Transfer Mode Operation — Revised definition of Receiver Buffer Overrun Error 156 14.7.1 LIN Message Frame Header — Revised third paragraph of description 161 14.14 Sleep and Wakeup Operation — Revised second paragraph of description 174 15.8 Input/Output Signals — Corrected reference from PTA0/TCH) to PTB0/TCH0 196 15.8.2 TIM Channel I/O Pins (PTB0/TCH0 and PTA1/TCH1) — Corrected reference to from PTA0/TCH) to PTB0/TCH0 196 Figure 16-1. Block Diagram Highlighting BRK and MON Blocks — Added 206 17.5 5-V DC Electrical Characteristics — Updated table notes 227 17.8 5-V Oscillator Characteristics — Updated table notes 230 17.9 3.3-V DC Electrical Characteristics — Updated table notes 231 Modular sections reworked for clarity. Throughout Updated to final Freescale format. Corrections per email review. Replaced ADC chapter with latest. Throughout Table 1-3. Function Priority in Shared Pins — Updated entry for PTA2 23 Figure 1-2. MCU Pin Assignments — Corrected pin assignments for the TSSOP packages. 21 17.11 Oscillator Characteristics — Updated deviation from trimmed internal oscillator specifications. 210 17.8 3.3-V DC Electrical Characteristics — Corrected capacitance values 208 17.11 Oscillator Characteristics — Corrected Note 8 211 13.4.1 External Pin Reset — Corrected location of RSTEN bit from CONFIG1 to CONFIG2. 120 13.4.2 Active Resets from Internal Sources — Corrected location of RSTEN bit from CONFIG1 to CONFIG2. 120 Chapter 18 Ordering Information and Mechanical Specifications — Replaced case outlines with appropriate 98A drawing. 219 Figure 2-1. Memory Map — Corrected address labels. 26 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 4 Freescale Semiconductor List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 3 Analog-to-Digital Converter (ADC10) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Chapter 6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Chapter 11 Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Chapter 13 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 14 Slave LIN Interface Controller (SLIC) Module . . . . . . . . . . . . . . . . . . . . . . . . . 133 Chapter 15 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Chapter 18 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 219 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 5 List of Chapters MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 19 19 23 Chapter 2 Memory 2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 25 34 34 35 36 37 38 40 40 Chapter 3 Analog-to-Digital Converter (ADC10) Module 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.2 Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.4 Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 43 43 45 46 46 46 46 46 47 48 48 48 48 49 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 7 Table of Contents 3.3.4.5 Linearity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 ADC10 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 ADC10 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 ADC10 Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 ADC10 Voltage Reference High Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 ADC10 Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.5 ADC10 Channel Pins (ADn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 ADC10 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 ADC10 Result High Register (ADRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 ADC10 Result Low Register (ADRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 ADC10 Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 50 50 50 50 50 51 51 51 51 51 52 52 52 54 54 55 Chapter 4 Auto Wakeup Module (AWU) 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 57 58 58 59 59 59 59 59 60 60 61 61 Chapter 5 Configuration Register (CONFIG) 5.1 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Chapter 6 Computer Operating Properly (COP) 6.1 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 8 Freescale Semiconductor Table of Contents 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.4 6.5 6.6 6.6.1 6.6.2 6.7 6.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 68 68 68 68 68 68 69 69 69 69 69 69 69 69 Chapter 7 Central Processor Unit (CPU) 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 71 72 72 73 73 74 75 75 75 75 75 76 81 Chapter 8 External Interrupt (IRQ) 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 8.5.1 8.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 83 83 85 85 86 86 86 86 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 9 Table of Contents 8.6 8.7 8.7.1 8.8 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Input Pins (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 86 86 87 Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1.1 MODEK = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1.2 MODEK = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.1 KBI Input Pins (KBI5:KBI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.1 Keyboard Status and Control Register (KBSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.2 Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.3 Keyboard Interrupt Polarity Register (KBIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 89 89 89 91 92 92 92 93 93 93 93 93 93 93 94 95 95 Chapter 10 Low-Voltage Inhibit (LVI) 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.5 10.5.1 10.5.2 10.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 97 97 98 98 98 98 99 99 99 99 99 Chapter 11 Oscillator Module (OSC) 11.1 11.2 11.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 10 Freescale Semiconductor Table of Contents 11.3.1 Internal Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1.1 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1.2 XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1.3 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1.4 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1.5 Bus Clock Times 4 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1.6 Bus Clock Times 2 (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2.3 External to Internal Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 OSC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7.1 Oscillator Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7.2 Oscillator Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.1 Oscillator Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 103 103 103 103 103 103 103 104 104 104 104 105 106 106 106 106 106 107 107 107 107 108 108 109 Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Port A Input Pullup/Down Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 Port A Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.3 Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.4 Port B Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 111 112 112 113 114 114 114 115 116 116 Chapter 13 System Integration Module (SIM) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 119 119 119 119 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 11 Table of Contents 13.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2.1 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2.2 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.1 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.2 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 120 120 120 121 122 122 122 122 123 123 123 123 123 123 126 126 127 127 128 128 128 128 128 129 130 131 131 132 Chapter 14 Slave LIN Interface Controller (SLIC) Module 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.1 Power Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3 SLIC Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.4 SLIC Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.5 SLIC Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.6 Wakeup from SLIC Wait with CPU in WAIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.7 SLIC Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.8 Normal and Emulation Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.9 Special Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.10 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 133 135 136 136 136 136 137 137 137 137 137 138 138 138 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 12 Freescale Semiconductor Table of Contents 14.6 SLIC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.1 SLCTX — SLIC Transmit Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.2 SLCRX — SLIC Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.1 SLIC Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.2 SLIC Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.3 SLIC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.4 SLIC Prescaler Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.5 SLIC Bit Time Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.6 SLIC State Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.6.1 LIN Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.6.2 Byte Transfer Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.7 SLIC Data Length Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.8 SLIC Identifier and Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9 Initialization/Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.1 LIN Message Frame Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.2 LIN Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.3 LIN Checksum Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.4 SLIC Module Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.5 SLCSV Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.6 SLIC Module Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.6.1 LIN Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.6.2 Byte Transfer Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.7 Handling LIN Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.7.1 LIN Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.7.2 Possible Errors on Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.8 Handling Command Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.8.1 Standard Command Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.8.2 Extended Command Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.8.3 Possible Errors on Command Message Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.9 Handling Request LIN Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.9.1 Standard Request Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.9.2 Extended Request Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.9.3 Transmit Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.9.4 Possible Errors on Request Message Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.10 Handling IMSG to Minimize Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.11 Sleep and Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.12 Polling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.13 LIN Data Integrity Checking Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.14 High-Speed LIN Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.15 Byte Transfer Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.16 Oscillator Trimming with SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.17 Digital Receive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.17.1 Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9.17.2 Digital Filter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 139 139 139 139 139 140 141 142 143 144 144 147 148 149 150 150 150 151 151 151 151 151 152 153 154 155 155 155 157 158 158 158 160 161 161 161 161 162 162 163 165 169 170 170 171 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 13 Table of Contents Chapter 15 Timer Interface Module (TIM) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.1 TIM Channel I/O Pins (TCH1:TCH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.2 TIM Clock Pin (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 173 173 173 174 174 175 176 176 177 177 178 179 179 179 179 179 179 180 180 180 180 181 182 183 185 Chapter 16 Development Support 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.4 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 187 187 189 189 189 190 190 190 191 191 191 192 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 14 Freescale Semiconductor Table of Contents 16.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 192 196 197 197 198 198 198 198 202 Chapter 17 Electrical Specifications 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 17.11 17.12 17.13 17.14 17.15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 3.3-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 203 204 204 205 206 207 208 209 210 210 213 215 217 218 Chapter 18 Ordering Information and Mechanical Specifications 18.1 18.2 18.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 15 Table of Contents MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 16 Freescale Semiconductor Chapter 1 General Description 1.1 Introduction The MC68HC908QL4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0.4 Table 1-1. Summary of Device Variations Device FLASH Memory Size RAM Memory Size Analog-to-Digital Converter MC68HC908QL4 4096 bytes 128 bytes 6 ch, 10 bit MC68HC908QL3 4096 bytes 128 bytes — MC68HC908QL2 2048 bytes 128 bytes 6 ch, 10 bit 1.2 Features Features include: • High-performance M68HC08 CPU core • Fully upward-compatible object code with M68HC05 Family • 5-V and 3.3-V operating voltages (VDD) • 8-MHz internal bus operation at 5 V, 4-MHz at 3.3 V • Software configurable input clock from either internal or external source • Trimmable internal oscillator – Selectable 1 MHz, 2 MHz, or 3.2MHz or 6.4 MHz internal bus operation – 8-bit trim capability – Trimmable to approximately 0.4%(1) – ± 25% untrimmed • Software selectable crystal oscillator range, 32–100 kHz, 1–8 MHz, and 8–32 MHz • Auto wakeup from STOP capability using dedicated internal 32-kHz RC or bus clock source • On-chip in-application programmable FLASH memory – Internal program/erase voltage generation – Monitor ROM containing user callable program/erase routines – FLASH security(2) 1. See 17.11 Oscillator Characteristics for internal oscillator specifications 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 17 General Description • On-chip random-access memory (RAM) • Slave LIN interface controller (SLIC) module – Full LIN messaging buffering of Identifier and 8 data bytes – Automatic baud rate and LIN message frame synchronization: No prior programming of bit rate required, 1–20 kbps LIN bus speed operation All LIN messages will be received (no message loss due to synchronization process) Input clock tolerance as high as ±50%, allowing internal oscillator to remain untrimmed Incoming break symbols allowed to be 10 to 20 bit times without message loss Supports automatic software trimming of internal oscillator using LIN synchronization data – Automatic processing and verification of LIN SYNCH BREAK and SYNCH BYTE – Automatic checksum calculation and verification with error reporting – Maximum of 2 interrupts per LIN message frame – Full LIN error checking and reporting – High-speed LIN capability up to 83.33 kbps to 120.00 kbps – Switchable UART-like byte transfer mode for processing bytes one at a time without LIN message framing constraints – Configurable digital receive filter • 2-channel, 16-bit timer interface module (TIM) with external clock source input • 6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10) • 6-bit keyboard interrupt with wakeup feature (KBI) – Programmable for rising/falling or high/low level detect – Software selectable to use internal or external pullup/pulldown device • External asynchronous interrupt pin with internal pullup (IRQ) • Master asynchronous reset pin with internal pullup (RST) • 13 bidirectional input/output (I/O) lines and one input only: – Six shared with keyboard interrupt function – Six shared with ADC10 – Two shared with TIM – Two shared with SLIC – One shared with reset – One input only shared with external interrupt (IRQ) – High current sink/source capability – Selectable pullups on all ports (pullup/down on port A), selectable on an individual bit basis – Three-state ability on all port pins • Low-voltage inhibit (LVI) module features: – Software selectable trip point in CONFIG register • System protection features: – Computer operating properly (COP) watchdog – Low-voltage detection with reset – Illegal opcode detection with reset – Illegal address detection with reset MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 18 Freescale Semiconductor MCU Block Diagram • Power-on reset • Memory mapped I/O registers • Power saving stop and wait modes • Available packages: – 16-pin small outline integrated circuit (SOIC) package – 16-pin thin shrink small outline package (TSSOP) Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QL4. 1.4 Pin Functions Table 1-2 provides a description of the pin functions. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 19 General Description PTA0/AD0/KBI0 INTERNAL OSC PTA3/RST/KBI3 INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/AD1/TCH1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE M68HC08 CPU PTB0/TCH0 PTB1 AUTO WAKEUP MODULE PTB4/SLCRX DDRB PTB3/AD5 PTB PTB2/AD4 LOW-VOLTAGE INHIBIT PTB5/SLCTX PTB6 2-CHANNEL 16-BIT TIMER MODULE PTB7 MC68HC908QL4 128 BYTES USER RAM COP MODULE MC68HC908QL4 4096 BYTES USER FLASH 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER VDD POWER SUPPLY DEVELOPMENT SUPPORT VSS MONITOR ROM BREAK MODULE RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device (pullup/down on port A) PTA[0:5]: Higher current sink and source capability Figure 1-1. Block Diagram MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 20 Freescale Semiconductor Pin Functions VDD 1 16 VSS PTA1/TCH1/KBI1 2 15 PTA0/KBI0 PTA2/IRQ/KBI2/TCLK 3 14 PTA5/OSC1/KBI5 PTA3/RST/KBI3 4 13 PTA4/OSC2/KBI4 PTB0/TCH0 5 12 PTB4/SLCRx PTB3 6 11 PTB5/SLCTx PTB2 7 10 PTB6 PTB1 8 9 PTB7 PTA4/OSC2/KBI4 PTA5/OSC1/KBI5 PTA0/KBI0 VSS VDD PTA1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTB4/SLCRx PTB5/SLCTx PTB6 PTB7 PTB1 PTB2 PTB3 PTB0/TCH0 16-PIN ASSIGNMENT MC68HC908QL3 TSSOP 16-PIN ASSIGNMENT MC68HC908QL3 SOIC VDD 1 16 VSS PTA1/AD1/TCH1/KBI1 2 15 PTA0/AD0/KBI0 PTA2/IRQ/KBI2/TCLK 3 14 PTA5/OSC1/AD3/KBI5 PTA3/RST/KBI3 4 13 PTA4/OSC2/AD2/KBI4 PTB0/TCH0 5 12 PTB4/SLCRx PTB3/AD5 6 11 PTB5/SLCTx PTB2/AD4 7 10 PTB6 PTB1 8 9 PTB7 16-PIN ASSIGNMENT MC68HC908QL4 AND MC68HC908QL2 SOIC PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTA0/AD0/KBI0 VSS VDD PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTB4/SLCRx PTB5/SLCTx PTB6 PTB7 PTB1 PTB2/AD4 PTB3/AD5 PTB0/TCH0 16-PIN ASSIGNMENT MC68HC908QL4 AND MC68HC908QL2 TSSOP Figure 1-2. MCU Pin Assignments MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 21 General Description Table 1-2. Pin Functions Pin Name Description Input/Output VDD Power supply Power VSS Power supply ground Power PTA0 — General purpose I/O port PTA0 PTA1 PTA2 Input/Output AD0 — A/D channel 0 input Input KBI0 — Keyboard interrupt input 0 Input PTA1 — General purpose I/O port Input/Output AD1 — A/D channel 1 input Input TCH1 — Timer Channel 1 I/O Input/Output KBI1— Keyboard interrupt input 1 Input PTA2 — General purpose input-only port Input IRQ — External interrupt with programmable pullup and Schmitt trigger input Input KBI2 — Keyboard interrupt input 2 Input TCLK — External clock source input for the TIM module Input PTA3 — General purpose I/O port PTA3 PTA4 PTA5 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6, PTB7 Input/Output RST — Reset input, active low with internal pullup and Schmitt trigger input Input KBI3 — Keyboard interrupt input 3 Input PTA4 — General purpose I/O port Input/Output OSC2 — XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSC2EN = 1 in PTAPUE register) Output Output AD2 — A/D channel 2 input Input KBI4 — Keyboard interrupt input 4 Input PTA5 — General purpose I/O port Input/Output OSC1 — XTAL, RC, or external oscillator input Input AD3 — A/D channel 3 input Input KBI5 — Keyboard interrupt input 5 Input PTB0 — General purpose I/O port Input/Output TCH0 — Timer Channel 0 I/O Input/Output PTB1 — General purpose I/O port Input/Output PTB2 — General purpose I/O port Input/Output AD4 — A/D channel 4 input Input PTB3 — General purpose I/O port Input/Output AD5 — A/D channel 5 input Input PTB4 — General purpose I/O port Input/Output SLCRx — SLC receive input Input PTB5 — General purpose I/O port Input/Output SLCTx — SLC transmit output Output General-purpose I/O port Input/Output MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 22 Freescale Semiconductor Pin Function Priority 1.5 Pin Function Priority Table 1-3 defines the priority of a shared pin if multiple functions are enabled. Only the shared pins are shown in the table. Table 1-3. Function Priority in Shared Pins Pin Name Highest-to-Lowest Priority Sequence (1) AD0 → TCH1 → KBI0 → PTA0 (1) AD1 → KBI1 → PTA1 PTA0 PTA1 PTA2 TCLK → IRQ → KBI2 → PTA2(2) PTA3 RST → KBI3 → PTA3 (1) PTA4 OSC2 → AD2 → KBI4 → PTA4 PTA5(1) OSC1 → AD3 → KBI5 → PTA5 PTB0 TCH0 → PTB0 PTB1 PTB1 (1) PTB2 AD4 → PTB2 PTB3(1) AD5 → PTB3 PTB4 SLCRx → PTB4 PTB5 SLCTx → PTB5 1. When a pin is to be used as an ADC pin, the I/O port function should be left as an input. The ADC does not override the port data direction register. 2. TCLK is not included in the priority scheme. When TCLK is enabled the other shared functions in the pin should be disabled. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 23 General Description MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 24 Freescale Semiconductor Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map is shown in Figure 2-1. 2.2 Unimplemented Memory Locations Executing code from an unimplemented location will cause an illegal address reset. In Figure 2-1, unimplemented locations are shaded. 2.3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1, reserved locations are marked with the word reserved or with the letter R. 2.4 Direct Page Registers Figure 2-2 shows the memory mapped registers of the MC68HC908QL4. Registers with addresses between $0000 and $00FF are considered direct page registers and all instructions including those with direct page addressing modes can access them. Registers between $0100 and $FFFF require non-direct page addressing modes. See Chapter 7 Central Processor Unit (CPU) for more information on addressing modes. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 25 Memory $0000 ↓ $0051 DIRECT PAGE REGISTERS 81 BYTES $0052 ↓ $007F UNIMPLEMENTED 47 BYTES $0080 ↓ $00FF RAM 128 BYTES $0100 ↓ $2B7D UNIMPLEMENTED 10,878 BYTES $2B7E ↓ $2E1F AUXILIARY ROM 674 BYTES $2E20 ↓ $EDFF UNIMPLEMENTED 49120 BYTES $EE00 ↓ RESERVED 2048 BYTES $EE00 ↓ $F5FF FLASH MEMORY 2048 BYTES $F600 ↓ $FDFF FLASH MEMORY 4096 BYTES $FDFF $FE00 ↓ $FE0F MISCELLANEOUS REGISTERS 16 BYTES $FE10 ↓ $FE1F UNIMPLEMENTED 16 BYTES $FE20 ↓ $FF7D MONITOR ROM 350 BYTES $FF7E ↓ $FFBD UNIMPLEMENTED 64 BYTES $FFBE ↓ $FFC1 MISCELLANEOUS REGISTERS 4 BYTES $FFC2 ↓ $FFCF UNIMPLEMENTED 14 BYTES $FFD0 ↓ $FFFF USER VECTORS 48 BYTES MC68HC908QL4, MC68HC908QL3 Memory Map MC68HC908QL2 Memory Map Figure 2-1. Memory Map MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 26 Freescale Semiconductor Direct Page Registers Addr. $0000 $0001 $0002 ↓ $0003 $0004 $0005 $0006 ↓ $000A $000B $000C $000D ↓ $0019 $001A $001B Register Name Read: Port A Data Register (PTA) Write: See page 112. Reset: Read: Port B Data Register (PTB) Write: See page 114. Reset: Bit 7 6 5 4 3 0 AWUL PTA5 PTA4 PTA3 U 0 U U U PTB7 PTB6 PTB5 PTB4 PTB3 2 1 Bit 0 PTA1 PTA0 U U U PTB2 PTB1 PTB0 DDRA1 DDRA0 PTA2 Unaffected by reset Reserved Read: Data Direction Register A (DDRA) Write: See page 112. Reset: Read: Data Direction Register B (DDRB) Write: See page 115. Reset: 0 0 0 0 DDRA5 DDRA4 DDRA3 0 0 0 0 0 0 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 0 0 0 0 0 0 0 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0 0 0 0 0 0 0 0 0 0 0 KEYF 0 IMASKK MODEK Reserved Read: Port A Input Pullup/Down OSC2EN Enable Register (PTAPUE) Write: See page 113. Reset: 0 Read: Port B Input Pullup Enable PTBPUE7 Register (PTBPUE) Write: See page 116. Reset: 0 0 Reserved Read: Keyboard Status and Control Register (KBSCR) Write: See page 94. Reset: 0 Read: Keyboard Interrupt Enable Register (KBIER) Write: See page 95. Reset: 0 ACKK 0 0 0 0 0 0 0 0 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 R = Reserved = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 27 Memory Addr. $001C $001D $001E Register Name Bit 7 6 Read: Keyboard Interrupt Polarity Register (KBIPR) Write: See page 95. Reset: 0 0 0 Read: IRQ Status and Control Register (INTSCR) Write: See page 87. Reset: 0 Read: Configuration Register 2 (1) (CONFIG2) Write: See page 63. Reset: 5 4 3 2 1 Bit 0 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 0 0 0 0 0 0 0 0 0 0 IRQF 0 IMASK MODE ACK 0 0 0 0 0 0 0 0 IRQPUD IRQEN R R R R OSCENINSTOP RSTEN 0 0 0 0 0 0 0 0(2) 1. One-time writable register after each reset. 2. RSTEN reset to 0 by a power-on reset (POR) only. $001F Read: Configuration Register 1 (1) (CONFIG1) Write: See page 64. Reset: COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD 0 0 0 0 0(2) 0 0 0 PS2 PS1 PS0 1. One-time writable register after each reset. 2. LVITRIP reset to 0 by a power-on reset (POR) only. $0020 $0021 $0022 $0023 $0024 $0025 Read: TIM Status and Control Register (TSC) Write: See page 180. Reset: TOF 0 0 TOIE TSTOP 0 0 1 0 0 0 0 0 Read: TIM Counter Register High (TCNTH) Write: See page 182. Reset: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Read: TIM Counter Register Low (TCNTL) Write: See page 182. Reset: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 R = Reserved Read: TIM Counter Modulo Register High (TMODH) Write: See page 182. Reset: Read: TIM Counter Modulo Register Low (TMODL) Write: See page 182. Reset: Read: TIM Channel 0 Status and Control Register (TSC0) Write: See page 183. Reset: 0 CH0F 0 0 = Unimplemented TRST U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 28 Freescale Semiconductor Direct Page Registers Addr. Register Name $0026 Read: TIM Channel 0 Register High (TCH0H) Write: See page 185. Reset: $0027 $0028 $0029 $002A $002B ↓ $0035 $0036 $0037 $0038 $0039 ↓ $003B $003C $003D Read: TIM Channel 0 Register Low (TCH0L) Write: See page 185. Reset: Read: TIM Channel 1 Status and Control Register (TSC1) Write: See page 183. Reset: Read: TIM Channel 1 Register High (TCH1H) Write: See page 185. Reset: Read: TIM Channel 1 Register Low (TCH1L) Write: See page 185. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset CH1F 0 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset Reserved Read: Oscillator Status and Control OSCOPT1 OSCOPT0 Register (OSCSC) Write: See page 108. Reset: 0 0 ECGST ICFS1 ICFS0 ECFS1 ECFS0 ECGON 1 0 0 0 0 0 Reserved Oscillator Trim Register Read: (OSCTRIM) Write: See page 109. Reset: TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 1 0 0 0 0 0 0 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Reserved Read: ADC10 Status and Control Register (ADSCR) Write: See page 52. Reset: COCO 0 0 0 1 1 1 1 1 Read: ADC10 Data Register High (ADRH) Write: See page 54. Reset: 0 0 0 0 0 0 AD9 AD8 R R R R R R R R 0 0 0 0 0 0 0 0 R = Reserved = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 29 Memory Addr. $003E $003F $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 Register Name Bit 7 6 5 4 3 2 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R R R R R R R R 0 0 0 0 0 0 0 0 ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ADACKEN 0 0 0 0 0 0 0 0 Read: SLIC Control Register 1 (SLCC1) Write: See page 139. Reset: 0 0 WAKETX TXABRT IMSG SLCIE 0 0 1 0 0 0 0 0 Read: SLIC Control Register 2 (SLCC2) Write: See page 140. Reset: 0 0 0 0 SLCWCM BTM 0 0 0 0 0 0 0 SLCACT 0 INITACK 0 0 0 0 0 0 1 0 0 0 0 0 RXFP1 RXFP0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 BT12 BT11 BT10 BT9 BT8 0 0 0 0 0 0 0 0 BT7 BT6 BT5 BT4 BT3 BT2 BT1 0 0 0 0 0 0 0 0 0 0 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 TXGO CHKMOD DLC5 DLC4 DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 0 0 0 Read: SLIC Identifier Register (SLCID) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Read: SLIC Data Register 7 (SLCD7) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 R = Reserved Read: ADC10 Data Register Low (ADRL) Write: See page 54. Reset: Read: ADC10 Clock Register (ADCLK) Write: See page 55. Reset: Read: SLIC Status Register (SLCS) Write: See page 141. Reset: Read: SLIC Prescale Register (SLCP) Write: See page 142. Reset: Read: SLIC Bit Time Register High (SLCBTH) Write: See page 143. Reset: Read: SLIC Bit Time Register Low (SLCBTL) Write: See page 143. Reset: Read: SLIC State Vector Register (SLCSV) Write: See page 144. Reset: Read: SLIC Data Length Code Register (SLCDLC) Write: See page 148. Reset: INITREQ = Unimplemented 0 0 SLCE 0 SLCF 0 U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 30 Freescale Semiconductor Direct Page Registers Addr. $004A $004B $004C $004D $004E $004F $0050 $0051 ↓ $005F $FE00 Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: SLIC Data Register 6 (SLCD6) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Read: SLIC Data Register 5 (SLCD5) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Read: SLIC Data Register 4 (SLCD4) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Read: SLIC Data Register 3 (SLCD3) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Read: SLIC Data Register 2 (SLCD2) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Read: SLIC Data Register 1 (SLCD1) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Read: SLIC Data Register 0 (SLCD0) Write: See page 149. Reset: R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 R R R R R R Reserved Read: Break Status Register (BSR) Write: See page 191. Reset: SBSW See note 1 R 0 1. Writing a 0 clears SBSW. $FE01 $FE02 Read: SIM Reset Status Register (SRSR) Write: See page 131. POR: Read: Break Auxiliary Register (BRKAR) Write: See page 191. Reset: POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R = Reserved = Unimplemented BDCOP 0 U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 31 Memory Addr. $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D ↓ $FE0F $FFBE Register Name Read: Break Flag Control Register (BFCR) Write: See page 191. Reset: Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 Read: Interrupt Status Register 1 (INT1) Write: See page 127. Reset: IF6 IF5 IF4 IF3 IF2 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Read: Interrupt Status Register 2 (INT2) Write: See page 127. Reset: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 R R R R R R R R 0 0 0 0 0 0 0 0 Read: Interrupt Status Register 3 (INT3) Write: See page 128. Reset: IF22 IF21 IF20 IF19 IF18 IF17 IF16 IF15 R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 HVEN MASS ERASE PGM 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVIOUT 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 Reserved Read: FLASH Control Register (FLCR) Write: See page 35. Reset: Read: Break Address High Register (BRKH) Write: See page 190. Reset: Read: Break Address Low Register (BRKL) Write: See page 190. Reset: Read: Break Status and Control Register (BRKSCR) Write: See page 191. Reset: Read: LVI Status Register (LVISR) Write: See page 99. Reset: Reserved Read: FLASH Block Protect Register (FLBPR) Write: See page 40. Reset: 0 Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 32 Freescale Semiconductor Direct Page Registers Addr. $FFBF $FFC0 $FFC1 $FFFF Register Name Bit 7 6 5 4 3 2 1 Bit 0 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 Reserved Read: Internal Oscillator Trim Write: Value (Optional) Reset: Resets to factory programmed value Reserved Read: COP Control Register (COPCTL) Write: See page 69. Reset: LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7) Table 2-1. Vector Addresses Vector Priority Vector Address Lowest IF22–IF16 $FFD0,1–$FFDC,D IF15 $FFDE,F ADC conversion complete vector IF14 $FFE0,1 Keyboard vector IF13 $FFE2,3 Unused vector IF12 $FFE4,5 Unused vector IF11 $FFE6,7 Unused vector IF10 $FFE8,9 Unused vector IF9 $FFEA,B SLIC vector IF8 $FFFC,D Unused vector IF7 $FFEE,F Unused vector IF6 $FFF0,1 Unused vector IF5 $FFF2,3 TIM overflow vector IF4 $FFF4,5 TIM channel 1 vector IF3 $FFF6,7 TIM channel 0 vector IF2 $FFF8,9 Unused vector IF1 $FFFA,B IRQ vector — $FFFC,D SWI vector — $FFFE,F Reset vector Highest Vector Unused vectors MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 33 Memory 2.5 Random-Access Memory (RAM) This MCU includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait or stop mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HC08 resets the stack pointer to $00FF. In the devices that have RAM above $00FF, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM). LDHX TXS #RamLast+1 ;point one past RAM ;SP 40000 bps) LIN message, the master node must allow a minimum idle time of eight bit times (of the slowest bit rate) between the messages. This prevents a valid message at another frequency from being detected as an invalid message. Table 14-6. Maximum LIN Bit Rates for High-Speed Operation Due to Digital Receive Filter SLIC Clock (MHz) Maximum LIN Bit Rate for ±1.5% SLIC Accuracy (for Master-Slave Communication (Bits / Second) DIGITAL RX FILTER NOT CONSIDERED Maximum LIN Bit Rate with Digital RX Filter Set to ÷4 (Bits / Second) Maximum LIN Bit Rate with Digital RX Filter Set to ÷3 (Bits / Second) THESE PRESCALERS NOT RECOMMENDED FOR HIGH-SPEED LIN OPERATION Maximum LIN Bit Rate with Digital RX Filter Set to ÷2 (Bits / Second) Maximum LIN Bit Rate with Digital RX Filter Set to ÷1 (Bits / Second) 8 120,000 120,000(1) 120,000(1) 120,000(1) 120,000(1) 6.4 96,000 100,000 120,000(1) 120,000(1) 120,000(1) 4.8 72,000 75,000 100,000 120,000(1) 120,000(1) 4 60,000 62,500 83,333 120,000(1) 120,000(1) 3.2 48,000 50,000 66,667 100,000 120,000(1) 2.4 36,000 37,500 50,000 75,000 120,000(1) 2 30,000 31,250 41,667 62,500 120,000(1) 1. Bit rates over 120,000 bits per second are not recommended for LIN communications, as physical layer delay between the TX and RX pins can cause the stop bit of a byte to be mis-sampled as the last data bit. This could result in a byte framing error. Table 14-7. Digital Receive Filter Absolute Cutoff (Ideal Conditions) SLIC Clock (MHz) Digital RX Filter Set to ÷4 Digital RX Filter Set to ÷3 Digital RX Filter Set to ÷2 Digital RX Filter Set to ÷1 Max. Bit Rate (Bits / Sec) Min Pulse Width Allowed (µs) Max. Bit Rate (Bits / Sec) Min Pulse Width Allowed (µs) Max. Bit Rate (Bits / Sec) Min Pulse Width Allowed (µs) Max. Bit Rate (Bits / Sec) Min Pulse Width Allowed (µs) 8 125,000 8.0 166,667 6.0 250,000 4.0 500,000 2.0 6.4 100,000 10.0 133,333 7.5 200,000 5.0 400,000 2.5 4.8 75,000 13.3 100,000 10.0 150,000 6.7 300,000 3.3 4 62,500 16.0 83,333 12.0 125,000 8.0 250,000 4.0 3.2 50,000 20.0 66,667 15.0 100,000 10.0 200,000 5.0 2.4 37,500 26.7 50,000 20.0 75,000 13.3 150,000 6.7 2 31,250 32.0 41,667 24.0 62,500 16.0 125,000 8.0 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 164 Freescale Semiconductor Initialization/Application Information 14.9.15 Byte Transfer Mode Operation This subsection describes the operation and limitations of the optional UART-like byte transfer mode (BTM). This mode allows sending and receiving individual bytes, but changes the behavior of the SLCBT registers (now read/write registers) and locks the SLCDLC to 1 byte data length. The SLCBT value now becomes the bit time reference for the SLIC, where the software sets the length of one bit time rather than the SLIC module itself. This is similar to an input capture/output compare (IC/OC) count in a timer module, where the count value represents the number of SLIC clock counts in one bit time. Byte transfer mode assumes that the user has a very stable, precise oscillator, resonator, or clock reference input into the MCU and is therefore not appropriate for use with internal oscillators. There is no synchronization method available to the user in this mode and the user must tell the SLIC how many clock counts comprise a bit time. Figure 14-18, Figure 14-19, Figure 14-20, and Figure 14-21 show calculations to determine the SLCBT value for different settings. NOTE It is possible to use the LIN autobauding circuitry in a non-LIN system to derive the correct bit timing values if system constraints allow. To do this the SLIC module must be activated in LIN mode (BTM=0) and receive a break symbol, 0x55 data byte and one additional data byte (at the desired BTM speed). Upon receiving this sequence of symbols which appears to be a LIN header, the SLIC module will assert an ID received successfully interrupt (SLCSV=0x2C). The value in the SLCBT registers will reflect the bit rate which the 0x55 data character was received and can be saved to RAM. The user then switches the SLIC into BTM mode and reloads this value from RAM and the SLIC will be configured to communicate in BTM mode at the baud rate which the 0x55 data character was sent. In the example in Figure 14-18, the user should write 0x16, as a write of 0x15 (decimal value of 21) would automatically revert to 0x14, resulting in transmitted bit times that are 1.33 SLIC clock periods too short rather than 0.667 SLIC clock periods too long. The optimal choice, which gives the smallest resolution error, is the closest even number of SLIC clocks to the exact calculated SLCBT value. There is a trade-off between maximum bit rate and resolution with the SLIC in BTM mode. Faster SLIC clock speeds improve resolution, but require higher numbers to be written to the SLCBT registers for a given desired bit rate. It is up to the user to determine what level of resolution is acceptable for the given application. Desired Bit Rate: External Crystal Frequency: 57,600 bps 4.9152 MHz 1 Second 57,600 Bits 1 Second 4,915,200 CGMXCLK Periods 17.36111 ms 1 Bit X X 4 CGMXCLK Period = = 813.802 ns 813.802 ns 1 SLIC Clock Period 1 SLIC Clock Period 1 SLIC Clock Period 17.36111 ms 1 Bit = 21.33 SLIC Clock Periods 1 Bit Therefore, the closest SLCBT value would be 21 SLIC clocks (SLCBT = 0x0015). Because you can only use even values in SLCBT, the closest acceptable value is 22 (0x0016). Figure 14-18. SLCBT Value Calculation Example 1 MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 165 Slave LIN Interface Controller (SLIC) Module Desired Bit Rate: External Crystal Frequency: 57,600 bps 9.8304 MHz 1 Second 57,600 Bits 1 Second 9,830,400 CGMXCLK Periods 17.36111 ms 1 Bit X X = 4 CGMXCLK Period = 1 SLIC Clock Period 17.36111 ms 1 Bit 406.90 ns 1 SLIC Clock Period 1 SLIC Clock Period = 406.90 ns 42.67 SLIC Clock Periods 1 Bit Therefore, the closest SLCBT value would be 42 SLIC clocks (SLCBT = 0x002A). Figure 14-19. SLCBT Value Calculation Example 2 Desired Bit Rate: External Crystal Frequency: 15,625 bps 8.000 MHz 1 Second 15,625 Bits 1 Second 8,000,000 CGMXCLK Periods 64 ms 1 Bit X X = 4 CGMXCLK Period = 64 ms 1 Bit 500 ns 1 SLIC Clock Period 1 SLIC Clock Period 1 SLIC Clock Period = 500 ns 128 SLIC Clock Periods 1 Bit Therefore, the closest SLCBT value would be 128 SLIC clocks (SLCBT = 0x0080). Figure 14-20. SLCBT Value Calculation Example 3 Desired Bit Rate: External Crystal Frequency: 9.615 bps 8.000 MHz 1 Second 9,615 Bits 1 Second 8,000,000 CGMXCLK Periods 104.004 ms 1 Bit X X 4 CGMXCLK Period = = 500 ns 500 ns 1 SLIC Clock Period 1 SLIC Clock Period 1 SLIC Clock Period 104.004 ms 1 Bit = 208.008 SLIC Clock Periods 1 Bit Therefore, the closest SLCBT value would be 42 SLIC clocks (SLCBT = 0x00D0). Figure 14-21. SLCBT Value Calculation Example 4 This resolution affects the sampling accuracy of the SLIC module on receiving bytes, but only as far as locating the sample point of each bit within a given byte. The best sample point of the bit may be off by as much as one SLIC clock period from the exact center of the bit, if the proper SLCBT value for the desired bit rate is an odd number of SLIC clock periods. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 166 Freescale Semiconductor Initialization/Application Information Figure 14-22 shows an example of this error. In this example, the user has additionally chosen an incorrect value of 30 SLIC clocks for the length of one bit time, and a filter prescaler of 1. This makes little difference in the receive sampling of this particular bit, as the sample point is still within the bit and the digital filter will catch any noise pulses shorter than 16 filter clocks long.The ideal value of SLCBT would be 35 SLIC clocks, but the closest available value is 34, placing the sample point at 17 SLIC clocks into the bit. The error in the bit time value chosen by the user in the above example will grow throughout the byte, as the sample point for the next bit will be only 30 SLIC clock cycles later (1 full bit time at this bit rate setting). The SLIC resynchronizes upon every falling edge received. In a 0x00 data byte, however, there are no falling edges after the beginning of the start bit. This means that the accumulated error of the sampling point over the data byte with these settings could be as high as 30 SLIC clock cycles (10 bits x {2 SLIC clocks due to user error + 1 SLIC clock resolution error}) placing it at the boundary between the last bit and the stop bit. This could result in missampling and missing a byte framing error on the last bit on high speed communications when the SLCBT count is relatively low. A properly chosen SLCBT value would result in a maximum error of 10 SLIC clock counts over a given byte. This is less than one filter delay time, and will not cause missampling of any of the bits in that byte. At the falling edge of the next start bit, the SLIC will resynchronize and any accumulated sampling error returns to 0. The sampling error becomes even less significant at lower speeds, when higher values of SLCBT are used to define a bit time, as the worst case bit time resolution error is still only one SLIC clock per bit (or maximum of 10 SLIC clocks per byte). UNFILTERED RX DATA FILTERED RX DATA (³1 PRESCALE) FILTER CLOCK (³1 PRESCALE) 16 FILTER CLOCKS (³1 PRESCALE) FILTER BEGINS COUNTING DOWN 16 FILTER CLOCKS (³1 PRESCALE) FILTER REACHES 0X0 AND TOGGLES FILTER OUTPUT FILTER BEGINS COUNTING UP FILTER REACHES 0XF AND TOGGLES FILTER OUTPUT SLIC CLOCK 15 SLIC CLOCKS (1/2 OF SLCBT VALUE) 35 SLIC CLOCKS (ACTUAL FILTERED BIT LENGTH) IDEAL SLIC SAMPLE POINT (17 SLIC CLOCKS) This example assumes a SLCBT value of 30 (0x1E). Transmitted bits will be sent out as 30 SLIC clock cycles long. SLIC SAMPLE POINT (BASED ON SLCBT VALUE) The proper closest SLCBT setting would be 34 (0x22), which gives the ideal sample point of 17 SLIC clocks and transmitted bits are 34 SLIC clocks long. Figure 14-22. BTM Mode Receive Byte Sampling Example MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 167 Slave LIN Interface Controller (SLIC) Module The error also comes into effect with transmitted bit times. Using the previous example with a SLCBT value of 34, transmitted bits will appear as 34 SLIC clock periods long. This is one SLIC clock short of the proper length. Depending on the frequency of the SLIC clock, one period of the SLIC clock might be a large or a small fraction of one ideal bit time. Raising the frequency of the SLIC clock will reduce this error relative to the ideal bit time, improving the resolution of the SLIC clock relative to the bit rate of the bus. In any case, the error is still one SLIC clock cycle. Raising the SLIC clock frequency, however, requires programming a higher value for SLCBT to maintain the same target bit rate. Smaller values of SLCBT combined with higher values of the SLIC clock frequency (smaller clock period) will give faster bit rates, but the SLIC clock period becomes an increasingly significant portion of one bit time. Because BTM mode does not perform any synchronization and relies on the accuracy of the data provided by the user software to set its sample point and generate transmitted bits, the constraint on maximum speeds is only limited to the limits imposed by the digital filter delay and the SLIC input clock. Because the digital filter delay cannot be less than 16 SLIC clock cycles, the fastest possible pulse which would pass the filter is 16 clock periods at 8 MHz, or 500,000 bits/second. The values shown in Table 14-7 are the same values shown in Table 14-8 and indicate the absolute fastest bit rates which could just pass the minimum digital filter settings (prescaler = divide by 1) under perfect conditions. Because perfect conditions are almost impossible to attain, more robust values must be chosen for bit rates. For reliable communication, it is best to ensure that a bit time is no smaller 2x–3x longer than the filter delay on the digital receive filter. This is true in LIN or BTM mode and ensures that valid data bits which have been shortened due to ground shift, asymmetrical rise and fall times, etc., are accepted by the filter without exception. This would translate to 2x to 3x reduction in the maximum speeds shown in Table 14-7. Recommended maximum bit rates are shown in Table 14-8, and ensure that a single bit time is at least twice the length of one filter delay value. If system noise is not adequately filtered out it might be necessary to change the prescaler of the filter and lower the bit rate of the communication. If valid communications are being absorbed by the filter, corrective action must be taken to ensure that either the bit rate is reduced or whatever physical fault is causing bit times to shorten is corrected (ground offset, asymmetrical rise/fall times, insufficient physical layer supply voltage, etc.). Table 14-8. Recommended Maximum Bit Rates for BTM Operation Due to Digital Filter SLIC Clock (MHz) Maximum BTM Bit Rate with Digital RX Filter Set to ÷4 (Bits / Second) Maximum BTM Bit Rate with Digital RX Filter Set to ÷3 (Bits / Second) Maximum BTM Bit Rate with Digital RX Filter Set to ÷2 (Bits / Second) Maximum BTM Bit Rate with Digital RX Filter Set to ÷1 (Bits / Second) 8 62,500 83,333 120,000(1) 120,000(1) 6.4 50,000 66,667 100,000 120,000(1) 4.8 37,500 50,000 75,000 120,000(1) 4 31,250 41,667 62,500 120,000(1) 3.2 25,000 33,333 50,000 100,000 2.4 18,750 25,000 37,500 75,000 2 15,625 20,833 31,250 62,500 1. Bit rates over 120,000 bits per second are not recommended for BTM communications, as physical layer delay between the TX and RX pins can cause the stop bit of a byte to be missampled as the last data bit. This could result in a byte framing error. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 168 Freescale Semiconductor Initialization/Application Information 14.9.16 Oscillator Trimming with SLIC SLCACT can be used as an indicator of LIN bus activity. SLCACT tells the user that the SLIC is currently processing a message header (therefore synchronizing to the bus) or processing a message frame (including checksum). Therefore, at idle times between message frames or during a message frame which has been marked as a “don’t care” by writing IMSG, it is possible to trim the oscillator circuit of the MCU with no impact to the LIN communications. It is important to note the exact mechanisms with which the SLIC sets and clears SLCACT. Any falling edge which successfully passes through the digital receive filter will cause SLCACT to become set. This might even include noise pulses, if they are of sufficient length to pass through the digital RX filter. Although in these cases SLCACT is becoming set on a noise spike, it is very probable that noise of this nature will cause other system issues as well such as corruption of the message frame. The software can then further qualify if it is appropriate to trim the oscillator. SLCACT will only be cleared by the SLIC upon successful completion of a normal LIN message frame (see 14.8.3 SLIC Status Register description for more detail). This means that in some cases, if a message frame terminates with an error condition or some source other than those cited in the SLCACT bit description, SLCACT might remain set during an otherwise idle bus time. SLCACT will then clear upon the successful completion of the next LIN message frame. These mechanisms might result in SLCACT being set when it is safe (from the SLIC module perspective) to trim the oscillator. However, SLCACT will only be clear when the SLIC considers it safe to trim the oscillator. In a particular system, it might also be possible to improve the opportunities for trimming by using system knowledge and use of IMSG. If a message ID is known to be considered a “don’t care” by this particular node, it should be safe to trim the oscillator during that message frame (provided that it is safe for the application software as well). After the software has done an identifier lookup and determined that the ID corresponds to a “don’t care” message, the software might choose to set IMSG. From that time, the application software should have at least one byte time of message traffic in which to trim the oscillator before that ignored message frame expires, regardless of the state of SLCACT. If the length of that ignored message frame is known, that knowledge might also be used to extend the time of this oscillator trimming opportunity. Now that the mechanisms for recognizing when the SLIC module indicates safe oscillator trimming opportunities are understood, it is important to understand how to derive the information needed to perform the trimming. The value in SLCBT will indicate how many SLIC clock cycles comprise one bit time and for any given LIN bus speed, this will be a fixed value if the oscillator is running at its ideal frequency. It is possible to use this ideal value combined with the measured value in SLCBT to determine how to adjust the oscillator of the microcontroller. The actual oscillator trimming algorithm is very specific to each particular implementation, and applications might or might not require the oscillator even to be trimmed. The SLIC can maintain communications even with input oscillator variation of ±50% (with 4 MHz nominal, that means that any input clock into the SLIC from 2 MHz to 6 MHz will still guarantee communications). Because Freescale internal oscillators are at least within ±25% of their nominal value, even when untrimmed, this means that trimming of the oscillator is not even required for LIN communications. If the application can tolerate the range of frequencies which might appear within this manufacturing range, then it is not necessary ever to trim the oscillator. This can be a tremendous advantage to the customer, enabling migration to very low-cost ROM devices which have no non-volatile memory in which to store the trim value. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 169 Slave LIN Interface Controller (SLIC) Module NOTE Even though most internal oscillators are within ±25% before trimming, they are stable at some frequency in that range, within at least ±5% over the entire operating voltage and temperature range. The trimming operation simply eliminates the offset due to factory manufacturing variations to re-center the base oscillator frequency to the nominal value. Please refer to the electrical specifications for the oscillator for more specific information, as exact specifications might differ from module to module. 14.9.17 Digital Receive Filter The receiver section of the SLIC module includes a digital low-pass filter to remove narrow noise pulses from the incoming message. block diagram of the digital filter is shown in Figure 14-23. DIGITAL RX FILTER PRESCALER (RXFP[1:0]) INPUT SYNC RX DATA FROM SLCRX PIN D 4-BIT UP/DOWN COUNTER Q UP/DOWN OUT 4 EDGE & COUNT COMPARATOR D Q FILTERED RX DATA OUT HOLD SLIC CLOCK Figure 14-23. SLIC Module Rx Digital Filter Block Diagram 14.9.17.1 Digital Filter Operation The clock for the digital filter is provided by the SLIC Interface clock. At each positive edge of the clock signal, the current state of the receiver input signal from the SLCRX pad is sampled. The SLCRX signal state is used to determine whether the counter should increment or decrement at the next positive edge of the clock signal. The counter will increment if the input data sample is high but decrement if the input sample is low. The counter will thus progress up towards the highest count value (determined by RXFP bit settings), on average, the SLCRX signal remains high or progress down towards ‘0’ if, on average, the SLCRX signal remains low. The final counter value which determines when the filter will change state is generated by shifting the RXFP value right two positions and bitwise OR-ing the result with the value 0x0F. For example, a prescale setting of divide by 3 (RXFP = 0x80) would give a count value of 0x2F. When the counter eventually reaches this value, the digital filter decides that the condition of the SLCRX signal is at a stable logic level 1 and the data latch is set, causing the filtered Rx data signal to become a logic level 1. Furthermore, the counter is prevented from overflowing and can only be decremented from this state. Alternatively, when the counter eventually reaches the value ‘0’, the digital filter decides that the condition of the SLCRX signal is at a stable logic level 0 and the data latch is reset, causing the filtered Rx data MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 170 Freescale Semiconductor Initialization/Application Information signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only be incremented from this state. The data latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the SLCRX signal. 14.9.17.2 Digital Filter Performance The performance of the digital filter is best described in the time domain rather than the frequency domain. If the signal on the SLCRX signal transitions, then there will be a delay before that transition appears at the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. This ‘filter delay’ is not an issue for SLIC operation, as there is no need for message arbitration. The effect of random noise on the SLCRX signal depends on the characteristics of the noise itself. Narrow noise pulses on the SLCRX signal will be completely ignored if they are shorter than the filter delay. This provides a degree of low-pass filtering. Figure 14-23 shows the configuration of the digital receive filter and the consequential effect on the filter delay. This filter delay value indicates that for a particular setup, only pulses of which are greater than the filter delay will pass the filter. For example, if the frequency of the SLIC clock (fSLIC) is 3.2 MHz, then the period (tSLIC) is of the SLIC clock is 313 ns. With the default receive filter prescaler setting of division by 3, the resulting maximum filter delay in the absence of noise will be 15.00 µs. By simply changing the prescaler of the receive filter, the user can then select alternatively 5 µs, 10 µs, or 20 µs as a minimum filter delay according to the systems requirements. If noise occurs during a symbol transition, the detection of that transition may be delayed by an amount equal to the length of the noise burst. This is just a reflection of the uncertainty of where the transition is truly occurring within the noise. NOTE The user must always account for the worst case bit timing of their LIN bus when configuring the digital receive filter, especially if running at faster speeds. Ground offset and other physical layer conditions can cause shortening of bits as seen at the digital receive pin, for example. If these shortened bit lengths are less than the filter delay, the bits will be interpreted by the filter as noise and will be blocked, even though the nominal bit timing might be greater than the filter delay. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 171 Slave LIN Interface Controller (SLIC) Module MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 172 Freescale Semiconductor Chapter 15 Timer Interface Module (TIM) 15.1 Introduction This section describes the timer interface module (TIM). The TIM module is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. The TIM module shares its pins with general-purpose input/output (I/O) port pins. See Figure 15-1 for port location of these shared pins. 15.2 Features Features include the following: • Two input capture/output compare channels – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action • Buffered and unbuffered output compare pulse-width modulation (PWM) signal generation • Programmable clock input – 7-frequency internal bus clock prescaler selection – External clock input pin if available, See Figure 15-1 • Free-running or modulo up-count operation • Toggle any channel pin on overflow • Counter stop and reset bits 15.3 Functional Description Figure 15-2 shows the structure of the TIM. The central component of the TIM is the 16-bit counter that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the input capture and output compare functions. The counter modulo registers, TMODH:TMODL, control the modulo value of the counter. Software can read the counter value, TCNTH:TCNTL, at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels. 15.3.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs or the external clock input pin, TCLK if available. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the clock source. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 173 Timer Interface Module (TIM) PTA0/AD0/KBI0 INTERNAL OSC PTA3/RST/KBI3 INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/AD1/TCH1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE M68HC08 CPU PTB0/TCH0 PTB1 AUTO WAKEUP MODULE PTB4/SLCRX DDRB PTB3/AD5 PTB PTB2/AD4 LOW-VOLTAGE INHIBIT PTB5/SLCTX PTB6 2-CHANNEL 16-BIT TIMER MODULE PTB7 MC68HC908QL4 128 BYTES USER RAM COP MODULE MC68HC908QL4 4096 BYTES USER FLASH 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER VDD POWER SUPPLY DEVELOPMENT SUPPORT VSS MONITOR ROM BREAK MODULE RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device (pullup/down on port A) PTA[0:5]: Higher current sink and source capability Figure 15-1. Block Diagram Highlighting TIM Block and Pins 15.3.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can be enabled to generate interrupt requests. 15.3.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can be enabled to generate interrupt requests. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 174 Freescale Semiconductor Functional Description TCLK TCLK (IF AVAILABLE) PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TCNTH:TCNTL TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 TOV0 ELS0B ELS0A PORT LOGIC CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L TCH0 CH0F 16-BIT LATCH CH0IE MS0A INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A PORT LOGIC CH1MAX TCH1 16-BIT COMPARATOR TCH1H:TCH1L CH1F 16-BIT LATCH MS1A CH1IE INTERRUPT LOGIC Figure 15-2. TIM Block Diagram 15.3.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 15.3.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: • When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. • When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 175 Timer Interface Module (TIM) current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 15.3.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares. 15.3.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 15-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the TIM to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1). OVERFLOW OVERFLOW OVERFLOW PERIOD POLARITY = 1 (ELSxA = 0) TCHx PULSE WIDTH POLARITY = 0 TCHx (ELSxA = 1) OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 15-3. PWM Period and Pulse Width MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 176 Freescale Semiconductor Functional Description The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000. See 15.8.1 TIM Status and Control Register. The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 15.3.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 15.3.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written to the timer channel (TCHxH:TCHxL). Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. • When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 15.3.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 177 Timer Interface Module (TIM) NOTE In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 15.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the counter by setting the TIM stop bit, TSTOP. b. Reset the counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 15-2. b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 15-2. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 15.8.1 TIM Status and Control Register. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 178 Freescale Semiconductor Interrupts 15.4 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow interrupt requests. TOF and TOIE are in the TSC register. • TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM interrupt requests are enabled when CHxIE =1. CHxF and CHxIE are in the TSCx register. 15.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 15.5.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 15.5.2 Stop Mode The TIM module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. TIM operation resumes after an external interrupt. If stop mode is exited by reset, the TIM is reset. 15.6 TIM During Break Interrupts A break interrupt stops the counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 15.7 I/O Signals The TIM module can share its pins with the general-purpose I/O pins. See Figure 15-1 for the port pins that are shared. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 179 Timer Interface Module (TIM) 15.7.1 TIM Channel I/O Pins (TCH1:TCH0) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. TCH0 can be configured as buffered output compare or buffered PWM pin. 15.7.2 TIM Clock Pin (TCLK) TCLK is an external clock input that can be the clock source for the counter instead of the prescaled internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS[2:0]. The minimum TCLK pulse width is specified in the Timer Interface Module Characteristics table in the Electricals section. The maximum TCLK frequency is the least of 4 MHz or bus frequency ÷ 2. 15.8 Registers The following registers control and monitor operation of the TIM: • TIM status and control register (TSC) • TIM control registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0 and TSC1) • TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L) 15.8.1 TIM Status and Control Register The TIM status and control register (TSC) does the following: • Enables TIM overflow interrupts • Flags TIM overflows • Stops the counter • Resets the counter • Prescales the counter clock Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 15-4. TIM Status and Control Register (TSC) TOF — TIM Overflow Flag Bit This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a 1 to TOF has no effect. 1 = Counter has reached modulo value 0 = Counter has not reached modulo value MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 180 Freescale Semiconductor Registers TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the counter until software clears the TSTOP bit. 1 = Counter stopped 0 = Counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. Also, when the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until the TSTOP bit is cleared. TRST — TIM Reset Bit Setting this write-only bit resets the counter and the TIM prescaler. Setting TRST has no effect on any other timer registers. Counting resumes from $0000. TRST is cleared automatically after the counter is reset and always reads as 0. 1 = Prescaler and counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the counter at a value of $0000. PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the counter as Table 15-1 shows. Table 15-1. Prescaler Selection PS2 PS1 PS0 TIM Clock Source 0 0 0 Internal bus clock ÷ 1 0 0 1 Internal bus clock ÷ 2 0 1 0 Internal bus clock ÷ 4 0 1 1 Internal bus clock ÷ 8 1 0 0 Internal bus clock ÷ 16 1 0 1 Internal bus clock ÷ 32 1 1 0 Internal bus clock ÷ 64 1 1 1 TCLK (if available) 15.8.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 181 Timer Interface Module (TIM) NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Write: Reset: Figure 15-5. TIM Counter High Register (TCNTH) Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 15-6. TIM Counter Low Register (TCNTL) 15.8.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the counter. When the counter reaches the modulo value, the overflow flag (TOF) becomes set, and the counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 Figure 15-7. TIM Counter Modulo High Register (TMODH) Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 1 1 1 1 Figure 15-8. TIM Counter Modulo Low Register (TMODL) NOTE Reset the counter before writing to the TIM counter modulo registers. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 182 Freescale Semiconductor Registers 15.8.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers does the following: • Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, or PWM operation • Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIM overflow • Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation Bit 7 Read: CH0F Write: 0 Reset: 0 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 Figure 15-9. TIM Channel 0 Status and Control Register (TSC0) Bit 7 Read: CH1F Write: 0 Reset: 0 6 CH1IE 0 5 0 0 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 = Unimplemented Figure 15-10. TIM Channel 1 Status and Control Register (TSC1) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the counter registers matches the value in the TIM channel x registers. Clear CHxF by reading the TSCx register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Writing a 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIM interrupt service requests on channel x. 1 = Channel x interrupt requests enabled 0 = Channel x interrupt requests disabled MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TSC0. Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to general-purpose I/O. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 183 Timer Interface Module (TIM) MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 15-2. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 15-2). 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). Table 15-2. Mode, Edge, and Level Selection MSxB MSxA ELSxB ELSxA X 0 0 0 X 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 Capture on rising or falling edge 0 1 0 0 Software compare only 0 1 0 1 0 1 1 0 0 1 1 1 1 X 0 1 1 X 1 0 1 X 1 1 Mode Output preset Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Input capture Output compare or PWM Capture on falling edge only Toggle output on compare Clear output on compare Set output on compare Buffered output compare or buffered PWM Toggle output on compare Clear output on compare Set output on compare ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 15-2 shows how ELSxB and ELSxA work. NOTE After initially enabling a TIM channel register for input capture operation and selecting the edge sensitivity, clear CHxF to ignore any erroneous edge detection flags. TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow. NOTE When TOVx is set, a counter overflow takes precedence over a channel x output compare if both occur at the same time. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 184 Freescale Semiconductor Registers CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 15-11 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 15-11. CHxMAX Latency 15.8.5 TIM Channel Registers These read/write registers contain the captured counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Figure 15-12. TIM Channel x Register High (TCHxH) Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Figure 15-13. TIM Channel Register Low (TCHxL) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 185 Timer Interface Module (TIM) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 186 Freescale Semiconductor Chapter 16 Development Support 16.1 Introduction This section describes the break module, the monitor module, and the monitor mode entry methods. 16.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. Features include: • Accessible input/output (I/O) registers during the break Interrupt • Central processor unit (CPU) generated break interrupts • Software-generated break interrupts • Computer operating properly (COP) disabling during break interrupts 16.2.1 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: • A CPU generated address (the address in the program counter) matches the contents of the break address registers. • Software writes a 1 to the BRKA bit in the break status and control register. When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 16-2 shows the structure of the break module. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 187 Development Support PTA0/AD0/KBI0 INTERNAL OSC PTA3/RST/KBI3 INTERNAL CLOCK SOURCE 4, 8, 12.8, or 25.6 MHz DDRA PTA2/IRQ/KBI2/TCLK PTA PTA1/AD1/TCH1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 EXTERNAL INTERRUPT MODULE M68HC08 CPU PTB0/TCH0 PTB1 AUTO WAKEUP MODULE PTB4/SLCRX DDRB PTB3/AD5 PTB PTB2/AD4 LOW-VOLTAGE INHIBIT PTB5/SLCTX PTB6 2-CHANNEL 16-BIT TIMER MODULE PTB7 MC68HC908QL4 128 BYTES USER RAM COP MODULE MC68HC908QL4 4096 BYTES USER FLASH 6-CHANNEL 10-BIT ADC SLAVE LIN INTERFACE CONTROLLER VDD POWER SUPPLY DEVELOPMENT SUPPORT VSS MONITOR ROM BREAK MODULE RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device (pullup/down on port A) PTA[0:5]: Higher current sink and source capability Figure 16-1. Block Diagram Highlighting BRK and MON Blocks MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 188 Freescale Semiconductor Break Module (BRK) ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] CONTROL BKPT (TO SIM) 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 16-2. Break Module Block Diagram When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. • When a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. • When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction is executed. By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can be generated continuously. CAUTION A break address should be placed at the address of the instruction opcode. When software does not change the break address and clears the BRKA bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 16.2.1.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 13.8.2 Break Flag Control Register and the Break Interrupts subsection for each module. 16.2.1.2 TIM During Break Interrupts A break interrupt stops the timer counter. 16.2.1.3 COP During Break Interrupts The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 189 Development Support 16.2.2 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) 16.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Bit 7 Read: Write: Reset: 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 16-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match 16.2.2.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 16-4. Break Address Register High (BRKH) Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 16-5. Break Address Register Low (BRKL) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 190 Freescale Semiconductor Break Module (BRK) 16.2.2.3 Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode. Read: Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: Bit 0 BDCOP 0 = Unimplemented Figure 16-6. Break Auxiliary Register (BRKAR) BDCOP — Break Disable COP Bit This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit. 1 = COP disabled during break interrupt 0 = COP enabled during break interrupt 16.2.2.4 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Read: Write: Bit 7 6 5 4 3 2 R R R R R R R = Reserved Reset: 1 SBSW Note(1) Bit 0 R 0 1. Writing a 0 clears SBSW. Figure 16-7. Break Status Register (BSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt 16.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 16-8. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 191 Development Support 16.2.3 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes. However, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. 16.3 Monitor Module (MON) The monitor module allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. Features include: • Normal user-mode pin functionality • One pin dedicated to serial communication between MCU and host computer • Standard non-return-to-zero (NRZ) communication with host computer • Standard communication baud rate (7200 @ 2-MHz bus frequency) • Execution of code in random-access memory (RAM) or FLASH • FLASH memory security feature(1) • FLASH memory programming interface • Use of external 9.8304 MHz crystal or clock to generate internal frequency of 2.4576 MHz • Simple internal oscillator mode of operation (no external clock or high voltage) • Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) • Normal monitor mode entry if VTST is applied to IRQ 16.3.1 Functional Description Figure 16-9 shows a simplified diagram of monitor mode entry. The monitor module receives and executes commands from a host computer. Figure 16-10, Figure 16-11, and Figure 16-12 show example circuits used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. The monitor code has been updated from previous versions of the monitor code to allow enabling the internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if programmed) to generate the desired internal frequency (3.2 MHz). Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value is not $FFFF) because entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must remain low during this monitor session in order to maintain communication. 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 192 Freescale Semiconductor Monitor Module (MON) POR RESET NO CONDITIONS FROM Table 16-1 PTA0 = 1, RESET VECTOR BLANK? IRQ = VTST? YES PTA0 = 1, PTA1 = 1, AND PTA4 = 0? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE HOST SENDS 8 SECURITY BYTES IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO Figure 16-9. Simplified Monitor Mode Entry Flowchart MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 193 Development Support VDD VDD 10 kΩ* VDD 0.1 µF RST (PTA3) MAX232 1 1 µF + VDD VTST 15 C1– 1 µF + 1 µF 7 10 8 9 10 kΩ* PTA1 IRQ (PTA2) VDD 9.1 V 10 kΩ* 10 kΩ + PTA4 74HC125 5 6 DB9 3 1 kΩ V– 6 5 C2– 2 1 µF V+ 2 C2+ VDD 1 µF + 4 OSC1 (PTA5) 16 C1+ + 3 9.8304 MHz CLOCK 74HC125 3 2 PTA0 4 VSS 1 5 * Value not critical Figure 16-10. Monitor Mode Circuit (External Clock, with High Voltage) VDD N.C. RST (PTA3) VDD 0.1 µF MAX232 1 1 µF + 16 9.8304 MHz CLOCK + 3 4 1 µF C1+ VDD C1– C2+ + 5 C2– 15 + 1 µF 10 kΩ* V+ 2 VDD 1 µF 10 kΩ 74HC125 5 6 + 2 7 10 3 8 9 2 74HC125 3 PTA1 N.C. PTA4 N.C. IRQ (PTA2) V– 6 DB9 5 OSC1 (PTA5) 1 µF PTA0 4 VSS 1 Figure 16-11. Monitor Mode Circuit (External Clock, No High Voltage) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 194 Freescale Semiconductor Monitor Module (MON) VDD N.C. RST (PTA3) VDD 0.1 µF MAX232 1 1 µF + 4 N.C. 1 µF 15 C1– + + PTA1 N.C. PTA4 N.C. 10 kΩ* VDD V– 6 1 µF 10 kΩ 74HC125 5 6 + DB9 3 IRQ (PTA2) 1 µF V+ 2 C2+ 5 C2– 2 OSC1 (PTA5) 16 C1+ + 3 1 µF VDD 7 10 8 9 74HC125 3 2 PTA0 VSS 4 1 5 * Value not critical Figure 16-12. Monitor Mode Circuit (Internal Clock, No High Voltage) Table 16-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one of the following sets of conditions is met: • If $FFFE and $FFFF do not contain $FF (programmed state): – The external clock is 9.8304 MHz – IRQ = VTST • If $FFFE and $FFFF contain $FF (erased state): – The external clock is 9.8304 MHz – IRQ = VDD (this can be implemented through the internal IRQ pullup) • If $FFFE and $FFFF contain $FF (erased state): IRQ = VSS (internal oscillator is selected, no external clock required) The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the values on PTA1 and PTA4 pins can be changed. Once out of reset, the MCU waits for the host to send eight security bytes (see 16.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to receive a command. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 195 Development Support Table 16-1. Monitor Mode Signal Requirements and Options Mode IRQ (PTA2) Serial Mode CommuniSelection RST Reset cation (PTA3) Vector PTA0 PTA1 PTA4 Communication Speed COP Comments External Bus Baud Clock Frequency Rate VTST VDD X 1 1 0 Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VDD X $FFFF (blank) 1 X X Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VSS X $FFFF (blank) 1 X X Disabled X 3.2 MHz (Trimmed) 9600 Internal clock is active. User X X Not $FFFF X X X Enabled X X X MON08 Function [Pin No.] VTST [6] RST [4] — COM [8] — OSC1 [13] — — Normal Monitor Forced Monitor MOD0 MOD1 [12] [10] 1. PTA0 must have a pullup resistor to VDD in monitor mode. 2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus frequency / 256 and baud rate using internal oscillator is bus frequency / 333. 3. External clock is a 9.8304 MHz oscillator on OSC1. 4. X = don’t care 5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector. NC 1 2 GND NC 3 4 RST NC 5 6 IRQ NC 7 8 PTA0 NC 9 10 PTA4 NC 11 12 PTA1 OSC1 13 14 NC VDD 15 16 NC . 16.3.1.1 Normal Monitor Mode RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in monitor mode, but the pin functions will be determined by the settings in the configuration registers (see Chapter 5 Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH and BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register. If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to IRQ. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 196 Freescale Semiconductor Monitor Module (MON) 16.3.1.2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit programming. NOTE If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR). Once the reset vector has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode. If monitor mode was entered as a result of the reset vector being blank, the COP is always disabled regardless of the state of IRQ. If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset in user mode. Internal circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode without requiring high voltage on the IRQ pin. Once out of reset, the monitor code is initially executing with the internal clock at its default frequency. If IRQ is held high, all pins will default to regular input port functions except for PTA0 and PTA5 which will operate as a serial communication port and OSC1 input respectively (refer to Figure 16-11). That will allow the clock to be driven from an external source through OSC1 pin. If IRQ is held low, all pins will default to regular input port function except for PTA0 which will operate as serial communication port. Refer to Figure 16-12. Regardless of the state of the IRQ pin, it will not function as a port input pin in monitor mode. Bit 2 of the Port A data register will always read 0. The BIH and BIL instructions will behave as if the IRQ pin is enabled, regardless of the settings in the configuration register. See Chapter 5 Configuration Register (CONFIG). The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will automatically force the MCU to come back to the forced monitor mode. 16.3.1.3 Monitor Vectors In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. NOTE Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST (when RST pin available) low will not exit monitor mode in this situation. Table 16-2 summarizes the differences between user mode and monitor mode regarding vectors. Table 16-2. Mode Differences Functions Modes Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 197 Development Support 16.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 16-13. Monitor Data Format 16.3.1.5 Break Signal A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of approximately two bits and then echoes back the break signal. MISSING STOP BIT 0 1 2 3 4 5 6 APPROXIMATELY 2 BITS DELAY BEFORE ZERO ECHO 7 0 1 2 3 4 5 6 7 Figure 16-14. Break Transaction 16.3.1.6 Baud Rate The monitor communication baud rate is controlled by the frequency of the external or internal oscillator and the state of the appropriate pins as shown in Table 16-1. Table 16-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in forced monitor mode, the effective baud rate is the bus frequency divided by 335. 16.3.1.7 Commands The monitor ROM firmware uses these commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 198 Freescale Semiconductor Monitor Module (MON) FROM HOST READ 4 ADDRESS HIGH READ ADDRESS HIGH 4 1 ADDRESS LOW 1 ADDRESS LOW 4 DATA 1 3, 2 4 ECHO RETURN Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 16-15. Read Transaction FROM HOST 3 ADDRESS HIGH WRITE WRITE 3 1 ADDRESS HIGH 1 ADDRESS LOW 3 ADDRESS LOW 1 DATA DATA 3 1 2, 3 ECHO Notes: 1 = Echo delay, approximately 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. Figure 16-16. Write Transaction A brief description of each monitor mode command is given in Table 16-3 through Table 16-8. Table 16-3. READ (Read Memory) Command Description Operand Data Returned Opcode Read byte from memory 2-byte address in high-byte:low-byte order Returns contents of specified address $4A Command Sequence SENT TO MONITOR READ ECHO READ ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA RETURN MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 199 Development Support Table 16-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE ADDRESS HIGH WRITE ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 16-5. IREAD (Indexed Read) Command Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed None Returns contents of next two addresses $1A Command Sequence FROM HOST IREAD IREAD DATA ECHO DATA RETURN Table 16-6. IWRITE (Indexed Write) Command Description Operand Data Returned Opcode Write to last address accessed + 1 Single data byte None $19 Command Sequence FROM HOST IWRITE IWRITE DATA DATA ECHO A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 200 Freescale Semiconductor Monitor Module (MON) Table 16-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 16-8. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode $28 Command Sequence FROM HOST RUN RUN ECHO The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6. SP HIGH BYTE OF INDEX REGISTER SP + 1 CONDITION CODE REGISTER SP + 2 ACCUMULATOR SP + 3 LOW BYTE OF INDEX REGISTER SP + 4 HIGH BYTE OF PROGRAM COUNTER SP + 5 LOW BYTE OF PROGRAM COUNTER SP + 6 SP + 7 Figure 16-17. Stack Pointer at Monitor Mode Entry MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 201 Development Support 16.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. See Figure 16-18. Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE The MCU does not transmit a break character until after the host sends the eight security bytes. VDD 4096 + 32 BUSCLKX4 CYCLES COMMAND BYTE 8 BYTE 2 BYTE 1 RST FROM HOST PA0 4 BREAK 2 1 COMMAND ECHO 1 BYTE 8 ECHO Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 4 = Wait 1 bit time before sending next byte 5 = Wait until the monitor ROM runs 1 BYTE 2 ECHO FROM MCU 4 1 BYTE 1 ECHO 5 Figure 16-18. Monitor Mode Entry Timing To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 202 Freescale Semiconductor Chapter 17 Electrical Specifications 17.1 Introduction This section contains electrical and timing specifications. 17.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 17.5 5-V DC Electrical Characteristics and 17.8 3.3-V DC Electrical Characteristics for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage VIN VSS –0.3 to VDD +0.3 V VTST VSS –0.3 to +9.1 V I ±15 mA IPTA0—IPTA5 ±25 mA Storage temperature TSTG –55 to +150 °C Maximum current out of VSS IMVSS 100 mA Maximum current into VDD IMVDD 100 mA Mode entry voltage, IRQ pin Maximum current per pin excluding PTA0–PTA5, VDD, and VSS Maximum current for pins PTA0–PTA5 1. Voltages references to VSS. NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 203 Electrical Specifications 17.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit Temperature Code TA (TL to TH) – 40 to +125 – 40 to +105 – 40 to +85 °C M V C VDD 3.0 to 5.5 V — 17.4 Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance 16-pin SOIC 16-pin TSSOP θJA 90 133 °C/W I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD x VDD) + PI/O = K/(TJ + 273°C) W Constant(2) K PD x (TA + 273°C) + PD2 x θJA W/°C Average junction temperature TJ TA + (PD x θJA) °C TJM 150 °C Maximum junction temperature 1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 204 Freescale Semiconductor 5-V DC Electrical Characteristics 17.5 5-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.4 VDD –1.5 VDD –0.8 — — — — — — — — 50 — — — — — — 0.4 1.5 0.8 Unit Output high voltage ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins ILoad = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 1.6 mA, all I/O pins ILoad = 10.0 mA, all I/O pins ILoad = 15.0 mA, PTA0, PTA1, PTA3–PTA5 only VOL Maximum combined IOL (all I/O pins) IOHL — — 50 mA Input high voltage PTA0–PTA5, PTB0–PTB7 VIH 0.7 x VDD — VDD V Input low voltage PTA0–PTA5, PTB0–PTB7 VIL VSS — 0.3 x VDD V VHYS 0.06 x VDD — — V IINJ –2 — +2 mA IINJTOT –25 — +25 mA Ports Hi-Z leakage current IIL –1 ±0.1 +1 µA Capacitance Ports (as input)(3) CIN — — 8 pF VPOR 750 — — mV RPOR 0.035 — — V/ms VTST VDD + 2.5 — 9.1 V Pullup resistors PTA0–PTA5, PTB0–PTB7 RPU 16 26 36 kΩ Pulldown resistors(7) PTA0–PTA5 RPD 16 26 36 kΩ Low-voltage inhibit reset, trip falling voltage VTRIPF 3.90 4.20 4.50 V Low-voltage inhibit reset, trip rising voltage VTRIPR 4.00 4.30 4.60 V Low-voltage inhibit reset/recover hysteresis VHYS — 100 — mV Input hysteresis(3) (4) DC injection current, all ports Total dc current injection (sum of all I/O)(4) POR rearm voltage (3)(5) POR rise time ramp rate Monitor mode entry voltage (3) V mA V (6) 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. 3. Values are based on characterization results, not tested in production. 4. Guaranteed by design, not tested in production. 5. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum VDD is reached. 6. RPU is measured at VDD = 5.0 V. Pullup resistors only available when PTAPUEx is enabled with KBIPx = 0. 7. RPD is measured at VDD = 5.0 V, Pulldown resistors only available when PTAPUEx is enabled with KBIPx =1. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 205 Electrical Specifications 17.6 Typical 5-V Output Drive Characteristics 1.6 1.4 VDD-VOH (V) 1.2 1.0 5V PTA 0.8 5V PTB 0.6 0.4 0.2 0.0 0 -5 -10 -15 -20 -25 -30 IOH (mA ) Figure 17-1. Typical 5-Volt Output High Voltage versus Output High Current (25°C) 1.6 1.4 1.2 VOL (V) 1.0 5V PTA 0.8 5V PTB 0.6 0.4 0.2 0.0 0 5 10 15 20 25 30 IOL (mA ) Figure 17-2. Typical 5-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 206 Freescale Semiconductor 5-V Control Timing 17.7 5-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBUS) — 8 MHz Internal clock period (1/fOP) tcyc 125 — ns tRL 100 — ns tILIH 100 — ns — tcyc RST input pulse width low(2) (2) IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period tILIL (3) Note 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Values are based on characterization results, not tested in production. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc. tRL RST tILIL tILIH IRQ Figure 17-3. RST and IRQ Timing MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 207 Electrical Specifications 17.8 3.3-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.3 VDD –1.0 VDD –0.8 — — — — — — — — 50 — — — — — — 0.3 1.0 0.8 Unit Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10.0 mA, PTA0, PTA1, PTA3–PTA5 only VOL Maximum combined IOL (all I/O pins) IOHL — — 50 mA Input high voltage PTA0–PTA5, PTB0–PTB7 VIH 0.7 x VDD — VDD V Input low voltage PTA0–PTA5, PTB0–PTB7 VIL VSS — 0.3 x VDD V VHYS 0.06 x VDD — — V IINJ –2 — +2 mA IINJTOT –25 — +25 mA Ports Hi-Z leakage current IIL –1 ±0.1 +1 µA Capacitance Ports (as input)(3) CIN — — 8 pF POR rearm voltage VPOR 0.75 — — V RPOR 0.035 — — V/ms VTST VDD + 2.5 — VDD + 4.0 V Pullup PTA0–PTA5, PTB0–PTB7 RPU 16 26 36 kΩ Pulldown resistors(7) PTA0–PTA5 RPD 16 26 36 kΩ Low-voltage inhibit reset, trip falling voltage VTRIPF 2.65 2.8 3.0 V Low-voltage inhibit reset, trip rising voltage VTRIPR 2.75 2.9 3.10 V Low-voltage inhibit reset/recover hysteresis VHYS — 100 — mV Input hysteresis(3) DC injection current, all ports(4) (4) Total dc current injection (sum of all I/O) POR rise time ramp rate(3)(5) Monitor mode entry voltage (3) resistors(6) V mA V 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. 3. Values are based on characterization results, not tested in production. 4. Guaranteed by design, not tested in production. 5. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum VDD is reached. 6. RPU is measured at VDD = 3.3 V. Pullup resistors only available when PTAPUEx is enabled with KBIPx = 0. 7. RPD is measured at VDD = 3.3 V, Pulldown resistors only available when PTAPUEx is enabled with KBIPx =1. MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 208 Freescale Semiconductor Typical 3.3-V Output Drive Characteristics 17.9 Typical 3.3-V Output Drive Characteristics 1.2 1.0 VDD-VOH (V) 0.8 3.3V PTA 0.6 3.3V PTB 0.4 0.2 0.0 0 -5 -10 -15 -20 -25 IOH (mA) Figure 17-4. Typical 3.3-Volt Output High Voltage versus Output High Current (25°C) 1.2 1.0 0.8 VOL (V) 3.3V PTA 0.6 3.3V PTB 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) Figure 17-5. Typical 3.3-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 6 Freescale Semiconductor 209 Electrical Specifications 17.10 3.3-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBus) — 4 MHz Internal clock period (1/fOP) tcyc 250 — ns tRL 200 — ns tILIH 200 — ns — tcyc RST input pulse width low(2) (2) IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period tILIL (3) Note 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Values are based on characterization results, not tested in production. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc. tRL RST tILIL tILIH IRQ Figure 17-6. RST and IRQ Timing 17.11 Oscillator Characteristics Characteristic Symbol Min Typ Max fINTCLK — — — — 4 8 12.8 25.6 — — — — — ± 0.4 — — — — — ±2 — — — — ±5 ±5 ±5 — — — — ±5 — — — — ± 10 ± 10 ± 10 Unit (1) Internal oscillator frequency ICFS1:ICFS0 = 00 ICFS1:ICFS0 = 01 ICFS1:ICFS0 = 10 (not allowed if VDD