Freescale Semiconductor
Advance Information
Document Number: MC33094
Rev. 1.0, 10/2006
Ignition Control
33094
Designed for automotive ignition applications in 12 V systems, the
33094 provides outstanding control of the ignition coil when used with
an appropriate Motorola Power Darlington Transistor. Engine control
systems utilizing these devices for ignition coil control exhibit
exceptional fuel efficiency and low exhaust emissions. The device is
designed to be controlled from a single–ended Hall Sensor input. The
circuit is built using high–density Integrated–Injection Logic (IIL)
processing incorporating high current–gain PNP and NPN
transistors.
The 33094 is packaged in an economical surface mount package
and specified over an ambient temperature of –40°C to 125°C with a
maximum junction temperature of 150°C.
IGNITION CONTROL
DW SUFFIX
EG SUFFIX (PB-FREE)
98ASB42567B
16-PIN SOICW
Features
•
•
•
•
•
•
•
•
•
•
External Capacitors Program the Device’s Timing Characteristics
Overvoltage Shutdown Protection
Auto Start–Up Capability After Overvoltage Condition Ceases
Allows for Push Start–Up in Automotive Applications
Ignition Coil Current Limiting
Ignition Coil Voltage Limiting
Band Gap Reference for Enhanced Stability Over Temperature
Negative Edge Filter for Hall Sensor Input Transient Protection
Hall Sensor Inputs for RPM and Position Sensing
Pb-Free Packaging Designated by Suffix Code EG
ORDERING INFORMATION
Device
MC33094DW/R2
MCZ33094EG/R2
33094
SUPPLY
ADAPTIVE CAPACITOR
STALL CAPACITOR
RAMP CAPACITOR
DISTRIBUTOR SIGNAL
NEGATIVE INPUT
COIL
MASTER BIAS
OUTPUT
GROUND
START
CURRENT SENSE
PROCESS TEST
Figure 1. 33094 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Temperature
Range (TA)
Package
-40°C to 125°C
16 SOICW
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
MASTER
BIAS (MB)
GND
VCC
2
6
9
Master Bias
Current Reference
VR
Dump
Master Bias
NEGATIVE
INPUT (INV(-)) 7
VR
Band Gap
Reference
BG
Hi-Bat
VCC
Output Current
Driver and Limiter
ZC
Stall
CURRENT
14 SENSE (S)
Master Bias
VR
Ramp Capacitor
Charging and Sensing
25% 25%
Reset
CR > CA
Adaptive Capacitor
Charging and Sensing
12 OUTPUT (O)
11 COIL (CL)
Stall
PROCESS 13
TEST (T)
DISTRIBUTOR
SIGNAL (D)
Limit
Internal
Logic
START (ST) 8
RAMP
4
CAPACITOR
(CR)
10
VR
Input Voltage
Comparator
Negative
Edge Filter
ADAPTIVE 3
CAPACITOR
(CA)
VCC Comparator
and Clamp
VR Zener
Reference
Master
Bias
CR>CA
Adaptive
Comparator
CR
BG
25% Reset
Stall BG
Stall Sensing
Charging
and Sensing
VR
25%
15
STALL
CAPACITOR (CS)
Figure 2. 33094 Simplified Internal Block Diagram
33094
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
NC
NC
STALL CAPACITOR
MASTER BIAS
CURRENT SENSE
ADAPTIVE CAPACITOR
PROCESS TEST
RAMP CAPACITOR
NC
OUTPUT
IC GROUND
COIL
NEGATIVE INPUT
DISTRIBUTOR SIGNAL
START
SUPPLY
Figure 3. 33094 Pin Connections
Table 1. 33094 Pin Definitions
Pin Number
Pin Name
Formal Name
1, 5, 16
NC
No Connect
No Connection to the circuit
2
MB
Master Bias
Internal bias circuit set pin - ext. resistor
3
CA
Adaptive Capacitor
Manages dwell timing - ext. capacitor
4
CR
Ramp Capacitor
Manages dwell timing - ext. capacitor
6
GND
IC Ground
7
VIN(-)
Negative Input
8
ST
Start
9
VCC
Supply
10
D
Distributor Signal
11
CL
Coil
12
O
Output
13
T
Process Test
Definition
Supply ground
Distributor signal from a sensor
Start/Run mode input
Supply voltage (battery, ingition ON)
Monitor for the battery side of the spart coil
Sparl coil voltage monitor
Supplies base current to the ext. Darlington transnsior
Used to measure internal functions
14
S
Current Sense
Spark coil current sensing input
15
CS
Stall Capacitor
Controls spark coil current - ext. capacitor
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Power Supply Voltage
VCC
28.6
V
Operating Frequency Range
fOP
1.0 to 400
Hz
Junction Temperature
TJ
150
°C
Operating Temperature
TA
ELECTRICAL RATINGS
THERMAL RATINGS
°C
Continuous
-30 to 105
Limited
-40 to 125
Storage Temperature
Peak Package Reflow Temperature During Reflow
(2) (3)
,
TSTG
-55 to 150
°C
TPPRT
Note 3
°C
RθJA
97
°C/W
THERMAL RESISTANCE
Thermal Resistance
Notes
1. ESD data is available upon request.
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
33094
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 6.0 V ≤ VD = VCC ≤ 16 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
ICC
5.0
8.4
18
mA
Overvoltage Shutdown (VIN(-) = 0V, VCA = Open, VCS = 3.0V,
VST = 28V) (5)
VCC3
23.7
27.5
31
V
Start-VCC Latch (VIN(-) = 0V, VCA = VCR = VCS = Open,
VST = 25V, VD = 14V IST = 40mA)
VCC5
8.0
16.1
–
V
SUPPLY AND MASTER BIAS
Supply Current (VCC = 16V, VIN(-) = 0V, VD = 3.0V,
VCA = VCR = VCS = VST = Open) (4)
Adaptive Dwell High Supply Voltage (VIN(-) = 11V, VCA = Open,
VCR = 3.0V, VCS = 3.0V, VST = 6.0V, VD = 13V)
V
Threshold (6)
VCC1
16.5
18.9
19.5
Hysteresis (7)
VCC2 (HYS)
0.2
0.5
0.8
VMB
1.12
1.2
1.32
V
Input Positive Threshold Voltage (VCC = 6.0V, VCA = VCR = Open,
VCS = 1.0V, VST = 6.0V) (9)
VIN(-)(TH)A
50
54
65
%VCC
Input Positive Threshold Voltage (VCC = 16V, VCA = VCR = Open,
VCS = 1.0V, VST = 10V) (10)
VIN(-)(TH)B
50
54
65
%VCC
Input Hysteresis (VCC = 6.0V, VCA = VCR = VCS = Open,
VST = 6.0V) (11)
VIN(-)(HYS)A
0.6
0.72
1.2
V
Input Hysteresis (VCC = 16V, VD = 3.0V,
VCA = VCR = VCS = Open, VST = 10V) (12)
VIN(-)(HYS)B
1.6
2.23
3.2
V
ZI
70
94
250
kΩ
Master Bias Voltage (VCC = 16V, VIN(-) = 0V, VD = 3.0V,
VCA = VCR = VCS = VST = Open) (8)
INPUTS
Input Impedance (VCC = 14V, VIN(-) = 10V, VD = 3.0V,
VCA = VCR = VCS = VST = Open) (13)
Notes
4. Current sourced into Supply pin.
5. Ramp up VCC from 24 to 31V in 0.1 increments and note the supply voltage, VCC, which causes VO to fall below 1.0V.
6.
Ramp up VCC from 14 to 20V in 0.1 increments and measure VCC, when ICA ≤ 2.0 µΑ.
7.
Ramp down VCC from 20 to 14V and measure VCC, when ICA ≥ 2.0 µΑ and compute hysteresis difference from VCC1.
8.
9.
Voltage measured at Master Bias pin.
Ramp up VIN(-) from 1.0 to 5.0V in 0.1 increments. Record VIN(-) when ICR goes positive and convert to % of VCC by dividing by VCC.
10.
Ramp up VIN(-) from 3.0 to 10V in 0.1 increments. Record VIN(-) when ICR goes positive and convert to % of VCC by dividing by VCC.
11.
Ramp up VIN(-) from VIN(-)(TH)A in 0.1 increments. Record VIN(-) when ICR goes positive. VIN(-)(HYS)A = VIN(-)(TH)A - (VIN(-)).
12.
Ramp up VIN(-) from VIN(-)(TH)B in 0.1 increments. Record VIN(-) when ICR goes positive. VIN(-)(HYS)B = VIN(-)(TH)B - (VIN(-)).
13.
Measure IIN(-) into Pin 7; ZI = 10 V/IIN(-).
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VD = VCC ≤ 16 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUT AND DWELL
Output Current (VIN(-) = 0V, VCA = VCR = Open, VCS = 3.0V, VST = 10V,
VO = 2.1V) (14)
Normal Condition (VCC = 14V, VD = 6.0V)
mA
IO1
40
52
65
IO2
40
52
65
Output Leakage Current (VCC = 14V, VIN(-) = 10V, VCA = VCR = VCS =
Open, VST = 10V, VS = 0V, VD = 18V, VO = 0V) (15)
IO3
1.0
-1.33
100
µA
Output Clamp Voltage (VCC = 14V, VIN(-) = 10V, VCA = VCR = VCS =
Open, VST = 10V, VD = 14V, VO = 0V, VCL = 20V, ICL = 10mA) (16)
VCL
13.7
14.52
15.58
V
Output Clamp Dynamic Impedance (VCC = 14V, VIN(-) = 10V, VCA = VCR
= VCS = Open, VST = 10V, VD = 14V, VO = 0V, ICL = 12mA,
∆ICL = 2.0mA) (17)
ZCL
10
37
75
Ω
Normal Condition: D1 = (ICA2/ICA1) x CR
Data from ICA2, ICA1, and CR characteristics
D1
14.5
17.6
20.5
High Voltage Condition: D2 = (ICA3/ICA1) x CR
Data from ICA3, ICA1, and CR characteristics
D2
4.1
5.3
5.9
VCRO
-60
0
60
mV
VSS
0
1.48
16.7
mV
High Voltage Condition (VCC = 14V, VD = 22V)
Dwell (18)
Adaptive Dwell Logic, Ramp Threshold (VCC = 14V, VIN(-) = 10V,
VCA = VCS = Open, VST = 0V, VS = 0V, VD = 10V) (14)
Soft Shutdown Voltage (VCC = 6.0V, VIN(-) = 10V, VCA = VCR = VCS =
Open, VST = 0V) Measure VS
%
Notes
14. Capability measured by forcing the Output to 2.0V with the Current Sense pin (S) open while measuring the Output current to ground.
15. Measured by clamping the output voltage with the S pin to ground, then increasing the VD from 6.0 to 18V and measuring output leakage
current to ground.
16. Output Clamp voltage with reference to ground while forcing 10mA into the Coil pin (CL).
17. Output Clamp impedance measured with ICL = 11 ±1.0mA into the Coil pin (CL) and noting the corresponding Output Clamp Voltage
change (ZCL = ∆VCL/∆ICL).
18.
19.
Dwell is defined as Run Mode Down Current divided by the Run Mode Up Current times the Ramp Control Current Ratio and is
calculated from other measured characteristics as defined above.
Set the VCR (ramp Capacitor) voltage to 1.5V; Ramp VCR voltage from 1.8 to 2.2V in 0.02V increments and note the Ramp voltage (VCR)
which causes the Output voltage to go > 1.0V; VCRO = 2.0V - VCR.
33094
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VD = VCC ≤ 16 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
ICA1
-7.91
-6.53
-5.62
µA
ADAPTIVE CAPACITOR
Run Mode, Adaptive, Charge Current (VCC = 6.0V, VIN(-) = 5.0V,
VCA = Open, VCR = 3.0V, VCS = 3.0V, VST = 6.0V) (20)
µA
Run Mode, Adaptive Capacitor, Discharge Current
(VCA = Open, VCR = 3.0V, VCS = 3.0V, VST = 6.0V)
Normal Condition (VCC = 6.0V, VIN(-) = 10V)
ICA2
3.7
4.77
5.63
High Voltage Condition (VCC = 22V, VIN(-) = 17V, VD = 13V)
ICA3
1.05
1.43
1.82
µA
Start Mode, Adaptive Capacitor Currents
(VCA = VCR = VCS = Open, VST = 10V)
Charge Current (VCC = 5.0V, VIN(-) = 10V) (21)
Discharge Current (VCC = 6.0V, VIN(-) = 0V)
(22)
ICA4
-112
-87
-80
ICA5
67.6
89.4
109
Start Mode, Adaptive Capacitor, Clamp Voltage
(VCC = 6.0V, VCA = VCR = VCS = Open, VST = 10V)
V
High Clamp Voltage (VIN(-) = 10V)
VCA1
2.23
2.30
2,65
Low clamp Voltage (VIN(-) = 0V)
VCA2
0.95
1.1
1.26
AG
0.85
0.99
1.15
Times
Start Mode, Stall Control, Charge Current (VCC = 5.0V, VIN(-) = 0V,
VCA = VCR = Open, VCS = 1.0V, VST = 10V)
ICS1
-2.7
-2.33
-2.13
µA
Run Mode, Stalled, Stall Control, Discharge Current (VCC = 14V,
VIN(-) = 0V, VCA = VCR = Open, VCS = 1.0V, VST = 0V)
ICS2
7.5
9.69
13.2
µA
Run Mode, Stall Control, Charge Current (VCC = 14V,
VIN(-) = 10V, VCA = 2.0V, VCR = 3.0V, VCS = 1.0V, VST = 0V)
ICS3
-33.1
-27
-23.5
µA
Run Mode, Stall Control, Discharge Current (VCC = 14V, VIN(-) = 10V,
VCA = 2.0V, VCR = Open, VCS = 1.0V, VST = 0V, VMB = 0V)
ICS4
0.76
1.02
1.26
µA
Stall Control Threshold Voltage (VCC = 14V, VIN(-) = 0V, VCA = VCR =
Open, VST = 0V) (24)
VCS1
1.95
2.06
2.45
V
Stall Control Saturation Voltage (VCC = 14V, VIN(-) = 0V,
VCA = VCR = VCS = Open, VST = 0V)
VCS2
20
35.3
165
mV
Adaptive Gain (VCC = 14V, VIN(-) = 11V, VST = 6.0V, VCA = Open, VCR =
3.0V, VCS = 3.0V, VD = 13V) (23)
STALL CAPACITOR
Notes
20. Open VCR (Ramp Capacitor) initially then force VCR = 3.9V and measure ICA1.
21.
22.
23.
Start Mode Adaptive Control sourcing current.
Start Mode Adaptive Control sink current.
Measure ICA. Calculate: AG = ICR1/ICA.
24.
Ramp VCS (Stall Capacitor) from 1.5 to 2.5V in 20 mV steps. Record VCS when ICS goes negative.
25.
Set VST = 10V, VCS = 1.0V, Fail if output is on. Set VCS = 3.0V, Fail if output in off.
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VD = VCC ≤ 16 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CR
22
24.4
28
%
VCR(hyh)
6.0
19.19
180
mV
RAMP CAPACITOR
Ramp Control Current Ratio (VCC = 14V, VIN(-) = 0V,
VCR = 3.0V, VST = 0V, VCA = VCS = Open) (26)
Ramp Capacitor Reset Hysteresis (VCC = 14V, VIN(-) = 10V,
VCA = 2.0V, VCS = 3.0V, VST = 6.0V) (27)
Notes
26. Set VCA (Adaptive Capacitor) to 0.5V, then open VCA. Set VCR (Ramp Capacitor) to 0.9V Percent ratio of CR UpCurrent as compared
to the CR Down Current; (ICR1/(ICR1-ICR2) x 100).
27.
Open VCR, Force VCR = 1.3V. Ramp VCR down in 30mV steps until ICR goes negative, VCR1. Ramp VCR up in 3.0mV steps, toggle input
between steps, until ICR goes positive, VCR2. VCR(hys)-VCR2 - Vcr1.
VMB
NC
1
16
2
15
NC
ICS
15.25kΩ
ICA
+
VCA
2.0V
VS
10Ω
3
14
4
13
5
12
6
11
7
10
VCS
3.0V
20Ω
+
ICR
+
VCR
3.0V
NC
200Ω
VO
VCL
IIN(-)
+
55Ω
5.0kΩ
VIN(-)
10V
+
27kΩ
+
VST
0V
IST
ID
250Ω
8
9
ICC
+
ICL
VD
13V
VCC
13V
Figure 4. Test Circuit
33094
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V ≤ VCC ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Negative Edge Filter, Falling Edge Time Constant (VCC = 16V, VIN(-) = 0V,
VCA = VCR = VCS = Open, VST = 10V (28)
t1
400
613.65
1000
µs
Propagation Delay Time (VCC = 14V, VIN(-) = 10V, VCA = VCS = Open,
VCR =3.0V, VST = 0V) (29)
t2
0
3.45
15
µs
tSDP
1.15
1.46
1.71
ms
tSDN
1.19
2.06
2.8
ms
tSOD
71
87
107
ms
tSSD
4.6
7.48
8.8
ms
tSST
13.6
20.9
26.5
ms
fSS
1.69
2.26
2.8
Hz
tBIT
25
66.65
200
ms
TIMING
Start Delay, Positive Edge (Data from ICA4, VCA1, VCA2) (30)
Start Delay, Negative Edge (Data from VCA4, ICA5, VCA2, t1)
Start to Output Disable Time
(31)
(32)
Stall to Spark Output Propagation Delay (Data from ICS3, VCS1, VCS2)
Stall Shutdown Time (Data from ICS2, VCS1, VCS2)
Stall Frequency
(33)
(34)
(35)
Battery Interrupt Time (VCC = VIN(-) = VST = 0V, VCA = VCR = Open,
VCS = 6.0V) (36)
Notes
28. Measure time until VO > 0.2V. The Negative Edge Filter prevents multiple output sparks caused by switching transients present at the
input by disabling the once used input for the filter time t.
29. Propagation delay time measurement of input to output response; Step change VIN(-) from 0 to 10V.
Measure the time required for VO < 1.5V
30.
tSDP = (VCA1 - VCA2) x CA/ICA4; CA = 0.1 µF
31.
tSDN = [(VCA1 - VCA2) x CA/ICA5]+t1; CA = 0.1 µF
32.
tSOD = (VCA1 - VCA2) x CS/ICA1; CS = 0.1 µF
33.
tSSD = (VCA1 - VCA2) x CS/ICA3; CS = 0.1 µF
34.
tSST = (VCA1 - VCA2) x CS/ICA2; CS = 0.1 µF
35.
fSS = 1/[(5.4/VIN(-)(TH)) + (4.3/ICS4) + (2/ICS2)] x CS; CS = 0.1 µF
36.
tBIT = [(VCS - 0.7V)/ICS1] x CS; CS = 0.1 µF
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
VIN(-)
Run Mode (37)
VOUT
VIN(-)
Start Mode (38)
VOUT
VIN(-)
VOUT
Stall Mode (39)
Figure 5. Basic Timing Diagrams
Notes
37. The falling edge of the VIN(-) signals is a charge command, while the rising edge signals a spark command.
38.
39.
During start mode. stall conditions are prevented.
During a stall, the coil is discharged slowly and a quick charge and spark occur on the next spark command.
9.0
8.0
VCC = 16V
VST = 10V
V
= 10V
ST
VCC = 14V
7.0
VCS = 1.0V
6.0
VCA = VCR = Open
5.0
4.0
3.0
-50
VCC = 6.0V
VST = 6.0V
0
50
100
T, Temperature (°C)
Figure 6. Input positive Threshold Voltage versus
Temperature
150
VIN(-)(+TH), Input Negative Threshold (V)
VIN(-)(+TH), Input Positive Threshold (V)
ELECTRICAL PERFORMANCE CURVES
7.0
V
CC
= 16V
6.0
5.0
V
4.0
V
= 1.0V
ST
=V
=V
= Open
CR
CS
CA
3.0
V
CC
2.0
-50
0
50
100
T, Temperature (°C)
= 6.0V
150
Figure 7. Input Negative Threshold Voltage versus
Temperature
33094
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
∆IO, Output Current Change (%)
3.2
3.0
VO from 10 to 22V
2.8
2.6
2.4
2.2
-50
0
50
100
150
T, Temperature (°C)
Figure 8. Output Current Change versus Temperature
ZCL, Output Clamp Dynamic Impedence (Ω)
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
50
VO = 0V
ICL = 12mA
∆ΙCL = 2.0mA
ZCL = ∆VCL/∆ΙCL
45
40
35
30
25
-50
0
50
100
150
T, Temperature (°C)
Figure 11. Output Clamp Dynamic Impedance versus
Temperature
160
120
VIN(-) = Open
VCC = 16V
Pin 6 = 10V
ZI = 10 V/IIN(-)
ICC, Supply Current (mA)
ZI, Input Impedence (kΩ)
8.7
140
100
80
60
40
-50
0
50
100
150
T, Temperature (°C)
Figure 9. Input Impedance versus Temperature
VIN(-) = 0V
VCC = 6.0V
VD = 3.0V
8.6
8.5
8.4
8.3
8.2
8.1
-50
0
50
100
T, Temperature (°C)
150
Figure 12. Supply Drain Current versus Temperature
VCL, Output Clamp Voltage (V)
15.2
15
14.8
VO - 0V
ICL = 10mA
14.6
14.4
14.2
14
-50
0
50
100
T, Temperature (°C)
150
Figure 10. Output Clamp Voltage versus Temperature
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The MC33094DW is designed for engine compartment
use in 12 V automotive ignition applications to provide high
performance control of the ignition coil when used with an
appropriate Freescale Power Darlington Transistor. Engine
control systems utilizing these devices for ignition coil control
exhibit superior fuel efficiency and lower exhaust emissions
over predecessor systems. The device is designed for single
input control from a Hall sensor to determine crankshaft
position.
The device, a bipolar linear integrated circuit, is built using
high–density Integrated–Injection Logic (IIL) processing
incorporating high current–gain PNP and NPN transistors. All
module inputs are transient voltage protected through the
use of resistors, capacitors, and/or zener diodes working in
conjunction with internal protection elements. These
elements provide protection of critical circuitry from externally
induced high–voltage transients which may degrade the
devices operational performance. At the module level, it is
recommended that the VCC pin of the device be transient
decoupled using an external resistor and capacitor to work in
conjunction with the on–chip internal zener string to provide
robust module protection of the device power pin. The D
(Distributor Signal) input of module should be protected from
transients through the use of an external resistor and zener
diode. The Start input (ST) of the module should be
decoupled through the use of two resistors and a capacitor to
work in conjunction with the on–chip internal clamp
(Figure 13).
The output of the device incorporates a high current–gain
PNP designed to drive an external power Darlington
transistor to provide control of the ignition coil. The output
drive is carefully synchronized with the output from the
distributor. The charging and discharging of three capacitors,
external to the device, provide timing signals which program
the dwell and charge time control of the ignition coil over a
wide rpm range.
The timing and charge/discharge rates of the three
external capacitors are accurately controlled by internal
circuitry acted upon by sensor and distributor signal detection
of the device.
A feedback path from the emitter of the external power
Darlington transistor to the device provide monitoring of the
ignition coil current. An internal comparator of the device
senses and limits the maximum ignition coil current to
approximately 6.5 amps. Other circuitry within the device
provides an interruption of the coil current so as to generate
the spark, or slowly discharges the coil in a controlled manner
so as to prevent a spark and limit the total module energy
dissipation.
When the external Darlington is switched off, the
Darlington collector will instantly experience a dramatic
increase in voltage as a result of the collapsing field of the
ignition coil (inductive kick). The external voltage divider
working in conjunction with the internal device zener string
and power PNP form a dynamic clamp which limits the
inductive kick voltage to less than 350 V. This feature
protects the Darlington transistor from damaging stress or
breakdown.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
BLOCK DIAGRAM DESCRIPTION (Figure 2)
The Band–Gap Reference generates a nominal 1.2V
having very good stability with temperature variations. The
Band–Gap Reference conceptually provides a low
temperature drift voltage by summing a strongly negative
Temperature Coefficient (TC) voltage with an equally strong
positive TC voltage. The negative TC voltage element is a
result of a transistor emitter–to–base voltage while the
positive TC voltage is developed as a result of a positive TC
current imposed across a resistor. The positive TC current
relies on the matching of currents in different sizes of
transistors. The result is a very stable reference voltage
independent of temperature variations. The Band–Gap
Reference voltage provides a thermally stable voltage
reference for critically sensitive circuits within the IC. It also
sets the master bias current for all precision currents on the
IC.
The VR Zener Reference block contains a 6.75 V zener
regulator, which also exhibits a very low temperature
coefficient.
The VCC Comparator and Clamp block limits the VCC
voltage to one VBE plus three zener drops in addition to
comparing the VCC voltage to 15 and 22V. When the VCC
voltage is greater than either of these two values, the IC
changes the adaptive capacitor discharge rate and when
above 22V the IC forces the coil current to shutdown. The
minimum VCC value the IC will operate at is 4.0V and VBAT of
5.0V. Below 7.5V, the VR reference is no longer maintained,
and the IC consumes excess power and excess voltage is
dropped in the external VCC resistor.
The Master Bias Current Reference block generates
precise currents used throughout the IC. The MB pin is held
at 1.2V by a differential amplifier with feedback. Capacitive
loading on the MB pin reduces the effectiveness of the
internal dominant pole, and loading as modest as 200pF may
cause the differential amplifier to oscillate.
33094
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The Input Voltage Comparator block requires an input
signal between ground and VBAT and detects the swing in the
input signal (VIN(-)). The thresholds for the input comparator
are approximately 56.2% of VBAT for rising signals and 36%
of VBAT for falling signals. The input signal may come from a
Hall effect sensor or reluctance sensor on the distributor.
The Negative Edge Filter block is an inverting buffer for the
signal from the Input Voltage Comparator and has a time
constant of approximately 0.1µs for rising edges and 500µs
for falling edges.
The Adaptive Capacitor Charging and Sensing block
charges, discharges, and senses the adaptive capacitor
voltage. The adaptive capacitor has a single charge rate of
8.4µA and two discharge rates. The 1.688µA slow discharge
rate is used only during very high VCC operation and
represents an effort to reduce excess dwell and therefore
power dissipation during high voltage operation. The 5.88µA
discharge rate is used under normal VCC operating
conditions. Under a start mode, this block will discharge the
adaptive capacitor forcing an enhanced start mode dwell.
The start/run modes are set internally by detecting the engine
frequency, which corresponds to the ramp capacitor voltage.
The Stall Capacitor Charging and Sensing block controls
the charging and discharging rates of the stall capacitor. The
charging rate is 31.5µA, and the two discharging rates are
1.0µA and 7.0µA. The stall capacitor potential commands the
IC to maintain or reduce the coil current. When the engine is
turning very slowly (or stalled), the stall capacitor will have
enough time to discharge below threshold and thereby
reduce coil current. The output current limiter forces the coil
current to be proportional to the stall capacitor voltage when
the stall capacitor voltage is less than 2.0V.
The Ramp Capacitor Charging and Sensing block charges
the ramp capacitor at approximately 8.4µA and discharges it
at about 33.6µA. The charging circuit is always on and
sources current during the “not 25%” part of the engine cycle.
The discharging circuit is only on and sinking current during
the “25%” part of the engine cycle. The positive edge of the
distributor input signal sets the 25% mode, and the ramp
comparator output clears this mode.
The CR > CA Adaptive Comparator block signals the point
where the ramp capacitor voltage is greater than the adaptive
capacitor voltage. The point at which the two capacitor
voltages are equal is the point where charging of the coil is
begun. The adaptive algorithm used in the IC maintains the
required excess dwell throughout all reasonable
accelerations and decelerations without causing excess coil
power dissipation, in addition, it insures that more than
adequate spark energy is available for very high engine
speeds, when excess dwell is impossible.
The Output Current Driver and Limiter block sources a
limited supply current of about 50mA to the base of the
Darlington power transistor. The Darlington will cause the coil
to conduct to about 6.5 amps and the voltage drop on the S
pin of the IC will rise to the threshold of the current limiter. The
current limiter will then hold the coil current at that level until
either a spark is commanded by the logic block, or the engine
begins to stall (causing the coil to slowly discharge).
The Internal Logic block performs the required memory
and gating functions on the IC to implement the adaptive
ignition control algorithm.
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION
IGNITION CIRCUIT OPERATION DESCRIPTION
When initially powered up, all module capacitors start
discharged (0V). The VCC capacitor will power up first, and
the IC’s internal logic latches are indeterminate. The following
conditions will hold: STALL = 1, because the stall capacitor
voltage is less than 2.0 V; 25% = 0, because the ramp
capacitor is less than the Band Gap Reference voltage (VBG);
and ICOIL = 0 amps, because the stall capacitor is at 0V.
Because 25% = 0, the ramp capacitor charges towards Vr.
At cranking frequencies, the ramp capacitor always exceeds
the start mode threshold at the input (ZC or VIN-1), and
therefore the stall signal resets the start mode latch upon the
first ac signal (this causes the adaptive capacitor to be
discharged). With the adaptive capacitor held low, very high
rates of acceleration are possible. If the adaptive capacitor
were allowed to adapt the dwell at low frequencies, severe
limitations to engine acceleration would occur.
See Figure 15. At point A, a spark from the previous cycle
occurs as the field around the coil collapses rapidly. At the
same time ZC (VIN- > 10V) will set the 25% clock signal which
commands the adaptive and ramp capacitors to discharge
and the stall capacitor to charge. At point B, as the ramp
capacitor voltage crosses the 1.2V (VBG) level, the 25% clock
is cleared and the polarities and amplitude of the ramp and
stall capacitor currents change to their appropriate levels. At
this point the adaptive capacitor is discharged and begins to
float. At point C, the coil turns on and ramps until the coil
current is limited to 6.5 amps. The adaptive capacitor, at point
D, remains discharged and the dwell is maximized to 6.5
amps because the start/run latch has yet to be set. At point
E, ZC (VIN- > 10V, ZC = high) turns the coil off causing a
spark to occur and at which point a new cycle begins. As the
engine frequency increases, the peak voltage on the ramp
capacitor at the ac signal will fall below the start mode enable
threshold level. The start mode enable detector then sets the
start/run latch to the run mode (CADUMP = 0) by clocking a
zero into the start/run latch at the zero cross. At this time the
adaptive algorithm is evoked and the adaptive capacitor is
allowed to charge and discharge according to it’s other logical
inputs. After normal run mode operation is entered, the start
mode may not be reentered even though the ramp capacitor
voltage again exceeds the start mode enable threshold. A
start mode may only be evoked by a STALL signal transition
from logic 1 to 0. The STALL signal transition occurs at a VINfrequency of approximately 2.0 Hz.
The IC and circuit provides for other than normal starting
procedures such as push starting the engine. Since the stall
capacitor will be discharged in this low frequency mode, the
IC will provide a spark timing with a maximum retardation of
about 6.5ms.
After the start mode operation is exited, the normal
operation algorithm is entered and a different sequence of
events dominate the IC’s performance. See Figures 16, 17,
and 18. At point A, the spark from the previous cycle occurs
and the 25% part of the cycle begins. During this part of the
cycle, the stall capacitor will charge and the ramp and
adaptive capacitors will discharge. At point B, the “not 25%”
part of the cycle, also called the 75% part of the cycle, begins.
The stall capacitor discharges, while the ramp capacitor
charges. During this part of the cycle the adaptive capacitor
floats. At point C, the ramp capacitor voltage equals the
voltage on the adaptive capacitor. At this time, the coil turns
on and the coil current ramps to the point where it is limited.
When the coil current reaches the limit, point D, the adaptive
capacitor begins to charge, until zero cross
(ZC = 1logic(high)), point E. This turns the coil off and
induces a spark. The 75% part of the cycle lasts until point E,
at which time the cycle begins again.
The adaptive dwell algorithm causes the engine to
maintain a fixed percent of excess dwell time (if possible).
The mechanism that permits this involves the floating nature
of the adaptive capacitor. During engine deceleration, the
initial coil turn–on might occur early, but the next coil turn–on
will be retarded to it’s correct location due to the % adjusted
adaptive capacitor charge time. During acceleration, the coil
may not charge up as early as desired the first time, however,
the spark will still be correctly slaved to the distributor. The
side effect of this is that the adaptive capacitor will not receive
as much charge time for that cycle and will have a lower
average value the next cycle, thus starting the coil charging
sooner, as can be seen in Figure 17. In this figure, the output
voltage rises before the adaptive capacitor charge signal
occurs.
See Figure 13. In the Stall mode the output is slaved by the
stall capacitor. The stall capacitor can discharge completely,
but starting at point X it charges during the 25% of the engine
cycle (duration of when ZC is logic high = 1). At the same time
a spark from the previous cycle occurs. The DWELL signal
will be high as long as the engine is in stall, but falls gradually
preventing a spark at point Y when the STALL goes low
starting at 2.4V. The coil will be slaved to the stall capacitor,
and at point Z the coil will charge to 6.5 amps as the stall
capacitor charges to 2.0V. At that time the STALL comparator
will trip (STALL = 0) and the DWELL signal will fall, triggering
a reduced spark with some retardation (6.5ms). At this point
a new cycle begins.
33094
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
Each of the three different modes (Stall, Start, and Run)
have their own differences. The Stall capacitor controls the
output in the stall mode, however is disabled in both the start
and run modes. The output is clamped longer in the start
mode as compared to the run mode due to the more energy/
current in the coil causing a longer/bigger spark.
Other less likely operating sequences are possible. For
example, there is a possibility of VCC exceeding 15V during
engine operation (High battery = logic 1). Above about 17V
on VBAT, the excess current limit percentage falls to 5% to
conserve IC and circuit power dissipation. Above 25V,
current to the coil is disabled. Care was placed in this design
to account for all possible operating modes.
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
+VOUT
Ignition
330
55
15.3k
0.1µ
2
MB 6
G
9
18V
VCC
4.0k
Band-Gap
Reference
VCC Clamp and
Zener Ref.
Master
Bias
10
200
D
VIN(-)
10k
7
Input
Comp. and
Negative
Edge Filter
VIN(-)
SW
27k
0.1µ
Output Current
Driver and Limiter
Internal
Logic
CL
12
O
8
ST
200
14
CR > CA
Comparator
13
T
BU931,
MJE5742
or
MJH10012
11
S
Adaptive
Capacitor
3
CA
0.1µ
Ramp
Capacitor
4
CR
0.1µ
Stall
Capacitor
15
CS
56
0.05
5.0W
0.1µ
Figure 13. Typical Ignition Circuit Application
INTRODUCTION
The MC33094 is designed for engine compartment use in
12V automotive ignition applications to provide high
performance control of the ignition coil when used with an
appropriate Motorola Power Darlington Transistor. Engine
control systems utilizing these devices for ignition coil control
exhibit superior fuel efficiency and lower exhaust emissions
over predecessor systems. The device is designed for single
input control from a Hall sensor to determine crankshaft
position.
The device, a bipolar linear integrated circuit, is built using
high–density Integrated–Injection Logic (IIL) processing
incorporating high current–gain PNP and NPN transistors. All
module inputs are transient voltage protected through the
use of resistors, capacitors, and/or zener diodes working in
conjunction with internal protection elements. These
elements provide protection of critical circuitry from externally
induced high–voltage transients which may degrade the
devices operational performance. At the module level, it is
recommended the VCC pin of the device be transient
decoupled using an external resistor and capacitor to work in
conjunction with the on–chip internal zener string to provide
robust module protection of the device power pin. The D
(Distributor input) input of module should be protected from
transients through the use of an external resistor and zener
diode. The Start input of the module should be decoupled
through the use of two resistors and a capacitor to work in
conjunction with the on–chip internal clamp (Figure 13).
The output of the device incorporates a high current–gain
PNP designed to drive an external power Darlington
transistor to provide control of the ignition coil. The output
drive is carefully synchronized with the output from the
distributor. The charging and discharging of three capacitors,
external to the device, provide timing signals which program
the dwell and charge time control of the ignition coil over a
wide RPM range.
The timing and charge/discharge rates of the three
external capacitors are accurately controlled by internal
circuitry acted upon by sensor and distributor signal detection
of the device.
A feedback path from the emitter of the external power
Darlington transistor to the device provide monitoring of the
33094
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
ignition coil current. An internal comparator of the device
senses and limits the maximum ignition coil current to
approximately 6.5 amps. Other circuitry within the device
provides an interruption of the coil current so as to generate
the spark, or slowly discharges the coil in a controlled manner
so as to prevent a spark and limit the total module energy
dissipation.
When the external Darlington is switched off, the
Darlington collector will instantly experience a dramatic
increase in voltage as a result of the collapsing field of the
ignition coil (inductive kick). The external voltage divider
working in conjunction with the internal device zener string
and power PNP form a dynamic clamp which limits the
inductive kick voltage to less than 350V. This feature protects
the Darlington transistor from damaging stress or breakdown.
IGNITION CIRCUIT OPERATION DESCRIPTION
capacitor will be discharged in this low frequency mode, the
IC will provide a spark timing with a maximum retardation of
about 6.5 ms.
After the start mode operation is exited, the normal
operation algorithm is entered and a different sequence of
events dominate the IC’s performance. See Figures 16,
Figures 17 and Figures 18. At point A, the spark from the
previous cycle occurs and the 25% part of the cycle begins.
During this part of the cycle, the stall capacitor will charge and
the ramp and adaptive capacitors will discharge. At point B,
the “not 25%” part of the cycle, also called the 75% part of the
cycle, begins. The stall capacitor discharges, while the ramp
capacitor charges. During this part of the cycle the adaptive
capacitor floats. At point C, the ramp capacitor voltage equals
the voltage on the adaptive capacitor. At this time, the coil
turns on and the coil current ramps to the point where it is
limited. When the coil current reaches the limit, point D, the
adaptive capacitor begins to charge, until zero cross (ZC =
1logic(high)), point E. This turns the coil off and induces a
spark. The 75% part of the cycle lasts until point E, at which
time the cycle begins again.
The adaptive dwell algorithm causes the engine to
maintain a fixed percent of excess dwell time (if possible).
The mechanism that permits this involves the floating nature
of the adaptive capacitor. During engine deceleration, the
initial coil turn–on might occur early, but the next coil turn–on
will be retarded to it’s correct location due to the % adjusted
adaptive capacitor charge time. During acceleration, the coil
may not charge up as early as desired the first time, however,
the spark will still be correctly slaved to the distributor. The
side effect of this is that the adaptive capacitor will not receive
as much charge time for that cycle and will have a lower
average value the next cycle, thus starting the coil charging
sooner, as can be seen in Figure 18. In this figure, the output
voltage rises before the adaptive capacitor charge signal
occurs.
See Figure 14. In the Stall mode the output is slaved by the
stall capacitor. The stall capacitor can discharge completely,
but starting at point X it charges during the 25% of the engine
cycle (duration of when ZC is logic high = 1). At the same time
a spark from the previous cycle occurs. The DWELL signal
will be high as long as the engine is in stall, but falls gradually
preventing a spark at point Y when the STALL goes low
starting at 2.4V. The coil will be slaved to the stall capacitor,
and at point Z the coil will charge to 6.5 amps as the stall
capacitor charges to 2.0V. At that time the STALL comparator
will trip (STALL = 0) and the DWELL signal will fall, triggering
When initially powered up, all module capacitors start
discharged (0V). The VCC capacitor will power up first, and
the IC’s internal logic latches are indeterminate. The following
conditions will hold: STALL = 1, because the stall capacitor
voltage is less than 2.0 V; 25% = 0, because the ramp
capacitor is less than the Band Gap Reference voltage (VBG);
and ICOIL = 0 amps, because the stall capacitor is at 0V.
Because 25% = 0, the ramp capacitor charges towards
VR. At cranking frequencies, the ramp capacitor always
exceeds the start mode threshold at the input (ZC), and
therefore the stall signal resets the start mode latch upon the
first ac signal (this causes the adaptive capacitor to be
discharged). With the adaptive capacitor held low, very high
rates of acceleration are possible. If the adaptive capacitor
were allowed to adapt the dwell at low frequencies, severe
limitations to engine acceleration would occur.
See Figure 14. At point A, a spark from the previous cycle
occurs as the field around the coil collapses rapidly. At the
same time ZC (ZC (input) = high(1)) will set the 25% clock
signal which commands the adaptive and ramp capacitors to
discharge and the stall capacitor to charge. At point B, as the
ramp capacitor voltage crosses the 1.2V (VBG) level, the 25%
clock is cleared and the polarities and amplitude of the ramp
and stall capacitor currents change to their appropriate
levels. At this point the adaptive capacitor is discharged and
begins to float. At point C, the coil turns on and ramps until
the coil current is limited to 6.5 amps. The adaptive capacitor,
at point D, remains discharged and the dwell is maximized to
6.5 amps because the start/run latch has yet to be set. At
point E, ZC (ZC = high) turns the coil off causing a spark to
occur and at which point a new cycle begins. As the engine
frequency increases, the peak voltage on the ramp capacitor
at the ac signal will fall below the start mode enable threshold
level. The start mode enable detector then sets the start/run
latch to the run mode (CADUMP = 0) by clocking a zero into
the start/run latch at the zero cross. At this time the adaptive
algorithm is evoked and the adaptive capacitor is allowed to
charge and discharge according to it’s other logical inputs.
After normal run mode operation is entered, the start mode
may not be reentered even though the ramp capacitor
voltage again exceeds the start mode enable threshold. A
start mode may only be evoked by a STALL signal transition
from logic 1 to 0. The STALL signal transition occurs at a ZC
frequency of approximately 2.0 Hz.
The IC and circuit provides for other than normal starting
procedures such as push starting the engine. Since the stall
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
TYPICAL APPLICATIONS
a reduced spark with some retardation (6.5 ms). At this point
a new cycle begins.
Each of the three different modes (Stall, Start, and Run)
have their own differences. The Stall capacitor controls the
output in the stall mode, however is disabled in both the start
and run modes. The output is clamped longer in the start
mode as compared to the run mode due to the more energy/
current in the coil causing a longer/bigger spark.
Other less likely operating sequences are possible. For
example, there is a possibility of VCC exceeding 15V during
engine operation (High battery = logic 1). Above about 17V
on Vbat, the excess current limit percentage falls to 5% to
conserve IC and circuit power dissipation. Above 25V,
current to the coil is disabled. Care was placed in this design
to account for all possible operating modes.
33094
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
Engine Cycle
11.68V
VIN(-)
(Pin 7)
(ZC)
1.08V
0V
1.7V
Gradual
Fall
VOUT
(Pin 12)
300mV
0V
6.78V
6.09V
VCA
(Pin 3)
4.9V
6.8V
VCR
(Pin 4)
1.2V
6.56V
VCS
(Pin 15)
2.4V
2.0V
80mV
X
Y
Linear
Charge
Z
Figure 14. Stall Mode 60 RPM (Frequency: 2.0 Hz @ 100 ms)
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
TYPICAL APPLICATIONS
11.68V
VIN(-)
(Pin 7)
(ZC)
1.12V
0V
1.8V
1.36V
VOUT
(Pin 12)
0V
5.9V
VCA
Floats
VCA
(Pin 3)
4.3V
VCA = VCR
6.1V
VCR
(Pin 4)
1.1V
6.5V
VCS
(Pin 15)
5.1V
A
B
CD
E
Figure 15. Start Mode 300 RPM (Frequency: 10 Hz @ 20 ms)
11.68V
VIN(-)
(Pin 7)
(ZC)
1.8V
0V
1.86V
1.34V
VOUT
(Pin 12)
0V
2.2V
VCA
(Pin 3)
2.18V
2.98V
VCR
(Pin 4)
1.1V
6.4V
VCS
(Pin 15)
5.82V
A
B
25%
Cycle
C D E
75%
Cycle
Figure 16. Run Mode 900 RPM (Frequency: 30 Hz @10 ms)
33094
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
11.68V
VIN(-)
(Pin 7)
(ZC)
1.8V
0V
1.84V
VOUT
(Pin 12)
1.36V
0V
1.724V
VCA
(Pin 3)
1.5V
1.46V
2.0V
VCA = VCR
VCR
(Pin 4)
1.08V
6.42V
6.36V
VCS
(Pin 15)
6.06V
A
B
C
D
E
Figure 17. Run Mode 2000 RPM (Frequency: 66.67 Hz @ 5.0 ms)
12.2V
VIN(-)
(Pin 7)
(ZC)
1.8V
0V
1.86V
VOUT
(Pin 12)
0V
1.31V
VCA
(Pin 3)
VCA = VCR
VCR
(Pin 4)
1.17V
1.13V
1.48V
1.12V
6.53V
6.51V
VCS
(Pin 15)
6.46V
A
B
C
D
E
Figure 18. Run Mode 5000 RPM (Frequency: 166.67 Hz @ 2.0 ms)
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
DW SUFFIX
EG SUFFIX (PB-FREE)
16-PIN
PLASTIC PACKAGE
98ASB42567B
ISSUE F
33094
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
1.0
DATE
10/2006
DESCRIPTION OF CHANGES
•
•
•
•
•
Initial Release
Converted to Freescale format
Added MCZ33094EG/R2 to the Ordering Information
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 4.
Added note Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC
standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels
(MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter
the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on
page 4
33094
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
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Japan:
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For Literature Requests Only:
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1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
MC33094
Rev. 1.0
10/2006
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