MCZ33975AEKR2

Freescale Semiconductor Technical Data Document Number: MC33975 Rev 11.0, 01/2014 Multiple Switch Detection Interface with Suppressed Wake-up and 32 mA Wetting Current 33975 33975A MULTIPLE SWITCH DETECTION INTERFACE WITH SUPPRESSED WAKE-UP The 33975 Multiple Switch Detection Interface with Suppressed Wakeup is designed to detect the closing and opening of up to 22 switch contacts. The switch status, either open or closed, is transferred to the microprocessor unit (MCU) through a serial peripheral interface (SPI). The device also features a 22-to-1 analog multiplexer for reading inputs as analog. The 33975 device has two modes of operation, Normal and Sleep. Normal mode allows programming of the device and supplies switch contacts with pull-up or pull-down current as it monitors the switch change of state. The Sleep mode provides low quiescent current, which makes the 33975 ideal for automotive and industrial products requiring low sleep state currents. Improvements are a programmable interrupt timer for Sleep mode that can be disabled, switch detection currents of 32 mA and 4.0 mA for switch-to-ground inputs, and an interrupt bit that can be reset. This device is powered using SMARTMOS technology. Features Designed to operate from 5.5 V  VPWR  28 V Switch input voltage: (33975: -14 to 38 V) (33975A: -14 to 40 V) Interfaces to microprocessor using 3.3 V/5.0 V SPI protocol Selectable wake-up on change of state 14 switch-to-ground inputs 8 programmable inputs (switches to battery or ground) Selectable wetting current (32 mA or 4.0 mA for switch-to-ground inputs) • Sleep State current VPWR 100 A, VDD 20 A • • • • • • • EK SUFFIX (PB-FREE) 98ASA10556D 32-PIN SOICW EP Applications • Automotive systems • Industrial control systems • Process control systems • Security systems • Systems requiring switch status verification for safety, operation, or process control purposes VDD POWER SUPPLY LVI VBAT VBAT 33975 SP0 SP1 VBAT VPWR VDD ENABLE VDD SP7 WAKE SG0 SG1 SG12 SG13 SI SCLK CS SO INT AMUX MCU MOSI SCLK CS MISO INT AN0 WATCHDOG RESET GND Figure 1. 33975 Simplified Application Diagram © Freescale Semiconductor, Inc., 2005 - 2014. All rights reserved. 1 Orderable Parts Table 1. Orderable Part Variations Part Number MC33975TEK/R2 MC33975ATEK/R2 Temperature (TA) Package -40 to 125 °C 32 SOICW-EP Switch Input Voltage Range Reference Location -14 to 38 VDC 5 -14 to 40 VDC 5 33975 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM 5.0 V VPWR VPWR VPWR SP0 32.0 mA 4.0 mA 16.0 mA To + 2.0 4.0 V ‚ SPI mA Ref Comparator POR Bandgap Sleep PWR SP0 SP1 SP2 VPWR VDD GND VPWR, VDD, 5.0V SP3 SP4 SP5 SP6 VPWR VPWR 32.0 mA SP7 4.0 mA 5.0 V Oscillator and Clock Control SP7 16.0 mA To + 2.0 4.0 V ‚ SPI mA Ref Comparator VPWR VPWR 32.0 mA SG0 4.0 mA VPWR 5.0 V 5.0 V Temperature Monitor and Control 5.0 V 125 k VPWR 5.0 V SG0 To 4.0 V ‚+ SPI Ref Comparator SG1 SG2 SG3 WAKE WAKE Control VDD SPI Interface and Control SG4 125 k INT SG5 INT Control SG6 VDD SG7 MUX Interface SG8 40 A CS SG9 SCLK VDD SI SG10 SG11 SG12 VPWR VPWR 32.0 mA SO SG13 4.0 mA SG13 To 4.0 V ‚+ SPI Ref Comparator + VDD ‚ Analog Mux Output AMUX Figure 2. 33975 Simplified Internal Block Diagram 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS GND SI SCLK CS SP0 SP1 SP2 SP3 SG0 SG1 SG2 SG3 SG4 SG5 SG6 VPWR 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 SO VDD AMUX INT SP7 SP6 SP5 SP4 SG7 SG8 SG9 SG10 SG11 SG12 SG13 WAKE Figure 3. 33975 Pin Connections Table 2. Pin Definitions A functional description of each Pin can be found in the Functional Pin Description section on page 12. Pin Pin Name Formal Name Description 1 GND Ground 2 SI SPI Slave In SPI control data input pin from MCU to 33975 3 SCLK Serial Clock SPI control clock input pin 4 CS Chip Select SPI control chip select input pin from MCU to 33975. Logic [0] allows data to be transferred in 5–8 25–28 SPn Programmable Switches 0–3 Programmable Switches 4–7 Programmable switch-to-battery or switch-to-ground input pins 9–15, 18–24 SGn Switch-to-Ground Inputs 0–6 Switch-to-Ground Inputs 13–7 Switch-to-ground input pins 16 VPWR Battery Input Battery supply input pin. This pin requires external reverse battery protection. 17 WAKE Wake-up Open drain wake-up output is designed to control a power supply enable pin 29 INT Interrupt Open-drain output to MCU is used to indicate input switch change of state 30 AMUX Analog Multiplex Output 31 VDD Voltage Drain Supply 32 SO SPI Slave Out Ground for logic, analog, and switch-to-battery inputs Analog multiplex output 3.3/5.0 V supply sets SPI communication level for the SO driver Provides digital data from 33975 to the MCU 33975 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these limits may cause malfunction or permanent damage to the device. Rating Symbol Value Unit VDD Supply Voltage – -0.3 to 7.0 VDC CS, SI, SO, SCLK, INT, AMUX – -0.3 to 7.0 VDC WAKE – -0.3 to 40 VDC VPWR Supply Voltage – -0.3 to 50 VDC VPWR Supply Voltage at -40 C – -0.3 to 45 VDC Switch Input Voltage Range – ELECTRICAL RATINGS VDC 33975 -14 to 38 33975A -14 to 40 Frequency of SPI Operation (VDD = 5.0 V) – 6.0 VESD ±2000 ESD Voltage(1) MHz V Human Body Model(2) ±2000 Applies to all non-input Pins ±200 Machine Model Charge Device Model Corner Pins 750 Interior Pins 500 THERMAL RATINGS C Operating Temperature Ambient TA -40 to 125 Junction TJ -40 to 150 TC -40 to 125 TSTG -55 to 150 C PD 1.7 W Case Storage Temperature Power Dissipation (3) Notes 1. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model. 2. 3. All Programmable Switches (SP) and Switch-to-Ground (SG) input pins when tested individually. Maximum power dissipation at TJ =150 C junction temperature with no heatsink used. 4. Thermal resistance between the die and the exposed die pad. 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these limits may cause malfunction or permanent damage to the device. Rating Symbol Value Junction to Ambient RJA 71 Between the die and the exposed die pad(4) RJC 1.2 TPPRT Note 6 Unit ELECTRICAL RATINGS C/W Thermal Resistance Peak Package Reflow Temperature During Reflow(5), (6) °C Notes 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33975 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 8.0 V  VPWR  28 V, -40 C  TC  125 C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C. Characteristic Symbol Min Typ Max VPWR(QF) VPWR(FO) VPWR(QF) 5.5 – 8.0 8.0 – 28 28 – 38/40 Unit POWER INPUT Supply Voltage V Supply Voltage Range Quasi-functional(7) Fully Operational Supply Voltage Range Quasi-functional (8) Supply Voltage VPWR(POR) VPWR Supply Voltage Power On Reset Supply Current V 4.2 4.6 5.0 – 4.0 8.0 40 70 100 3.0 – 5.5 – 0.25 0.5 – 10 20 12 15 18 7.0 24 9.0 32 – 36 1.8 2.1 2.4 0.5 1.0 – 3.6 4.0 4.4 – 2.0 5.0 IPWR(ON) All Switches Open, Normal Mode, Tri-state Disabled Sleep State Supply Current mA A IPWR(SS) Scan Timer = 64 ms, Switches Open Logic Supply Voltage VDD Logic Supply Current IDD All Switches Open, Normal Mode Sleep State Logic Supply Current mA A IDD(SS) Scan Timer = 64 ms, Switches Open V SWITCH INPUT Pulse Wetting Current Switch-to-Battery (Current Sink) IPULSE 5.5 V  VPWR  28 V Pulse Wetting Current Switch-to-Ground (Current Source) IPULSE 5.5 V  VPWR  8.0 V 8.0 V  VPWR  28 V Sustain Current Switch-to-Battery Input (Current Sink) ISUS(MAX) - ISUS(MIN) ISUS(MIN) X 100 mA ISUSTAIN 5.5 V  VPWR  8.0 V 8.0 V  VPWR  28 V Sustain Current Matching Between Channels on Switch-to-Ground Inputs mA ISUSTAIN 5.5 V  VPWR  28 V Sustain Current Switch-to-Ground Input (Current Source) mA mA IMATCH % Notes 7. Device operational. Wetting and sustain currents are reduced. Operating the analog multiplexer below 8.0 V is not recommended. 8. Thermal considerations must be taken when operating the device above 28 V. 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 8.0 VCharacteristics  VPWR  28 V, noted -40 C under  TCconditions  125 C,ofunless 3.0 V otherwise  VDD  5.5 V, 8.0 V  VPW noted. Where applicable, typical values = 13 reflect V, TA =the 25parameter’s C. approxima noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR Characteristic SWITCH INPUT (CONTINUED) Symbol IOFFSET Input Offset Voltage when Selected as Analog VOFFSET V(SP&SGINPUTS) to AMUX output Max Unit -2.0 1.4 2.0 A -10 2.5 10 – 10 30 mV VOL Sink 250 A Analog Operational Amplifier Output Voltage Characteristic Typ DIGITAL INTERFACE Input Offset Current when Selected as Analog Analog Operational Amplifier Output Voltage Min mV VOH Source 250 A V VDD - 0.1 – – Switch Detection Threshold VTH 3.70 4.0 4.3 V (9), (10) TLIM 155 – 185 C TLIM(HYS) 5.0 10 15 C Temperature Monitor Temperature Monitor Hysteresis(10) Notes 9. Thermal shutdown of 16mA and 32mA pull-up and pull-down current sources only. 4.0mA and 2.0mA current source/sink and all other functions remain active. 10. This parameter is guaranteed by design; however it is not production tested. 33975 8 Analog Integrated Circuit Device Data Freescale Semiconductor Sym ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions of 3.0 V  VDD  5.5 V, 8.0 V  VPWR  28 V, -40 C  TC  125 C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C. Characteristic Symbol Min Typ Max Unit Thresholds(11) VIH 0.7 x VDD – VDD + 0.3 V Input Logic Low Voltage Thresholds(11) VIL GND - 0.3 – 0.2 x VDD V Input Logic High Voltage SCLK, SI, Tri-state SO Input Current ISCLK, ISI, ISO(TRI) 0.0 V to VDD CS Input Current A -10 – 10 A ICS CS = VDD CS Pull-up Current -10 – 10 30 – 100 VDD - 0.8 – VDD A ICS CS = 0.0 V SO High State Output Voltage VSO(HIGH) I SO(HIGH) = -200 A SO Low State Output Voltage V VSO(LOW) I SO(HIGH) = 1.6 mA Input Capacitance on SCLK, SI, Tri-state SO(12) – – 0.4 CIN – – 20 pF – 15 40 100 A INT Internal Pull-up Current INT Voltage V V INT(HIGH) INT = Open Circuit INT Voltage V VDD - 0.5 – VDD – 0.2 0.4 20 40 100 4.0 4.3 5.3 V INT(LOW) I INT = 1.0 mA WAKE Internal Pull-Up current I WAKE(PU) WAKE Voltage V V WAKE (HIGH) WAKE = Open Circuit WAKE Voltage V V WAKE(LOW) I WAKE = 1.0 mA V – WAKE Voltage(12) 0.2 0.4 V WAKE(MAX) Maximum Voltage Applied to WAKE Through External Pull-up A V – – 40 Notes 11. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK. 12. This parameter is guaranteed by design however, is not production tested. DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions of 3.0V  VDD  5.5V, 8.0V  VPWR  28V, -40C  TC  125C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25C. Characteristic Symbol Min Typ Max Unit SWITCH INPUT 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions of 3.0V  VDD  5.5V, 8.0V  VPWR  28V, -40C  TC  125C, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25C. Characteristic Symbol Min Typ Max Unit t PULSE (ON) 15 16 22 ms – 5.0 16 100 200 300 – – 10 – – 10 – – 10 100 – – 50 – – 16 – – 20 – – t R (SI) – 5.0 – ns t F (SI) – 5.0 – ns Time from Falling Edge of CS to SO Low Impedance(16) t SO(EN) – – 55 ns Impedance(17) t SO(DIS) – – 55 ns t VALID – 25 55 ns Pulse Wetting Current Time Interrupt Delay Time s t INT-DLY Normal Mode Sleep Mode Switch Scan Time t SCAN Calibrated Scan Timer Accuracy t SCAN TIMER Sleep Mode Calibrated Interrupt Timer Accuracy % t INT TIMER Sleep Mode s % DIGITAL INTERFACE TIMING(13) Required Low State Duration on VPWR for Reset(14) Falling Edge of CS to Rising Edge of SCLK t LEAD Required Setup Time Falling Edge of SCLK to Rising Edge of CS Falling Edge of SCLK to SI SI, CS, SCLK Signal Rise Time(15) Time(15) Time from Rising Edge of SCLK to SO Data Valid(18) Notes 13. 14. 15. 16. 17. 18. ns t SI(HOLD) Required Hold Time Time from Rising Edge of CS to SO High ns t SI(SU) Required Setup Time SI, CS, SCLK Signal Fall ns t LAG Required Setup Time SI to Falling Edge of SCLK s t RESET VPWR  0.2V ns These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0V SPI interface. This parameter is guaranteed by design but not production tested. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on the SO pin. Time required for output states data to be terminated at the SO pin. Time required to obtain valid data out from SO following the rise of SCLK with a 200pF load. 33975 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CS 0.2 VDD tLEAD tLAG 0.7 VDD 0.2 VDD SCLK tSI(SU) tSI(HOLD) 0.7 VDD 0.2 VDD SI MSB in tSO(EN) tVALID 0.7 VDD 0.2 VDD SO tSO(DIS) MSB out LSB out Figure 4. SPI Timing Characteristics VPWR VDD WAKE Wake-Up From Interrupt Timer Expire INT CS Wake-Up From Closed Switch SGn Power-Up Normal Mode Tri-State Command Sleep Command Sleep Mode (Disable Tri-State) Normal Mode Sleep Command Sleep Mode Normal Mode Sleep Command Figure 5. Sleep Mode to Normal Mode Operation INT CS Switch state change with Switch state change with CS low generates INT CS low generates INT Latch switch status on falling edge of CS Rising edge of CS does not clear INT because state change occurred while CS was low SGn Switch open ‚Äö Switch closed ‚Äö SGn Bit in SPI Word 1 Switch Status Command 0 Switch Status Command 0 Switch Status Command 1 Switch Status Command 1 Switch Status Command 0 Switch Status Command Figure 6. Normal Mode Interrupt Operation 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DESCRIPTIONS INTRODUCTION FUNCTIONAL DESCRIPTIONS INTRODUCTION The 33975 device is an integrated circuit designed to provide systems with ultra-low quiescent sleep/wake-up modes and a robust interface between switch contacts and a microprocessor. The 33975 replaces many of the discrete components required when interfacing to microprocessorbased systems while providing switch ground offset protection, contact wetting current, and system wake-up. The 33975 features 8-programmable switch-to-ground or switch-to-battery inputs and 14 switch-to-ground inputs. All switch inputs may be read as analog inputs through the analog multiplexer (AMUX). Other features include a programmable wake-up timer, programmable interrupt timer, programmable wake-up/interrupt bits, and programmable wetting current settings. This device is designed primarily for automotive applications but may be used in a variety of other applications such as computer, telecommunications, and industrial controls. FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS) SERIAL INPUT (SI) The system MCU selects the 33975 to receive communication using the chip select (CS) pin. With CS in a logic low state, command words may be sent to the 33975 via the serial input (SI) pin, and switch status information can be received by the MCU via the serial output (SO) pin. The falling edge of CS enables the SO output, latches the state of the INT pin, and the state of the external switch inputs. Rising edge of the CS initiates the following sequence: The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CS signal. To program a complete word, 24 bits of information must be entered into the device. 1. Disables the SO driver (high-impedance) 2. INT pin is reset to logic [1], except when additional switch changes occur during CS low (see Figure 6, page 11). 3. Activates the received command word, allowing the 33975 to act upon new data from switch inputs. To avoid any spurious data, it is essential the high-to-low and low-to-high transitions of the CS signal occur only when SCLK is in a logic low state. A clean CS signal is needed to ensure no incomplete SPI words are sent to the device. Internal to the 33975 device is an active pull-up to VDD on CS. In Sleep Mode the negative edge of CS (VDD applied) will wake up the 33975 device. Data received from the device during CS wake-up may not be accurate. SERIAL CLOCK (SCLK) The system clock (SCLK) pin clocks the internal shift register of the 33975. The SI data is latched into the input shift register on the falling edge of SCLK signal. The SO pin shifts the switch status bits out on the rising edge of SCLK. The SO data is available for the MCU to read on the falling edge of SCLK. False clocking of the shift register must be avoided to ensure validity of data. It is essential the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended, though not necessary, that the SCLK pin is commanded to a low logic state as long as the device is not accessed and CS is in a logic high state. When the CS is in a logic high state, any signal on the SCLK and SI pin will be ignored and the SO pin is tri-state. SERIAL OUTPUT (SO) The SO pin is the output from the shift register. The SO pin remains tri-stated until the CS pin transitions to a logic low state. All open switches are reported as a zero, all closed switches are reported as a one. The negative transition of CS enables the SO driver. The first positive transition of SCLK will make the status data bit 24 available on the SO pin. Each successive positive clock will make the next status data bit available for the MCU to read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. INTERRUPT OUTPUT (INT) The INT pin is an interrupt output from the 33975 device. The INT pin is an open-drain output with an internal pull-up to VDD. In Normal mode, a switch state change will trigger the INT pin (when enabled). The INT pin is latched on the falling edge of CS, and cleared on the rising edge of CS. The INT pin will not clear with rising edge of CS if a switch contact change has occurred while the CS was low. In a multiple 33975 device system with WAKE high and VDD in (Sleep mode), the falling edge of INT will place all 33975s in Normal mode. WAKE INPUT (WAKE) The WAKE pin is an open-drain output and a wake-up input. The pin is designed to control a power supply Enable pin. In the Normal mode, the WAKE pin is low. In the Sleep mode, the WAKE pin is high. The WAKE pin has a pull-up to the internal +5.0 V supply. 33975 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTIONS FUNCTIONAL PIN DESCRIPTION In Sleep mode with the WAKE pin high, the falling edge of WAKE will place the 33975 in Normal mode. In Sleep mode with VDD applied, the INT pin must be high for a negative edge of WAKE to wake up the device. If VDD is not applied to the device in Sleep mode, INT does not affect the WAKE operation. LOAD SUPPLY VOLTAGE (VPWR) The VPWR pin is battery input and Power-ON Reset to the 33975 IC. The VPWR pin requires external reverse battery and transient protection. The maximum input voltage on VPWR is 50 V. All wetting, sustain, and internal logic current is provided from the VPWR pin. LOGIC VOLTAGE (VDD) The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive the SO output, and the pull-up current for CS and INT pins. VDD must be applied for a wake-up from the negative edge of CS or INT. GROUND (GND) The GND pin provides ground for the IC as well as ground for inputs programmed as switch-to-battery inputs. PROGRAMMABLE SWITCHES (SP0–SP7) The 33975 device has 8 switch inputs capable of being programmed to read switch-to-ground or switch-to-battery contacts. The input is compared with a 4.0 V reference. When programmed to be switch-to-battery, voltages greater than 4.0 V are considered closed. Voltages less than 4.0 V are considered open. The opposite holds true when inputs are programmed as switch-to-ground. Programming features are defined in Table 6 through Table 11 in the Functional Device Operation section of this datasheet beginning on page 16. Voltages greater than the VPWR supply voltage will source current through the SP inputs to the VPWR pin. Transient battery voltages greater than 38/40 V must be clamped by an external device. SWITCH-TO-GROUND (SG0–SG13) The SGn pins are switch-to-ground inputs only. The input is compared with a 4.0 V reference. Voltages greater than 4.0 V are considered open. Voltages less than 4.0 V are considered closed. Programming features are defined in Table 6 through Table 11 in the Functional Device Operation section of this datasheet beginning on page 16. Voltages greater than the VPWR supply voltage will source current through the SG inputs to the VPWR pin. Transient battery voltages greater than 38/40 V must be clamped by an external device. 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTIONS FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC33975 - Functional Block Diagram Analog Control and Protection Circuitry Bandgap Voltage Regulation Temp. Sense Oscillator & Clock MCU Interface and Control Interrupt/Wake-up SPI Interface Programmable Monitor Inputs SP0 - SP7 Monitor Inputs SG0 - SG13 Multiplex Control Control & Protection Interface & Control Prog. Monitor Monitor Figure 7. Functional Internal Block Description ANALOG CONTROL AND PROTECTION CIRCUITRY: The 33975 is designed to operate from 5.5 V to 38/40 V on the VPWR pin. Characteristics are provided from 8.0 to 28 V for the device. Switch contact currents and the internal logic supply are generated from the VPWR pin. The VDD supply pin is used to set the SPI communication voltage levels, current source for the SO driver, and pull-up current on INT and CS. The on-chip voltage regulator and bandgap supplies the required voltages to the internal monitor circuitry. The temperature monitor is active in the Normal Mode. MCU INTERFACE AND CONTROL: The 33975 Multiple Switch Detection Interface with Suppressed Wake-up is designed to detect the closing and opening of up to 22 switch contacts. The switch status, either open or closed, is transferred to the microprocessor unit (MCU) through a serial peripheral interface (SPI). The device also features a 22-to-1 analog multiplexer for reading inputs as analog. The 33975 device has two modes of operation, Normal and Sleep. SWITCH PROGRAMMABLE INPUTS: Programmable switch detection inputs. These 8 inputs can selectively detect switch closures to ground or battery. The 33975 device has 8 switch inputs capable of being programmed to read switch-to-ground or switch-to-battery contacts. The input is compared with a 4.0 V reference. When programmed to be switch-to-battery, voltages greater than 4.0 V are considered closed. Voltages less than 4.0 V are considered open. The opposite holds true when inputs are programmed as switch-to-ground. SWITCH–TO-GROUND INPUTS: Switch detection interface inputs. These 14 inputs can detect switch closures to ground only. The input is compared with a 4.0 V reference. Voltages greater than 4.0 V are considered open. Voltages less than 4.0 V are considered closed. Note: Each of these inputs may be used to supply current to sensors external to a module. 33975 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTIONS FUNCTIONAL INTERNAL BLOCK DESCRIPTION MCU INTERFACE DESCRIPTION The 33975 device directly interfaces to a 3.3 or 5.0 V microcontroller unit (MCU). SPI serial clock frequencies up to 6.0 MHz may be used for programming and reading switch input status (production tested at 4.16 MHz). Figure 8 illustrates the configuration between an MCU and one 33975. Serial peripheral interface (SPI) data is sent to the 33975 device through the SI input pin. As data is being clocked into the SI pin, status information is being clocked out of the device by the SO output pin. The response to a SPI command will always return the switch status, reset flag, and thermal flag. Input switch states are latched into the SO register on the falling edge of the chip select (CS) pin. Twenty-four bits are required to complete a transfer of information between the 33975 and the MCU. MC68HCXX Microcontroller 33975 MOSI SI Shift Register MISO SCLK Parallel Ports SO SCLK CS INT INT 33975 SI SO SCLK MC68HCXX Microcontroller Shift Register INT MOSI SI MISO SO 24-Bit Shift Register SCLK Figure 9. SPI Parallel Interface with Microprocessor MC68HCXX Microcontroller Receive Buffer To Logic CS Parallel Ports CS 33975 INT INT Figure 8. SPI Interface with Microprocessor Two or more 33975 devices may be used in a module system. Multiple ICs may be SPI-configured in parallel or serial. Figures 9 and 10 show the configurations. When using the serial configuration, 48-clock cycles are required to transfer data in/out of the ICs. 33975 MOSI SI Shift Register MISO SCLK Parallel Ports INT SO SCLK CS INT 33975 SI SO SCLK CS INT Figure 10. SPI Serial Interface with Microprocessor 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION POWER SUPPLY POWER-ON RESET (POR) The 33975 is designed to operate from 5.5 to 38/40 V on the VPWR pin. Characteristics are provided from 8.0 to 28 V for the device. Switch contact currents and the internal logic supply are generated from the VPWR pin. The VDD supply pin is used to set the SPI communication voltage levels, current source for the SO driver, and pull-up current on INT and CS. VDD supply may be removed from the device to reduce quiescent current. If VDD is removed while the device is in Normal mode, the device will remain in Normal mode. If VDD is removed in Sleep mode, the device will remain in Sleep mode until a wake-up input is received (WAKE high to low, switch input or interrupt timer expires). Removing VDD from the device disables SPI communication and will not allow the device to wake up from the INT and CS pins. Applying VPWR to the device will cause a Power-ON Reset and place the device in Normal mode. Default settings from Power-ON Reset via a VPWR or Reset Command are as follows: • Programmable switch – Set to switch-to-battery • All inputs set as wake-up • Wetting current on (16 mA pull-down, 32 mA pull-up) • Wetting current timer on (20 ms) • All inputs tri-state • Analog select 00000 (no input channel selected) Note The 33975 device provides indication that a reset has occurred by placing a logic [1] in bit 22 of the SO buffer. The reset bit is cleared on rising edge of CS. OPERATIONAL MODES • Tri-state Register (Tri-state Command) • Analog Select Register (Analog Command) • Calibration of Timers (Calibration Command) • Reset (Reset Command) Figure 6, page 11, is a graphical description of the device operation in Normal mode. Switch states are latched into the input register on the falling edge of CS. The INT to the MCU is cleared on the rising edge of CS. However, INT will not clear on the rising edge of CS if a switch has closed during SPI communication (CS low). This prevents switch states from being missed by the MCU. The 33975 has two operating modes, Normal mode and Sleep mode. A discussion on Normal mode begins below. A discussion on Sleep Mode begins on page 21. NORMAL MODE Normal mode may be entered by the following events: • Application of VPWR to the IC • Change-of-switch state (when enabled) • Falling edge of WAKE • Falling edge of INT (with VDD = 5.0 V and WAKE at Logic [1]) • Falling edge of CS (with VDD = 5.0 V) • Interrupt timer expires Only in Normal mode with VDD applied can the registers of the 33975 be programmed through the SPI. The registers that may be programmed in Normal mode are listed below. Further explanation of each register is provided in subsequent paragraphs. • Programmable Switch Register (Settings Command) • Wake-up/Interrupt Register (Wake-up/Interrupt Command) • Wetting Current Register (Metallic Command) • Wetting Current Timer Register (Wetting Current Timer Enable Command) PROGRAMMABLE SWITCH REGISTER Inputs SP0 to SP7 may be programmable for switch-tobattery or switch-to-ground. These inputs types are defined using the settings command (refer to Table 6). To set an SPn input for switch-to-battery, a logic [1] for the appropriate bit must be set. To set an SPn input for switch-to-ground, a logic [0] for the appropriate bit must be set. The MCU may change or update the Programmable Switch Register via software at any time in Normal mode. Regardless of the setting, when the SPn input switch is closed a logic [1] will be placed in the Serial Output Response Register (refer to Table 17, page 21). Table 6. Settings Command Settings Command Not used Battery/Ground Select 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 X X X X X X X X sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 33975 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES WAKE-UP/INTERRUPT REGISTER IC in Sleep mode (refer to Table 7). Programming the wakeup/interrupt bit to logic [1] will enable the specific input to generate an interrupt with switch change of state and will enable the specific input as wake-up. The MCU may change or update the Wake-up/Interrupt Register via software at any time in Normal mode. The Wake-up/Interrupt Register defines the inputs that are allowed to wake the 33975 from Sleep mode or set the INT pin low in Normal mode. Programming the wake-up/interrupt bit to logic [0] will disable the specific input from generating an interrupt and will disable the specific input from waking the Table 7. Wake-Up /Interrupt Command Wake-up/Interrupt Command Command Bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 X X X X X X X X sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 0 0 1 1 X X sg1 3 sg1 2 sg1 1 sg1 0 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 WETTING CURRENT REGISTER The 33975 has two levels of switch-to-ground contact current, 32 and 4.0 mA, and two levels of switch-to-battery contact current, 16 and 2.0 mA (see Figure 11). The metallic command is used to set the switch contact current level (refer to Table 8). Programming the metallic bit to logic [0] will set the switch wetting current to 2.0 mA/4.0 mA. Programming the metallic bit to logic [1] will set the switch contact wetting current to 16 mA/32 mA. The MCU may change or update the Wetting Current Register via software at any time in Normal Mode. Wetting current is designed to provide higher levels of current during switch closure. The higher level of current is designed to keep switch contacts from building up oxides that form on the switch contact surface. Switch Contact Voltage 32 mA Switch Wetting Current 4.0 mA Switch Sustain Current 20 ms Wetting Current Timer Figure 11. Contact Wetting and Sustain Current for Switch-to-Ground Input Table 8. Metallic Command Metallic Command Command Bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 X X X X X X X X sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 0 1 0 1 X X sg1 3 sg1 2 sg1 1 sg1 0 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 WETTING CURRENT TIMER REGISTER Each switch input has a designated 20 ms timer. The timer starts when the specific switch input crosses the comparator threshold (4.0 V). When the 20 ms timer expires, the contact current is reduced from 16 to 2.0 mA for switch-to-battery inputs and 32 to 4.0 mA for switch-to-ground inputs. The wetting current timer may be disabled for a specific input. When the timer is disabled, wetting current will continue to flow through the closed switch contact. With multiple wetting current timers disabled, power dissipation for the IC must be considered. The MCU may change or update the Wetting Current Timer Register via software at any time in Normal mode. This allows the MCU to control the amount of time wetting current is applied to the switch contact. Programming the wetting current timer bit to logic [0] will disable the wetting current timer. Programming the wetting current timer bit to logic [1] will enable the wetting current timer (refer to Table 9). 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 9. Wetting Current Timer Enable Command Wetting Current Timer Commands Command Bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 X X X X X X X X sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 0 0 0 1 0 0 0 X X sg1 3 sg1 2 sg1 1 sg1 0 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 TRI-STATE REGISTER comparator on each input remains active. This command allows the use of each input as a comparator with a 4.0 V threshold. The MCU may change or update the Tri-state Register via software at any time in Normal mode. The tri-state command is use to set the SPn or SGn input node as high-impedance (refer to Table 10). By setting the Tri-state Register bit to logic [1], the input will be highimpedance regardless of the metallic command setting. The Table 10. Tri-state Command Tri-State Commands Command Bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 0 0 0 1 0 0 1 X X X X X X X X 0 0 0 0 1 0 1 0 X X 7 6 5 4 3 2 1 0 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0 ANALOG SELECT REGISTER selects the input as high-impedance. Setting bit 6 and bit 5 to 0,1 selects 4.0 mA, and 1,0 selects 32 mA. Setting bit 6 and bit 5 to 1,1 in the Analog Select Register is not allowed and will place the input as an analog input with high-impedance. Analog currents set by the analog command are pull-up currents for all SGn and SPn inputs (refer to Table 11). The analog command does not allow pull-down currents on the SPn inputs. Setting the current to 32 or 4.0 mA may be useful for reading sensor inputs. Further information is provided in the Typical Applications section of this datasheet beginning on page 23. The MCU may change or update the Analog Select Register via software at any time in Normal mode. The analog voltage on switch inputs may be read by the MCU using the analog command (refer to Table 11). Internal to the IC is a 22-to-1 analog multiplexer. The voltage present on the selected input pin is buffered and made available on the AMUX output pin. The AMUX output pin is clamped to a maximum of VDD volts regardless of the higher voltages present on the input pin. After an input has been selected as the analog, the corresponding bit in the next SO data stream will be logic [0]. When selecting a channel to be read as analog, the user must also set the desired current (32 mA, 4.0 mA, or high-impedance). Setting bit 6 and bit 5 to 0,0 Table 11. Analog Command Analog Command Not used Current Select Analog Channel Select 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 X X X X X X X X X 32 mA 4.0 mA 0 0 0 0 0 33975 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 12. Analog Channel Bits 43210 Analog Channel Select 00000 No Input Selected 00001 SG0 00010 SG1 00011 SG2 00100 SG3 00101 SG4 00110 SG5 00111 SG6 01000 SG7 01001 SG8 01010 SG9 01011 SG10 01100 SG11 01101 SG12 01110 SG13 01111 SP0 10000 SP1 10001 SP2 10010 SP3 10011 SP4 10100 SP5 10101 SP6 10110 SP7 CALIBRATION OF TIMERS oscillator frequency changes with temperature, calibration is required for an accurate time base. Calibrating the timers has no affect on the quiescent current measurement. The calibration command simply makes the time base more accurate. The calibration command may be used to update the device on a periodic basis. All reset conditions clear the calibration register and places the device in the uncalibrated state. In cases where an accurate time base is required, the user may calibrate the internal timers using the calibration command (refer to Table 13). After the 33975 device receives the calibration command, the device expects 512 s logic [0] calibration pulse on the CS pin. The pulse is used to calibrate the internal clock. No other SPI pins should transition during this 512 s calibration pulse. Because the Table 13. Calibration Command Calibration Command Command Bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 X X X X X X X X X X X X X X X X RESET The reset command resets all registers to Power-ON Reset (POR) state. Refer to Table , page 20, for POR states or the paragraph entitled Power-ON Reset (POR) on page 16 of this datasheet. 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 14. Reset Command Reset Command Command Bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X SPI COMMAND SUMMARY Output (SO) data for input voltages greater or less than the threshold level. Open switches are always indicated with a logic [0], closed switches are indicated with logic [1]. Table below provides a comprehensive list of SPI commands recognized by the 33975 and the reset state of each register. Table 16 and Table 17 contain the Serial Table 15. SPI Command Summar MSB Command Bits Setting Bits LSBI 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Switch Status Command 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X Settings Command Bat=1, Gnd=0 (Default state = 1) 0 0 0 0 0 0 0 1 X X X X X X X X SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Wake-up/Interrupt Bit Wake-up=1 Nonwake-up=0 (Default state = 1) 0 0 0 0 0 0 1 0 X X X X X X X X SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 0 0 0 0 0 0 1 1 X X Metallic Command Metallic = 1 Non-metallic = 0 (Default state = 1) 0 0 0 0 0 1 0 0 X X 0 0 0 0 0 1 0 1 X X Analog Command 0 0 0 0 0 1 1 0 X X Wetting Current Timer Enable Command Timer ON = 1 Timer OFF = 0 (Default state = 1) 0 0 0 0 0 1 1 1 X X 0 0 0 0 1 0 0 0 X X Tri-state Command Input Tri-state=1 0 0 0 0 1 0 0 1 X X 0 0 0 0 1 0 1 0 X X Calibration Command (Default state uncalibrated) 0 0 0 0 1 0 1 1 X X X X X X X X X X Sleep Command (See Sleep Mode on page 21) 0 0 0 0 1 1 0 0 X X X X X X X X X X Reset Command 0 1 1 1 1 1 1 1 X X X X X X X X X X SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0 3 2 1 0 X X X X X X SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0 3 2 1 0 X X X X X X X X X X X X X 32m 4.0 A mA 0 0 0 0 0 0 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0 3 2 1 0 X X X X X X SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0 3 2 1 0 X X X X X X int int int sca sca sca n n time time time n time time time r r r r r r X X X X X X SO Response Will ther RST SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0 Always Send m 3 2 1 0 flg flg 33975 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Table 16. Serial Output (SO) Bit Data Type of Input Input Programmed Voltage on Input Pin SO SPI Bit SP Switch to Ground SPn < 4.0 V 1 Switch to Ground SPn > 4.0 V 0 Switch to Battery SPn < 4.0 V 0 Switch to Battery SPn > 4.0 V 1 N/A SGn < 4.0 V 1 N/A SGn > 4.0 V 0 SG Table 17. Serial Output (SO) Response Register SO Response Will Always Send ther RST SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0 m 3 2 1 0 flg flg EXAMPLE OF NORMAL MODE OPERATION The operation of the device in Normal mode is defined by the states of the programmable internal control registers. A typical application may have the following settings: • Programmable switch – set to switch-to-ground • All inputs set as wake-up • Wetting current on (32 mA) • Wetting current timer on (20 ms) • All inputs tri-state-disabled (comparator is active) • Analog select 00000 (no input channel selected) With the device programmed as above, an interrupt will be generated with each switch contact change of state (open-toclose or close-to-open) and 32 mA of contact wetting current will be source for 20 ms. The INT pin will remain low until switch status is acknowledged by the microprocessor. It is critical to understand INT will not be cleared on the rising edge of CS if a switch closure occurs while the CS is low. The maximum duration a switch state change can exist without acknowledgement depends on the software response time to the interrupt. Figure 6, page 11, shows the interaction between changing input states and the INT and CS pins. If desired the user may disable interrupts (wake-up/interrupt command) from the 33975 device and read the switch states on a periodic basis. Switch activation and deactivation faster than the MCU read rate will not be acknowledged. The 33975 device will exit the Normal mode and enter the Sleep mode only with a valid sleep command. SLEEP MODE Sleep mode is used to reduce system quiescent currents. Sleep mode may be entered only by sending the sleep command. All register settings programmed in Normal mode will be maintained in Sleep mode. The 33975 will exit Sleep mode and enter Normal mode when any of the following events occur: • Input switch change of state (when enabled) • Interrupt timer expire • Falling edge of WAKE • Falling edge of INT (with VDD = 5.0 V and WAKE at Logic [1]) • Falling edge of CS (with VDD = 5.0 V) • Power-on reset (POR) The VDD supply may be removed from the device during Sleep mode. However removing VDD from the device in Sleep mode will disable a wake-up from falling edge of INT and CS. Note: In cases where CS is used to wake the device, the first SO data message is not valid. The sleep command contains settings for two programmable timers for Sleep mode, the interrupt timer and the scan timer, as shown in Table 18. Table 18. Sleep Command Sleep Command Command Bits 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 X X X X X X X X X X int timer int timer int timer scan timer scan timer 0 scan timer 23 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES The interrupt timer is used as a periodic wake-up timer. When the timer expires, an interrupt is generated and the device enters Normal mode. Note: The interrupt timer in the 33975 device may be disabled by programming the interrupt bits to logic [1 1 1]. Table 19 shows the programmable settings of the Interrupt timer. The scan timer sets the polling period between input switch reads in Sleep mode. The period is set in the sleep command and may be set to 000 (no period) to 111 (64 ms). In Sleep mode when the scan timer expires, inputs will behave as programmed prior to sleep command. The 33975 will wake up for approximately 125 s and read the switch inputs. At the end of the 125 s, the input switch states are compared with the switch state prior to sleep command. When switch state changes are detected, an interrupt (when enabled; refer to wake-up/interrupt command description on page 17) is generated and the device enters Normal mode. Without switch state changes, the 33975 will reset the scan timer, inputs become tri-state, and the Sleep mode continues until the scan timer expires again. Table 20 shows the programmable settings of the Scan timer. Note: The interrupt and scan timers are disabled in the Normal Mode. Figure 5, page 11, is a graphical description of how the 33975 device exits Sleep mode and enters Normal mode. Notice that the device will exit Sleep mode when the interrupt timer expires or when a switch change of state occurs. The falling edge of INT triggers the MCU to wake from Sleep state. Figure 12 illustrates the current consumed during Sleep mode. During the 125 s, the device is fully active and switch states are read. The quiescent current is calculated by integrating the normal running current over scan period plus approximately 60 A. I=V/R oror0.270V/100ohm = 2.7mA I=V/R 0.270V/100=2.7mA Inputs active for Inputs active for 125 us 125s out of 32 out ms of 32ms I=V/R or I=V/R or6mV/100ohm = 60 uA 6.0mV/100=60A Table 19. Interrupt Timer Figure 12. Sleep Current Waveform Bits 543 Interrupt Period 000 32 ms TEMPERATURE MONITOR 001 64 ms 010 128 ms 011 256 ms 100 512 ms 101 1.024 s 110 2.048 s 111 No interrupt wake-up With multiple switch inputs closed and the device programmed with the wetting current timers disabled, considerable power will be dissipated by the IC. For this reason temperature monitoring has been implemented. The temperature monitor is active in the Normal mode only. When the IC temperature is above the thermal limit, the temperature monitor will do all of the following: • Generate an interrupt. • Force all wetting current sources to revert to 2.0 mA/ 4.0 mA sustain currents • Maintain the 2.0 mA/4.0 mA sustain currents and all other functionality. • Set the thermal flag bit in the SPI output register. The thermal flag bit in the SPI word will be cleared on the rising edge of CS provided the die temperature has cooled below the thermal limit. When die temperature has cooled below thermal limit, the device will resume previously programmed settings. Table 20. Scan Timer Bits 210 Scan Period 000 No Scan 001 1.0 ms 010 2.0 ms 011 4.0 ms 100 8.0 ms 101 16 ms 110 32 ms 111 64 ms 33975 22 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS OPERATIONAL MODES TYPICAL APPLICATIONS The 33975’s primary function is the detection of open or closed switch contacts. However, there are many features that allow the device to be used in a variety of applications. The following is a list of applications to consider for the IC: • Sensor power supply • Switch monitor for metallic or elastomeric switches • Analog sensor inputs (Ratiometric) • Power MOSFET/LED driver and monitor • Multiple 33975 devices in a module system The following paragraphs describe the applications in detail. SENSOR POWER SUPPLY Each input may be used to supply current to sensors external to a module. Many sensors such as Hall effect, pressure sensors, and temperature sensors require a supply voltage to power the sensor, and provide an open collector or analog output. Figure 13 shows how the 33975 may be used to supply power and interface to these types of sensors. In an application where the input makes continuous transitions, consider using the wake-up/interrupt command to disable the interrupt for the particular input. 33975 VBAT SP0 SP1 VPWR VDD MCU VDD VBAT SP7 WAKE SG0 SG1 VPWR VPWR 32 mA 32 mA 4.0 mA SI MOSI SCLK CS SCLK SO MISO INT INT CS Metallic switch contacts often develop higher contact resistance over time owing to contact corrosion. The corrosion is induced by humidity, salt, and other elements that exist in the environment. For this reason the 33975 provides two settings for contacts. When programmed for metallic switches, the device provides higher wetting current to keep switch contacts free of oxides. The higher current occurs for the first 20 ms of switch closure. Where longer duration of wetting current is desired, the user may send the wetting current timer command and disable the timer. Wetting current will be continuous to the closed switch. After the time period set by the MCU, the wetting current timer command may be sent again to enable the timer. The user must consider power dissipation on the device when disabling the timer. (Refer to the paragraph entitled Temperature Monitor, page 22.) To increase the amount of wetting current for a switch contact, the user has two options. Higher wetting current to a switch may be achieved by paralleling SGn or SPn inputs. This will increase wetting current by 32 mA for each input added to the switch-to-ground contact and 16 mA for switchto-battery contacts. The second option is to simply add an external resistor pull-up to the VPWR supply for switch-toground inputs or a resistor to ground for a switch-to-battery input. Adding an external resistor has no effect on the operation of the device. Elastomeric switch contacts are made of carbon and have a high contact resistance. Resistance of 1.0 k is common. In applications with elastomeric switches, the pull-up and pulldown currents must be reduced to prevent excessive power dissipation at the contact. Programming for a lower current settings is provided in the Functional Device Operation Section beginning on page 16 under Table 8, Metallic Command. SG12 ANALOG SENSOR INPUTS (RATIOMETRIC) VPWR VPWR Hall-Effect Sensor Reg METALLIC/ELASTOMERIC SWITCH 32 mA SG13 4.0 mA IOC[7:0] AMUX Input Capture Timer Port X VDD VPWR 0V 0V SG13 AMUX Figure 13. Sensor Power Supply The 33975 features a 22-to-1 analog multiplexer. Setting the binary code for a specific input in the analog command allows the microcontroller to perform analog to digital conversion on any of the 22 inputs. On rising edge of the CS, the multiplexer connects a requested input to the AMUX pin. The AMUX pin is clamped to max of VDD volts regardless of the higher voltages present on the input pin. After an input has been selected as the analog, the corresponding bit in the next SO data stream will be logic [0]. The input pin, when selected as analog, may be configured as analog with high-impedance, analog with 4.0 mA pull-up, or analog with 32 mA pull-up. Figure 14, page 24, shows how the 33975 may be used to provide a ratiometric reading of variable resistive input. 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 23 TYPICAL APPLICATIONS OPERATIONAL MODES 33975 VBAT SP0 SP1 ADC = VPWR VDD MCU VDD VBAT SP7 32 mA I1 4.0mA VPWR VPWR 4.0 mA SG12 SI MOSI SCLK SCLK CS CS SO MISO INT INT AMUX VPWR VPWR R1 32 Analog Sensor or Analog Switch mA SG13 I2 4.0mA 1.21k 0.1% 4.0 mA 4.0mA x 1.0k 4.0mA x 1.21k AN0 Analog Ports Using the equation yields the following: The ADC value of 213 counts is the value with 0% error (neglecting the resistor tolerance and AMUX input offset voltage). Now calculate the count value induced by the mismatch in current sources. From a sample device the maximum current source was measured at 3.979 mA and minimum current source was measured at 3.933 mA. This yields 1.16% error in A/D conversion due to the current source mismatch. The A/D measurement will be as follows: 4.36V to 5.32V R2 x 255 ADC = 210 counts WAKE SG0 SG1 ADC = I1 x R1 x 255 I2 x R2 VREF(H) VREF(L) Figure 14. Analog Ratiometric Conversion To read a potentiometer sensor, the wiper should be grounded and brought back to the module ground, as illustrated in Figure 14. With the wiper changing the impedance of the sensor, the analog voltage on the input will represent the position of the sensor. Using the Analog feature to provide 4.0 mA of pull-up current to an analog sensor may induce error due to the accuracy of the current source. For this reason, a ratiometric conversion must be considered. Using two current sources (one for the sensor and one to set the reference voltage to the A/D converter) will yield a maximum error (owing to the 33975) of 4%. Higher accuracy may be achieved through module level calibration. In this example, we use the resistor values from Figure 14 and assume the current sources are 4% from each other. The user may use the module end-of-line tester to calculate the error in the A/D conversion. By placing a 1.0 k, 0.1% resistor in the end-of-line test equipment and assuming a perfect 4.0 mA current source from the 33975, a calculated A/D conversion may be obtained. ADC = 3.933 mA x 1.0k 3.979 mA x 1.21k x 255 ADC = 208 counts This A/D conversion is 1.16% low in value. The error correction factor of 1.0115 may be used to correct the value: ADC = 208 counts x 1.0116 ADC = 210 counts An error correction factor may then be stored in E2 memory and used in the A/D calculation for the specific input. Each input used as analog measurement will have a dedicated calibrated error correction factor. POWER MOSFET/LED DRIVER AND MONITOR Because of the flexible programming of the 33975 device, it may be used to drive small loads like LEDs or MOSFET gates. It was specifically designed to power up in the Normal Mode with the inputs tri-state. This was done to ensure the LEDs or MOSFETs connected to the 33975 power up in the off-state. The Switch Programmable (SP0–SP7) inputs have a source-and-sink capability, providing effective MOSFET gate control. To complete the circuit, a pull-down resistor should be used to keep the gate from floating during the Sleep Modes. Figure 15, page 25, shows an application where the SG0 input is used to monitor the drain-to-source voltage of the external MOSFET. The 750 resistor is used to set the drain-to-source trip voltage. With the 4.0 mA current source enabled, an interrupt will be generated when the drain-to-source voltage is approximately 1.0 V. 33975 24 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS OPERATIONAL MODES current to the 750 resistor, the analog voltage on the SGn pin will be approximately: VBAT LOAD VPWR VPWR 32 mA 750 SG0 VSGn = ISGn x 750 + VDS 4.0 mA SG0 AMUX 100k 4.0 V Ref + - To SPI Comparator VPWR VPWR 32 mA SG0 4.0 mA SP0 To SPI 4.0 V +Ref Comparator 2.0 mA 16 mA VPWR VPWR 32 mA SG13 4.0 mA SG13 4.0 V Ref + - To SPI Comparator Figure 15. MOSFET or LED Driver Output The sequence of commands (from Normal mode with inputs tri-state) required to set up the device to drive a MOSFET are as follows: • wetting current timer enable command –Disable SPn wetting current timer (refer to Table 9, page 18). • metallic command –Set SPn to 16/32 mA or 2.0/4.0 mA gate drive current (refer to Table 8, page 17). • settings command –Set SPn as switch-to-battery (refer to Table 6, page 16). • tri-state command –Disable tri-state for SPn (refer to Table 10, page 18). After the tri-state command has been sent (tri-state disable), the MOSFET gate will be pulled to ground. From this point forward the MOSFET may be turned on and off by sending the settings command: • settings command –SPn as switch-to-ground (MOSFET ON). • settings command –SPn as switch-to-battery (MOSFET OFF). Monitoring of the MOSFET drain in the OFF state provides open load detection. This is done by using an input comparator. With the SGn input in tri-state, the load will pull up the input to battery. With the load open, the SGn pin is pulled down to ground through an external resistor. The open load is indicated by a logic [1] in the SO data bit. The analog command may be used to monitor the drain voltage in the MOSFET ON state. By sourcing 4.0 mA of As the voltage on the drain of the MOSFET increases, so does the voltage on the SGn pin. With the SGn pin selected as analog, the MCU may perform the A/D conversion. Using this method for controlling unclamped inductive loads is not recommended. Inductive fly-back voltages greater than VPWR may damage the IC. The SP0–SP7 pins of this device may also be used to send signals from one module to another. Operation is similar to the gate control of a MOSFET. For LED applications a resistor in series with the LED is recommended but not required. The switch-to-ground inputs are recommended for LED application. To drive the LED use the following commands: • wetting current timer enable command –Disable SGn wetting current timer. • metallic command –Set SGn to 32 mA. From this point forward the LED may be turned on and off using the tri-state command: • tri-state command –Disable tri-state for SGn (LED ON). • tri-state command –Enable tri-state for SGn (LED OFF). These parameters are easily programmed via SPI commands in Normal mode. Multiple 33975 Devices in a Module System Connecting power to the 33975 and the MCU for Sleep mode operation may be done in several ways. Table 21 shows several system configurations for power between the MCU and the 33975 and their specific requirements for functionality. Table 21. Sleep Mode Power Supply MCU VDD 33975 VDD Comments 5.0V 5.0V All wake-up conditions apply. (Refer to Sleep Mode, page 21.) 5.0V 0V 0V 5.0V 0V 0V SPI wake-up is not possible. Sleep mode is not possible. Current from the CS pull-up will flow through the MCU to the VDD that has been switched off. The negative edge of CS will put 33975 in Normal mode. SPI wake-up is not possible. Multiple 33975 devices may be used in a module system. SPI control may be done in parallel or serial. However when parallel mode is used, each device is addressed independently (refer to MCU Interface Description, page 15). 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 25 TYPICAL APPLICATIONS OPERATIONAL MODES Therefore, when sending the sleep command, one device will enter sleep before the other. For multiple devices in a system, it is recommended that the devices are controlled in serial (S0 from first device is connected to SI of second device). With two devices, 48 clock pulses are required to shift data in. When the WAKE feature is used to enable the power supply, both WAKE pins should be connected to the enable pin on the power supply. The INT pins may be connected to one interrupt pin on the MCU, or may have their own dedicated interrupt to the MCU. The transition from Normal to Sleep mode is done by sending the sleep command. With the devices connected in serial and the sleep command sent, both will enter Sleep mode on the rising edge of CS. When Sleep mode is entered, the WAKE pin will be logic [1]. If either device wakes up, the WAKE pin will transition low, waking the other device. A condition exists where the MCU is sending the sleep command (CS logic [0]) and a switch input changes state. With this event, the device that detects this input will not transition to Sleep mode, while the second device will enter Sleep mode. In this case, two switch status commands must be sent to receive accurate switch status data. The first switch status command will wake the device in Sleep mode. Switch status data may not be valid from the first switch status command because of the time required for the input voltage to rise above the 4.0 V input comparator threshold. This time is dependant on the impedance of SGn or SPn node. The second switch status command will provide accurate switch status information. It is recommended that the software wait 10 to 20 ms between the two switch status commands, allowing time for switch input voltages to stabilize. With all switch states acknowledged by the MCU, the sleep sequence may be initiated. All parameters for Sleep mode should be updated prior to sending the sleep command. The 33975 IC has an internal 5.0 V supply from the VPWR pin. A POR circuit monitors the internal 5.0 V supply. In the event of transients on the VPWR pin, an internal reset may occur. Upon reset the 33975 will enter Normal mode with the internal registers as defined in Table , page 20. Therefore it is recommended that the MCU periodically update all registers internal to the IC. USING THE WAKE FEATURE The 33975 provides a WAKE output and wake-up input designed to control an enable pin on system power supply. While in the Normal mode, the WAKE output is low, enabling the power supply. In the Sleep mode, the WAKE pin is high, disabling the power supply. The WAKE pin has a passive pullup to the internal 5.0 V supply but may be pulled up through a resistor to VPWR supply (see Figure 17, page 27). When the WAKE output is not used the pin should be pulled up to the VDD supply through a resistor, as shown in Figure 16, page 27). During the Sleep mode, a switch closure will set the WAKE pin low, causing the 33975 to enter the Normal mode. The power supply will then be activated, supplying power to the VDD pin and the microprocessor and the 33975. The microprocessor can determine the source of the wake-up by reading the interrupt flag. COST AND FLEXIBILITY Systems requiring a significant number of switch interfaces have many discrete components. Discrete components on standard PWB consume board space and must be checked for solder joint integrity. An integrated approach reduces solder joints, consumes less board space, and offers wider operating voltage, analog interface capability, and greater interfacing flexibility. 33975 26 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS OPERATIONAL MODES DD VBAT Power Supply VDD 33975 VBAT VPWR VPWR SP0 SP1 VDD VBAT VDD SP7 MC68HCXX Microprocessor WAKE SG0 SG1 SG12 CS CS INT INT SI MOSI SO MISO SCLK SCLK AMUX AN0 SG13 Figure 16. Power Supply Active in Sleep Mode VBAT Power Supply 33975 VBAT VPWR VDD Enable VPWR SP0 SP1 WAKE VBAT VDD VDD MC68HCXX Microprocessor SP7 SG0 SG1 CS CS INT INT SI MOSI SO MISO SCLK SCLK AMUX SG12 AN0 SG13 Figure 17. Power Supply Shutdown in Sleep Mode 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 27 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a “keyword” search on the “98A” number listed below. EK SUFFIX 32-PIN EXPOSED PAD 98ASA10556D REVISION D 33975 28 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS (CONTINUED) PACKAGE DIMENSIONS (Continued) EK SUFFIX 32-PIN EXPOSED PAD 98ASA10556D REVISION D 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 29 PACKAGE DIMENSIONS (CONTINUED) EK SUFFIX 32-PIN EXPOSED PAD 98ASA10556D REVISION D 33975 30 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY Revision 5.0 Date 6/2007 Description of Changes • • • • • • 6.0 11/2007 • • Implemented Revision History page Updated to Freescale form and style Added MCZ33975EK/R2 and MCZ33975AEK/R2 Removed Peak Package Reflow Temperature During Reflow, and added Peak Package Reflow Temperature During Reflow(5), (6) Removed MC33975AEK/R2 from the Ordering Information Replaced figures for 33975 Simplified Application Diagram, Power Supply Active in Sleep Mode, and Power Supply Shutdown in Sleep Mode. Adjusted ESD voltages for Human Body Model(2) and Applies to all non-input Pins. Updated document form and style. 7.0 2/2008 • Minor changes to text 8.0 8/2008 • Updated package drawing 9.0 8/2008 • Revised wording of Features on Page 1 - No parameter /technical changes. 10.0 8/2011 11.0 01/2014 • Revised Ordering Information table by adding part numbers MC33975TEK/R2 and MC33975ATEK/R2, and removing part numbers MC33975EK/R2, MCZ33975EK/R2 and MCZ33975AEK/R2. • Updated document form and style. • No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to last paragraph. 33975 Analog Integrated Circuit Device Data Freescale Semiconductor 31 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2014 Freescale Semiconductor, Inc. Document Number: MC33975 Rev 11.0 01/2014