N74F827DB

74F827 10-bit buffer/line driver; non-inverting; 3-state Rev. 04 — 29 January 2010 Product data sheet 1. General description The 74F827 10-bit buffer, provides high performance bus interface buffering for wide data/address paths or buses carrying parity. The device has NOR output enables (OE0, OE1) for maximum control flexibility. 2. Features I High impedance NPN base inputs for reduced loading (20 µA input current in HIGH and LOW states) I IIL = 20 µA compared to 600 µA in FAST family specification I Ideal for high speed, light bus loading with increased fan-in I Controlled rise and fall times to minimize ground bounce I Glitch-free power-up in 3-state I Flow-through pinout architecture for microprocessor oriented applications I Output sink capability, IOL = 64 mA 3. Ordering information Table 1. Ordering information Package Temperature range Name N74F827D N74F827DB 0 °C to 70 °C 0 °C to 70 °C SO24 SSOP24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm Version SOT137-1 SOT340-1 Type number NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state 4. Functional diagram 1 13 & EN1 2 3 4 5 6 7 8 9 10 11 2 3 1 23 22 21 20 19 18 17 16 15 14 1 13 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 OE0 OE1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 23 22 21 20 19 18 17 16 15 14 001aae885 4 5 6 7 8 9 10 11 001aae886 Fig 1. Logic symbol Fig 2. IEC logic symbol A0 2 OE0 OE1 1 13 23 Y0 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 A9 11 22 Y1 21 Y2 20 Y3 19 Y4 18 Y5 17 Y6 16 Y7 15 Y8 14 Y9 001aae887 Fig 3. Logic diagram 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 2 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state 5. Pinning information 5.1 Pinning 74F827 OE0 A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 24 VCC 23 Y0 22 Y1 21 Y2 20 Y3 19 Y4 18 Y5 17 Y6 16 Y7 15 Y8 14 Y9 13 OE1 001aal243 A8 10 A9 11 GND 12 Fig 4. Pin configuration 5.2 Pin description Table 2. Symbol OE0 A0 to A9 GND OE1 Y0 to Y9 VCC [1] Pin description Pin 1 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12 13 24 Description output enable input (active LOW) data input ground (0 V) output enable input (active LOW) supply voltage Unit load HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1200/106.7 Load value[1] HIGH/LOW 20 µA/20 µA 20 µA/20 µA 20 µA/20 µA 24 mA/64 mA - 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 data output One FAST Unit Load (UL) is defined as 20 µA in HIGH state, 0.6 µA in LOW state. 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 3 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state 6. Functional description 6.1 Function table Table 3. Input OEn L L H [1] Function selection[1] Output An L H X Yn L H Z disabled transparent Status H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO IIK IO Tamb Tstg [1] [2] Parameter supply voltage input voltage output voltage input clamping current output current ambient temperature storage temperature Conditions [1] Min −0.5 −0.5 −0.5 −30 [2] Max +7.0 +7.0 +7.0 +5 128 70 +150 Unit V V V mA mA °C °C output in HIGH-state VI < 0 V output in LOW-state in free-air [1] 0 −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 8. Recommended operating conditions Table 5. Symbol VCC VIH VIL IIK IOH IOL Recommended operating conditions Parameter supply voltage HIGH-level input voltage LOW-level input voltage input clamping current HIGH-level output current LOW-level output current Conditions Min 4.5 2.0 −18 −24 Typ 5.0 Max 5.5 0.8 64 Unit V V V mA mA mA 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 4 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state 9. Static characteristics Table 6. Static characteristics Conditions Min VIK VOH input clamping voltage HIGH-level output voltage VCC = 4.5 V; IIK = −18 mA VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0 V IOH = −15 mA VCC = ±10 % VCC = ±5 % IOH = −24 mA VCC = ±10 % VCC = ±5 % VOL LOW-level output voltage VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0 V IOL = 64 mA VCC = ±10 % VCC = ±5 % II IIH IIL IOZ input leakage current LOW-level input current VCC = 0 V; VI = 7.0 V VCC = 5.5 V; VI = 0.5 V VO = 2.7 V VO = 0.5 V IO ICC output current supply current VCC = 5.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs OFF-state [1] [2] All typical values are measured at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [2] Symbol Parameter 25 °C Typ[1] −0.73 Max −1.2 0 °C to 70 °C Unit Min −1.2 Max V - 3.3 - - 2.4 2.4 2.0 2.0 - V V V V - 0.42 50 70 60 - −100 - 0.55 0.55 100 20 −20 50 −50 V V µA µA µA µA µA HIGH-level input current VCC = 5.5 V; VI = 2.7 V OFF-state output current VCC = 5.5 V −225 mA 70 100 90 mA mA mA 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 7. Symbol Parameter Conditions 25 °C; VCC = 5.0 V Min tPLH LOW to HIGH propagation delay An to Yn; see Figure 5 CL = 50 pF CL = 300 pF, 1 output switching CL = 300 pF, 10 outputs switching 2.0 5.5 9.5 12.0 8.5 13.0 16.0 2.0 9.0 14.0 17.0 ns ns ns Typ Max 0 °C to 70 °C; Unit VCC = 5.0 V ± 0.5 V Min Max 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 5 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state Table 7. Dynamic characteristics …continued GND = 0 V; for test circuit, see Figure 7. Symbol Parameter Conditions 25 °C; VCC = 5.0 V Min tPHL HIGH to LOW propagation delay An to Yn; see Figure 5 CL = 50 pF CL = 300 pF, 1 output switching CL = 300 pF, 10 outputs switching tPZH OFF-state to HIGH propagation delay OEn to Yn; see Figure 6 CL = 50 pF CL = 300 pF, 1 output switching CL = 300 pF, 10 outputs switching tPZL OFF-state to LOW propagation delay OEn to Yn; see Figure 6 CL = 50 pF CL = 300 pF, 1 output switching CL = 300 pF, 10 outputs switching tPHZ HIGH to OFF-state propagation delay OEn to Yn; see Figure 6 CL = 50 pF CL = 300 pF, 1 output switching CL = 300 pF, 10 outputs switching tPLZ LOW to OFF-state propagation delay OEn to Yn; see Figure 6 CL = 50 pF CL = 300 pF, 1 output switching CL = 300 pF, 10 outputs switching 2.5 5.0 9.5 12.5 8.0 13.5 15.5 2.0 8.5 14.0 16.0 ns ns ns 2.5 5.0 15.0 15.0 8.0 19.0 19.0 2.0 8.5 20.0 20.0 ns ns ns 4.0 6.0 9.5 17.0 10.5 13.0 21.0 4.0 11.5 14.0 21.5 ns ns ns 5.0 8.0 15.0 15.0 12.0 20.0 20.0 4.5 14.0 21.0 21.0 ns ns ns 2.0 4.5 7.5 14.0 8.5 10.0 17.0 2.0 9.0 11.0 18.0 ns ns ns Typ Max 0 °C to 70 °C; Unit VCC = 5.0 V ± 0.5 V Min Max 11. Waveforms VI An input GND tPLH VOH Yn output VOL 001aal244 VM VM tPHL VM VM VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (An) to output (Yn) 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 6 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state VI OEn input GND tPLZ 3.5 V output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aal293 VM tPZL VM VOL + 0.3 V tPZH VOH − 0.3 V VM VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay 3-state output enable time to LOW-level and output disable time from LOW-level 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 7 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW 001aac221 90 % VM VCC VI VO DUT RT CL RL RL VEXT G VI positive pulse 0V VM 10 % mna616 a. Input pulse definition Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. b. Test circuit RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 7. Table 8. Input VI 3.0 V Test circuit for measuring switching times Test data Load fI 1 MHz tW 500 ns tr, tf ≤ 2.5 ns CL 50 pF RL 500 Ω VEXT tPHL, tPLH open tPZH, tPHZ open tPZL, tPLZ 7.0 V 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 8 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c y HE vMA Z 24 13 Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. 74F827_4 Package outline SOT137-1 (SO24) © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 9 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 12 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. 74F827_4 Package outline SOT340-1 (SSOP24) © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 10 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state 13. Abbreviations Table 9. Acronym DUT ESD HBM MM Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model 14. Revision history Table 10. 74F827_4 Modifications: Revision history Release date 20100129 Data sheet status Product data sheet Change notice Supersedes 74F827_3 Document ID • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12 “Package outline” Product specification Product specification 74F827_74F828_2 - 74F827_3 74F827_74F828_2 20040121 19941205 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 11 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74F827_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 29 January 2010 12 of 13 NXP Semiconductors 74F827 10-bit buffer/line driver; non-inverting; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 January 2010 Document identifier: 74F827_4