PCA9536D

PCA9536 4-bit I2C-bus and SMBus I/O port Rev. 05 — 25 January 2010 Product data sheet 1. General description The PCA9536 is an 8-pin CMOS device that provides 4 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9536 consists of a 4-bit Configuration register (input or output selection), 4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The power-on reset sets the registers to their default values and initializes the device state machine. The I2C-bus address is fixed and allows only one device on the same I2C-bus/SMBus. 2. Features 4-bit I2C-bus GPIO Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity Inversion register Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 4 I/O pins which default to 4 inputs with 100 kΩ internal pull-up resistor 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 (MSOP8), HVSON8 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 3. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C Type number PCA9536D PCA9536DP PCA9536TK Topside mark PCA9536 9536 9536 Package Name SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 SOT505-1 SOT908-1 TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm HVSON8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 × 3 × 0.85 mm [1] Also known as MSOP8. 4. Block diagram PCA9536 SCL SDA INPUT FILTER 4-bit I2C-BUS/SMBus CONTROL write pulse read pulse POWER-ON RESET INPUT/ OUTPUT PORTS IO1 IO2 IO3 IO0 VDD VSS 002aab851 All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9536 PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 2 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 5. Pinning information 5.1 Pinning IO0 IO1 IO2 VSS 1 2 8 7 VDD SDA SCL IO3 IO0 IO1 IO2 VSS 1 2 3 4 002aab850 8 7 VDD SDA SCL IO3 PCA9536D 3 4 002aab849 6 5 PCA9536DP 6 5 Fig 2. Pin configuration for SO8 terminal 1 index area Fig 3. Pin configuration for TSSOP8 IO0 IO1 IO2 VSS 1 2 8 7 VDD SDA SCL IO3 PCA9536TK 3 4 6 5 002aac459 Transparent top view Fig 4. Pin configuration for HVSON8 5.2 Pin description Table 2. Symbol IO0 IO1 IO2 VSS IO3 SCL SDA VDD Pin description Pin 1 2 3 4 5 6 7 8 Description input/output 0 input/output 1 input/output 2 supply ground input/output 3 serial clock line serial data line supply voltage PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 3 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 6. Functional description Refer to Figure 1 “Block diagram of PCA9536”. 6.1 Registers 6.1.1 Command byte Table 3. Command 0 1 2 3 Command byte Protocol read byte read/write byte read/write byte read/write byte Function Input Port register Output Port register Polarity Inversion register Configuration register The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. 6.1.2 Register 0 - Input Port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default ‘X’ is determined by the externally applied logic level, normally logic 1 when no external signal externally applied because of the internal pull-up resistors. Table 4. Register 0 - Input Port register bit description Legend: * default value Bit 7 6 5 4 3 2 1 0 Symbol I7 I6 I5 I4 I3 I2 I1 I0 Access read only read only read only read only read only read only read only read only Value 1* 1* 1* 1* X X X X determined by externally applied logic level Description not used PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 4 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 6.1.3 Register 1 - Output Port register This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value. ‘Not used’ bits can be programmed with either logic 0 or logic 1. Table 5. Register 1 - Output Port register bit description Legend: * default value Bit 7 6 5 4 3 2 1 0 Symbol O7 O6 O5 O4 O3 O2 O1 O0 Access R R R R R R R R Value 1* 1* 1* 1* 1* 1* 1* 1* reflects outgoing logic levels of pins defined as outputs by Register 3 Description not used 6.1.4 Register 2 - Polarity Inversion register This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. ‘Not used’ bits can be programmed with either logic 0 or logic 1. Table 6. Register 2 - Polarity Inversion register bit description Legend: * default value Bit 7 6 5 4 3 2 1 0 Symbol N7 N6 N5 N4 N3 N2 N1 N0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0* 0* 0* 0* 0* 0* 0* 0* inverts polarity of Input Port register data 0 = Input Port register data retained (default value) 1 = Input Port register data inverted Description not used PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 5 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 6.1.5 Register 3 - Configuration register This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VDD. ‘Not used’ bits can be programmed with either logic 0 or logic 1. Table 7. Register 3 - Configuration register bit description Legend: * default value Bit 7 6 5 4 3 2 1 0 Symbol C7 C6 C5 C4 C3 C2 C1 C0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* configures the directions of the I/O pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin configured as input (default value) Description not used 6.2 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9536 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9536 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. 6.3 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up (100 kΩ typical) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 6 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port data from shift register configuration register data from shift register write configuration pulse D FF CK Q D FF Q Q Q1 100 kΩ output port register data VDD IO0 to IO3 write pulse CK output port register input port register D FF read pulse CK polarity inversion register data from shift register write polarity pulse D FF CK 002aab852 Q2 VSS Q input port register data Q polarity inversion register data Remark: At power-on reset, all registers return to default values. Fig 5. Simplified schematic of IO0 to IO3 6.4 Device address slave address 1 0 0 0 fixed 0 0 1 R/W 002aab853 Fig 6. PCA9536 device address 6.5 Bus transactions Data is transmitted to the PCA9536 registers using the Write mode as shown in Figure 7 and Figure 8. Data is read from the PCA9536 registers using the Read mode as shown in Figure 9 and Figure 10. These devices do not implement an auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 7 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port SCL 1 2 3 4 5 6 7 8 9 command byte data to port 0 1 A DATA 1 A acknowledge from slave P STOP condition slave address SDA S 1 0 0 0 0 0 1 0 R/W acknowledge from slave write to port A 0 0 0 0 0 0 START condition acknowledge from slave tv(Q) data out from port data 1 valid 002aab854 Fig 7. Write to Output Port register SCL 1 2 3 4 5 6 7 8 9 command byte data to register 0 1/0 A DATA A acknowledge from slave P STOP condition slave address SDA S 1 0 0 0 0 0 1 0 R/W acknowledge from slave data to register A 0 0 0 0 0 0 START condition acknowledge from slave 002aab855 Fig 8. Write to Configuration register or Polarity Inversion register slave address SDA S 1 0 0 0 0 0 1 0 R/W acknowledge from slave slave address (cont.) S 1 0 0 0 0 0 1 1 R/W acknowledge from slave A A command byte A (cont.) START condition acknowledge from slave data from register DATA (first byte) A data from register DATA (last byte) NA P STOP condition (repeated) START condition acknowledge from master no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter 002aab856 Fig 9. Read from register PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 8 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port SCL 1 2 3 4 5 6 7 8 9 data from port data from port A acknowledge from master DATA 4 NA P STOP condition slave address SDA S 1 0 0 0 0 0 1 1 R/W acknowledge from slave read from port th(D) data into port DATA 2 A DATA 1 START condition no acknowledge from master tsu(D) DATA 3 DATA 4 002aab857 This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. Fig 10. Read Input Port register 7. Application design-in information VDD 2 kΩ VDD SDA SCL MASTER CONTROLLER VSS 10 kΩ 10 kΩ VDD SDA SCL IO0 IO1 SUBSYSTEM 1 (e.g. temp. sensor) INT PCA9536 IO2 RESET IO3 SUBSYSTEM 2 (e.g. counter) VSS enable A controlled switch (e.g. CBT device) B 002aab858 Device address is 1000 001X; IO0, IO2, IO3 configured as outputs; IO1 configured as input. Fig 11. Typical application PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 9 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 8. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD II VI/O IO(IOn) IDD ISS Ptot Tstg Tamb Tj(max) Parameter supply voltage input current voltage on an input/output pin output current on pin IOn supply current ground supply current total power dissipation storage temperature ambient temperature maximum junction temperature Conditions Min −0.5 VSS − 0.5 −65 −40 Max +6.0 ±20 5.5 ±50 85 100 200 +150 +85 +125 Unit V mA V mA mA mA mW °C °C °C PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 10 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 9. Static characteristics Table 9. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Supplies VDD IDD Istb supply voltage supply current standby current operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs VPOR VIL VIH IOL IL Ci I/Os VIL VIH IOL LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.5 V; VDD = 2.3 V VOL = 0.7 V; VDD = 2.3 V VOL = 0.5 V; VDD = 3.0 V VOL = 0.7 V; VDD = 3.0 V VOL = 0.5 V; VDD = 4.5 V VOL = 0.7 V; VDD = 4.5 V VOH HIGH-level output voltage IOH = −8 mA; VDD = 2.3 V IOH = −10 mA; VDD = 2.3 V IOH = −8 mA; VDD = 3.0 V IOH = −10 mA; VDD = 3.0 V IOH = −8 mA; VDD = 4.75 V IOH = −10 mA; VDD = 4.75 V ILIH ILIL Ci Co [1] [2] [3] [2] [2] [2] [2] [2] [2] [3] [3] [3] [3] [3] [3] Parameter Conditions Min 2.3 [1] Typ 290 225 0.25 1.5 6 6 10 13 14 19 17 24 3.7 3.7 Max 5.5 400 350 1 1.65 +0.3VDD 5.5 +1 10 +0.8 5.5 1 −100 5 5 Unit V μA μA μA V V V mA μA pF V V mA mA mA mA mA mA V V V V V V μA μA pF pF power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance VOL = 0.4 V VI = VDD = VSS VI = VSS −0.5 0.7VDD 3 −1 −0.5 2.0 8 10 8 10 8 10 1.8 1.7 2.6 2.5 4.1 4.0 - Input SCL; input/output SDA HIGH-level input leakage current LOW-level input leakage current input capacitance output capacitance VDD = 3.6 V; VI = VDD VDD = 5.5 V; VI = VSS VDD must be lowered to 0.2 V in order to reset part. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. The total current sourced by all I/Os must be limited to 85 mA. © NXP B.V. 2010. All rights reserved. PCA9536_5 Product data sheet Rev. 05 — 25 January 2010 11 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 10. Dynamic characteristics Table 10. Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tr tf tSP Port timing tv(Q) tsu(D) th(D) [1] [2] [3] Fast-mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1Cb[3] 20 + 0.1Cb[3] Max 400 0.9 300 300 50 Unit Max 100 3.45 1000 300 50 SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock rise time of both SDA and SCL signals fall time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter data output valid time data input set-up time data input hold time tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data output to be valid following SCL LOW. Cb = total capacitance of one bus line in pF. [1] [2] 0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 - kHz μs μs μs μs μs μs ns ns μs μs ns ns ns 100 1 200 - 100 1 200 - ns ns μs SDA tf tLOW tr SCL tHD;STA S tHIGH tSU;STA tHD;DAT tSU;STO Sr P S 002aab271 tSU;DAT tf tHD;STA tSP tBUF tr Fig 12. Definition of timing PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 12 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW tHIGH bit 6 (A6) bit 0 (R/W) acknowledge (A) STOP condition (P) 1/f SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab175 Rise and fall times refer to VIL and VIH Fig 13. I2C-bus timing diagram 11. Test information VDD open VSS VDD PULSE GENERATOR VI DUT RT VO RL 500 Ω CL 50 pF 002aab880 RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 14. Test circuitry for switching times from output under test CL 50 pF 500 Ω S1 2VDD open VSS 500 Ω 002aab881 Fig 15. Test circuit Table 11. Test tv(Q) Test data Load CL 50 pF RL 500 Ω 2VDD Switch PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 13 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 12. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 pin 1 index A1 (A 3) θ Lp L A 1 4 e bp wM detail X 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ 8o o 0 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 16. Package outline SOT96-1 (SO8) PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 14 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 D E A X c y HE vMA Z 8 5 A2 pin 1 index A1 (A3) A θ Lp L 1 e bp 4 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 θ 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 Fig 17. Package outline SOT505-1 (TSSOP8) PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 15 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm SOT908-1 0 1 scale 2 mm X D B A E A A1 c detail X terminal 1 index area terminal 1 index area 1 e1 e b 4 v w M M CAB C C y1 C y exposed tie bar (4×) L Eh exposed tie bar (4×) 8 5 Dh DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.3 0.2 c 0.2 D(1) 3.1 2.9 Dh 2.25 1.95 E(1) 3.1 2.9 Eh 1.65 1.35 e 0.5 e1 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT908-1 REFERENCES IEC JEDEC MO-229 JEITA EUROPEAN PROJECTION ISSUE DATE 05-09-26 05-10-05 Fig 18. Package outline SOT908-1 (HVSON8) PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 16 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 13. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 17 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 18 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 14. Acronym ACPI CDM DUT ESD FET GPIO HBM I2C-bus I/O LED MM POR SMBus Abbreviations Description Advanced Configuration and Power Interface Charged Device Model Device Under Test ElectroStatic Discharge Field-Effect Transistor General Purpose Input/Output Human Body Model Inter-Integrated Circuit bus Input/Output Light-Emitting Diode Machine Model Power-On Reset System Management Bus PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 19 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 16. Revision history Table 15. Revision history Release date 20100125 Data sheet status Product data sheet Change notice Supersedes PCA9536_4 Document ID PCA9536_5 Modifications: • Table 9 “Static characteristics”, sub-section “Supplies”: – IDD Typical value changed from “104 μA” to “290 μA” – IDD Maximum value changed from “175 μA” to “400 μA” • Table 10 “Dynamic characteristics”: Unit for “tf, fall time of both SDA and SCL signals” changed from “μs” to “ns” Remark: The changes made in this revision are to correct typographical errors only. There is no change in the performance of the device. PCA9536_4 PCA9536_3 PCA9536_2 (9397 750 14124) PCA9536_1 (9397 750 12895) 20070911 20061009 20040930 20040820 Product data sheet Product data sheet Objective data sheet Objective data sheet PCA9536_3 PCA9536_2 PCA9536_1 - PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 20 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9536_5 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 January 2010 21 of 22 NXP Semiconductors PCA9536 4-bit I2C-bus and SMBus I/O port 19. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 6.5 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4 Register 0 - Input Port register . . . . . . . . . . . . . 4 Register 1 - Output Port register. . . . . . . . . . . . 5 Register 2 - Polarity Inversion register . . . . . . . 5 Register 3 - Configuration register . . . . . . . . . . 6 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 7 Application design-in information . . . . . . . . . . 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Handling information. . . . . . . . . . . . . . . . . . . . 17 Soldering of SMD packages . . . . . . . . . . . . . . 17 Introduction to soldering . . . . . . . . . . . . . . . . . 17 Wave and reflow soldering . . . . . . . . . . . . . . . 17 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 January 2010 Document identifier: PCA9536_5