PCA9539PW

PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 05 — 28 July 2008 Product data sheet 1. General description The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection), input, output and polarity inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity inversion register. All registers can be read by the system master. The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and a different address range. The PCA9539; PCA9539R open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. In the PCA9539, the RESET pin causes the same reset/default I/O input configuration to occur without de-powering the device, holding the registers and I2C-bus state machine in their default state until the RESET input is once again HIGH. This input requires a pull-up to VDD. In the PCA9539R however, only the device state machine is initialized by the RESET pin and the internal general-purpose registers remain unchanged. Using the PCA9539R RESET pin will only reset the I2C-bus interface should it be stuck LOW to regain access to the I2C-bus. This allows the I/O pins to retain their last configured state so that they can keep any lines in their previously defined state and not cause system errors while the I2C-bus is being restored. Two hardware pins (A0, A1) vary the fixed I2C-bus address and allow up to four devices to share the same I2C-bus/SMBus. 2. Features I I I I 16-bit I2C-bus GPIO with interrupt and reset Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity inversion register NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset I I I I I I I I I Active LOW interrupt output Active LOW reset input Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 16 I/O pins which default to 16 inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Offered in three different packages: SO24, TSSOP24, and HVQFN24 3. Ordering information Table 1. Ordering information Package Name PCA9539D PCA9539PW PCA9539RPW PCA9539BS PCA9539RBS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 × 4 × 0.85 mm SOT616-1 SO24 TSSOP24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT137-1 SOT355-1 Type number 3.1 Ordering options Table 2. PCA9539D PCA9539PW PCA9539RPW PCA9539BS PCA9539RBS Ordering options Topside mark PCA9539D PCA9539PW PA9539RPW 9539 539R Temperature range −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C Type number PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 2 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 4. Block diagram PCA9539 PCA9539R A0 A1 write pulse read pulse I2C-BUS/SMBus CONTROL SCL SDA INPUT FILTER 8-bit INPUT/ OUTPUT PORTS 8-bit INPUT/ OUTPUT PORTS IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 VDD write pulse read pulse POWER-ON RESET VDD RESET VSS LP FILTER INT 002aad722 Remark: All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9539; PCA9539R PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 3 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 5. Pinning information 5.1 Pinning INT A1 RESET IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 1 2 3 4 5 6 7 8 9 24 VDD 23 SDA 22 SCL 21 A0 20 IO1_7 19 IO1_6 18 IO1_5 17 IO1_4 16 IO1_3 15 IO1_2 14 IO1_1 13 IO1_0 002aad719 INT A1 RESET IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 1 2 3 4 5 6 7 8 9 24 VDD 23 SDA 22 SCL 21 A0 20 IO1_7 19 IO1_6 18 IO1_5 17 IO1_4 16 IO1_3 15 IO1_2 14 IO1_1 13 IO1_0 002aad720 PCA9539D PCA9539PW PCA9539RPW IO0_6 10 IO0_7 11 VSS 12 IO0_6 10 IO0_7 11 VSS 12 Fig 2. Pin configuration for SO24 Fig 3. PCA9539BS PCA9539RBS 24 RESET 20 SDA 23 A1 Pin configuration for TSSOP24 terminal 1 index area IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 1 2 3 4 5 6 19 SCL 18 A0 17 IO1_7 16 IO1_6 15 IO1_5 14 IO1_4 13 IO1_3 IO1_2 12 002aad721 IO1_0 10 21 VDD 22 INT VSS 9 Transparent top view Fig 4. Pin configuration for HVQFN24 PCA9539_PCA9539R_5 IO1_1 11 7 IO0_6 IO0_7 8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 4 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 5.2 Pin description Table 3. Symbol INT A1 RESET Pin description Pin SO24, TSSOP24 1 2 3 HVQFN24 22 23 24 interrupt output (open-drain) address input 1 active LOW reset input. Driving this pin LOW causes: Description • • IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 VSS IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 A0 SCL SDA VDD [1] PCA9539 to reset its state machine and registers PCA9539R to reset its state machine, but has no effect on its registers 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9[1] 10 11 12 13 14 15 16 17 18 19 20 21 port 0 input/output 0 port 0 input/output 1 port 0 input/output 2 port 0 input/output 3 port 0 input/output 4 port 0 input/output 5 port 0 input/output 6 port 0 input/output 7 supply ground port 1 input/output 0 port 1 input/output 1 port 1 input/output 2 port 1 input/output 3 port 1 input/output 4 port 1 input/output 5 port 1 input/output 6 port 1 input/output 7 address input 0 serial clock line input serial data line open-drain input/output supply voltage HVQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 5 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6. Functional description Refer to Figure 1 “Block diagram of PCA9539; PCA9539R”. 6.1 Device address slave address 1 1 1 0 1 A1 A0 R/W fixed programmable 002aad724 Fig 5. PCA9539; PCA9539R device address 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. Table 4. Command 0 1 2 3 4 5 6 7 Command byte Register Input port 0 Input port 1 Output port 0 Output port 1 Polarity inversion port 0 Polarity inversion port 1 Configuration port 0 Configuration port 1 PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 6 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.2 Registers 0 and 1: Input port registers This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. Table 5. Bit Symbol Default Table 6. Bit Symbol Default Input port 0 register 7 I0.7 X 6 I0.6 X 5 I0.5 X 4 I0.4 X 3 I0.3 X 2 I0.2 X 1 I0.1 X 0 I0.0 X Input port 1 register 7 I1.7 X 6 I1.6 X 5 I1.5 X 4 I1.4 X 3 I1.3 X 2 I1.2 X 1 I1.1 X 0 I1.0 X 6.2.3 Registers 2 and 3: Output port registers This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 7. Bit Symbol Default Table 8. Bit Symbol Default Output port 0 register 7 O0.7 1 6 O0.6 1 5 O0.5 1 4 O0.4 1 3 O0.3 1 2 O0.2 1 1 O0.1 1 0 O0.0 1 Output port 1 register 7 O1.7 1 6 O1.6 1 5 O1.5 1 4 O1.4 1 3 O1.3 1 2 O1.2 1 1 O1.1 1 0 O1.0 1 6.2.4 Registers 4 and 5: Polarity inversion registers This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. Table 9. Bit Symbol Default Table 10. Bit Symbol Default PCA9539_PCA9539R_5 Polarity inversion port 0 register 7 N0.7 0 6 N0.6 0 5 N0.5 0 4 N0.4 0 3 N0.3 0 2 N0.2 0 1 N0.1 0 0 N0.0 0 Polarity inversion port 1 register 7 N1.7 0 6 N1.6 0 5 N1.5 0 4 N1.4 0 3 N1.3 0 2 N1.2 0 1 N1.1 0 0 N1.0 0 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 7 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.5 Registers 6 and 7: Configuration registers This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output. At reset, the device's ports are inputs. Table 11. Bit Symbol Default Table 12. Bit Symbol Default Configuration port 0 register 7 C0.7 1 6 C0.6 1 5 C0.5 1 4 C0.4 1 3 C0.3 1 2 C0.2 1 1 C0.1 1 0 C0.0 1 Configuration port 1 register 7 C1.7 1 6 C1.6 1 5 C1.5 1 4 C1.4 1 3 C1.3 1 2 C1.2 1 1 C1.1 1 0 C1.0 1 6.3 Power-on reset When power is applied to VDD, an internal power-on reset holds the PCA9539; PCA9539R in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9539; PCA9539R registers and SMBus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. 6.4 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). In the PCA9539 the registers and SMBus/I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input typically requires a pull-up to VDD. In the PCA9539R, only the device state machine is initialized. The internal general-purpose registers remain unchanged. Using the PCA9539R hardware reset pin will only reset the I2C-bus interface should it be stuck LOW to regain access to the I2C-bus. This allows the I/O pins to retain their last configured state so that they can keep any lines in their previously defined state and not cause system errors while the I2C-bus is being restored. 6.5 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists between the pin and either VDD or VSS. PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 8 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset data from shift register configuration register data from shift register write configuration pulse write pulse D FF CK Q D FF CK output port register input port register D FF read pulse CK Q Q2 output port register data VDD Q1 Q Q I/O pin VSS input port register data to INT polarity inversion register data from shift register write polarity pulse D FF CK 002aad723 Q polarity inversion register data At power-on reset, all registers return to default values. Fig 6. Simplified schematic of I/Os 6.6 Bus transactions 6.6.1 Writing to the port registers Data is transmitted to the PCA9539; PCA9539R by sending the device address and setting the least significant bit to a logic 0 (see Figure 5 “PCA9539; PCA9539R device address”). The command byte is sent after the address and determines which register will receive the data following the command byte. The eight registers within the PCA9539; PCA9539R are configured to operate as four register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and Configuration ports. After sending data to one register, the next data byte will be sent to the other register in the pair (see Figure 7 and Figure 8). For example, if the first byte is sent to Output port 1 (register 3), then the next byte will be stored in Output port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 9 of 31 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 05 — 28 July 2008 © NXP B.V. 2008. All rights reserved. PCA9539_PCA9539R_5 NXP Semiconductors SCL 1 2 3 4 5 6 7 8 9 command byte A 0 0 0 0 0 0 1 0 A 0.7 acknowledge from slave data to port 0 DATA 0 0.0 A 1.7 acknowledge from slave data to port 1 DATA 1 1.0 A P slave address SDA S 1 1 1 0 1 A1 A0 0 R/W START condition acknowledge from slave STOP condition write to port tv(Q) data out from port 0 tv(Q) data out from port 1 DATA VALID 002aad725 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Fig 7. Write to output port registers PCA9539; PCA9539R SCL 1 2 3 4 5 6 7 8 9 data to register data to register LSB DATA 0 A acknowledge from slave MSB DATA 1 LSB A P command byte A 0 0 0 0 0 1 1 0 A acknowledge from slave slave address SDA S 1 1 1 0 1 A1 A0 0 R/W MSB START condition acknowledge from slave STOP condition 002aad726 10 of 31 Fig 8. Write to configuration registers NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.6.2 Reading the port registers In order to read data from the PCA9539; PCA9539R, the bus master must first send the PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see Figure 5 “PCA9539; PCA9539R device address”). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9539; PCA9539R (see Figure 9, Figure 10 and Figure 11). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input port 1, then the next byte read would be Input port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. slave address SDA S 1 1 1 0 1 A1 A0 0 R/W acknowledge from slave slave address (cont.) S 1 1 1 0 1 A1 A0 1 R/W acknowledge from slave A A COMMAND BYTE A (cont.) START condition acknowledge from slave data from lower or upper byte of register MSB DATA (first byte) LSB A acknowledge from master MSB DATA (last byte) data from upper or lower byte of register LSB NA P STOP condition (repeated) START condition no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter 002aad727 Remark: Transfer can be stopped at any time by a STOP condition. Fig 9. Read from register PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 11 of 31 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 05 — 28 July 2008 © NXP B.V. 2008. All rights reserved. PCA9539_PCA9539R_5 NXP Semiconductors data into port 0 data into port 1 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset INT tv(INT_N) SCL 1 2 3 4 5 6 7 8 R/W 9 I0.x A 7 6 5 4 3 2 1 0 A 7 6 5 I1.x 4 3 2 1 0 A 7 6 5 I0.x 4 3 2 1 0 A 7 6 5 I1.x 4 3 2 STOP condition 1 0 1 P trst(INT_N) slave address SDA S 1 1 1 0 1 A1 A0 1 START condition read from port 0 acknowledge from slave acknowledge from master acknowledge from master acknowledge from master non acknowledge from master PCA9539; PCA9539R read from port 1 002aad728 Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read input port register). 12 of 31 Fig 10. Read input port register, scenario 1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 05 — 28 July 2008 © NXP B.V. 2008. All rights reserved. PCA9539_PCA9539R_5 NXP Semiconductors data into port 0 DATA 00 th(D) DATA 01 DATA 02 tsu(D) DATA 11 th(D) DATA 03 data into port 1 DATA 10 DATA 12 tsu(D) 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset INT tv(INT_N) SCL 1 2 3 4 5 6 7 8 R/W 9 I0.x A DATA 00 A acknowledge from master I1.x DATA 10 A acknowledge from master I0.x DATA 03 A acknowledge from master I1.x DATA 12 STOP condition 1 P trst(INT_N) slave address SDA S 1 1 1 0 1 A1 A0 1 START condition read from port 0 acknowledge from slave non acknowledge from master PCA9539; PCA9539R read from port 1 002aad729 Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read input port register). 13 of 31 Fig 11. Read input port register, scenario 2 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.6.3 Interrupt output The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input port register is read (see Figure 10). A pin configured as an output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around. Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input port register. 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 12). SDA SCL data line stable; data valid change of data allowed mba607 Fig 12. Bit transfer 7.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 13). SDA SDA SCL S START condition P STOP condition SCL mba608 Fig 13. Definition of START and STOP conditions PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 14 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 14). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 14. System configuration 7.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement 002aaa987 9 Fig 15. Acknowledgement on the I2C-bus PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 15 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 8. Application design-in information VDD (5 V) VDD MASTER CONTROLLER SCL SDA INT RESET VSS 10 kΩ 10 kΩ 10 kΩ 10 kΩ 2 kΩ VDD 100 kΩ (×3) SUB-SYSTEM 1 (e.g., temp sensor) INT PCA9539 SCL SDA INT RESET IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 B IO0_6 IO0_7 IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 VSS SUB-SYSTEM 3 (e.g., alarm system) 10 DIGIT NUMERIC KEYPAD ALARM enable SUB-SYSTEM 2 (e.g., counter) RESET A controlled switch (e.g., CBT device) VDD A1 A0 002aad730 Device address configured as 1110 100X for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7 and (IO1_0 to IO1_7) configured as inputs. Fig 16. Typical application PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 16 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 8.1 Minimizing IDD when the I/Os are used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 16. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 17 shows a high value resistor in parallel with the LED. Figure 18 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. VDD 3.3 V 5V VDD LED 100 kΩ VDD LED LEDn LEDn 002aac189 002aac190 Fig 17. High value resistor in parallel with the LED Fig 18. Device supplied by a lower voltage 9. Limiting values Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI/O IO II IDD ISS Ptot Tstg Tamb Tj(max) Parameter supply voltage voltage on an input/output pin output current input current supply current ground supply current total power dissipation storage temperature ambient temperature maximum junction temperature operating on an I/O pin Conditions Min −0.5 −65 −40 Max +6.0 ±50 ±20 160 200 200 +150 +85 125 Unit V V mA mA mA mA mW °C °C °C VSS − 0.5 6 PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 17 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 10. Static characteristics Table 14. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Supplies VDD IDD Istb supply voltage supply current standby current Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs VPOR VIL VIH IOL IL Ci I/Os VIL VIH IOL VOH LOW-level input voltage HIGH-level input voltage LOW-level output current HIGH-level output voltage VDD = 2.3 V to 5.5 V; VOL = 0.5 V VDD = 2.3 V to 5.5 V; VOL = 0.7 V IOH = −8 mA; VDD = 2.3 V IOH = −10 mA; VDD = 2.3 V IOH = −8 mA; VDD = 3.0 V IOH = −10 mA; VDD = 3.0 V IOH = −8 mA; VDD = 4.75 V IOH = −10 mA; VDD = 4.75 V ILIH ILIL Ci Co IOL VIL VIH ILI [1] [2] [2] [2] [3] [3] [3] [3] [3] [3] Conditions Min 2.3 −0.5 0.7VDD Typ 135 0.25 0.25 1.5 6 9 11 3.7 3.7 - Max 5.5 200 1 1 1.65 Unit V µA µA µA V power-on reset voltage[1] LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance no load; VI = VDD or VSS Input SCL; input/output SDA +0.3VDD V 5.5 +1 10 V mA µA pF VOL = 0.4 V VI = VDD = VSS VI = VSS 3 −1 −0.5 0.7VDD 8 10 1.8 1.7 2.6 2.5 4.1 4.0 - +0.3VDD V 5.5 1 −1 5 5 V mA mA V V V V V V µA µA pF pF mA HIGH-level input leakage current LOW-level input leakage current input capacitance output capacitance LOW-level output current LOW-level input voltage HIGH-level input voltage input leakage current VDD = 5.5 V; VI = VDD VDD = 5.5 V; VI = VSS Interrupt INT VOL = 0.4 V 3 −0.5 0.7VDD −1 Select inputs A0, A1 and RESET +0.3VDD V 5.5 +1 V µA VDD must be lowered to 0.2 V for at least 5 µs in order to reset part. Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. © NXP B.V. 2008. All rights reserved. PCA9539_PCA9539R_5 Product data sheet Rev. 05 — 28 July 2008 18 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset [3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7). 11. Dynamic characteristics Table 15. Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tVD;ACK tHD;DAT tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data valid acknowledge time data hold time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter data output valid time data input set-up time data input hold time valid time on pin INT reset time on pin INT reset pulse width reset recovery time reset time [5][6] [4] [3] [3] [2] [1] Fast-mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0.1 0 50 100 1.3 0.6 20 + 0.1Cb 20 + 0.1Cb Max 400 0.9 300 300 50 Unit Max 100 3.45 300 1000 50 0 4.7 4.0 4.7 4.0 0.3 0 300 250 4.7 4.0 - kHz µs µs µs µs µs ns ns ns µs µs ns ns ns Port timing tv(Q) tsu(D) th(D) tv(INT_N) trst(INT_N) tw(rst) trec(rst) trst [1] [2] [3] [4] [5] [6] 150 1 4 0 400 200 4 4 - 150 1 4 0 400 200 4 4 - ns ns µs µs µs ns ns ns Interrupt timing RESET timing tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF. tv(Q) measured from 0.7VDD on SCL to 50 % I/O output. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus. PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 19 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset SDA tBUF tLOW SCL tr tf tHD;STA tSP tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P 002aaa986 Fig 19. Definition of timing on the I2C-bus START SCL ACK or read cycle SDA 30 % trst RESET 50 % trec(rst) 50 % tw(rst) trst IOn 50 % after reset, I/Os reconfigured as inputs 002aad732 50 % Fig 20. Definition of RESET timing in PCA9539 START SCL ACK or read cycle SDA 30 % trst RESET 50 % trec(rst) 50 % tw(rst) trst IOn 50 % after reset, I/Os unchanged; device state machine reset 002aad733 50 % Fig 21. Definition of RESET timing in PCA9539R PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 20 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset SCL 2 1 0 A P 70 % 30 % SDA tsu(D) th(Q) input tv(INT_N) INT 002aad734 50 % trst(INT_N) Fig 22. Expanded view of read input port register SCL 2 1 0 A P 70 % SDA tv(Q) output 002aad735 50 % Fig 23. Expanded view of write to output port register protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW tHIGH bit 6 (A6) bit 1 (D1) bit 0 (D0) acknowledge (A) STOP condition (P) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab285 Rise and fall times refer to VIL and VIH. Fig 24. I2C-bus timing diagram PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 21 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 12. Test information VDD open GND VDD PULSE GENERATOR VI DUT RT VO RL 500 Ω CL 50 pF 002aab284 RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance of Zo of the pulse generators. Fig 25. Test circuitry for switching times RL S1 from output under test CL 50 pF 500 Ω RL 500 Ω 2VDD open GND 002aac226 Fig 26. Load circuit Table 16. Test tv(Q) Test data Load CL 50 pF RL 500 Ω 2 × VDD Switch PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 22 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 13. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c y HE vMA Z 24 13 Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 27. Package outline SOT137-1 (SO24) PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 23 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 12 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 28. Package outline SOT355-1 (TSSOP24) PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 24 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-1 D B A terminal 1 index area A A1 E c detail X e1 1/2 e C b 12 vMCAB wMC 13 e y1 C y e 7 L 6 Eh 1/2 e e2 1 18 terminal 1 index area 24 Dh 0 19 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 29. Package outline SOT616-1 (HVQFN24) PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 25 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 14. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 26 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 17 and 18 Table 17. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 18. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 27 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 19. Acronym ACPI CBT CDM CMOS ESD FET FF GPIO HBM I2C-bus I/O LED MM SMBus Abbreviations Description Advanced Configuration and Power Interface Cross-Bar Technology Charged-Device Model Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Field-Effect Transistor Flip-Flop General Purpose Input/Output Human Body Model Inter-Integrated Circuit bus Input/Output Light Emitting Diode Machine Model System Management Bus PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 28 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 17. Revision history Table 20. Revision history Release date 20080728 Data sheet status Product data sheet Change notice Supersedes PCA9539_PCA9539R_4 Document ID PCA9539_PCA9539R_5 Modifications: • Section 1 “General description”: – split (old) 4th paragraph to 2 (new) 4th and (new) 5th paragraphs – (new) 5th paragraph re-written • Table 2 “Ordering options”: – changed Topside mark for Type number PCA9539RPW from “PCA9539RPW” to “PA9539RPW” – changed Topside mark for Type number PCA9539RBS from “9539R” to “539R” PCA9539_PCA9539R_4 PCA9539_3 PCA9539_2 (9397 750 14048) PCA9539_1 (9397 750 12898) 20080519 20060921 20040930 20040827 Product data sheet Product data sheet Product data sheet Product data sheet - PCA9539_3 PCA9539_2 PCA9539_1 - PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 29 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 28 July 2008 30 of 31 NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 20. Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 7 7.1 7.1.1 7.2 7.3 8 8.1 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 Registers 0 and 1: Input port registers . . . . . . . 7 Registers 2 and 3: Output port registers. . . . . . 7 Registers 4 and 5: Polarity inversion registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Registers 6 and 7: Configuration registers . . . . 8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9 Writing to the port registers . . . . . . . . . . . . . . . 9 Reading the port registers . . . . . . . . . . . . . . . 11 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 14 Characteristics of the I2C-bus. . . . . . . . . . . . . 14 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 START and STOP conditions . . . . . . . . . . . . . 14 System configuration . . . . . . . . . . . . . . . . . . . 15 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application design-in information . . . . . . . . . 16 Minimizing IDD when the I/Os are used to control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 Static characteristics. . . . . . . . . . . . . . . . . . . . 18 Dynamic characteristics . . . . . . . . . . . . . . . . . 19 Test information . . . . . . . . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Handling information. . . . . . . . . . . . . . . . . . . . 26 Soldering of SMD packages . . . . . . . . . . . . . . 26 Introduction to soldering . . . . . . . . . . . . . . . . . 26 Wave and reflow soldering . . . . . . . . . . . . . . . 26 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 27 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 18 18.1 18.2 18.3 18.4 19 20 Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 30 30 31 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 July 2008 Document identifier: PCA9539_PCA9539R_5