CAT1026YI-42

H CAT1026, CAT1027 Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM LE FEATURES ■ Precision VCC power supply voltage monitor ■ 16-Byte page write buffer — Five threshold voltage options ■ Built-in inadvertent write protection — Externally adjustable down to 1.25 V A D F R E ETM ■ Low power CMOS technology — 5V, 3.3 V and 3 V systems ■ Additional voltage monitoring EE GEN FR ALO ■ 1,000,000 Program/Erase cycles ■ Manual reset capability ■ Watchdog timer (CAT1027 only) ■ 100 year data retention ■ Active high or low reset ■ 8-pin DIP, SOIC, TSSOP, MSOP or TDFN — Valid reset guaranteed to VCC = 1 V 2 ■ 400 kHz I C bus ■ 3.0 V to 5.5 V operation (3 x 3 mm foot-print) packages — TDFN max height is 0.8mm ■ Industrial and extended temperature ranges DESCRIPTION The CAT1026 and CAT1027 are complete memory and supervisory solutions for microcontroller-based systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I2C bus. The CAT1026 and CAT1027 provide a precision VCC sense circuit with five reset threshold voltage options that support 5V, 3.3V and 3V systems. The power supply monitor and reset circuit protects memory and systems controllers during power up/down and against brownout conditions. If power supply voltages are out of tolerance reset signals become active preventing the system microcontroller, ASIC, or peripherals from operating. used as an input for push-button manual reset capability. The CAT1026 and CAT1027 provide an auxiliary voltage sensor input, VSENSE, which is used to monitor a second system supply. The auxiliary high impedance comparator drives the open drain output, VLOW, whenever the sense voltage is below 1.25V threshold. The CAT1027 is designed with a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. The CAT1027 features a watchdog timer interrupt input, WDI. The on-chip 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the The CAT1026 features two open drain reset outputs: reset threshold during power up. one (RESET) drives high and the other (RESET) drives Available packages include an 8-pin DIP, 8-pin SOIC, 8low whenever VCC falls below the threshold. Reset pin TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN outputs become inactive typically 200 ms after the package thickness is 0.8mm maximum. TDFN footprint is supply voltage exceeds the reset threshold value. With 3x3mm. both active high and low reset signals, interface to microcontrollers and other ICs is simple. CAT1027 has only a RESET output. In addition, the RESET pin can be © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc No. 3010, Rev. K CAT1026, CAT1027 BLOCK DIAGRAM EXTERNAL LOAD SENSE AMPS SHIFT REGISTERS DOUT ACK RESET Threshold Options Part Dash Minimum Maximum Number Threshold Threshold VCC WORD ADDRESS BUFFERS VSS COLUMN DECODERS START/STOP LOGIC SDA 2kbit EEPROM XDEC CONTROL LOGIC DATA IN STORAGE VCC Monitor HIGH VOLTAGE/ TIMING CONTROL VCC STATE COUNTERS + RESET Controller - WDI (CAT1027) VREF Auxiliary Voltage Monitor VSENSE + - RESET (CAT1026) SCL SLAVE ADDRESS COMPARATORS RESET VLOW VREF PIN CONFIGURATION DIP Package (P, L) SOIC Package (J, W) TSSOP Package (U, Y) MSOP Package (R, Z) VLOW 1 RESET 2 CAT1026 8 VCC 7 RESET (Bottom View) TDFN Package: 3mm x 3mm 0.8mm maximum height - (RD4, ZD4) VCC 8 1 VLOW RESET 7 2 RESET 3 VSENSE CAT1026 VSENSE 3 6 SCL SCL 6 VSS 4 5 SDA SDA 5 4 VSS 8 VCC VCC 8 1 VLOW 7 WDI WDI 7 2 RESET VSENSE 3 6 SCL SCL 6 3 VSENSE VSS 4 5 SDA SDA 5 4 VSS VLOW 1 RESET 2 CAT1027 Doc. No. 3010, Rev. K CAT1027 2 -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 CAT1026, CAT1027 PIN DESCRIPTION RESET/RESET RESET: RESET OUTPUTS RESET (RESET CAT1026 Only) These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the RESET pin must be connected through a pull-up resistor. VSENSE: AUXILIARY VOLTAGE MONITOR INPUT The VSENSE input is a second voltage monitor which is compared against CAT1026 and CAT1027 internal reference voltage of 1.25V typically. Whenever the input voltage is lower than 1.25V, the open drain VLOW output will be driven low. An external resistor divider is used to set the voltage level to be sensed. Connect VSENSE to VCC if unused. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. VLOW: AUXILIARY VOLTAGE MONITOR OUTPUT This open drain output goes low when VSENSE is less than 1.25V and goes high when VSENSE exceeds the reference voltage. WDI (CAT1027 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active. SCL: SERIAL CLOCK Serial clock input. PIN FUNCTIONS Pin Name RESET OPERATING TEMPERATURE RANGE Function Industrial -40˚C to 85˚C Active Low Reset Input/Output Extended -40˚C to 125˚C VSS Ground SDA Serial Data/Address SCL Clock Input RESET VCC VSENSE Active High Reset Output (CAT1026 only) Power Supply Auxiliary Voltage Monitor Input VLOW Auxiliary Voltage Monitor Output WDI Watchdog Timer Interrupt (CAT1027 only) CAT10XX FAMILY OVERVIEW Device Manual Reset Input Pin Watchdog Watchdog Monitor Pin Write Protection Pin Independent Auxiliary Voltage Sense RESET: Active High and LOW EEPROM CAT1021 SDA 2k CAT1022 SDA 2k CAT1023 WDI 2k CAT1024 2k CAT1025 2k CAT1026 2k CAT1027 WDI 2k For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets. 3 Doc No. 3010, Rev. K CAT1026, CAT1027 ABSOLUTE MAXIMUM RATINGS Lead Soldering Temperature (10 seconds) ...... 300°C Temperature Under Bias ................. –55°C to +125°C Output Short Circuit Current(2) ........................ 100 mA Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ........... –2.0 V to VCC + 2.0 V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. VCC with Respect to Ground ............ –2.0 V to + 7.0 V Package Power Dissipation Capability (TA = 25°C) .................................. 1.0 W DC OPERATING CHARACTERISTICS VCC = 3.0 V to 5.5 V and over the recommended temperature conditions unless otherwise specified. Symbol Parameter Test Conditions Min ILI Input Leakage Current VIN = GND to Vcc ILO Output Leakage Current VIN = GND to Vcc ICC1 Power Supply Current (Write) ICC2 Power Supply Current (Read) ISB Standby Current VIL(1) Input Low Voltage -0.5 0.3 x Vcc V (1) Input High Voltage 0.7 x Vcc Vcc + 0.5 V 0.4 V VIH Typ Max Units -2 10 µA -10 10 µA fSCL = 400 kHz VCC = 5.5 V 3 mA fSCL = 400 kHz VCC = 5.5 V 1 mA CAT1026 50 VIN = GND or Vcc CAT1027 60 Vcc = 5.5V VOL Output Low Voltage (SDA, RESET , VLOW) IOL = 3 mA VCC = 2.7 V VOH Output High Voltage (RESET) IOH = -0.4 mA VCC = 2.7 V Vcc 0.75 CAT102x-45 (VCC = 5.0 V) 4.50 4.75 CAT102x-42 (VCC = 5.0 V) 4.25 4.50 CAT102x-30 (VCC = 3.3 V) 3.00 3.15 CAT102x-28 (VCC = 3.3 V) 2.85 3.00 CAT102x-25 (VCC = 3.0 V) 2.55 2.70 Reset Threshold (VCC Monitor) VTH µA V V VRVALID Reset Output Valid VCC Voltage 1.00 V VRT(2) Reset Threshold Hysteresis 15 mV VREF Auxiliary Voltage Monitor Threshold 1.2 1.25 Notes: 1. VIL min and VIH max are reference values only and are not tested. 2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. Doc. No. 3010, Rev. K 4 1.3 V CAT1026, CAT1027 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol COUT (1) CIN(1) Test Test Conditions Max Units VOUT = 0 V 8 pF VIN = 0 V 6 pF Output Capacitance Input Capacitance AC CHARACTERISTICS VCC = 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle(2) Symbol Parameter fSCL Min Max Units Clock Frequency 400 kHz tSP Input Filter Spike Suppression (SDA, SCL) 100 ns tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 0.6 µs tR(1) SDA and SCL Rise Time 300 ns tF(1) SDA and SCL Fall Time 300 ns tHD;STA Start Condition Hold Time 0.6 µs tSU;STA Start Condition Setup Time (for a Repeated Start) 0.6 µs tHD;DAT Data Input Hold Time 0 ns tSU;DAT Data Input Setup Time 100 ns tSU;STO Stop Condition Setup Time 0.6 µs tAA SCL Low to Data Out Valid tDH Data Out Hold Time 50 ns tBUF(1) Time the Bus must be Free Before a New Transmission Can Start 1.3 µs tWC(3) Write Cycle Time (Byte or Page) 900 5 ns ms Notes: 1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 2. Test Conditions according to “AC Test Conditions” table. 3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. 5 Doc No. 3010, Rev. K CAT1026, CAT1027 VOLTAGE MONITOR AND RESET CIRCUIT AC CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units tPURST Reset Timeout Note 2 130 200 270 ms tRPD1 VTH to RESET Output Delay Note 3 5 µs tGLITCH VCC Glitch Reject Pulse Width Note 4, 6 30 ns tWD Watchdog Timeout Note 1 2.1 sec tRPD2 VSENSE to VLOW Delay Note 5 5 µs Max Units 1.0 1.6 POWER-UP TIMING6,7 Test Conditions Symbol Parameter Min Typ tPUR Power-Up to Read Operation 270 ms tPUW Power-Up to Write Operation 270 ms AC TEST CONDITIONS Parameter Conditions Input Pulse Voltages 0.2 VCC to 0.8 VCC Input Rise and Fall Times 10 ns Input Reference Voltages 0.3 VCC , 0.7 VCC Output Reference Voltages 0.5 VCC Output Load Current Source: IOL = 3 mA; CL = 100 pF RELIABILITY CHARACTERISTICS Symbol NEND (6) Parameter Reference Test Method Min Max Units Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR(6) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(6) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(6)(8) Latch-Up JEDEC Standard 17 100 mA Notes: 1. Test Conditions according to “AC Test Conditions” table. 2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table. 3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table. 4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data. 5. 0 < VSENSE ≤ VCC, VLOW Output Reference Voltage and Load according to “AC Test Conditions” Table. 6. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 7. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. 8. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to VCC + 1 V. Doc. No. 3010, Rev. K 6 CAT1026, CAT1027 DEVICE OPERATION Reset Controller Description The CAT1026 and CAT1027 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs. Data Protection The CAT1026 and CAT1027 devices have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200 ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2 V. During power-down, the RESET outputs will be active when VCC falls below VTH. The RESET output will be valid so long as VCC is >1.0 V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Reset output timing is shown in Figure 1. In addition, to avoid data corruption due to the loss of power supply voltage during the memory internal write operation, the system controller should monitor the unregulated DC power. Using the second voltage sensor, VSENSE, to monitor an unregulated power supply, the CAT1026 and CAT1027 signals an impending power failure by setting VLOW low. Manual Reset Capability The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET input will initiate a reset timeout after detecting a high to low transition. When RESET I/O is driven to the active state, the 200 msec timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT1027 device will provide a reset signal after a time-out interval of 1.6 seconds for a lack of activity. CAT1027 is designed with the Watchdog timer feature on the WDI pin. If WDI does not toggle within 1.6 second intervals, the reset condition will be generated on reset output. The watchdog timer is cleared by any transition on monitored line. Monitoring Two Voltages The CAT1026 and CAT1027 feature a second voltage sensor, VSENSE, which drives the open drain VLOW output low whenever the input voltage is below 1.25 V. The auxiliary voltage monitor timing is shown in Figure 2. As long as reset signal is asserted, the watchdog timer will not count and will stay cleared. By using an external resistor divider the sense circuitry can be set to monitor a second supply in the system. The circuit shown in Figure 3 provides an externally adjustable threshold voltage, VTH_ADJ to monitor the auxiliary voltage. The low leakage current at VSENSE allows the use of large value resistors, to reduce the system power consumption. The VLOW output can be externally connected to the RESET output to generate a reset condition when either of the supplies is invalid. In other applications, VLOW signal can be used to interrupt the system controller for an impending power failure notification. 7 Doc No. 3010, Rev. K CAT1026, CAT1027 t Figure 1. RESET Output Timing GLITCH VTH VRVALID t PURST VCC t RPD1 t PURST t RPD1 RESET RESET Figure 2. Auxiliary Voltage Monitor Timing VREF VSENSE tRPD2 tRPD2 tRPD2 VLOW Figure 3. Auxiliary Voltage Monitor VCC VAUX CAT1026/27 Externally adjustable threshold R1 VTH-ADJ VLOW VSENSE R2 VTH-ADJ = VREF × Doc. No. 3010, Rev. K R + R2 R1 + R 2 = 1.25V × 1 R2 R2 8 Power Fail Interrupt tRPD2 CAT1026, CAT1027 device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT1026 and CAT1027 monitor the SDA and SCL lines and will not respond until this condition is met. EMBEDDED EEPROM OPERATION The CAT1026 and CAT1027 feature a 2kbit embedded serial EEPROM that supports the I 2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. I2C Bus Protocol The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. After the Master sends a START condition and the slave address byte, the CAT1026 and CAT1027 monitor the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1026 and CAT1027 then perform a Read or Write operation depending on the R/W bit. START Condition The START Condition precedes all commands to the Figure 4. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 5. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION 9 START CONDITION ADDRESS Doc No. 3010, Rev. K CAT1026, CAT1027 ACKNOWLEDGE WRITE OPERATIONS After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1026 and CAT1027 acknowledge once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. The CAT1026 and CAT1027 respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT1026 and CAT1027 begin a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1026 and CAT1027 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Figure 6. Start/Stop Timing SDA SCL START BIT STOP BIT Figure 7. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 8. Slave Address Bits Default Configuration CAT Doc. No. 3010, Rev. K 1 0 1 0 0 0 10 0 R/W CAT1026, CAT1027 Page Write The CAT1026 and CAT1027 write up to 16 bytes of data in a single write cycle, by using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1026 and CAT1027 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1026 and CAT1027 in a single write cycle. Figure 9. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS S T O P DATA P S A C K A C K A C K Figure 10. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS (n) DATA n S T DATA n+15 O P DATA n+1 S P A C K A C K 11 A C K A C K A C K Doc No. 3010, Rev. K CAT1026, CAT1027 Acknowledge Polling Read Operations Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1026 and CAT1027 initiate the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. The READ operation for the CAT1026 and CAT1027 is initiated in the same manner as the write operation with one exception, the R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Figure 11. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S T O P SLAVE ADDRESS S P A C K DATA N O A C K SCL SDA 8 9 8TH BIT DATA OUT Doc. No. 3010, Rev. K NO ACK 12 STOP CAT1026, CAT1027 Immediate/Current Address Read Sequential Read The CAT1026 and CAT1027 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1026 and CAT1027 receive a slave address (with the R/W bit set t o one), an acknowledge is issued, and the requested 8-bit byte is transmitted. The master device does not send an acknowledge, but will generate a STOP condition. The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1026 and CAT1027 send the inital 8-bit byte requested, the Master responds with an acknowledge which tells the device it requires more data. The CAT1026 and CAT1027 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition. The data being transmitted from the CAT1026 and CAT1027 is sent sequentially with the data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT1026 and CAT1027 address bits so that the entire memory array can be read during one operation. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1026 and CAT1027 acknowledge, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT1026 and CAT1027 then respond with an acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Figure 12. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS (n) S T O P SLAVE ADDRESS P S S A C K A C K A C K DATA n N O A C K Figure 13. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K 13 Doc No. 3010, Rev. K CAT1026, CAT1027 PACKAGE OUTLINES 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) 0.245 (6.17) 0.295 (7.49) 0.300 (7.62) 0.325 (8.26) D 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX 0.015 (0.38) — 0.110 (2.79) 0.150 (3.81) 0.100 (2.54) BSC 0.310 (7.87) 0.380 (9.65) 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) Dimension D Pkg Min Max 8L 0.355 (9.02) 0.400 (10.16) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. Doc. No. 3010, Rev. K 14 CAT1026, CAT1027 8-LEAD 150 MIL WIDE SOIC (J, W) 0.1497 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) D 0.0532 (1.35) 0.0688 (1.75) 0.050 (1.27) BSC 0.0040 (0.10) 0.0098 (0.25) 0.013 (0.33) 0.020 (0.51) 0.0099 (0.25) X 45° 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0°–8° 0.016 (0.40) 0.050 (1.27) Dimension D Pkg Min Max 8L 0.1890(4.80) 0.1968(5.00) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 3. Lead coplanarity is 0.004" (0.102mm) maximum. 15 Doc No. 3010, Rev. K CAT1026, CAT1027 8-LEAD TSSOP (U, Y) Doc. No. 3010, Rev. K 16 CAT1026, CAT1027 8 LEAD MSOP (R, Z) 0.38 0.28 0.0150 0.0110 0.1970 0.1890 5.00 4.80 S 0.0256 [0.65] BSC 0.1220 0.1142 3.10 2.90 0.0374 0.0295 0.0433 [1.10] MAX. 0.039 [0.10] MAX. S 0.0059 0.0020 0.15 0.05 0.95 0.75 S 0.0150 0.0110 0.38 0.28 WITH PLATING 0.0276 0.0157 0.70 0.40 0.1220 0.1142 3.10 2.90 0.0091 0.0051 0.23 0.13 0.0050 [0.127] 0˚ - 6˚ WITH PLATING BASE METAL 0.0118 [0.30] REF. SECTION A - A Notes: (1) All dimensions are in mm Angles in degrees. 2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side. 3 Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side. 4 Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm. (5) This part is compliant with JEDEC Specification MO-187 Variations AA. (6) Lead span/stand off height/coplanarity are considered as special characteristics. (S) (7) Controlling dimensions in inches. [mm] 17 Doc No. 3010, Rev. K CAT1026, CAT1027 TDFN 3X3 PACKAGE (RD4, ZD4) 5 0.75 + 0.05 A B 3.00 + 0.10 (S) 8 2X 1 3.00 + 0.10 (S) 4 0.15 C 2X 0.0 - 0.05 0.15 C PIN 1 INDEX AREA 5 8 1.50 + 0.10 0.75 + 0.05 C 2.30 + 0.10 C0.35 0.25 min. PIN 1 ID 1 0.30 + 0.07 (8x) 1.95 REF. (2x) NOTE: 1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY SHALL NOT EXCEED 0.08 mm. 3. WARPAGE SHALL NOT EXCEED 0.10 mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S) 5. REFER JEDEC MO-229 / WEEC Doc. No. 3010, Rev. K 18 0.30 + 0.10 (8x) 0.65 TYP. (6x) CAT1026, CAT1027 Ordering Information Prefix CAT Optional Company ID Device # Suffix 1026 Product Number 1026: 2K 1027: 2K J I Temperature Range I = Industrial (-40˚C to 85˚C) E = Extended (-40˚C to +125˚C) Package P: PDIP J: SOIC R: MSOP U: TSSOP RD4: 8-pad TDFN (3x3mm) L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free) ZD4: TDFN 3x3mm (Lead free, Halogen free) -30 TE13 Tape & Reel SOIC: 2000/Reel TSSOP: 2000/Reel MSOP: 2500/Reel TDFN: 2000/Reel Reset Threshold Voltage 45: 4.5-4.75V 42: 4.25-4.5V 30: 3.0-3.15V 28: 2.85-3.0V 25: 2.55-2.7V Note: (1) The device used in the above example is a CAT1026JI-30TE13 (Supervisory circuit with I2C serial 2k CMOS EEPROM, SOIC, Industrial Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel). 19 Doc No. 3010, Rev. K REVISION HISTORY Date Rev. Reason 9/25/2003 F Added Green Package logo Updated DC Operating Characteristic notes Updated Reliability Characteristics notes 11/7/2003 G Eliminated Automotive temperature range Updated Ordering Information with “Green” package marking codes 4/12/2004 H Eliminated data sheet designation Updated Reel Ordering Information 11/1/2004 I Changed SOIC package designators Eliminated 8-pad TDFN (3x4.9mm) package Added package outlines 11/04/04 J Update Pin Configuration 11/11/04 M Update Features Update Description Updae DC Operating Characteristic Update AC Characteristics Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ I2C is a trademark of Philips Corporation. Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 3010 K 11/11/04