CAT24C01, CAT24C02,
CAT24C04, CAT24C08, CAT24C16
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
FEATURES
DEVICE DESCRIPTION
The CAT24C01/02/04/08/16 are 1-Kb, 2-Kb, 4-Kb,
8-Kb and 16-Kb respectively CMOS Serial EEPROM
devices organized internally as 8/16/32/64 and 128
pages respectively of 16 bytes each. All devices
support both the Standard (100kHz) as well as Fast
(400kHz) I²C protocol.
Supports Standard and Fast I²C protocol
1.7V to 5.5V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I²C Bus Inputs (SCL and SDA).
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial and Extended temperature range
RoHS-compliant 8-lead PDIP, SOIC, MSOP
and TSSOP, 8-pad TDFN and 5-lead TSOT-23
packages.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile
memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data
serially while automatically incrementing the internal
address count.
External address pins make it possible to address
up to eight CAT24C01 or CAT24C02, four CAT24C04,
two CAT24C08 and one CAT24C16 device on the
same bus.
For Ordering Information details, see page 16.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L), SOIC (W),
TSSOP (Y), MSOP (Z),
TDFN (VP2)
VCC
TSOT-23 (TD)
CAT24C16 / 08 / 04 / 02 / 01
1
NC / NC / NC / A0 / A0
1
8
VCC SCL
NC / NC / A1 / A1 / A1
2
7
WP
VSS
2
NC / A2 / A2 / A2 / A2
3
6
SCL
VSS
4
5
SDA SDA
3
5
WP
4
VCC
SCL
A2, A1, A0
For the location of Pin 1, please consult the
corresponding package drawing.
A0, A1, A2
SDA
WP
PIN FUNCTIONS
Name
CAT24Cxx
VSS
Description
Device Address Input
SDA
Serial Data Input/Output
SCL
Serial Clock Input
WP
Write Protect Input
VCC
Power Supply
VSS
Ground
NC
Not Connect
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
*
1
The Green & Gold seal identifies RoHS-compliant packaging,
using NiPdAu pre-plated lead frames.
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature
-65°C to +150°C
Voltage on any pin with respect to Ground
(2)
-0.5V to +6.5V
RELIABILITY CHARACTERISTICS(3)
Symbol
NEND
(4)
TDR
Parameter
Min
Units
Endurance
1,000,000
Program/Erase Cycles
100
Years
Data Retention
D.C. OPERATING CHARACTERISTICS
VCC = 1.8V to 5.5V, TA = -40°C to +125°C and VCC = 1.7V to 5.5V, TA = -40°C to +85°C, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 400kHz
1
mA
ICCW
Write Current
Write, fSCL = 400kHz
2
mA
Standby Current
All I/O Pins at GND or VCC
ISB
IL
I/O Pin Leakage
Pin at GND or VCC
TA = -40°C to +85°C
1
TA = -40°C to
2
TA = -40°C to +85°C
1
TA = -40°C to
2
µA
µA
VIL
Input Low Voltage
-0.5
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage VCC < 2.5V, IOL = 3.0mA
0.4
V
VOL2
Output Low Voltage VCC < 2.5V, IOL = 1.0mA
0.2
V
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8V to 5.5V, TA = -40°C to +125°C and VCC = 1.7V to 5.5V, TA = -40°C to +85°C, unless otherwise specified.
Symbol Parameter
Max
Units
CIN
(3)
SDA I/O Pin Capacitance
VIN = 0V
8
pF
CIN
(3)
Input Capacitance (other pins)
VIN = 0V
6
pF
(5)
IWP
WP Input Current
Conditions
VIN < 0.5 x VCC, VCC = 5.5V
200
VIN < 0.5 x VCC, VCC = 3.3V
150
VIN < 0.5 x VCC, VCC = 1.8V
100
VIN > 0.5 x VCC
µA
1
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C.
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
Doc. No. MD-1115 Rev. G
2
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
A.C. CHARACTERISTICS(1)
VCC = 1.8V to 5.5V, TA = -40°C to +125°C and VCC = 1.7V to 5.5V, TA = -40°C to +85°C, unless otherwise specified.
Symbol
Standard
Parameter
Min
FSCL
tHD:STA
Max
Clock Frequency
Fast
Min
100
START Condition Hold Time
Units
Max
400
kHz
4
0.6
µs
tLOW
Low Period of SCL Clock
4.7
1.3
µs
tHIGH
High Period of SCL Clock
4
0.6
µs
4.7
0.6
µs
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
µs
tSU:DAT
Data In Setup Time
250
100
ns
tR
SDA and SCL Rise Time
1000
300
ns
tF(2)
SDA and SCL Fall Time
300
300
ns
tSU:STO
STOP Condition Setup Time
tBUF
Bus Free Time Between STOP and START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
Ti(2)
Noise Pulse Filtered at SCL and SDA Inputs
4
0.6
µs
4.7
1.3
µs
3.5
100
0.9
100
100
µs
ns
100
ns
tSU:WP
WP Setup Time
0
0
µs
tHD:WP
WP Hold Time
2.5
2.5
µs
tWR
tPU
(2, 3)
Write Cycle Time
5
5
ms
Power-up to Ready Mode
1
1
ms
A.C. TEST CONDITIONS
Input Drive Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Time
≤ 50ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Level
0.5 x VCC
Output Test Load
Current Source IOL = 3mA (VCC ≥ 2.5V); IOL = 1mA (VCC < 2.5V); CL = 100pF
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
3
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
POWER-ON RESET (POR)
I²C BUS PROTOCOL
Each CAT24Cxx* incorporates Power-On Reset
(POR) circuitry which protects the internal logic
against powering up in the wrong state.
The I²C bus consists of two ‘wires’, SCL and SDA.
The two wires are connected to the VCC supply via
pull-up resistors. Master and Slave devices connect to
the 2-wire bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
A CAT24Cxx device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the
POR trigger level. This bi-directional POR feature
protects the device against ‘brown-out’ failure
following a temporary loss of power.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
PIN DESCRIPTION
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while
SCL is high will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes
all commands. It consists of a HIGH to LOW transition
on SDA while SCL is HIGH. The START acts as a
‘wake-up’ call to all receivers. Absent a START, a
Slave will not respond to commands. The STOP
condition completes all commands. It consists of a
LOW to HIGH transition on SDA while SCL is HIGH.
SCL: The Serial Clock input pin accepts the Serial
Clock generated by the Master.
DEVICE ADDRESSING
* For common features, the CAT24C01/02/04/08/16 will be refered
to as CAT24Cxx
The Master initiates data transfer by creating a
START condition on the bus. The Master then
broadcasts an 8-bit serial Slave address. For normal
Read/Write operations, the first 4 bits of the Slave
address are fixed at 1010 (Ah). The next 3 bits are
used as programmable address bits when cascading
multiple devices and/or as internal address bits. The
¯¯, specifies whether a
last bit of the slave address, R/W
Read (1) or Write (0) operation is to be performed.
The 3 address space extension bits are assigned as
illustrated in Figure 2. A2, A1 and A0 must match the
state of the external address pins, and a10, a9 and a8
are internal address bits.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode,
this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device
address when cascading multiple devices. When not
driven, these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this
pin is pulled LOW internally.
ACKNOWLEDGE
After processing the Slave address, the Slave
responds with an acknowledge (ACK) by pulling down
the SDA line during the 9th clock cycle (Figure 3). The
Slave will also acknowledge the address byte and
every data byte presented in Write mode. In Read
mode the Slave shifts out a data byte, and then
releases the SDA line during the 9th clock cycle. As
long as the Master acknowledges the data, the Slave
will continue transmitting. The Master terminates the
session by not acknowledging the last data byte
(NoACK) and by issuing a STOP condition. Bus timing
is illustrated in Figure 4.
FUNCTIONAL DESCRIPTION
The CAT24Cxx supports the Inter-Integrated Circuit
(I²C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and
a device receiving data as a receiver. Data flow is
controlled by a Master device, which generates the
serial clock and all START and STOP conditions. The
CAT24Cxx acts as a Slave device. Master and Slave
alternate as either transmitter or receiver.
Doc. No. MD-1115 Rev. G
4
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
Figure 1. Start/Stop Timing
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
CAT24C01 and CAT24C02
1
0
1
0
A2
A1
a8
R/W
CAT24C04
1
0
1
0
A2
a9
a8
R/W
CAT24C08
1
0
1
0
a10
a9
a8
R/W
CAT24C16
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (RECEIVER)
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
START
Figure 4. Bus Timing
tHIGH
tF
tR
tLOW
tLOW
SCL
tHD:DAT
tSU:STA
tSU:DAT
tHD:SDA
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
5
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
WRITE OPERATIONS
BYTE WRITE
ACKNOWLEDGE POLLING
In Byte Write mode, the Master sends the START
¯¯ bit set
condition and the Slave address with the R/W
to zero to the Slave. After the Slave generates an
acknowledge, the Master sends the byte address that
is to be written into the address pointer of the
CAT24Cxx. After receiving another acknowledge from
the Slave, the Master transmits the data byte to be
written into the addressed memory location. The
CAT24Cxx device will acknowledge the data byte and
the Master generates the STOP condition, at which
time the device begins its internal Write cycle to
nonvolatile memory (Figure 5). While this internal
cycle is in progress (tWR), the SDA output will be tristated and the CAT24Cxx will not respond to any
request from the Master device (Figure 6).
The acknowledge (ACK) polling routine can be used
to take advantage of the typical write cycle time.
Once the stop condition is issued to indicate the end
of the host’s write operation, the CAT24Cxx initiates
the internal write cycle. The ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the CAT24Cxx is still busy with the write
operation, NoACK will be returned. If the CAT24Cxx
has completed the internal write operation, an ACK
will be returned and the host can then proceed with
the next read or write operation.
HARDWARE WRITE PROTECTION
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is
left floating or is grounded, it has no impact on the
operation of the CAT24Cxx. The state of the WP pin
is strobed on the last falling edge of SCL immediately
preceding the first data byte (Figure 8). If the WP pin
is HIGH during the strobe interval, the CAT24Cxx will
not acknowledge the data byte and the Write request
will be rejected.
PAGE WRITE
The CAT24Cxx writes up to 16 bytes of data in a
single write cycle, using the Page Write operation
(Figure 7). The Page Write operation is initiated in the
same manner as the Byte Write operation, however
instead of terminating after the data byte is
transmitted, the Master is allowed to send up to fifteen
additional bytes. After each byte has been transmitted
the CAT24Cxx will respond with an acknowledge and
internally increments the four low order address bits.
The high order bits that define the page address
remain unchanged. If the Master transmits more than
sixteen bytes prior to sending the STOP condition, the
address counter ‘wraps around’ to the beginning of
page and previously transmitted data will be
overwritten. Once all sixteen bytes are received and
the STOP condition has been sent by the Master, the
internal Write cycle begins. At this point all received
data is written to the CAT24Cxx in a single write cycle.
Doc. No. MD-1115 Rev. G
DELIVERY STATE
The CAT24Cxx is shipped erased, i.e., all bytes
are FFh.
6
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
Figure 5. Byte Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
a7 - a0
d7 - d0
S
T
O
P
S
P
A
C
K
SLAVE
A
C
K
A
C
K
* For the CAT24C01 a7 = 0
Figure 6. Write Cycle Timing
SCL
8th Bit
Byte n
SDA
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Page Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
DATA
BYTE
n
ADDRESS
BYTE
SLAVE
ADDRESS
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
S
P
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
n=1
P ≤ 15
Figure 8. WP Timing
ADDRESS
BYTE
DATA
BYTE
1
8
a7
a0
9
1
8
d7
d0
SCL
SDA
tSU:WP
WP
tHD:WP
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
7
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
READ OPERATIONS
IMMEDIATE READ
¯¯ bit set
Upon receiving a Slave address with the R/W
to ‘1’, the CAT24Cxx will interpret this as a request for
data residing at the current byte address in memory.
The CAT24Cxx will acknowledge the Slave address,
will immediately shift out the data residing at the
current address, and will then wait for the Master to
respond. If the Master does not acknowledge the data
(NoACK) and then follows up with a STOP condition
(Figure 9), the CAT24Cxx returns to Standby mode.
SELECTIVE READ
Selective Read operations allow the Master device to
select at random any memory location for a read
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24Cxx acknowledges the byte
address, the Master device resends the START
condition and the slave address, this time with the
¯¯ bit set to one. The CAT24Cxx then responds
R/W
with its acknowledge and sends the requested data
byte. The Master device does not acknowledge the
data (NoACK) but will generate a STOP condition
(Figure 10).
SEQUENTIAL READ
If during a Read session, the Master acknowledges
st
the 1 data byte, then the CAT24Cxx will continue
transmitting data residing at subsequent locations until
the Master responds with a NoACK, followed by a
STOP (Figure 11). In contrast to Page Write, during
Sequential Read the address count will automatically
increment to and then wrap-around at end of memory
(rather than end of page). In the CAT24C01, the
internal address count will not wrap around at the end
of the 128 byte memory space.
Doc. No. MD-1115 Rev. G
8
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
Figure 9. Immediate Read Sequence and Timing
BUS ACTIVITY:
MASTER
N
O
S
T
A
R
T
S
AT
CO
KP
SLAVE
ADDRESS
S
P
A
C
K
SLAVE
DATA
BYTE
8
SCL
9
8th Bit
SDA
DATA OUT
NO ACK
STOP
Figure 10. Selective Read Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
T
A
R
T
ADDRESS
BYTE
SLAVE
ADDRESS
N
O
S
AT
CO
KP
SLAVE
ADDRESS
P
S
S
A
C
K
A
C
K
SLAVE
A
C
K
DATA
BYTE
Figure 11. Sequential Read Sequence
N
O
BUS ACTIVITY:
MASTER
A
C
K
A
C
K
SLAVE
ADDRESS
S
AT
CO
KP
A
C
K
P
SLAVE
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
9
DATA
BYTE
n+2
DATA
BYTE
n+x
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L)(1)
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
E1
6.10
eB
7.87
L
2.92
6.35
7.11
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC standard MS-001.
Doc. No. MD-1115 Rev. G
10
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
SOIC 8-Lead 150mils (W)(1)
SYMBOL
E1
E
MIN
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
e
PIN # 1
IDENTIFICATION
NOM
1.27 BSC
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-012.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
11
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
TSSOP 8-Lead 4.4mm (Y)(1)
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.90
e
0.65 BSC
L
1.00 REF
L1
0.50
θ1
0°
0.60
1.05
0.75
8°
e
TOP VIEW
D
A2
A
A1
c
θ1
L1
SIDE VIEW
L
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC specification MS-153.
Doc. No. MD-1115 Rev. G
12
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
MSOP 8-Lead 3 x 3mm (Z) (1)
SYMBOL
MIN
NOM
MAX
A
E
E1
1.10
A1
0.05
0.10
0.15
A2
0.75
0.85
0.95
b
0.22
c
0.13
D
2.90
0.38
0.23
3.00
3.10
E
4.80
4.90
5.00
E1
2.90
3.00
3.10
e
L
0.65 BSC
0.40
0.60
0.80
L1
0.95 REF
L2
0.25 BSC
θ
0º
6º
TOP VIEW
D
A
A2
A1
DETAIL A
e
b
c
SIDE VIEW
END VIEW
θ
L2
L
L1
DETAIL A
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-187.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
13
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
TDFN 8-Pad 2 x 3mm (VP2)(1)
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A2
0.45
0.55
0.65
A3
A2
A3
FRONT VIEW
0.20
0.25
0.30
2.10
D
1.90
2.00
D2
1.30
1.40
1.50
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
L
BOTTOM VIEW
0.20 REF
b
e
L
050 TYP
0.20
0.30
0.40
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC standard MO-229.
Doc. No. MD-1115 Rev. G
14
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
TSOT-23 5-Lead (TD)(1)
SYMBOL
D
MIN
NOM
A
e
1.00
A1
0.01
0.05
0.10
A2
0.80
0.87
0.90
b
0.30
c
0.12
D
E1
E
MAX
0.45
0.15
0.20
2.90 BSC
E
2.80 BSC
E1
1.60 BSC
e
0.95 TYP
L
0.30
L1
0.40
0.50
0.60 REF
L2
0.25 BSC
θ
0º
8º
TOP VIEW
A2 A
b
θ
L
A1
c
L2
L1
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-193.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
15
Doc. No. MD-1115 Rev. G
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device #
CAT
24C16
Suffix
Y
Optional ID
Product Number
–G
I
Temperature Range
I = Industrial (-40ºC to +85ºC)
E = Extended (-40ºC to +125ºC)
24C01
24C02
24C04
24C08
24C16
T3
Tape & Reel
T: Tape & Reel
3: 3,000/Reel
Lead Finish
G: NiPdAu
Blank: Matte-Tin
L:
W:
Y:
Z:
VP2:
TD:
Package
PDIP
SOIC, JEDEC
TSSOP
MSOP (4)
TDFN
TSOT-23
For Product Top Mark Codes, click here:
http://www.catsemi.com/techsupport/producttopmark.asp
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT24C16YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel).
(4) For availability, please contact your nearest ON Semiconductor Sales Office.
(5) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
Doc. No. MD-1115 Rev. G
16
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
REVISION HISTORY
Date
Revision
Comments
18-Jul-06
A
Combine 5 data sheets into one data sheet.
31-Jul-06
B
Update Package Marking
29-Nov-06
C
Update Features
Update Pin Configuration
Update Functional Symbol
Added 8-Lead MSOP Package Outline
Remove Package Marking
Update Example of Ordering Information
14-Jun-07
D
Update PDIP 8-Lead 300mils Package Outline
Update document code to include MD-
03-Jul-07
E
Add Extended Temperature range
Update D.C. Operating Characteristics table
Update all Package Outline Drawing
09-Sept-08
F
Update Supply Voltage Range
Update all Package Outline Drawing
Update Document Layout
23-Oct-08
G
Change logo and fine print to ON Semiconductor
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center:
Phone: 81-3-5773-3850
17
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
Doc. No. MD-1115 Rev. G
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