CAT24C128

CAT24C128 128 kb I2C CMOS Serial EEPROM Description The CAT24C128 is a 128 kb Serial CMOS EEPROM, internally organized as 16,384 words of 8 bits each. It features a 64−byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). Features http://onsemi.com • • • • • • • • • • • Supports Standard and Fast I2C Protocol 1.8 V to 5.5 V Supply Voltage Range 64−Byte Page Write Buffer Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Range 8−lead PDIP, SOIC, TSSOP, MSOP and UDFN Packages This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant* VCC PDIP−8 L SUFFIX CASE 646AA TSSOP−8 Y SUFFIX CASE 948AL SOIC−8 W SUFFIX CASE 751BD MSOP−8 Z SUFFIX CASE 846AD UDFN−8 HU3 SUFFIX CASE 517AX PIN CONFIGURATION A0 A1 A2 VSS 1 VCC WP SCL SDA PDIP (L), SOIC (W), TSSOP (Y), MSOP (Z), UDFN (HU3) SCL CAT24C128 SDA For the location of Pin 1, please consult the corresponding package drawing. A2, A1, A0 WP PIN FUNCTION Pin Name VSS A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground Figure 1. Functional Symbol *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. © Semiconductor Components Industries, LLC, 2009 September, 2009 − Rev. 11 1 Publication Order Number: CAT24C128/D CAT24C128 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Rating −65 to +150 −0.5 to +6.5 Units °C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol NEND (Note 3) TDR Endurance Data Retention Parameter Min 1,000,000 100 Units Program / Erase Cycles Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC TA = −40°C to +85°C TA = −40°C to +125°C I/O Pin Leakage TA = −40°C to +85°C TA = −40°C to +125°C Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC < 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA −0.5 VCC x 0.7 Min Max 1 3 1 2 1 2 VCC x 0.3 VCC + 0.5 0.4 0.2 V V V V mA Units mA mA mA Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol CIN (Note 4) CIN (Note 4) IWP (Note 5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0 V VIN = 0 V VIN < VIH VIN > VIH Max 8 6 200 1 Units pF pF mA mA 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. http://onsemi.com 2 CAT24C128 Table 5. A.C. CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C) (Note 6) Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF (Note 7) tSU:STO tBUF tAA tDH Ti (Note 7) tSU:WP tHD:WP tWR tPU (Notes 7 and 8) 6. 7. 8. Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data Hold Time Data Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to SDA Data Out Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power−up to Ready Mode 0 2.5 5 1 100 100 0 2.5 5 1 4 4.7 3.5 100 100 4 4.7 4 4.7 0 250 1000 300 0.6 1.3 0.9 Parameter Min Max 100 0.6 1.3 0.6 0.6 0 100 300 300 Min Fast Max 400 Units kHz ms ms ms ms ms ns ns ns ms ms ms ns ns ms ms ms ms Test conditions according to “A.C. Test Conditions” table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. A.C. TEST CONDITIONS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC v 50 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF http://onsemi.com 3 CAT24C128 Power−On Reset (POR) The CAT24C128 incorporates Power−On Reset (POR) circuitry which protects the device against powering up in the wrong state. The CAT24C128 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. When not driven, these pins are pulled LOW internally. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. Functional Description The CAT24C128 supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C128 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. I2C Bus Protocol The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull−up resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 3). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices and must match the state of the external address pins. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge all address bytes and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 5. http://onsemi.com 4 CAT24C128 SCL SDA START CONDITION STOP CONDITION Figure 2. START/STOP Conditions DEVICE ADDRESS 1 0 1 0 A2 A1 A0 R/W Figure 3. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER 1 8 9 BUS RELEASE DELAY (RECEIVER) DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) ACK SETUP (≥ tSU:DAT) Figure 4. Acknowledge Timing tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA tHIGH tLOW tR tHD:DAT tSU:DAT tSU:STO tDH tBUF Figure 5. Bus Timing http://onsemi.com 5 CAT24C128 Write Operations Byte Write Upon receiving a Slave address with the R/W bit set to ‘0’, the CAT24C128 will interpret the next two bytes as address bytes. These bytes are used to initialize the internal address counter; the 2 most significant bits are ‘don’t care’, the next 8 point to one of 256 available pages and the last 6 point to a location within a 64 byte page. A byte following the address bytes will be interpreted as data. The data will be loaded into the Page Write Buffer and will eventually be written to memory at the address specified by the 14 active address bits provided earlier. The CAT24C128 will acknowledge the Slave address, address bytes and data byte. The Master then starts the internal Write cycle by issuing a STOP condition (Figure 6). During the internal Write cycle (tWR), the SDA output will be tri−stated and additional Read or Write requests will be ignored (Figure 7). Page Write latched and the address count automatically increments to and then wraps−around at the page boundary. Previously loaded data can thus be overwritten by new data. What is eventually written to memory reflects the latest Page Write Buffer contents. Only data loaded within the most recent Page Write sequence will be written to memory. Acknowledge Polling The ready/busy status of the CAT24C128 can be ascertained by sending Read or Write requests immediately following the STOP condition that initiated the internal Write cycle. As long as internal Write is in progress, the CAT24C128 will not acknowledge the Slave address. Hardware Write Protection By continuing to load data into the Page Write Buffer after the 1st data byte and before issuing the STOP condition, up to 64 bytes can be written simultaneously during one internal Write cycle (Figure 8). If more data bytes are loaded than locations available to the end of page, then loading will continue from the beginning of page, i.e. the page address is BUS ACTIVITY: MASTER S T A R T S SLAVE * = Don’t Care Bit A C K With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C128. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAT24C128 will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C128 is shipped erased, i.e., all bytes are FFh. ADDRESS BYTE a7−a0 S T O P P A C K A C K A C K SLAVE ADDRESS ** ADDRESS BYTE a13−a8 DATA BYTE Figure 6. Byte Write Sequence SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing http://onsemi.com 6 CAT24C128 BUS ACTIVITY: S T A R MASTER T S SLAVE * = Don’t Care Bit P v 63 A C K ADDRESS BYTE a13−a8 ** A C K A C K A C K A C K A C K A C K ADDRESS BYTE a7−a0 DATA BYTE n DATA BYTE n+1 DATA BYTE n+P S T O P P SLAVE ADDRESS Figure 8. Page Write Sequence ADDRESS BYTE 1 SCL 8 9 1 DATA BYTE 8 SDA a7 a0 tSU:WP d7 d0 WP tHD:WP Figure 9. WP Timing Read Operations Immediate Read Upon receiving a Slave address with the R/W bit set to ‘1’, the CAT24C128 will interpret this as a request for data residing at the current byte address in memory. The CAT24C128 will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the CAT24C128 returns to Standby mode. Selective Read with data, the Master instead follows up with an Immediate Read sequence, then the CAT24C128 will use the 14 active address bits to initialize the internal address counter and will shift out data residing at the corresponding location. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 11), the CAT24C128 returns to Standby mode. Sequential Read To read data residing at a specific location, the internal address counter must first be initialized as described under Byte Write. If rather than following up the two address bytes If during a Read session the Master acknowledges the 1st data byte, then the CAT24C128 will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page). http://onsemi.com 7 CAT24C128 BUS ACTIVITY: MASTER S T A R T S SLAVE A C K DATA BYTE N O A C K S T O P P SLAVE ADDRESS SCL 8 9 SDA 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: MASTER S T A R T S SLAVE ADDRESS ** A C K ADDRESS BYTE a13−a8 ADDRESS BYTE a7−a0 S T A R T S SLAVE ADDRESS N O A C K S T O P P SLAVE * = Don’t Care Bit A C K A C K A C K DATA BYTE Figure 11. Selective Read Sequence BUS ACTIVITY: MASTER SLAVE ADDRESS N O A C K S T O P P SLAVE A C K DATA BYTE n A C K DATA BYTE n+1 A C K DATA BYTE n+2 A C K DATA BYTE n+x Figure 12. Sequential Read Sequence http://onsemi.com 8 CAT24C128 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL A A1 A2 b E1 b2 c D E E1 e eB PIN # 1 IDENTIFICATION D L 7.87 2.92 3.30 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 BSC 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 7.11 MIN NOM MAX 5.33 TOP VIEW E A A2 A1 b2 L c e SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. b eB END VIEW http://onsemi.com 9 CAT24C128 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 θ 0º 8º D h A1 A θ c e SIDE VIEW b L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 10 CAT24C128 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL A A1 A2 b E1 E c D E E1 e L L1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 NOM MAX 1.20 0.15 0.90 1.05 0.30 0.20 3.00 6.40 4.40 0.65 BSC 1.00 REF 3.10 6.50 4.50 0.50 0.60 0.75 θ e 0º 8º TOP VIEW D A2 A q1 c A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. L1 END VIEW L http://onsemi.com 11 CAT24C128 PACKAGE DIMENSIONS UDFN8, 2x3 CASE 517AX−01 ISSUE O D A DETAIL A DAP SIZE 1.3 x 1.8 E PIN #1 IDENTIFICATION E2 A1 PIN #1 INDEX AREA TOP VIEW SIDE VIEW D2 BOTTOM VIEW SYMBOL A A1 A3 b D D2 E E2 e K L MIN 0.45 0.00 0.20 1.90 1.50 2.90 0.10 NOM 0.50 0.02 0.127 REF 0.25 2.00 1.60 3.00 0.20 0.50 TYP 0.10 REF MAX 0.55 0.05 K 0.30 2.10 1.70 3.10 0.30 e b L DETAIL A A3 0.40 A 0.30 0.35 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. A1 FRONT VIEW http://onsemi.com 12 CAT24C128 PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD−01 ISSUE O SYMBOL A A1 A2 b c E E1 D E E1 e L L1 L2 0.40 0.05 0.75 0.22 0.13 2.90 4.80 2.90 3.00 4.90 3.00 0.65 BSC 0.60 0.95 REF 0.25 BSC 0.80 0.10 0.85 MIN NOM MAX 1.10 0.15 0.95 0.38 0.23 3.10 5.00 3.10 θ 0º 6º TOP VIEW D A A2 DETAIL A A1 e SIDE VIEW b c END VIEW q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A http://onsemi.com 13 CAT24C128 Example of Ordering Information Prefix CAT Device # 24C128 Suffix Y I −G T3 Company ID Product Number 24C128 Temperature Range I = Industrial (−40°C to +85°C) E = Extended (−40°C to +125°C) Lead Finish G: NiPdAu Blank: Matte−Tin Tape & Reel (Note 9) T: Tape & Reel 3: 3000/Reel Package L: PDIP W: SOIC, JEDEC Y: TSSOP HU3: UDFN (2 x 3 mm) Z: MSOP 9. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ORDERABLE PART NUMBERS Order Number CAT24C128LI−G CAT24C128WI−GT3 CAT24C128YI−GT3 CAT24C128HU3IGT3* CAT24C128ZI−GT3 CAT24C128LE−G CAT24C128WE−GT3 CAT24C128YE−GT3 CAT24C128HU3EGT3* CAT24C128ZE−GT3 Order Number *Part number is not exactly the same as the “Example of Ordering Information” shown above. For part numbers marked with “*” there are NO hyphens in the orderable part numbers. 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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 14 CAT24C128/D