LM392DR2G

LM392 Low Power Operational Amplifier and Comparator The LM392 contains two functions: an op amp and a comparator. Both devices can operate on single−supply power and both have a common−mode range down to ground. Operation from split power supplies is also possible. Low power−supply current is independent of the supply voltage level. The output of the comparator interfaces directly with either TTL or CMOS logic. Low quiescent current makes the LM392 ideal for portable equipment. MARKING DIAGRAM 8 Features • • • • • • http://onsemi.com 8 1 Wide Power−Supply Range: 3 V to 32 V Low Input Offset Voltage: 2 mV Low Quiescent Current: 600 mA Input CMV Range includes GND Op Amp is Unity Gain Stable These Devices are Pb−Free and are RoHS Compliant SOIC−8 NB CASE 751 XXXXX A L Y W G Typical Applications • Level Detectors • Voltage Controlled Oscillators • Transducer Amplifiers 1 LM392 ALYWX G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION OUTPUT A (Comparator) INVERTING INPUT A 1 8 2 − A + + B V+ 7 See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. OUTPUT B (Operational Amplifier) − NONINVERTING INPUT A 3 6 INVERTING INPUT B GND 4 5 NONINVERTING INPUT B Figure 1. Logic Diagram and Pinout © Semiconductor Components Industries, LLC, 2009 September, 2009 − Rev. 4 1 Publication Order Number: LM392/D LM392 MAXIMUM RATINGS Rating Symbol Value Unit VS 32 or $16 V VIDR 32 V Input Voltage VI 0.3 to 32 V Output Short − Circuit to Ground tSO Continuous Thermal Impedance qJA 160 °C/W Storage Temperature Range Tstg −65 to 150 °C 260 °C Supply Voltage Differential Input Voltage Lead Temperature (Soldering, 10 Seconds) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 LM392 ELECTRICAL CHARACTERISTICS (Both Amplifiers) (V+ = 5 V, TA= 25°C unless otherwise stated) LM392 Conditions TA At output switch point, VO = 1.4 V, Rs = 0 W, V+ = 5 V to 30 V, VCM = 0 to (V+ − 1.5 V) 25°C 0°C to 70°C IN(+) or IN(−), VCM = 0 V 25°C IN(+) or IN(−) 0°C to 70°C IN(+) or IN(−) 25°C Parameter Input Offset Voltage Input Bias Current Input Offset Current Min Typ Max Unit $2 $5 mV $7 50 Input Common−Mode Voltage Range = 30 V (Note 1) Supply Current 25°C 0°C to 70°C V+ = 30 V No Load $5 f = 1 kHz to 20 kHz, Input Referred Differential Input Voltage All VIN w V (or ELECTRICAL CHARACTERISTICS (V+ V−, If Used ) $50 nA $150 0 V+−1.5 0 V+−2 0°C to 70°C V+ = 5 V Amplifier−to−Amplifier Coupling nA 400 0°C to 70°C V+ 205 25°C 1 2 0.5 1 −78 0°C to 70°C V mA dB 32 V Max Unit = 5 V, TA= 25°C unless otherwise stated) LM392 Conditions TA Min Typ V+ = 15 V, Vo Swing = 1 V to 11 V, RL = 2 kW 25°C 25 100 Output Voltage Swing, High (VOH) RL = 2 kW 25°C V+−1.7 Output Voltage Swing, Low (VOL) RL = 2 kW 25°C Common−Mode Rejection Ratio VCM = 0 to V+ − 1.5 V 25°C 65 70 dB 25°C 65 100 dB Parameter OP AMP ONLY Large Signal Voltage Gain Power Supply Rejection Ratio V/mV V 20 mV Output Current Source VIN(+) = 1 V, VIN(−) = 0 V, V+ = 15 V, VO = 2 V 25°C 20 40 mA Output Current Sink VIN(−) = 1 V, VIN(+) = 0 V, V+ = 15 V, VO = 2 V 25°C 10 20 mA VIN(−) = 1 V, VIN(+) = 0 V, V+ = 15 V, VO = 200 mV 25°C 12 50 mA RS = 0 W (0°C to 70°C) 0°C to 70°C 7 mV/°C RS = 0 W (0°C to 70°C) 0°C to 70°C 10 pA/°C RL w 15 kW, V+ = 15 V 25°C 200 V/mV VIN = TTL Logic Swing, VREF = 1.4 V, VRL = 5 V, RL = 5.1 kW 25°C 200 ns VRL = 5 V, RL = 5.1 kW 25°C 600 ns Output Sink Current VIN(−) = 1 V, VIN(+) = 0 V, VO w 1.5 V 25°C 16 mA Saturation Voltage VIN(−) w 1 V, VIN(+) = 0, ISINK v 4 mA 25°C VIN(−) w 1 V, VIN(+) = 0, ISINK v 4 mA 0°C to 70°C VIN(−) = 0, VIN(+) w 1 V, VO = 5 V 25°C VIN(−) = 0, VIN(+) w 1 V, VO = 30 V 25°C Input Offset Voltage Drift Input Offset Current Drift COMPARATOR ONLY Voltage Gain Large Signal Response Time Response Time Output Leakage Current 50 6 250 400 mV 700 mV 0.1 nA 1.0 mA 1. The input common−mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common−mode voltage range is V+ − 1.5 V, but either or both inputs can go to 32 V without damage. http://onsemi.com 3 LM392 ORDERING INFORMATION Device LM392DR2G Operating Temperature Range 0°C to +70°C Package Shipping† SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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