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MC14066B
Quad Analog Switch/Quad
Multiplexer
The MC14066B consists of four independent switches capable of
controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation.
The MC14066B is designed to be pin−for−pin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings
as large as the full supply voltage can be controlled via each
independent control input.
Features
•
•
•
•
•
•
•
•
Triple Diode Protection on All Control Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linearized Transfer Characteristics
Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical
Pin−for−Pin Replacement for CD4016, CD4016, MC14016B
For Lower RON, Use The HC4066 High−Speed CMOS Device
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
IN 1
1
14
VDD
OUT 1
2
13
CONTROL 1
OUT 2
3
12
CONTROL 4
IN 2
4
11
IN 4
CONTROL 2
5
10
OUT 4
CONTROL 3
6
9
OUT 3
VSS
7
8
IN 3
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage Range
Value
Unit
−0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
−0.5 to VDD + 0.5
V
Iin
Input Current (DC or Transient)
per Control Pin
±10
mA
ISW
Switch Through Current
±25
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
MARKING DIAGRAMS
14
14
14066BG
AWLYWW
MC14066B
ALYWG
1
1
SOIC−14
SOEIAJ−14
14
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
14
066B
ALYW
1
TSSOP−14
A
WL, L
YY, Y
WW, W
G or
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 10
1
Publication Order Number:
MC14066B/D
MC14066B
BLOCK DIAGRAM
CONTROL 1
13
2
OUT 1
1
IN 1
5
CONTROL 2
IN 2
CONTROL 3
IN 3
CONTROL 4
IN 4
3
OUT 2
4
6
9
8
OUT 3
12
10
OUT 4
11
VDD = PIN 14
VSS = PIN 7
LOGIC DIAGRAM AND TRUTH TABLE
(1/4 OF DEVICE SHOWN)
IN/OUT
OUT/IN
CONTROL
Control
Switch
0 = VSS
OFF
1 = VDD
ON
Logic Diagram Restrictions
VSS ≤ Vin ≤ VDD
VSS ≤ Vout ≤ VDD
CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
VDD VDD
VDD
VSS
VDD
CMOS
INPUT
VDD
VDD
VDD
300
W
VSS
VSS
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2
MC14066B
ELECTRICAL CHARACTERISTICS
−55C
Characteristic
Symbol
VDD
Test Conditions
25C
125C
Min
Max
Min
Typ
(Note 2)
3.0
18
3.0
−
18
3.0
18
V
−
−
−
0.25
0.5
1.0
−
−
−
0.005
0.010
0.015
0.25
0.5
1.0
−
−
−
7.5
15
30
mA
Max
Min
Max
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
Power Supply Voltage
Range
VDD
—
Quiescent Current Per
Package
IDD
5.0
10
15
Control Inputs:
Vin = VSS or VDD,
Switch I/O: VSS v VI/O
v VDD, and
DVswitch v 500 mV (3)
ID(AV)
5.0
10
15
TA = 25C only The
channel component,
(Vin – Vout)/Ron, is
not included.)
Total Supply Current
(Dynamic Plus Quiescent,
Per Package
Typical
mA
(0.07 mA/kHz) f + IDD
(0.20 mA/kHz) f + IDD
(0.36 mA/kHz) f + IDD
CONTROL INPUTS (Voltages Referenced to VSS)
Low−Level Input Voltage
VIL
5.0
10
15
Ron = per spec,
Ioff = per spec
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
V
High−Level Input Voltage
VIH
5.0
10
15
Ron = per spec,
Ioff = per spec
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
V
Input Leakage Current
Iin
15
Vin = 0 or VDD
−
±0.1
−
±0.00001
±0.1
−
±1.0
mA
Input Capacitance
Cin
−
−
−
−
5.0
7.5
−
−
pF
SWITCHES IN AND OUT (Voltages Referenced to VSS)
Recommended
Peak−to−Peak Voltage Into
or Out of the Switch
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 1)
Output Offset Voltage
ON Resistance
VI/O
−
Channel On or Off
0
VDD
0
−
VDD
0
VDD
Vp–p
DVswitch
−
Channel On
0
600
0
−
600
0
300
mV
VOO
−
Vin = 0 V, No Load
−
−
−
10
−
−
−
mV
−
−
−
800
400
220
−
−
−
250
120
80
1050
500
280
−
−
−
1200
520
300
W
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W
±0.05
±100
−
±1000
nA
DVswitch v 500 mV
Vin = VIL or VIH
(Control), and Vin =
0 to VDD (Switch)
(3),
Ron
5.0
10
15
DRon
5.0
10
15
Ioff
15
Vin = VIL or VIH
(Control) Channel to
Channel or Any One
Channel
−
±100
−
Capacitance, Switch I/O
CI/O
−
Switch Off
−
−
−
10
15
−
−
pF
Capacitance, Feedthrough
(Switch Off)
CI/O
−
−
−
−
−
0.47
−
−
−
pF
DON Resistance Between
Any Two Channels
in the Same Package
Off−Channel Leakage
Current (Figure 6)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
MC14066B
ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25C unless otherwise noted.)
Symbol
Characteristic
Propagation Delay Times
Input to Output (RL = 10 kW)
tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns
VSS = 0 Vdc
Control to Output (RL = 1 kW) (Figure 2)
Output “1” to High Impedance
VDD
Vdc
Min
Typ
(Note 5)
Max
tPLH, tPHL
Unit
ns
5.0
10
15
−
−
−
20
10
7.0
40
20
15
5.0
10
15
−
−
−
40
35
30
80
70
60
tPHZ
ns
Output “0” to High Impedance
tPLZ
5.0
10
15
−
−
−
40
35
30
80
70
60
ns
High Impedance to Output “1”
tPZH
5.0
10
15
−
−
−
60
20
15
120
40
30
ns
High Impedance to Output “0”
tPZL
5.0
10
15
−
−
−
60
20
15
120
40
30
ns
Second Harmonic Distortion
VSS = – 5 Vdc
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 kW, f = 1.0 kHz)
−
5.0
−
0.1
−
%
Bandwidth (Switch ON) (Figure 3)
VSS = – 5 Vdc
(RL = 1 kW, 20 Log (Vout/Vin) = − 3 dB, CL = 50 pF,
Vin = 5 Vp−p)
−
5.0
−
65
−
MHz
Feedthrough Attenuation (Switch OFF)
VSS = – 5 Vdc
(Vin = 5 Vp−p, RL = 1 kW, fin = 1.0 MHz) (Figure 3)
−
5.0
−
– 50
−
dB
Channel Separation (Figure 4)
(Vin = 5 Vp−p, RL = 1 kW, fin = 8.0 MHz)
(Switch A ON, Switch B OFF)
VSS = – 5 Vdc
−
5.0
−
– 50
−
dB
Crosstalk, Control Input to Signal Output (Figure 5)
VSS = – 5 Vdc
(R1 = 1 kW, RL = 10 kW, Control tTLH = tTHL = 20 ns)
−
5.0
−
300
−
mVp−p
4. The formulas given are for the typical characteristics only at 25C.
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14066B
TEST CIRCUITS
Vout
VC
RL
ON SWITCH
CONTROL
SECTION
OF IC
20 ns
Vout
VSS
tPHZ
90%
tPZL
tPLZ
10%
90%
Vout
SOURCE
Figure 1. DV Across Switch
VDD
tPZH
LOAD
V
Vx
Vin
90%
50%
10%
VC
CL
Vin = VDD
Vx = VSS
Vin = VSS
Vx = VDD
10%
Figure 2. Turn−On Delay Time Test Circuit
and Waveforms
VDD - VSS
2
VC = VDD FOR BANDWIDTH TEST
VC = VSS FOR FEEDTHROUGH TEST
Vin
VDD - VSS
2
VDD
Vin
CL
RL
CL
Vout
RL
CL
VC
VSS
VDD
RL
VSS
Figure 3. Bandwidth and
Feedthrough Attenuation
Figure 4. Channel Separation
OFF CHANNEL UNDER TEST
VDD
Vin
A
Vout
1k
RL
10 k
CONTROL
SECTION
OF IC
CL = 50 pF
VSS
VSS
VDD
VC = -5.0 V TO +5.0 V SWING
Figure 5. Crosstalk,
Control to Output
Figure 6. Off Channel Leakage
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5
MC14066B
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kW
RANGE
VDD
X-Y
PLOTTER
VSS
Figure 7. Channel Resistance (RON) Test Circuit
350
300
300
250
200
150
TA = 125°C
100
25°C
-55°C
50
0
-10
R ON , “ON” RESISTANCE (OHMS)
R ON , “ON” RESISTANCE (OHMS)
350
-8.0 -6.0 -4.0 -2.0
0
0.2
4.0
6.0
8.0
250
200
150
25°C
-55°C
50
-8.0 -6.0 -4.0 -2.0
0
0.2
4.0
6.0
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 8. VDD = 7.5 V, VSS = − 7.5 V
Figure 9. VDD = 5.0 V, VSS = − 5.0 V
700
350
600
300
500
400
300
TA = 125°C
200
25°C
100
0
-10
TA = 125°C
100
0
-10
10
RON , “ON” RESISTANCE (OHMS)
R ON , “ON” RESISTANCE (OHMS)
TYPICAL RESISTANCE CHARACTERISTICS
-55°C
-8.0 -6.0 -4.0 -2.0
0
0.2
4.0
6.0
8.0
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
-8.0 -6.0 -4.0 -2.0
0
0.2
4.0
6.0
8.0
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 10. VDD = 2.5 V, VSS = − 2.5 V
Figure 11. Comparison at 25°C, VDD = −VSS
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6
10
TA = 25°C
250
0
-10
10
8.0
10
MC14066B
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The
0−to−5 V digital control signal is used to directly control a
5 V peak−to−peak analog signal.
The digital control logic levels are determined by VDD
and VSS. The VDD voltage is the logic high voltage, the VSS
voltage is logic low. For the example, VDD = +5 V = logic
high at the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by VDD
and VSS. The analog voltage must not swing higher than
VDD or lower than VSS.
The example shows a 5 V peak−to−peak signal which
allows no margin at either peak. If voltage transients above
VDD and/or below VSS are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
The absolute maximum potential difference between
VDD and VSS is 18 V. Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and VSS.
+5 V
VDD
VSS
+5.0 V
5 Vp-p
SWITCH
IN
ANALOG SIGNAL
SWITCH
OUT
+5 V
5 Vp-p
ANALOG SIGNAL
+ 2.5 V
GND
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
0-TO-5 V DIGITAL
MC14066B
CONTROL SIGNALS
Figure A. Application Example
VDD
VDD
DX
DX
SWITCH
IN
SWITCH
OUT
DX
DX
VSS
VSS
Figure B. External Germanium or Schottky Clipping Diodes
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7
MC14066B
ORDERING INFORMATION
Package
Shipping†
MC14066BDG
SOIC−14
(Pb−Free)
55 Units / Rail
NLV14066BDG*
SOIC−14
(Pb−Free)
55 Units / Rail
MC14066BDR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
NLV14066BDR2G*
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC14066BDTR2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
NLV14066BDTR2G*
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
MC14066BFELG
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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8
MC14066B
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
e
DETAIL A
h
A
X 45
M
A1
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
7
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0
7
MC14066B
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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10
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0
8
0
8
MC14066B
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965
ISSUE B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
M
E HE
L
7
1
DETAIL P
Z
D
VIEW P
A
e
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10
0
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10
0
0.028
0.035
--0.056
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