MJ14001 (PNP),
MJ14002* (NPN),
MJ14003* (PNP)
*Preferred Devices
High−Current Complementary
Silicon Power Transistors
Designed for use in high−power amplifier and switching circuit
applications.
Features
• High Current Capability − IC Continuous = 60 Amperes
• DC Current Gain − hFE = 15−100 @ IC = 50 Adc
• Low Collector−Emitter Saturation Voltage −VCE(sat) = 2.5 Vdc (Max)
@ IC = 50 Adc
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60 AMPERE
COMPLEMENTARY SILICON
POWER TRANSISTORS
60−80 VOLTS, 300 WATTS
• Pb−Free Packages are Available*
MARKING
DIAGRAM
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Collector−Emitter Voltage
Rating
MJ14001
MJ14002/03
VCEO
60
80
Vdc
Collector−Base Voltage
MJ14001
MJ14002/03
VCBO
60
80
Vdc
VEBO
5.0
Vdc
IC
60
Adc
Base Current − Continuous
IB
15
Adc
Emitter Current − Continuous
IE
75
Adc
Total Power Dissipation @ TC = 25°C
Derate Above 25°C
PD
300
1.71
W
W/°C
TJ, Tstg
− 65 to +200
°C
Emitter−Base Voltage
Collector Current − Continuous
Operating and Storage Junction
Temperature Range
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
TO−204 (TO−3)
CASE 197A
STYLE 1
MJ1400x = Device Code
xx = 1, 2, or 3
G
= Pb−Free Package
A
= Location Code
YY
= Year
WW
= Work Week
MEX
= Country of Orgin
ORDERING INFORMATION
360
PD, POWER DISSIPATION (WATTS)
MJ1400xG
AYYWW
MEX
330
Device
MJ14001
270
MJ14001G
210
MJ14002
150
MJ14002G
90
MJ14003
30
0
MJ14003G
0
40
80
120
160
TC, CASE TEMPERATURE (°C)
200
Package
Shipping
TO−3
100 Units/Tray
TO−3
(Pb−Free)
100 Units/Tray
TO−3
100 Units/Tray
TO−3
(Pb−Free)
100 Units/Tray
TO−3
100 Units/Tray
TO−3
(Pb−Free)
100 Units/Tray
240
Preferred devices are recommended choices for future use
and best overall value.
Figure 1. Power Derating
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 6
1
Publication Order Number:
MJ14001/D
MJ14001 (PNP), MJ14002* (NPN), MJ14003* (PNP)
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THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction−to−Case
Symbol
Max
Unit
RqJC
0.584
_C/W
ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Max
60
80
−
−
−
−
1.0
1.0
−
−
1.0
1.0
−
−
1.0
1.0
−
1.0
30
15
5.0
−
100
−
−
−
−
1.0
2.5
3.0
−
−
−
2.0
3.0
4.0
−
2000
Unit
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 1)
(IC = 200 mAdc, IB = 0)
VCEO(sus)
MJ14001
MJ14002, MJ14003
Collector Cutoff Current
(VCE = 30 Vdc, IB = 0)
(VCE = 40 Vdc, IB = 0)
MJ14001
MJ14402, MJ14003
Collector Cutoff Current
(VCE = 60 Vdc, VBE(off) = 1.5 V)
(VCE = 80 Vdc, VBE(off) = 1.5 V)
MJ14001
MJ14002, MJ14003
Collector Cutoff Current
(VCB = 60 Vdc, IE = 0)
(VCB = 80 Vdc, IE = 0)
MJ14001
MJ14002, MJ14003
Vdc
ICEO
mA
ICEX
mA
ICBO
Emitter Cutoff Current
(VBE = 5.0 Vdc, IC = 0)
IEBO
mA
mA
ON CHARACTERISTICS
DC Current Gain (Note 1)
(IC = 25 Adc, VCE = 3.0 V)
(IC = 50 Adc, VCE = 3.0 V)
(IC = 60 Adc, VCE = 3.0 V)
hFE
Collector−Emitter Saturation Voltage (Note 1)
(IC = 25 Adc, IB = 2.5 Adc)
(IC = 50 Adc, IB = 5.0 Adc)
(IC = 60 Adc, IB = 12 Adc)
VCE(sat)
Base−Emitter Saturation Voltage (Note 1)
(IC = 25 Adc, IB = 2.5 Adc)
(IC = 50 Adc, IB = 5.0 Adc)
(IC = 60 Adc, IB = 12 Adc)
VBE(sat)
−
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
Cob
pF
1. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
100
70
50
30
20
IC, COLLECTOR CURRENT (AMP)
5.0 ms
dc
10
7.0
5.0
3.0
2.0
TC = 25°C
WIRE BOND LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
1.0
0.7
0.5
0.3
0.2
0.1
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation: i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 2 is based on T J(pk) = 200_C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T J(pk)
v 200_C. T J(pk) may be calculated from the data in
Figure 13. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
1.0 ms
1.0 ms
MJ14001
MJ14002, MJ14003
1.0
2.0 3.0
5.0 7.0 10
20 30
50 70
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
100
Figure 2. Maximum Rated Forward Biased
Safe Operating Area
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2
MJ14001 (PNP), MJ14002* (NPN), MJ14003* (PNP)
TYPICAL ELECTRICAL CHARACTERISTICS
MJ14001, MJ14003 (PNP)
300
200
300
200
100
100
hFE , DC CURRENT GAIN
hFE , DC CURRENT GAIN
MJ14002 (NPN)
70
50
VCE = 3.0 V
TJ = −55°C
TJ = 25°C
TJ = 150°C
30
20
10
7.0
5.0
70
50
VCE = 3.0 V
TJ = −55°C
TJ = 25°C
TJ = 150°C
30
20
10
7.0
5.0
3.0
0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (AMPS)
50
3.0
0.7 1.0
70
2.0 3.0
5.0 7.0 10
20
IC, COLLECTOR CURRENT (AMPS)
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
2.8
TJ = 25°C
IC = 60 A
2.0
1.6
IC = 25 A
1.2
0.8
IC = 10 A
0.4
0
0.1
0.2 0.3
0.5 0.7 1.0
2.0 3.0
IB, BASE CURRENT (AMPS)
5.0 7.0 10
2.4
TJ = 25°C
IC = 60 A
2.0
1.6
IC = 25 A
1.2
0.8
IC = 10 A
0.4
0
0.1
0.2
0.3
0.5 0.7 1.0
2.0 3.0
IB, BASE CURRENT (AMPS)
5.0 7.0
10
Figure 6. Collector Saturation Region
2.8
2.8
TJ = 25°C
2.0
1.6
1.2
VBE(sat) @ IC/IB = 10
0.8
TJ = 25°C
2.4
V, VOLTAGE (VOLTS)
2.4
V, VOLTAGE (VOLTS)
70
2.8
Figure 5. Collector Saturation Region
2.0
1.6
1.2
VBE(sat) @ IC/IB = 10
0.8
VBE(on) @ VCE = 3.0 V
0.4
0
0.7
50
Figure 4. DC Current Gain
Figure 3. DC Current Gain
2.4
30
VCE(sat) @ IC/IB = 10
1.0
2.0 3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (AMPS)
VBE(on) @ VCE = 3.0 V
0.4
VCE(sat) @ IC/IB = 10
50
70
0
0.7
1.0
2.0 3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (AMPS)
Figure 8. “On” Voltages
Figure 7. “On” Voltages
http://onsemi.com
3
50
70
MJ14001 (PNP), MJ14002* (NPN), MJ14003* (PNP)
1.0
0.7
0.5
4.0
3.0
2.0
0.3
0.2
t, TIME (s)
μ
t, TIME (s)
μ
ts
tr
td
0.1
0.07
0.05
0.03
0.01
0.7 1.0
tf
0.3
0.2
0.1
0.07
MJ14002 (NPN)
MJ14001, MJ14003 (PNP)
0.02
1.0
0.7
0.5
2.0 3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (AMPS)
50
MJ14002 (NPN)
MJ14001, MJ14003 (PNP)
0.04
0.7 1.0
70
Figure 9. Turn−On Switching Times
2.0 3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (AMPS)
RB
0
C, CAPACITANCE (pF)
10000
7000
5000
tr ≤
20 ns
2000
1000
700
500
300
0
3.0
5.0 7.0 10
20 30
VR, REVERSE VOLTAGE (VOLTS)
2.0
50
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 12. Switching Test Circuit
0.2
0.2
RqJC(t) = r(t) RqJC
RqJC = 0.584°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
0.1
0.05
0.02
0.03
0.02
TO SCOPE
tr ≤ 20 ns
D = 0.5
0.3
0.1
0.07
0.05
RB
FOR CURVES OF FIGURES 3 & 6, RB & RL ARE VARIED.
INPUT LEVELS ARE APPROXIMATELY AS SHOWN.
FOR NPN CIRCUITS, REVERSE ALL POLARITIES.
70 100
Figure 11. Capacitance Variation
1.0
0.7
0.5
−30 V
RL
tr ≤ 20 ns
10 to 100 ms
VBB
DUTY CYCLE ≈ 2.0%
+7.0 V
MJ14002 (NPN)
MJ14001, MJ14003 (PNP)
100
1.0
VCC
−12 V
TJ = 25°C
200
+10
V
Cob
Cob
TO SCOPE
tr ≤ 20 ns
−12 V
10 to 100 ms
DUTY CYCLE ≈ 2.0%
3000
−30 V
RL
+2.0 V
Cib
70
Figure 10. Turn−Off Switching Times
VCC
Cib
50
0.01
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.02 0.03
0.05
0.07
0.1
0.2 0.3
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
t, TIME (ms)
20 30
Figure 13. Thermal Response
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4
50 70 100
200 300
500 700 1000 2000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−204 (TO−3)
CASE 197A−05
ISSUE K
DATE 21 FEB 2000
SCALE 1:1
A
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
E
D
−T−
U
DIM
A
B
C
D
E
G
H
K
L
N
Q
U
V
K
2 PL
0.30 (0.012)
V
SEATING
PLANE
T Q
M
M
Y
M
−Y−
L
2
G
H
B
INCHES
MIN
MAX
1.530 REF
0.990 1.050
0.250 0.335
0.057 0.063
0.060 0.070
0.430 BSC
0.215 BSC
0.440 0.480
0.665 BSC
0.760 0.830
0.151 0.165
1.187 BSC
0.131 0.188
MILLIMETERS
MIN MAX
38.86 REF
25.15 26.67
6.35
8.51
1.45
1.60
1.53
1.77
10.92 BSC
5.46 BSC
11.18 12.19
16.89 BSC
19.31 21.08
3.84
4.19
30.15 BSC
3.33
4.77
1
GENERIC
MARKING DIAGRAM*
−Q−
0.25 (0.010)
STYLE 1:
PIN 1. BASE
2. EMITTER
CASE: COLLECTOR
M
T Y
STYLE 2:
PIN 1. EMITTER
2. BASE
CASE: COLLECTOR
M
STYLE 3:
PIN 1. GATE
2. SOURCE
CASE: DRAIN
XXXXXX
A
YYWW
STYLE 4:
PIN 1. ANODE = 1
2. ANODE = 2
CASE: CATHODES
XXXXX
A
YY
WW
= Specific Device Code
= Assembly Locationa
= Year
= Work Week
*This information is generic. Please refer
to device data sheet for actual part
marking.
DOCUMENT NUMBER:
STATUS:
98ASB42128B
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
TO−204 (TO−3)
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98ASB42128B
PAGE 2 OF 2
ISSUE
K
REVISION
LEGALLY CHANGED TO ON
DATE
21 FEB 2000
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© Semiconductor Components Industries, LLC, 2003
February, 2000 − Rev. 05K
Case Outline Number:
197A
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