NB6L14MNG

NB6L14 2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer Multi−Level Inputs with Internal Termination http://onsemi.com Description MARKING DIAGRAM* The NB6L14 is a 3.0 GHz differential 1:4 LVPECL clock or data fanout buffer. The differential inputs incorporate internal 50  termination resistors that are accessed through the VT pin. This feature allows the NB6L14 to accept various logic standards, such as LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The VREF_AC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. The 1:4 fanout design was optimized for low output skew applications. The NB6L14 is a member of the ECLinPS MAX™ family of high performance clock and data management products. 1 1 • • • • • Input Clock Frequency > 3.0 GHz Input Data Rate > 2.5 Gb/s < 20 ps Within Device Output Skew 350 ps Typical Propagation Delay 150 ps Typical Rise and Fall Times Differential LVPECL Outputs, 700 mV Amplitude, Typical LVPECL Mode Operating Range: VCC = 2.375 V to 3.63 V with GND = 0 V Internal 50  Input Termination Resistors Provided VREF_AC Reference Output Voltage −40°C to +85°C Ambient Operating Temperature Available in 3 mm x 3 mm 16 Pin QFN These are Pb−Free Devices NB6L 14 ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) Features • • • • • • • QFN−16 MN SUFFIX CASE 485G 16 *For additional marking information, refer to Application Note AND8002/D. Q0 Q0 Q1 Q1 IN VT IN Q2 D EN Q Q2 Q3 VREFAC Q3 Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2012 May, 2012 − Rev. 5 1 Publication Order Number: NB6L14/D NB6L14 Q0 Q0 Q0 16 15 VCC GND 14 Q1 Q1 1 12 IN Q1 2 11 VT Q2 3 10 VREF_AC Q2 4 9 5 6 7 8 Q3 Q3 VCC EN /Q0 Exposed Pad (EP) 13 /Q1 IN 50  VT 50  /IN Q2 IN D EN /Q2 Q Q3 CLK VREF_AC /Q3 Figure 2. QFN−16 Pinout (Top View) Figure 3. Logic Diagram Table 1. EN TRUTH TABLE IN IN EN Q0:Q3 Q0:Q3 0 1 x 1 0 x 1 1 0 0 1 0+ 1 0 1+ + = On next negative transition of the input signal (IN). x = Don’t care. Table 2. PIN DESCRIPTION Pin Name I/O Description 1 Q1 LVPECL Output Non−inverted Differential Output. Typically Terminated with 50  Resistor to VCC–2.0 V. 2 Q1 LVPECL Output Inverted Differential Output. Typically Terminated with 50  Resistor to VCC – 2.0 V. 3 Q2 LVPECL Output Non−inverted Differential Output. Typically Terminated with 50  Resistor to VCC – 2.0 V. 4 Q2 LVPECL Output Inverted Differential Output. Typically Terminated with 50  Resistor to VCC – 2.0 V. 5 Q3 LVPECL Output Non−inverted Differential Output. Typically Terminated with 50  Resistor to VCC – 2.0 V. 6 Q3 LVPECL Output Inverted Differential Output. Typically Terminated with 50  Resistor to VCC – 2.0 V. 7 VCC − 8 EN LVTTL/LVCMOS 9 IN LVPECL, CML, LVDS, HSTL 10 VREF_AC 11 VT 12 IN LVPECL, CML, LVDS, HSTL 13 GND − Negative Supply Voltage 14 VCC − Positive Supply Voltage 15 Q0 LVPECL Output Noninverted Differential Output. Typically Terminated with 50  Resistor to VCC–2.0 V. 16 Q0 LVPECL Output Inverted Differential Output. Typically Terminated with 50  Resistor to VCC–2.0 V. − EP − Positive Supply Voltage Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will go HIGH on the next negative transition of IN input. The internal DFF register is clocked on the falling edge of IN input (see Figure 20). The EN pin has an internal pullup resistor and defaults HIGH when left open. Inverted Differential Clock Input. Internal 50  Resistor to Termination Pin, VT. Output Voltage Reference for capacitor−coupled inputs, only. Internal 100  center−tapped Termination Pin for IN and IN. Non−inverted Differential Clock Input. Internal 50  Resistor to Termination Pin, VT. The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal is applied on IN/IN inputs, then the device will be susceptible to self−oscillation. http://onsemi.com 2 NB6L14 Table 3. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity (Note 2) Flammability Rating > 4 kV > 100 V QFN−16 Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 167 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Positive Power Supply GND = 0 V VIo Positive Input/Output GND = 0 V IIN Input Current Condition 2 −0.5 V v VIo v VCC + 0.5 V Rating Unit 4.0 V 4.0 V "50 mA "2.0 mA 50 100 mA mA Source or Sink Current (IN/IN) IVREF_AC Source or Sink Current on VT Pin IOUT Output Current TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm QFN−16 QFN−16 42 35 °C/W °C/W JC Thermal Resistance (Junction−to−Case) (Note 3) QFN−16 4 °C/W Tsol Wave Solder 265 °C Continuous Surge Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L14 Table 5. DC CHARACTERISTICS, Multi−Level Inputs, LVPECL Outputs VCC = 2.375 V to 3.63 V, GND = 0 V, TA = −40°C to +85°C Characteristic Symbol ICC Min Typ Max Unit 35 47 65 mA VCC − 1145 2155 1355 VCC − 1020 2280 1480 VCC − 895 2405 1605 mV VCC = 3.3 V VCC = 2.5 V VCC − 1945 1355 555 VCC − 1875 1475 675 VCC − 1695 1605 805 mV VCC = 3.3 V VCC = 2.5 V 1100 VCC − 100 mV VCC mV Power Supply Current (Inputs and Outputs Open) LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS VOH VOL Output HIGH Voltage (Notes 4 and 5) (Q, Q) Output LOW Voltage (Notes 4 and 5) (Q, Q) DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (See Figures 10 and 11) Vth Input Threshold Reference Voltage Range (Note 6) VIH Single−Ended Input High Voltage Vth + 100 VIL Single−Ended Input LOW Voltage GND Vth − 100 mV VISE Single−Ended Input Voltage Amplitude (VIH − VIL) 200 VCC − GND mV VCC − 1.325 mV VREFAC VREFAC Output Reference Voltage (VCC w 2.5 V) VCC − 1.525 VCC − 1.425 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (See Figures 12 and 13) (Note 7) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage GND VIHD − 100 mV VCMR Input Common Mode Range (Differential Configuration) (Note 8) 950 VCC – 50 mV VID Differential Input Voltage (IN−IN) (VIHD−VILD) 100 VCC − GND mV IIH Input HIGH Current (VT Open) IN/IN −150 +150 A IIL Input LOW Current (VT Open) IN/IN −150 +150 A LVTTL/LVCMOS INPUT DC ELECTRICAL CHARACTERISTICS VIH Input HIGH Voltage 2.0 VCC V VIL Input LOW Voltage GND 0.8 V IIH Input HIGH Current, VCC = VIN = 3.63 V −10 50 A IIL Input LOW Current, VCC = 3.63 V, VIN = 0 V −150 0 A TERMINATION RESISTORS RTIN Internal Input Termination Resistor (IN to VT) 40 50 60  RDIFF_IN Differential Input Resistance (IN to IN) 80 100 120  NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL outputs loaded with 50  to VCC − 2.0 V for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth is applied to the complementary input when operating in single−ended mode. 7. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 8. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB6L14 Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, TA = −40°C to +85°C (Note 9) Symbol VOUTPP Characteristic Min Typ Output Voltage Amplitude (@ VINPPmin) (Note 10) fIN ≤ 1.25 GHz 1.25 GHz ≤ fin ≤ 2.0 GHz 2.0 GHz ≤ fin ≤ 3.0 GHz 550 380 250 700 500 320 fDATA Maximum Operating Data Rate tPD Propagation Delay tS tH tSKEW Within−Device Skew (Note 12) Max mV 2.5 Gb/s IN to Q 250 370 500 Set−Up Time (Note 11) EN to IN, IN 300 ps Hold Time (Note 11) EN to IN, IN 300 ps 5.0 20 Device to Device Skew (Note 13) tJITTER Unit ps ps 150 RMS Random Jitter (Note 14) Peak−to−Peak Data Dependent Jitter (Note 15) fIN = 2.5 GHz 1.0 fDATA = 2.5 Gb/s ps 14 VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) 100 tr,tf Output Rise/Fall Times @ Full Output Swing (20%−80%) 70 150 VCC − GND mV 200 ps VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPP (min) from a 50% duty cycle clock source. All loading with an external RL = 50  to VCC – 2.0 V. Input edge rates 40 ps (20%−80%). 10. Input and output voltage swing is a single−ended measurement operating in differential mode. 11. Set−up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set−up and hold times do not apply. 12. Within device skew is measured between two different outputs under identical power supply, temperature and input conditions. 13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 2^23−1 and K28.5 at 2.5Gb/s. 800 700 600 500 400 300 200 100 0 0 1 2 3 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 4. Output Voltage Amplitude (VOUTPP) versus Output Frequency at Ambient Temperature (Typical) http://onsemi.com 5 NB6L14 Figure 5. Typical Phase Noise Plot at fcarrier = 311.04 MHz Figure 6. Typical Phase Noise Plot at fcarrier = 622.08 MHz Figure 7. Typical Phase Noise Plot at fcarrier = 1 GHz Figure 8. Typical Phase Noise Plot at fcarrier = 2 GHz device (integrated between 12 kHz and 20 MHz; as shown in the shaded region of the plot) at each of the frequencies is 27 fs, 17 fs, 13 fs and 5 fs respectively. The input source used for the phase noise measurements is Agilent E8663B. The above phase noise plots captured using Agilent E5052A show additive phase noise of the NB6L14 device at frequencies 311.04 MHz, 622.08 MHz, 1 GHz and 2 GHz respectively at an operating voltage of 3.3 V in room temperature. The RMS Phase Jitter contributed by the http://onsemi.com 6 NB6L14 INn VTn INn 50  50  Figure 9. Input Structure VCC Vthmax IN VIH VIHmax VILmax Vth VIH Vth VIL Vth VIL IN VIHmin Vthmin Vth VILmin GND Figure 11. Vth Diagram Figure 10. Differential Input Driven Single−Ended VCC VIH(MAX) VIL D VIH VID = VIHD − VILD VCMR VIL D VIH Figure 12. Differential Inputs Driven Differentially VIL(MIN) GND Figure 13. VCMR Diagram IN VINPP = VIH(IN) − VIL(IN) IN Q VOUTPP = VOH(Q) − VOL(Q) Q tPD tPD Figure 14. AC Reference Measurement http://onsemi.com 7 NB6L14 VCC VCC VCC NB6L14 Zo = 50  LVPECL Driver VCC Zo = 50  IN 50  VT = VCC − 2 V Zo = 50  LVDS Driver 50  NB6L14 IN 50  VT = Open Zo = 50  IN 50  IN GND GND GND GND Figure 15. LVPECL Interface Figure 16. LVDS Interface VCC VCC NB6L14 Zo = 50  CML Driver IN 50  VT = VCC Zo = 50  50  IN GND GND Figure 17. Standard 50 W Load CML Interface VCC VCC VCC Zo = 50  Differential Driver VCC NB6L14 Zo = 50  IN 50  VT = VREF_AC* Zo = 50  Single−Ended Driver 50  IN GND Figure 18. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) NB6L14 IN 50  VT = VREF_AC* 50  IN GND GND Figure 19. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC) *VREFAC bypassed to ground with a 0.01 F capacitor http://onsemi.com 8 (Open) GND NB6L14 EN VCC/2 /IN IN VCC/2 tS tH VINPP tpd /Q VOUTPP Q Figure 20. EN Timing Diagram Q Zo = 50  D Receiver Device Driver Device Q D Zo = 50  50  50  VTT VTT = VCC − 2.0 V Figure 21. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NB6L14MNG QFN−16, 3x3 mm (Pb−Free) 123 Units / Rail NB6L14MNR2G QFN−16, 3x3 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE G 1 SCALE 2:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04795D QFN16 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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