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NCP3712ASNT1

NCP3712ASNT1

  • 厂商:

    ONSEMI(安森美)

  • 封装:

  • 描述:

    NCP3712ASNT1 - Over Voltage Protected High Side Switch - ON Semiconductor

  • 数据手册
  • 价格&库存
NCP3712ASNT1 数据手册
NCP3712ASNT1 Over Voltage Protected High Side Switch This switch is primarily intended to protect loads from transients by isolating the load from the transient energy rather than absorbing it. Features • Capable of Switching Loads of up to 200 mA without External • • • • • • • • • • • • • Rboost Switch Shuts Off in Response to an Over Voltage Input Transient Features Active Turn Off for Fast Input Transient Protection Flexible Over Voltage Protection Threshold Set with External Zener Automatic Recovery after Transient Decays Below Threshold Withstands Input Transients up to 105 V Peak Guaranteed Off State with Enbl Input ESD Resistant in Accordance with the 2000 V Human Body Model Extremely Low Saturation Voltage High Voltage Transient Isolation Power Switching to Electronic Modules DC Power Distribution in Line Operated Equipment Buffering Sensitive Circuits from Poorly Regulated Power Supplies Pre–conditioning of Voltage Regulator Input Voltage http://onsemi.com MARKING DIAGRAM TSOP–6 (SOT23–6, SC59–6) CASE 318G 6 1 BAGYW BAG = Specific Device Code Y = Year W = Work Week Applications Include: INTERNAL CIRCUIT DIAGRAM/ PIN CONFIGURATION Vin Q2 (5) R2 R4 Q1 Rboost N.C. Vout (6) (3) R1 R3 (2) Vin Vout Rboost NCP3712ASNT1 (4) VZ (1) Enbl + P. S. – VZ Ropt Enbl or 1 k (min) L O A D ORDERING INFORMATION Device NCP3712ASNT1 Package Shipping TSOP–6 3000 Units (SOT23–6, SC59–6) on 7” Reel SW Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2001 1 September, 2001 – Rev. 2 Publication Order Number: NCP3712ASNT1/D NCP3712ASNT1 MAXIMUM RATINGS* (TJ = 25°C unless otherwise noted) (Note 1) Rating Input–to–Output Voltage Reverse Input–to–Vz. Voltage Reverse Input–to–Rboost Voltage Output Load Current – Continuous Enbl Input Current – Continuous Vz Input Current – Continuous Rboost Input Current – Continuous Junction Temperature Operating Ambient Temperature Range Storage Temperature Range Device Power Dissipation (Minimum Footprint) Derate Above 25°C Latch–up Performance: Positive Negative *Maximum Ratings are those values beyond which damage to the device may occur. 1. This device contains ESD protection and exceeds the following tests: Human Body Model 1500 V per MIL–STD–883, Method 3015. Machine Model Method 150 V. Symbol Vio Vin(rev) Vin(rev) Iload Ienbl Iz Iboost TJ TA Tstg PD – ILatch–up 200 200 Value 105 –9.0 –5.0 –300 5.0 3.0 10 125 –40 to +85 –65 to +150 300 2.4 Unit V V V mA mA mA mA °C °C °C mW mW/°C mA http://onsemi.com 2 NCP3712ASNT1 ELECTRICAL CHARACTERISTICS (Vin = 12.5 VDC Ref to Gnd, TA = 25°C unless otherwise noted.) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Input–Output Breakdown Voltage (@ Iout = 200 µA) Output Reverse Breakdown Voltage (@ Iout = –1.0 mA Pulse) Output Leakage Current (Vin = Venbl = 30 V, TA = 25°C) Guaranteed “Off” State “ENBL NOT” Voltage Required “Off” State Iz Current (Rload = 100 W) Vin(off) (Vz = 16 V, Iload = 100 mA, Renbl = 1500 W) (IO ≤ 100 µA) V(BRio) V(–BRout) Iload(off) – Venbl(off) Iz(off) Voff 15.5 – 18.7 13 150 – – – –100 – – Vdc µAdc Vdc 105 – – –0.7 – – Vdc Vdc µAdc ON CHARACTERISTICS Input–Output On Voltage (Io = 100 mA, Ienbl = –3.0 mA) Output Load Current  Continuous (Ienbl = –3.0 mA, Vio(on) = 0.5 Vdc) (Iboost = –9.0 mA, Vio(on) = 0.5 Vdc) (Iboost = –9.0 mA, Vio(on) = 0.6 Vdc) Vin(on) (Vz = 16 V, Iload = 100 mA, Renbl = 1500 W) “ENBL NOT” Input Current (Io = 100 mA, Vio(on) = 0.35 Vdc, Renbl = 1500 W) Vio(on) – Io(on) – – – Von 8.5 Ienbl – – –1.0 – 10.5 mAdc – – – –200 –200 –300 Vdc 0.2 0.5 mAdc Vdc SWITCHING CHARACTERISTICS Characteristic Propagation Delay Time: Hi to Lo Prop Delay; Fig. 3 (Vin = Venbl = 13.5 V) Lo to Hi Prop Delay; Fig. 3 (Vin = 13.5 V, Venbl = 0 V) Transition Times: Fall Time; Fig. 4 (Vin = Venbl = 13.5 V) Rise Time; Fig. 4 (Vin = Venbl = 0 V) Symbol tPHL tPLH tf tr Min – – – – Typ 1.5 1.5 75 400 Max – – hS – – Units µS INTERNAL RESISTORS Input Leakage Resistor Input Resistor Output Leakage Resistor Enable Input Resistor R2 R1 R4 R3 7.0 3.3 1.4 1.4 10 4.7 2.4 2.4 13 6.1 3.2 3.2 kW kW kW kW http://onsemi.com 3 NCP3712ASNT1 A+ 1N4004 0.01 mF TYP FB* 0.027 mF TYP 18 V TYP R opt Enbl 1 Ienbl N.C. 2 Rboost Iboost 3 NCP3712 ASNT1 Vout 6 Vin 5 VZ 4 IZ Iload Rload Renbl KEY 0–500 W 1.0 k TYP FB* A– *FB = MMZ2012 Y601B Figure 2. Typical Applications Circuit for Load Dump Transient Protection 15 13.5 V SUPPLY RAIL “ENABLE NOT” INPUT 120 100 AMPLITUDE (V) 80 60 40 20 Voff 13.5 V SUPPLY RAIL Von LOAD DEPENDENT OUTPUT EXP DECAY TYPICAL INPUT TRANSIENT DEVICE OUTPUT VOLTAGE LOAD DEPENDENT EXP DECAY AMPLITUDE (V) 10 50% AMPLITUDE tpLH 5 0 0 5 10 15 20 25 30 35 40 45 50 TIME (ms) 0 0 50 100 150 200 250 300 350 TIME (ms) Figure 3. Enable NOT Switching Waveforms Figure 4. Load Dump Waveforms http://onsemi.com 4 NCP3712ASNT1 INFORMATION FOR USING THE TSOP–6 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection 0.094 2.4 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0 inches mm TSOP–6 (SOT23–6, SC59–6) TSOP–6 POWER DISSIPATION The power dissipation of the TSOP–6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the TSOP–6 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 950 milliwatts. PD = 150°C – 25°C 132°C/W = 950 milliwatts The 132°C/W for the TSOP–6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 950 milliwatts. There are other alternatives to achieving higher power dissipation from the TSOP–6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad™. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. http://onsemi.com 5 NCP3712ASNT1 PACKAGE DIMENSIONS TSOP–6 CASE 318G–02 ISSUE H A L 6 5 1 2 4 3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181 S B D G M 0.05 (0.002) H C K J http://onsemi.com 6 NCP3712ASNT1 Notes http://onsemi.com 7 NCP3712ASNT1 Thermal Clad is a registered trademark of the Bergquist Company. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800–282–9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 NCP3712ASNT1/D
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