DATA SHEET
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200 mA, Ultra-Low
Quiescent Current, IQ 12 mA,
Ultra-Low Noise, Low
Dropout Regulator
NCP752
XDFN6
CASE 711AE
MARKING DIAGRAMS
Noise sensitive RF applications such as Power Amplifiers in
satellite radios, infotainment equipment, and precision
instrumentation require very clean power supplies. The NCP752 is
200 mA LDO that provides the engineer with a very stable, accurate
voltage with ultra low noise and very high Power Supply Rejection
Ratio (PSRR) suitable for RF applications. The device doesn’t require
any additional noise bypass capacitor to achieve ultra low noise
performance. In order to optimize performance for battery operated
portable applications, the NCP752 employs the Auto Low−Power
Function for Ultra Low Quiescent Current consumption.
Features
Contact Factory for Other Voltage Options
Ultra Low Quiescent Current of Typ. 12 mA
Ultra Low Noise: 11.5 mVRMS from 100 Hz to 100 kHz
Very Low Dropout: 130 mV Typical at 200 mA
±2% Accuracy Over Load/Line/Temperature
High PSRR: 68 dB at 1 kHz
Power Good Output
Internal Soft−Start to Limit the Inrush Current
Thermal Shutdown and Current Limit Protections
Stable with a 1 mF Ceramic Output Capacitor
Available in TSOP−5 and XDFN 1.5 x 1.5 mm Package
Active Output Discharge for Fast Turn−Off
These are Pb−Free Devices
XXXAYWG
G
1
TSOP−5
= Specific Device Code
= Assembly Location
= Date Code
= Year
= Work Week
= Pb−Free Package
5
EN 3
4 PG
TSOP−5
1
OUT
IN
GND
EN
XDFN6
(Top view)
VOUT
PG
N/C
GND
OUT
NCP752
OUT
GND 2
PG
IN
OFF
5
IN 1
VIN
EN
XDFN6
PIN CONNECTIONS
• PDAs, Mobile phones, GPS, Smartphones
• Wireless Handsets, Wireless LAN, Bluetooth®, Zigbee®
• Portable Medical and Other Battery Powered Devices
ON
X MG
G
(Note: Microdot may be in either location)
Typical Applications
CIN
1
XXX
A
M
Y
W
G
• Operating Input Voltage Range: 2.0 V to 5.5 V
• Available in Fixed Voltage Options: 0.8 to 3.5 V
•
•
•
•
•
•
•
•
•
•
•
•
TSOP−5
CASE 483
100k
COUT
1 mF
VPG
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2013
September, 2022 − Rev. 3
1
Publication Order Number:
NCP752/D
NCP752
IN
ENABLE
LOGIC
EN
BANDGAP
REFERENCE
UVLO
0.8 V
−
THERMAL
SHUTDOWN
MOSFET
DRIVER WITH
CURRENT LIMIT
+
OUT
AUTO LOW
POWER MODE
PG
−
+
ACTIVE
DISCHARGE
EN
DELAY
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
XDFN 6
Pin No.
TSOP−5
Pin Name
Description
1
5
OUT
Regulated output voltage pin. A small 1 mF ceramic capacitor is needed from this pin to
ground to assure stability.
2
4
PG
3
2
GND
4
3
EN
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts
the regulator into shutdown mode.
N/C
Not connected. This pin can be tied to ground to improve thermal dissipation.
5
6
1
IN
Open Drain Power Good Output.
Power supply ground. Connected to the die through the lead frame. Soldered to the
copper plane allows for effective heat dissipation.
Input pin. A small capacitor is needed from this pin to ground to assure stability.
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2
NCP752
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
−0.3 V to 6 V
V
Output Voltage
VOUT
−0.3 V to VIN + 0.3 V
V
Enable Input
VEN
−0.3 V to VIN + 0.3 V
V
Power Good Output
VPG
−0.3 V to VIN + 0.3 V
V
Output Short Circuit Duration
tSC
Indefinite
s
TJ(MAX)
150
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Input Voltage (Note 1)
Maximum Junction Temperature
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JESD22−A114
ESD Machine Model tested per JESD22−A115
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS (Note 3)
Rating
Symbol
Value
Unit
Thermal Characteristics, TSOP−5,
Thermal Resistance, Junction−to−Air
RqJA
224
°C/W
Thermal Characteristics, XDFN6 1.5x1.5mm
Thermal Resistance, Junction−to−Air
RqJA
149
°C/W
3. Single component mounted on 1 oz FR 4 PCB with 645 mm2 cu area.
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3
NCP752
ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125 °C; VIN = VOUT(NOM) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, CIN = COUT = 1 mF, unless otherwise noted.
Typical values are at TJ = +25°C (Note 4)
Symbol
Min
VIN
2.0
VIN rising
UVLO
1.2
VOUT + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 0 − 200 mA
VOUT
−2
Line Regulation
VOUT + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA
RegLINE
300
mV/V
Load Regulation
IOUT = 0 mA to 200 mA
RegLOAD
20
mV/mA
IOUT = 1 mA to 200 mA or 200 mA to 1 mA in
1 ms, COUT = 1 ms
TranLOAD
±90
mV
IOUT = 200 mA, VOUT(nom) = 2.5 V
VDO
130
200
mV
VOUT = 90% VOUT(nom)
ICL
400
550
mA
IOUT = 0 mA
IQ
12
25
mA
IOUT = 200 mA
IGND
150
mA
VEN ≤ 0.4 V, TJ = +25°C
IDIS
0.12
mA
Parameter
Test Conditions
Operating Input Voltage
Undervoltage lock−out
Output Voltage Accuracy
Load Transient
Dropout voltage (Note 5)
Output Current Limit
Quiescent current
Ground current
Shutdown current
EN Pin Threshold Voltage
High Threshold
Low Threshold
EN Pin Input Current
Turn−on Time
210
VEN ≤ 0 V, VIN = 5.5 V
Typ
1.5
0.55
Max
Unit
5.5
V
1.9
V
+2
%
1
mA
V
VEN Voltage increasing
VEN Voltage decreasing
VEN_HI
VEN_LO
VEN = 5.5 V
IEN
100
COUT = 1.0 mF, IOUT = 0 mA to 200 mA
From VOUT = 10% VOUT(NOM) to 95%
VOUT(NOM)
tON1
80
ms
COUT = 1.0 mF, IOUT = 0 mA to 200 mA
From assertion of the EN to 95% VOUT(NOM)
tON2
200
ms
PSRR
70
68
53
dB
0.4
500
nA
Power Supply Rejection Ratio
VIN = 3 V, VOUT = 2.5 V
IOUT = 150 mA
Output Noise Voltage
VOUT = 2.5 V, VIN = 3 V, IOUT = 200 mA
f = 100 Hz to 100 kHz
VN
11.5
mVrms
Thermal Shutdown Temperature
Temperature increasing from TJ = +25°C
TSD
160
°C
Temperature falling from TSD
TSDH
−
20
−
°C
VOUT decreasing
VPG−
90
92
94
%VOUT
VOUT increasing
VPG+
92
94
96
%VOUT
Thermal Shutdown Hysteresis
f = 100 Hz
f = 1 kHz
f = 10 kHz
0.9
POWER GOOD OUTPUT
PG Threshold Voltage
PG Threshold Voltage
Hysteresis
PG Output Low Voltage
PG Pin Leakage
Measured on VOUT
2
%VOUT
IOUT(PG) = 1 mA
0.1
0.4
V
VIN = VOUT(NOM) + 0.3 V
0.002
1
mA
PG time−out delay
NCP752A
NCP752B
tRD
2
200
ms
PG reaction time
NCP752A
NCP752B
tRR
2
5
ms
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested
at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as
possible.
5. Characterized when VOUT falls 100 mV below the regulated voltage at VIN = VOUT(NOM) + 0.3 V.
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NCP752
VIN = 2 V
VOUT = 0.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
50 mV/div
VIN = 2 V
VOUT = 0.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VOUT = 0.8 V
100 mA/div
30 mA/div
50 mV/div
TYPICAL CHARACTERISTICS
IOUT = 30 mA
IOUT = 1 mA
VOUT = 0.8 V
IOUT = 100 mA
IOUT = 1 mA
50 ms/div
20 ms/div
Figure 3. Load Transient Response, 1 mA −
30 mA NCP752A/B, VOUT = 0.8 V
Figure 4. Load Transient Response, 1 mA −
100 mA NCP752A/B, VOUT = 0.8 V
100 mV/div
50 mV/div
VIN = 2 V
VOUT = 0.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VOUT = 0.8 V
VIN = 2 V
VOUT = 0.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VOUT = 0.8 V
200 mA/div
IOUT = 10 mA
IOUT = 1 mA
20 ms/div
50 ms/div
Figure 5. Load Transient Response, 10 mA −
110 mA NCP752A/B, VOUT = 0.8 V
Figure 6. Load Transient Response, 1 mA −
200 mA NCP752A/B, VOUT = 0.8 V
VIN = 2 V
VOUT = 0.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
50 mV/div
100 mV/div
100 mA/div
IOUT = 200 mA
IOUT = 110 mA
VOUT = 0.8 V
VIN = 2 V
VOUT = 0.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VOUT = 0.8 V
IOUT = 200 mA
200 mA/div
200 mA/div
IOUT = 210 mA
IOUT = 10 mA
IOUT = 1 mA
20 ms/div
50 ms/div
Figure 7. Load Transient Response, 10 mA −
210 mA NCP752A/B, VOUT = 0.8 V
Figure 8. Load Transient Response, 1 mA −
100 mA NCP752A/B, VOUT = 0.8 V
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NCP752
VIN = 2.3 V
VOUT = 1.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
50 mV/div
VIN = 2.3 V
VOUT = 1.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
100 mA/div
VOUT = 1.8 V
IOUT = 30 mA
30 mA/div
50 mV/div
TYPICAL CHARACTERISTICS
IOUT = 1 mA
VOUT = 1.8 V
IOUT = 100 mA
IOUT = 1 mA
20 ms/div
20 ms/div
Figure 9. Load Transient Response, 1 mA − 30 mA
NCP752A/B, VOUT = 1.8 V
100 mV/div
VIN = 2.3 V
VOUT = 1.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
50 mV/div
VOUT = 1.8 V
IOUT = 110 mA
VIN = 2.3 V
VOUT = 1.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VOUT = 1.8 V
IOUT = 200 mA
200 mA/div
100 mA/div
Figure 10. Load Transient Response, 1 mA −
100 mA NCP752A/B, VOUT = 1.8 V
IOUT = 10 mA
IOUT = 1 mA
20 ms/div
20 ms/div
Figure 12. Load Transient Response, 1 mA −
200 mA NCP752A/B, VOUT = 1.8 V
VIN = 2.3 V
VOUT = 1.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VIN = 2.3 V
VOUT = 1.8 V
CIN = COUT = 1 mF
tRISE = tFALL = 10 ms
50 V/div
100 mV/div
Figure 11. Load Transient Response, 1 mA − 30 mA
NCP752A/B, VOUT = 1.8 V
VOUT = 1.8 V
VOUT = 1.8 V
IOUT = 200 mA
200 mA/div
200 mA/div
IOUT = 210 mA
IOUT = 10 mA
IOUT = 1 mA
100 ms/div
20 ms/div
Figure 13. Load Transient Response, 10 mA −
210 mA NCP752A/B, VOUT = 1.8 V
Figure 14. Load Transient Response, 1 mA −
200 mA NCP752A/B, VOUT = 1.8 V
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NCP752
TYPICAL CHARACTERISTICS
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
50 mV/div
VOUT = 3.3 V
IOUT = 30 mA
100 mA/div
30 mA/div
50 mV/div
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
IOUT = 1 mA
VOUT = 3.3 V
IOUT = 100 mA
IOUT = 1 mA
20 ms/div
100 ms/div
Figure 15. Load Transient Response, 1 mA − 30 mA
NCP752A/B, VOUT = 3.3 V
Figure 16. Load Transient Response, 1 mA −
100 mA NCP752A/B, VOUT = 3.3 V
100 mV/div
50 mV/div
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VOUT = 3.3 V
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VOUT = 3.3 V
200 mA/div
100 mA/div
IOUT = 200 mA
IOUT = 110 mA
IOUT = 10 mA
IOUT = 1 mA
20 ms/div
20 ms/div
Figure 17. Load Transient Response, 10 mA −
110 mA NCP752A/B, VOUT = 3.3 V
Figure 18. Load Transient Response, 1 mA −
200 mA NCP752A/B, VOUT = 3.3 V
IOUT = 10 mA
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
50 mV/div
100 mV/div
VOUT = 3.3 V
200 mA/div
VIN = 3.8 V
VOUT = 3.3 V
CIN = COUT = 1 mF
tRISE = tFALL = 1 ms
VOUT = 3.3 V
IOUT = 200 mA
200 mA/div
IOUT = 200 mA
IOUT = 1 mA
20 ms/div
100 ms/div
Figure 19. Load Transient Response, 10 mA −
200 mA NCP752A/B, VOUT = 3.3 V
Figure 20. Load Transient Response, 1 mA −
200 mA NCP752A/B, VOUT = 3.3 V
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NCP752
IOUT = 1 mA
VOUT = 0 V
VPG = 0 V
IOUT = 1 mA
100 ms/div
100 ms/div
VPG = 1.8 V
VOUT = 0 V
VPG = 0 V
IOUT = 1 mA
VEN = 0 V
VIN = 2.3 V
CIN = COUT = 1 mF
VOUT = 1.8 V
VOUT = 0 V
VPG = 0 V
VPG = 1.8 V
IOUT = 1 mA
100 ms/div
100 ms/div
VOUT = 3.3 V
VIN = 2.3 V
CIN = COUT = 1 mF
VPG = 3.3 V
1 V/div
VEN = 1.2 V
Figure 24. Turn−On Response After Asserting EN
NCP752B, VOUT = 1.8 V
100 mA/div 2 V/div
1 V/div
1 V/div
1 V/div
Figure 23. Turn−On Response After Asserting EN
NCP752A, VOUT = 1.8 V
VEN = 0 V
VEN = 1.2 V
VOUT = 0 V
VPG = 0 V
IOUT = 1 mA
2 V/div
VOUT = 1.8 V
VIN = 2.3 V
CIN = COUT = 1 mF
1 V/div
VEN = 1.2 V
Figure 22. Turn−On Response After Asserting EN
NCP752B, VOUT = 0.8 V
100 mA/div 1 V/div
500 mV/div
500 mV/div
1 V/div
Figure 21. Turn−On Response After Asserting EN
NCP752A, VOUT = 0.8 V
VEN = 0 V
VIN = 2 V
CIN = COUT = 1 mF
400 mV/div
VIN = 2 V
CIN = COUT = 1 mF
100 mA/div
VOUT = 0 V
VPG = 0 V
VPG = 0.8 V
VEN = 0 V
VEN = 1.2 V
VIN = 3.8 V
CIN = COUT = 1 mF
VOUT = 3.3 V
VPG = 3.3 V
VOUT = 0 V
VPG = 0 V
IOUT = 1 mA
100 ms/div
2 V/div
200 mA/div
VPG = 0.8 V
VOUT = 0.8 V
VEN = 0 V
100 mA/div
VOUT = 0.8 V
VEN = 1.2 V
100 mA/div
VEN = 0 V
1 V/div
VEN = 1.2 V
100 mA/div 400 mV/div
200 mA/div
1 V/div
TYPICAL CHARACTERISTICS
200 ms/div
Figure 25. Turn−On Response After Asserting EN
NCP752A, VOUT = 3.3 V
Figure 26. Turn−On Response After Asserting EN
NCP752B, VOUT = 3.3 V
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NCP752
TYPICAL CHARACTERISTICS
VPG = 0.8 V
VOUT = 0 V
VPG = 0 V
VIN = 2.0 V
CIN = COUT = 1 mF
VEN = 0 V
VOUT = 1.8 V
VPG = 1.8 V
VIN = 2.3 V
CIN = COUT = 1 mF
Figure 28. Turn−Off Response After De−asserting
EN NCP752A/B, VOUT = 1.8 V
VOUT = 3.3 V
VEN = 0 V
VPG = 3.3 V
VOUT = 0 V
VPG = 0 V
400 mV/div 200 mV/div
Figure 27. Turn−Off Response After De−asserting
EN NCP752A/B, VOUT = 0.8 V
1 V/div
500 ms/div
2 V/div 1 V/div
500 ms/div
VEN = 1.2 V
VPG = 0.8 V
VOUT = 0 V
VPG = 0 V
500 ms/div
Thermal Shutdown
500 ms/div
VOUT = 1.8 V
VPG = 1.8 V
VOUT = 0 V
VPG = 0 V
2 V/div
VIN = 2.3 V
CIN = COUT = 1 mF
Figure 30. Turn−Off Response Due to Thermal
Shutdown NCP752A/B, VOUT = 0.8 V
1 V/div
Figure 29. Turn−Off Response After De−asserting
EN NCP752A/B, VOUT = 3.3 V
Normal
Operation
VIN = 2.0 V
CIN = COUT = 1 mF
VOUT = 0.8 V
Normal
Operation
VIN = 3.8 V
CIN = COUT = 1 mF
1 V/div 500 mV/div
VOUT = 0 V
VPG = 0 V
VOUT = 3.3 V
VPG = 3.3 V
Normal
Operation
Thermal Shutdown
VIN = 3.8 V
CIN = COUT = 1 mF
500 ms/div
VOUT = 0 V
VPG = 0 V
Thermal Shutdown
500 ms/div
Figure 31. Turn−Off Response Due to Thermal
Shutdown, VOUT = 1.8 V
Figure 32. Turn−Off Response Due to Thermal
Shutdown, VOUT = 3.3 V
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1 V/div
VOUT = 0.8 V
1 V/div
500 mV/div
VEN = 1.2 V
VEN = 0 V
2 V/div
400 mV/div 200 mV/div
VEN = 1.2 V
NCP752
VIN = 2.0 V
CIN = COUT = 1 mF
IOUT = 1 mA
VPG = 0.8 V
VIN = 2.0 V
CIN = COUT = 1 mF
IOUT = 1 mA
500 ms/div
500 ms/div
VOUT = 1.8 V
VPG = 1.8 V
VOUT = 0 V
VPG = 0 V
Thermal
Shutdown
Normal Operation
VOUT = 1.8 V
VPG = 1.8 V
VOUT = 0 V
VPG = 0 V
VIN = 2.3 V
CIN = COUT = 1 mF
IOUT = 1 mA
500 ms/div
100 mA/div
VIN = 2.3 V
CIN = COUT = 1 mF
IOUT = 1 mA
500 ms/div
Figure 36. Recovery from Thermal Shutdown
NCP752B, VOUT = 1.8 V
VOUT = 3.3 V
VPG = 3.3 V
VOUT = 0 V
VPG = 0 V
Thermal
Shutdown
2 V/div 1 V/div
Normal Operation
VOUT = 3.3 V
VPG = 3.3 V
VOUT = 0 V
VPG = 0 V
VIN = 3.8 V
CIN = COUT = 1 mF
100 mA/div
VIN = 3.8 V
CIN = COUT = 1 mF
IOUT = 1 mA
Normal Operation
IOUT = 1 mA
500 ms/div
500 ms/div
Figure 37. Recovery from Thermal Shutdown
NCP752A, VOUT = 3.3 V
Figure 38. Recovery from Thermal Shutdown
NCP752B, VOUT = 3.3 V
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2 V/div 1 V/div
Figure 35. Recovery from Thermal Shutdown
NCP752A, VOUT = 1.8 V
Thermal
Shutdown
100 mA/div
Normal Operation
1 V/div 500 mV/div
Figure 34. Recovery from Thermal Shutdown
NCP752B, VOUT = 0.8 V
1 V/div 500 mV/div
Figure 33. Recovery from Thermal Shutdown
NCP752A, VOUT = 0.8 V
Thermal
Shutdown
VOUT = 0.8 V
100 mA/div
VOUT = 0 V
VPG = 0 V
Normal Operation
400 mV/div 200 mV/div
VPG = 0.8 V
Thermal
Shutdown
100 mA/div
Normal Operation
VOUT = 0.8 V
100 mA/div
Thermal
Shutdown
400 mV/div 200 mV/div
TYPICAL CHARACTERISTICS
NCP752
TYPICAL CHARACTERISTICS
100 mA/div
VIN = VEN = 2.0 V
1 V/div 500 mV/div
1 V/div500 mV/div
VIN = VEN = 2.0 V
VOUT = 0.8 V
VPG = 0.8 V
VOUT = 0 V
VPG = 0 V
VIN = VEN = 0 V
VOUT = 0.8 V
VPG = 0.8 V
IOUT = 1 mA
2 ms/div
500 ms/div
Figure 40. Input Voltage Turn−off Response
NCP752B, VOUT = 0.8 V
1 V/div 500 mV/div
Figure 39. Input Voltage Turn−on Response
NCP752B, VOUT = 0.8 V
100 mA/div
1 V/div500 mV/div
VIN = VEN = 2.3 V
VOUT = 1.8 V
VPG = 1.8 V
VOUT = 0 V
VPG = 0 V
VIN = VEN = 0 V
VIN = VEN = 2.3 V
VOUT = 1.8 V
IOUT = 1 mA
500 ms/div
Figure 41. Input Voltage Turn−on Response
NCP752B, VOUT = 1.8 V
Figure 42. Input Voltage Turn−off Response
NCP752B, VOUT = 1.8 V
2 V/div 1 V/div
VIN = VEN = 2.3 V
2 V/div 1 V/div
VOUT = 0 V
VPG = 0 V
VIN = VEN = 0 V
VPG = 1.8 V
500 ms/div
100 mA/div
VOUT = 0 V
VPG = 0 V
VIN = VEN = 0 V
VOUT = 1.8 V
VPG = 1.8 V
VIN = VEN = 3.8 V
VOUT = 3.3 V
VOUT = 0 V
VPG = 0 V
VIN = VEN = 0 V
VPG = 3.3 V
VOUT = 0 V
VPG = 0 V
VIN = VEN = 0 V
1 ms/div
500 ms/div
Figure 43. Input Voltage Turn−on Response
NCP752B, VOUT = 3.3 V
Figure 44. Input Voltage Turn−off Response
NCP752B, VOUT = 3.3 V
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NCP752
VOUT = 0 V
VPG = 0 V
VIN = 0 V
VEN = 0 V
VOUT = 2.0 V
VPG = 0.8 V
VIN = VEN = 2.0 V
VOUT = 2.0 V
VPG = 0.8 V
VOUT = 0 V
VPG = 0 V
VIN = 0 V
VEN = 0 V
IOUT = 1 mA
500 ms/div
500 ms/div
VOUT = 3.3 V
100 mA/div
VPG = 3.8 V
2 V/div 1 V/div
VIN = VEN = 3.8 V
VOUT = 0 V
VPG = 0 V
VIN = 0 V
VEN = 0 V
Figure 46. Input Voltage Turn−off Response
NCP752B, VOUT = 0.8 V
2 V/div 1 V/div
Figure 45. Input Voltage Turn−on Response
NCP752B, VOUT = 0.8 V
VIN = VEN = 3.8 V
VOUT = 3.3 V
VPG = 3.8 V
VOUT = 0 V
VPG = 0 V
VIN = 0 V
VEN = 0 V
IOUT = 1 mA
500 ms/div
500 ms/div
2 V/div 1 V/div
Figure 47. Input Voltage Turn−on Response
NCP752B, VOUT = 3.3 V
Figure 48. Input Voltage Turn−off Response
NCP752B, VOUT = 3.3 V
Short−Circuit removed from the
output
VOUT = 3.3 V
VPG = 3.8 V
VOUT pulled to ground due to
output short−circuit
VOUT = 0 V
VPG = 0 V
VPG = 3.8 V
VPG = 0 V
200 mA/div
200 mA/div
VOUT = 0 V
IOUT = 360 mA
VOUT = 3.3 V
VIN = 3.8 V
ISC = 360 mA
500 ms/div
IOUT = 1 mA
500 ms/div
Figure 49. Short−Circuit Response NCP752B,
VOUT = 3.3 V
Figure 50. Recovery from Short−Circuit
NCP752B, VOUT = 3.3 V
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12
2 V/div 1 V/div
100 mA/div 500 mV/div
VIN = VEN = 2.0 V
500 mV/div 1 V/div
1 V/div 500 mV/div
TYPICAL CHARACTERISTICS
NCP752
TYPICAL CHARACTERISTICS
IOUT = 10 mA
VIN = 3.0 V
VIN = 2.5 V
20 mV/div 500 mV/div
20 mV/div 500 mV/div
IOUT = 10 mA
VIN = 2.0 V
VOUT = 0.8 V
COUT = 1 mF
tRISE = tFALL = 1 ms
VIN = 2.0 V
VOUT = 0.8 V
COUT = 1 mF
tRISE = tFALL = 1 ms
200 ms/div
200 ms/div
Figure 51. Line Transient 2 V − 2.5 V NCP752A/B,
VOUT = 0.8 V
Figure 52. Line Transient 2 V − 3 V NCP752A/B,
VOUT = 0.8 V
IOUT = 10 mA
1 V/div
VIN = 3.3 V
VIN = 2.8 V
VIN = 2.3 V
20 mV/div
20 mV/div 500 mV/div
IOUT = 10 mA
VOUT = 1.8 V
COUT = 1 mF
tRISE = tFALL = 1 ms
VIN = 2.3 V
VOUT = 1.8 V
COUT = 1 mF
tRISE = tFALL = 1 ms
200 ms/div
200 ms/div
Figure 53. Line Transient 2.3 V − 2.8 V NCP752A/B,
VOUT = 1.8 V
Figure 54. Line Transient 2.3 V − 3.3 V NCP752A/B,
VOUT = 1.8 V
IOUT = 10 mA
20 mV/div 500 mV/div
VIN = 4.2 V
20 mV/div 500 mV/div
IOUT = 10 mA
VIN = 4.8 V
VIN = 3.8 V
VOUT = 3.3 V
COUT = 1 mF
tRISE = tFALL = 1 ms
VIN = 3.8 V
VOUT = 3.3 V
COUT = 1 mF
tRISE = tFALL = 1 ms
200 ms/div
200 ms/div
Figure 55. Line Transient 3.8 V − 4.2 V NCP752A/B,
VOUT = 3.3 V
Figure 56. Line Transient 3.8 V − 4.8 V NCP752A/B,
VOUT = 3.3 V
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13
NCP752
TYPICAL CHARACTERISTICS
0.810
1.820
VIN = 2 V
COUT = COUT = 1 mF
IOUT = 10 mA
0.806
1.810
0.804
1.805
0.802
0.800
1.800
0.798
1.795
0.796
1.790
0.794
1.785
0.792
0.790
−40
−20
0
20
40
60
80
100
120
140
1.780
−40
VDO, DROPOUT VOLTAGE (mV)
VOUT, OUTPUT VOLTAGE (V)
3.300
3.295
3.290
3.285
−20
0
20
40
60
80
100
120
140
60
80
100
120
140
VOUT = 1.8 V
COUT = COUT = 1 mF
0.35
0.3
0.25
TJ = 125°C
0.2
TJ = 25°C
0.15
0.1
TJ = −40°C
0.05
0
0
20
40
60
80
100 120 140 160 180 200
TJ, JUNCTION TEMPERATURE (°C)
IOUT, OUTPUT CURRENT (mA)
Figure 59. Output Voltage vs. Temperature
VOUT = 3.3 V
Figure 60. Dropout Voltage vs. Load Current
VOUT = 1.8 V
50
0.2
VOUT = 3.3 V
COUT = COUT = 1 mF
0.18
IQ, QUIESCENT CURRENT (mA)
VDO, DROPOUT VOLTAGE (mV)
40
Figure 58. Output Voltage vs. Temperature
VOUT = 1.8 V
3.305
3.280
−40
20
Figure 57. Output Voltage vs. Temperature
VOUT = 0.8 V
VIN = 3.8 V
COUT = COUT = 1 mF
IOUT = 10 mA
3.310
0
TJ, JUNCTION TEMPERATURE (°C)
0.4
3.315
−20
TJ, JUNCTION TEMPERATURE (°C)
3.320
0.16
0.14
TJ = 125°C
0.12
TJ = 25°C
0.1
0.08
TJ = −40°C
0.06
0.02
0
VIN = 2.3 V
COUT = COUT = 1 mF
IOUT = 10 mA
1.815
VOUT, OUTPUT VOLTAGE (V)
VOUT, OUTPUT VOLTAGE (V)
0.808
0
20
40
60
80
100 120 140 160 180 200
45
TJ = 125°C
40
35
TJ = 25°C
30
25
TJ = −40°C
20
15
10
VOUT = 0.8 V
COUT = COUT = 1 mF
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IOUT, OUTPUT CURRENT (mA)
VIN, INPUT VOLTAGE (V)
Figure 61. Dropout Voltage vs. Load Current
VOUT = 3.3 V
Figure 62. Quiescent Current vs. Input Voltage
VOUT = 0.8 V
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14
5.5
NCP752
TYPICAL CHARACTERISTICS
50
TJ = 125°C
40
35
TJ = 25°C
30
25
TJ = −40°C
20
15
10
VOUT = 1.8 V
COUT = COUT = 1 mF
5
0
5
VLINE_REG, LINE REGULATION (mV)
IQ, QUIESCENT CURRENT (mA)
45
4.5
4
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
25
TJ = −40°C
20
15
10
VOUT = 3.3 V
COUT = COUT = 1 mF
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Figure 64. Quiescent Current vs. Input Voltage
VOUT = 3.3 V
10
VIN = VOUT + 0.5 V or 2 V
Up to 5.5 V
COUT = COUT = 1 mF
IOUT = 10 mA
VOUT = 3.3 V
1.5
VOUT = 0.8 V
1
0.5
0
−40
−20
0
20
40
60
80
100
120
VIN = VOUT + 0.5 V
COUT = COUT = 1 mF
IOUT = 0 mA − 200 mA
9
8
7
6
5
4
VOUT = 3.3 V
3
2
VOUT = 0.8 V
1
0
−40
140
−20
0
20
40
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 66. Load Regulation vs. Temperature
450
VEN, ENABLE THRESHOLD (V)
1
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 0.8 V
350
VIN = VOUT + 0.5 V or 2 V
COUT = COUT = 1 mF
VOUT = GND
200
−40
60
Figure 65. Line Regulation vs. Temperature
500
ISC, SHORT−CIRCUIT (mA)
TJ = 25°C
30
Figure 63. Quiescent Current vs. Input Voltage
VOUT = 1.8 V
2
250
35
VIN, INPUT VOLTAGE (V)
3
300
TJ = 125°C
40
VIN, INPUT VOLTAGE (V)
2.5
400
45
0
5.5
VLOAD_REG, LOAD REGULATION
(mV)
IQ, QUIESCENT CURRENT (mA)
50
−20
0
20
40
60
80
100
120
VIN = VOUT + 0.5 V or 2 V
COUT = COUT = 1 mF
VOUT = GND
0.9
0.8
VEN Increasing
0.7
0.6
VEN Decreasing
0.5
0.4
0.3
−40
140
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 67. Short−Circuit vs. Temperature
Figure 68. Enable Threshold vs. Temperature
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15
140
140
NCP752
TYPICAL CHARACTERISTICS
1
VIN = VEN
COUT = COUT = 1 mF
VOUT = GND
1.8
1.7
1.6
VIN Increasing
1.5
1.4
VIN Decreasing
1.3
1.2
1.1
1
−40
−20
0
20
40
60
80
100
120
0.3
0.2
0.1
0
−40
−20
0
20
40
VOUT = 0.8 V
200
VOUT = 3.3 V
180
VIN = VOUT + 0.5 V or 2 V
COUT = COUT = 1 mF
VEN = 0 V to 1 V
IOUT = 10 mA
−20
0
20
40
60
80
100
120
VPG, POWER GOOD THRESHOLD
(%VOUT)
100
60
80
100
120
98
97
96
95
VOUT Rising
94
93
VOUT Falling
92
91
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 71. Turn−on Time vs. Temperature
Figure 72. PG Threshold vs. Temperature
5
VIN = VOUT + 0.5 V or 2 V
COUT = COUT = 1 mF
4.5
4
3.5
3
2.5
2
1.5
1
0.5
−20
0
20
40
60
80
100
120
100
140
90
80
140
VPG = 5.5 V
COUT = COUT = 1 mF
70
60
50
40
30
20
10
0
−40
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 73. PG Threshold Hysteresis vs.
Temperature
Figure 74. PG Pin Leakage vs. Temperature
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16
140
VIN = VOUT + 0.5 V or 2 V
COUT = COUT = 1 mF
99
90
−40
140
IPG_LEAK, POWER GOOD LEAKAGE
(nA)
tON, TURN−ON TIME (ms)
VPG_HYST, POWER GOOD HYSTERESIS (%VOUT)
0.4
Figure 70. Disable Current vs. Temperature
220
0
−40
0.5
Figure 69. UVLO Threshold vs. Temperature
240
100
−40
0.6
TJ, JUNCTION TEMPERATURE (°C)
260
120
0.7
TJ, JUNCTION TEMPERATURE (°C)
280
140
0.8
140
300
160
VEN = VOUT + 0.5 V
COUT = COUT = 1 mF
VEN = 0 V
0.9
IDIS, DISABLE CURRENT (mA)
VUVLO, UVLO THRESHOLD (V)
2
1.9
140
NCP752
100
5
90
4.5
80
70
60
50
40
30
VIN = 2 V
COUT = 1 mF
IPG = 1 mA
20
10
0
−40
−20
0
20
40
60
80
100
120
tRD, tRR, PG TIMING (ms)
VPG_LOW, POWER GOOD VOLTAGE
(mV)
TYPICAL CHARACTERISTICS
4
3.5
3
PG Timeout Delay
2.5
2
1.5
PG Reaction Time
1
0.5
140
0
−40
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 75. PG Low Voltage vs. Temperature
Figure 76. NCP752A PG Reaction Time, Delay
Timing
200
140
100
180
PG Timeout Delay
160
140
120
VIN = VOUT + 0.5 V
COUT = CIN = 1 mF
NCP752B
100
80
60
40
20
CAPACITOR ESR (W)
tRD, tRR, PG TIMING (ms)
VIN = VOUT + 0.5 V
COUT = CIN = 1 mF
NCP752A
PG Reaction Time
0
−40
−20
0
20
40
60
80
100
120
140
Unstable Operation
10
1
VOUT = 3.3 V
Stable Operation
0.1
0.01
VIN = VOUT + 0.3 V or 2.0 V
COUT = CIN = 1 mF
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
OUTPUT CURRENT (mA)
Figure 77. NCP752B PG Reaction Time, Delay
Timing
Figure 78. Stability vs. Output Capacitors ESR
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17
200
NCP752
APPLICATION INFORMATION
to GND through a 1 kΩ resistor. In the disable state the
device consumes as low as typ. 120 nA from the VIN. If the
EN pin voltage > 0.9 V the device is guaranteed to be
enabled. The NCP752 regulates the output voltage and the
active discharge transistor is turned−off. The EN pin has an
internal pull*down current source with typ. value of
100 nA which assures that the device is turned−off when the
EN pin is not connected. A build in deglitch time in the EN
block prevents from periodic on/off oscillations that can
occur due to noise on EN line. In the case that the EN
function isn’t required the EN pin should be tied directly to
IN.
The NCP752 is a high performance, 200 mA LDO voltage
regulator with open−drain PG flag. This device delivers
excellent noise and dynamic performance. Thanks to its
adaptive ground current feature the device consumes only
12 mA of quiescent current at no−load condition. The
regulator features very−low noise of 11.5 mVRMS, PSRR of
typ. 68 dB at 1 kHz and very good load/line transient
response. The device is an ideal choice for battery powered
portable applications.
A logic EN input provides ON/OFF control of the output
voltage. When the EN is low the device consumes as low as
typ. 120 nA from the IN pin.
The device is fully protected in case of output overload,
output short circuit condition and overheating, assuring a
very robust design.
Reverse Current
The PMOS pass transistor has an inherent body diode
which will be forward biased in the case that VOUT > VIN.
Due to this fact in cases where the extended reverse current
condition is anticipated the device may require additional
external protection.
Input Capacitor Selection (CIN)
It is recommended to connect a minimum of 1 mF Ceramic
X5R or X7R capacitor close to the IN pin of the device.
Larger input capacitors may be necessary if fast and large
load transients are encountered in the application. There is
no requirement for the min./max. ESR of the input capacitor
but it is recommended to use ceramic capacitors for their low
ESR and ESL.
Output Current Limit
Output Current is internally limited within the IC to a
typical 400 mA. The NCP752 will source this amount of
current measured with the output voltage 100 mV lower
than the nominal VOUT. If the Output Voltage is directly
shorted to ground (VOUT = 0 V), the short circuit protection
will limit the output current to 410 mA (typ). The current
limit and short circuit protection will work properly up to
VIN = 5.5 V at TA = 25°C. There is no limitation for the short
circuit duration.
Output Capacitor Selection (COUT)
The NCP752 is designed to be stable with small 1.0 mF
and larger ceramic capacitors on the output. The minimum
effective output capacitance for which the LDO remains
stable is 500 nF. The safety margin is provided to account for
capacitance variations due to DC bias voltage, temperature,
initial tolerance. There is no requirement for the minimum
value of Equivalent Series Resistance (ESR) for the COUT
but the maximum value of ESR should be less than 700 mΩ.
Larger output capacitors could be used to improve the load
transient response or high frequency PSRR characteristics.
It is not recommended to use tantalum capacitors on the
output due to their large ESR. The equivalent series
resistance of tantalum capacitors is also strongly dependent
on the temperature, increasing at low temperature. The
tantalum capacitors are generally more costly than ceramic
capacitors.
Thermal Shutdown
When the die temperature exceeds the Thermal Shutdown
threshold (TSD − 160°C typical), Thermal Shutdown event
is detected and the device is disabled. The IC will remain in
this state until the die temperature decreases below the
Thermal Shutdown Reset threshold (TSDU − 140°C
typical). Once the IC temperature falls below the 140°C the
LDO is enabled again. The thermal shutdown feature
provides protection from a catastrophic device failure due to
accidental overheating. This protection is not intended to be
used as a substitute for proper heat sinking.
Power Dissipation
No−load Operation
As power dissipated in the LDO increases, it might
become necessary to provide some thermal relief. The
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. The maximum power dissipation the
NCP752 can handle is given by:
The regulator remains stable and regulates the output
voltage properly within the ±2% tolerance limits even with
no external load applied to the output.
Enable Operation
The NCP752 uses the EN pin to enable/disable its output
and to control the active discharge function. If the EN pin
voltage is < 0.4 V the device is guaranteed to be disabled.
The pass transistor is turned−off so that there is virtually no
current flow between the IN and OUT. In case of the option
equipped with active discharge − the active discharge
transistor is turned−on and the output voltage VOUT is pulled
P D(MAX) +
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18
ƪ125 * T Aƫ
q JA
(eq. 1)
NCP752
100 kHz − 10 MHz it can be tuned by the selection of COUT
capacitor and proper PCB layout.
For reliable operation junction tempertaure should be
limited to +125°C.
The power dissipated by the NCP752 for given
application conditions can be calculated as follows:
P D(MAX) + V INI GND ) I OUTǒV IN * V OUTǓ
Output Noise
The IC is designed for very−low output voltage noise. The
typical noise performance of 11.5 mVRMS makes the device
suitable for noise sensitive applications.
(eq. 2)
Load Regulation
The NCP752 features very good load regulation of typical
4 mV in the 0 mA to 200 mA range. In order to achieve this
very good load regulation a special attention to PCB design
is necessary. The trace resistance from the OUT pin to the
point of load can easily approach 100 mW which will cause
a 20 mV voltage drop at full load current, deteriorating the
excellent load regulation.
Internal Soft Start
Line Regulation
PCB Layout Recommendations
The Internal Soft−Start circuitry will limit the inrush
current during the LDO turn−on phase. Please refer to
typical characteristics section for typical inrush current
values. The soft−start function prevents from any output
voltage overshoots and assures monotonic ramp−up of the
output voltage.
To obtain good transient performance and good regulation
characteristics place CIN and COUT capacitors close to the
device pins and make the PCB traces wide. In order to
minimize the solution size use 0402 capacitors. Larger
copper area connected to the pins will also improve the
device thermal resistance. The actual power dissipation can
be calculated by the formula given in Equation 2.
The IC features very good line regulation of 0.3 mV/V
measured from VIN = VOUT + 0.5 V to 5.5 V.
Power Supply Rejection Ratio
At low frequencies the PSRR is mainly determined by the
feedback open−loop gain. At higher frequencies in the range
ORDERING INFORMATION
VOUT
Option
Marking
Rotation
NCP752AMX18TCG
1.8 V
A
90°
NCP752AMX28TCG (Note 6)
2.8 V
D
90°
NCP752AMX30TCG (Note 6)
3.0 V
E
90°
NCP752AMX33TCG (Note 6)
3.3 V
F
90°
NCP752ASN18T1G
1.8 V
EDA
NCP752ASN28T1G
2.8 V
EDC
NCP752ASN30T1G
3.0 V
EDD
NCP752ASN33T1G
3.3 V
EDE
NCP752BMX18TCG (Note 6)
1.8 V
A
270°
NCP752BMX28TCG (Note 6)
2.8 V
D
270°
NCP752BMX30TCG (Note 6)
3.0 V
E
270°
NCP752BMX33TCG (Note 6)
3.3 V
F
270°
NCP752BSN18T1G
1.8 V
EEA
NCP752BSN28T1G
2.8 V
EEC
NCP752BSN30T1G
3.0 V
EED
NCP752BSN33T1G
3.3 V
EEE
Device
Description
Ver. A
PG Time-out
Delay: 2 ms (Typ)
PG Reaction Time: 2 ms (Typ)
Package
Shipping†
XDFN6
(Pb−Free)
3000 or 5000 /
Tape & Reel
(Note 6)
TSOP−5
(Pb−Free)
Ver. B
PG Time-out Delay: 200 ms
(Typ)
PG Reaction Time: 5 ms (Typ)
XDFN6
(Pb−Free)
3000 or 5000 /
Tape & Reel
(Note 6)
TSOP−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
6. Product processed after October 1, 2022 are shipped with quantity 5000 units / tape & reel.
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19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
XDFN6 1.5x1.5, 0.5P
CASE 711AE
ISSUE B
DATE 27 AUG 2015
SCALE 4:1
D
L
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20mm FROM TERMINAL TIP.
L1
DETAIL A
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
ALTERNATE TERMINAL
CONSTRUCTIONS
E
PIN ONE
REFERENCE
ÉÉ
ÉÉ
EXPOSED Cu
0.10 C
2X
2X
0.10 C
DIM
A
A1
A3
b
D
E
e
L
L1
L2
TOP VIEW
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTIONS
A
DETAIL B
A3
0.05 C
GENERIC
MARKING DIAGRAM*
A1
0.05 C
C
SIDE VIEW
DETAIL A
e
SEATING
PLANE
1
XXXMG
G
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
5X
L
3
1
MILLIMETERS
MIN
MAX
0.35
0.45
0.00
0.05
0.13 REF
0.20
0.30
1.50 BSC
1.50 BSC
0.50 BSC
0.40
0.60
--0.15
0.50
0.70
L2
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
6
4
6X
RECOMMENDED
MOUNTING FOOTPRINT*
b
0.10 C A
BOTTOM VIEW
0.05 C
B
NOTE 3
6X
0.35
5X
0.73
1.80
0.83
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON56376E
XDFN6, 1.5 X 1.5, 0.5 P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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