DATA SHEET
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0.9 V, Rail-to-Rail, Single
Operational Amplifier
NCS2001, NCV2001
Features
•
•
•
•
•
•
•
•
•
•
0.9 V Guaranteed Operation
Rail−to−Rail Common Mode Input Voltage Range
Rail−to−Rail Output Drive Capability
No Output Phase Reversal for Over−Driven Input Signals
0.5 mV Trimmed Input Offset
10 pA Input Bias Current
1.4 MHz Unity Gain Bandwidth at "2.5 V, 1.1 MHz at "0.5 V
Tiny SC70−5 and SOT23−5 Packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
XXXMG
G
1
5
4
1
5
SC70−5
SQ SUFFIX
CASE 419A
23
| XXX
1
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
VOUT
1
VCC
Non−Inverting
Input
2
3
+ −
5
VEE
4
Inverting
Input
Style 1 Pinout (SN1T1, SQ1T2)
VOUT
1
VEE
Non−Inverting
Input
2
3
+ −
5
VCC
4
Inverting
Input
Style 2 Pinout (SN2T1, SQ2T2)
See detailed ordering, marking and shipping information in the
dimensions section on page 14 of this data sheet.
Single Cell NiCd/NiMH Battery Powered Applications
Cellular Telephones
Pagers
Personal Digital Assistants
Electronic Games
Digital Cameras
Camcorders
Hand−Held Instruments
Rail to Rail Input
0.8 V
to
7.0 V
5
5
ORDERING INFORMATION
Typical Applications
•
•
•
•
•
•
•
•
SOT23−5
SN SUFFIX
CASE 483
M
The NCS2001 is an industry first sub−one voltage operational
amplifier that features a rail−to−rail common mode input voltage range,
along with rail−to−rail output drive capability. This amplifier is
guaranteed to be fully operational down to 0.9 V, providing an ideal
solution for powering applications from a single cell Nickel Cadmium
(NiCd) or Nickel Metal Hydride (NiMH) battery. Additional features
include no output phase reversal with overdriven inputs, trimmed input
offset voltage of 0.5 mV, extremely low input bias current of 40 pA, and
a unity gain bandwidth of 1.4 MHz at 5.0 V. The tiny NCS2001 is the
ideal solution for small portable electronic applications and is available
in the space saving SOT23−5 and SC70−5 packages with two industry
standard pinouts.
MARKING DIAGRAMS
Rail to Rail Output
+
-
This device contains 63 active transistors.
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2017
October, 2021 − Rev. 19
1
Publication Order Number:
NCS2001/D
NCS2001, NCV2001
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
7.0
V
Input Differential Voltage Range (Note 1)
VIDR
VEE −300 mV to 7.0 V
V
Input Common Mode Voltage Range (Note 1)
VICR
VEE −300 mV to 7.0 V
V
Output Short Circuit Duration (Note 2)
tSc
Indefinite
sec
Junction Temperature
TJ
150
°C
RqJA
PD
235
340
°C/W
mW
RqJA
PD
280
286
°C/W
mW
Supply Voltage (VCC to VEE)
Power Dissipation and Thermal Characteristics
SOT23−5 Package
Thermal Resistance, Junction−to−Air
Power Dissipation @ TA = 70°C
SC70−5 Package
Thermal Resistance, Junction−to−Air
Power Dissipation @ TA = 70°C
Operating Ambient Temperature Range
NCS2001
NCV2001 (Note 3)
TA
Storage Temperature Range
Tstg
−65 to 150
°C
VESD
1500
V
ESD Protection at any Pin Human Body Model (Note 4)
°C
−40 to +105
−40 to +125
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Either or both inputs should not exceed the range of VEE −300 mV to VEE +7.0 V.
2. Maximum package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded.
TJ = TA + (PD RqJA).
3. NCV prefix is qualified for automotive usage.
4. ESD data available upon request.
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0 V, RL to GND, TA = 25°C unless otherwise noted.)
Characteristics
Symbol
Input Offset Voltage
VCC = 0.45 V, VEE = −0.45 V
TA = 25°C
TA = 0°C to 70°C
TA = −40°C to 125°C
VCC = 1.5 V, VEE = −1.5 V
TA = 25°C
TA = 0°C to 70°C
TA = −40°C to 125°C
VCC = 2.5 V, VEE = −2.5 V
TA = 25°C
TA = 0°C to 70°C
TA = −40°C to 125°C
Min
Typ
Max
VIO
Input Offset Voltage Temperature Coefficient (RS = 50)
TA = −40°C to 125°C
Input Bias Current (VCC = 1.0 V to 5.0 V)
Unit
mV
−6.0
−8.5
−9.5
0.5
−
−
6.0
8.5
9.5
−6.0
−7.0
−7.5
0.5
−
−
6.0
7.0
7.5
−6.0
−7.5
−7.5
0.5
−
−
6.0
7.5
7.5
DVIO/DT
−
8.0
−
mV/°C
IIB
−
10
−
pA
Input Common Mode Voltage Range
VICR
−
VEE to VCC
−
V
Large Signal Voltage Gain
VCC = 0.45 V, VEE = −0.45 V
RL = 10 k
RL = 2.0 k
VCC = 1.5 V, VEE = −1.5 V
RL = 10 k
RL = 2.0 k
VCC = 2.5 V, VEE = −2.5 V
RL = 10 k
RL = 2.0 k
AVOL
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2
kV/V
−
−
40
20
−
−
−
−
40
40
−
−
20
15
40
40
−
−
NCS2001, NCV2001
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0 V, RL to GND, TA = 25°C unless otherwise noted.)
Characteristics
Symbol
Output Voltage Swing, High State Output (VID = +0.5 V)
VCC = 0.45 V, VEE = −0.45 V
TA = 25°C
RL = 10 k
RL = 2.0 k
TA = 0°C to 70°C
RL = 10 k
RL = 2.0 k
TA = −40°C to 125°C
RL = 10 k
RL = 2.0 k
VCC = 1.5 V, VEE = −1.5 V
TA = 25°C
RL = 10 k
RL = 2.0 k
TA = 0°C to 70°C
RL = 10 k
RL = 2.0 k
TA = −40°C to 125°C
RL = 10 k
RL = 2.0 k
VCC = 2.5 V, VEE = −2.5 V
TA = 25°C
RL = 10 k
RL = 2.0 k
TA = 0°C to 70°C
RL = 10 k
RL = 2.0 k
TA = −40°C to 125°C
RL = 10 k
RL = 2.0 k
VOH
Output Voltage Swing, Low State Output (VID = −0.5 V)
VCC = 0.45 V, VEE = −0.45 V
TA = 25°C
RL = 10 k
RL = 2.0 k
TA = 0°C to 70°C
RL = 10 k
RL = 2.0 k
TA = −40°C to 125°C
RL = 10 k
RL = 2.0 k
VCC = 1.5 V, VEE = −1.5 V
TA = 25°C
RL = 10 k
RL = 2.0 k
TA = 0°C to 70°C
RL = 10 k
RL = 2.0 k
TA = −40°C to 125°C
RL = 10 k
RL = 2.0 k
VCC = 2.5 V, VEE = −2.5 V
TA = 25°C
RL = 10 k
RL = 2.0 k
TA = 0°C to 70°C
RL = 10 k
RL = 2.0 k
TA = −40°C to 125°C
RL = 10 k
RL = 2.0 k
VOL
Min
3
Max
Unit
V
0.40
0.35
0.494
0.466
−
−
0.40
0.35
−
−
−
−
0.40
0.35
−
−
−
−
1.45
1.40
1.498
1.480
−
−
1.45
1.40
−
−
−
−
1.45
1.40
−
−
−
−
2.45
2.40
2.498
2.475
−
−
2.45
2.40
−
−
−
−
2.45
2.40
−
−
−
−
V
−
−
−0.494
−0.480
−0.40
−0.35
−
−
−
−
−0.40
−0.35
−
−
−
−
−0.40
−0.35
−
−
−1.493
−1.480
−1.45
−1.40
−
−
−
−
−1.45
−1.40
−
−
−
−
−1.45
−1.40
−2.492
−2.479
−2.45
−2.40
−
−
−
−
−2.45
−2.40
−
−
−
−
−2.45
−2.40
−
−
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Typ
NCS2001, NCV2001
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0 V, RL to GND, TA = 25°C unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
Common Mode Rejection Ratio (Vin = 0 to 5.0 V)
CMRR
60
70
−
dB
Power Supply Rejection Ratio (VCC = 0.5 V to 2.5 V, VEE = −2.5 V)
PSRR
55
65
−
dB
Output Short Circuit Current
VCC = 0.45 V, VEE = −0.45 V, VID = "0.4 V
Source Current High Output State
Sink Current Low Output State
VCC = 1.5 V, VEE = −1.5 V, VID = "0.5 V
Source Current High Output State
Sink Current Low Output State
VCC = 2.5 V, VEE = −2.5 V, VID = "0.5 V
Source Current High Output State
Sink Current Low Output State
ISC
Power Supply Current (Per Amplifier, VO = 0 V)
VCC = 0.45 V, VEE = −0.45 V
TA = 25°C
TA = 0°C to 70°C
TA = −40°C to 125°C
VCC = 1.5 V, VEE = −1.5 V
TA = 25°C
TA = 0°C to 70°C
TA = −40°C to 125°C
VCC = 2.5 V, VEE = −2.5 V
TA = 25°C
TA = 0°C to 70°C
TA = −40°C to 125°C
ID
mA
0.5
−
1.2
−3.0
−
−1.5
15
−
29
−40
−
−20
40
−
76
−96
−
−50
mA
−
−
−
0.51
−
−
1.10
1.10
1.10
−
−
−
0.72
−
−
1.40
1.40
1.40
−
−
−
0.82
−
−
1.50
1.50
1.50
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0 V, RL to GND, TA = 25°C unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
Differential Input Resistance (VCM = 0 V)
Rin
−
u1.0
−
tera W
Differential Input Capacitance (VCM = 0 V)
Cin
−
3.0
−
pF
Equivalent Input Noise Voltage (f = 1.0 kHz)
en
−
100
−
nV/√Hz
−
−
0.5
1.1
1.3
1.4
−
−
−
Gain Bandwidth Product (f = 100 kHz)
VCC = 0.45 V, VEE = −0.45 V
VCC = 1.5 V, VEE = −1.5 V
VCC = 2.5 V, VEE = −2.5 V
GBW
MHz
Gain Margin (RL = 10 k, CL = 5.0 pf)
Am
−
6.5
−
dB
Phase Margin (RL = 10 k, CL = 5.0 pf)
fm
−
60
−
°
Power Bandwidth (VO = 4.0 Vpp, RL = 2.0 k, THD = 1.0%, AV = 1.0)
BWP
−
80
−
kHz
Total Harmonic Distortion (VO = 4.0 Vpp, RL = 2.0 k, AV = 1.0)
f = 1.0 kHz
f = 10 kHz
THD
−
−
0.008
0.08
−
−
1.0
1.0
1.6
1.6
6.0
6.0
Slew Rate (VS = "2.5 V, VO = −2.0 V to 2.0 V, RL = 2.0 k, AV = 1.0)
Positive Slope
Negative Slope
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4
%
SR
V/ms
NCS2001, NCV2001
0
VCC = 2.5 V
VEE = −2.5 V
RL to GND
TA = 25°C
−0.2
High State Output
Sourcing Current
−0.4
−0.6
0.6
0.4
Low State Output
Sinking Current
0.2
0
VEE
100
1.0 k
10 k
100 k
VCC
−0.1
VCC = 2.5 V
VEE = −2.5 V
IL to GND
TA = 25°C
−0.2
−0.3
High State Output
Sourcing Current
Low State Output
Sinking Current
0.3
0.2
0.1
0
1.0 M
VEE
0
2.0
4.0
12
Figure 3. Split Supply Output Saturation vs.
Load Current
80
45
60
0
10
VCC = 2.5 V
VEE = −2.5 V
1.0
25
50
75
Gain
40
AVOL, Gain (dB)
IIB, Input Current (pA)
10
Figure 2. Split Supply Output Saturation vs.
Load Resistance
100
0
8.0
IL, Load Current (mA)
1000
0
6.0
RL, Load Resistance (W)
Phase
20
−90
0
125
Phase
Margin = 60°
VCC = 2.5 V
VEE = −2.5 V
RL = 10 k to GND
TA = 25°C
−20
100
−40
−225
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
f, Frequency (Hz)
Figure 4. Input Bias Current vs. Temperature
Figure 5. Gain and Phase vs. Frequency
2V
0.2 V
−2 V
V+
2 V/div
V+
0.1 V/div
0V
0.2 V
2V
VOUT
2 V/div
−2 V
−135
−180
TA, Ambient Temperature (°C)
−2 V
−45
Fm, Excess Phase (°)
VCC
Vsat, Output Saturation Voltage (V)
Vsat, Output Saturation Voltage (V)
0
VOUT
0.1 V/div
0V
−2 V
1 ms/div)
1 ms/div)
Figure 6. Transient Response
Figure 7. Slew Rate
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5
NCS2001, NCV2001
90
6
CMR, Common Mode Rejection (dB)
VO, Output Voltage (Vpp)
VS = ±2.5 V
5
AV = 1.0
RL = 10 k
TA = 25°C
4
VS = ±1.5 V
3
2
VS = ±0.5 V
1
0
1.E+03
1.E+04
1.E+05
70
VCC = 2.5 V
VEE = −2.5 V
TA = 25°C
60
50
40
30
20
10
0
1.E+01
1.E+06
1.E+02
1.E+03
Figure 9. Common Mode Rejection
vs. Frequency
250
IISCI, Output Short Circuit Current (mA)
PSR −
VCC = 2.5 V
VEE = −2.5 V
TA = 25°C
60
50
40
30
20
10
PSR +
0
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
PSR −
1.E+06
1.E+07
Output Pulsed Test
at 3% Duty Cycle
1.E+0
−40°C
200
25°C
150
85°C
100
50
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VS, Supply Voltage (V)
f, Frequency (Hz)
Figure 10. Power Supply Rejection
vs. Frequency
Figure 11. Output Short Circuit Sinking
Current vs. Supply Voltage
1.0
Output Pulsed Test
at 3% Duty Cycle
85°C
−40°C
200
150
25°C
85°C
100
50
0.5
1.0
1.5
2.0
2.5
3.0
ID, Supply Current (mA)
IISCI, Output Short Circuit Current (mA)
1.E+06
Figure 8. Output Voltage vs. Frequency
70 PSR +
0
0
1.E+05
f, Frequency (Hz)
80
250
1.E+04
f, Frequency (Hz)
90
PSR, Power Supply Rejection (dB)
80
0.8
25°C
0.6
−40°C
0.4
0.2
0.0
0.0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
VS, Supply Voltage (V)
VS, Supply Voltage (V)
Figure 12. Output Short Circuit Sourcing
Current vs. Supply Voltage
Figure 13. Supply Current vs. Supply Voltage
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6
3.5
NCS2001, NCV2001
10
0.1
AV = 1000
AV = 100
AV = 10
0.01
AV = 1.0
VS = ±0.5 V
Vout = 0.4 Vpp
0.001
10
10
THD, Total Harmonic Distortion (%)
THD, Total Harmonic Distortion (%)
1.0
1.0
100
1.0 k
RL = 2.0 k
TA = 25°C
10 k
1.0
0.1
0.01
0.001
10
100 k
100
RL = 10 k
TA = 25°C
Figure 15. Total Harmonic Distortion vs.
Frequency with 1.0 V Supply
10 k
100 k
10
AV = 1000
AV = 100
AV = 1.0
VS = ±2.5 V
Vout = 4.0 Vpp
RL = 2.0 k
TA = 25°C
100
1.0 k
10 k
AV = 1000
1.0
AV = 100
AV = 1.0
0.1
0.01
10
100 k
VS = ±2.5 V
Vout = 4.0 Vpp
RL = 10 k
TA = 25°C
AV = 10
100
1.0 k
10 k
100 k
f, Frequency (Hz)
f, Frequency (Hz)
Figure 16. Total Harmonic Distortion vs.
Frequency with 5.0 V Supply
Figure 17. Total Harmonic Distortion vs.
Frequency with 5.0 V Supply
1.3
GBW, Gain Bandwidth Product (MHz)
2.5
SR, Slew Rate (V/ms)
VS = ±0.5 V
Vout = 0.4 Vpp
Figure 14. Total Harmonic Distortion vs.
Frequency with 1.0 V Supply
0.01
10
+Slew Rate, VS = ±2.5 V
−Slew Rate, VS = ±2.5 V
1.5
−Slew Rate, VS = ±0.45 V
1.0
0
−50
AV = 10
1.0 k
f, Frequency (Hz)
0.1
0.5
AV = 100
f, Frequency (Hz)
AV = 10
2.0
AV = 1000
AV = 1.0
THD, Total Harmonic Distortion (%)
THD, Total Harmonic Distortion (%)
10
RL = 10 k
CL = 10 pF
TA = 25°C
−25
+Slew Rate, VS = ±0.45 V
0
25
50
75
100
125
1.2
1.1
1.0
0.9
−50
VCC = 2.5 V
VEE = −2.5 V
RL = 10 k
CL = 10 pF
−25
0
25
50
75
100
TA, Ambient Temperature (°C)
TA, Ambient Temperature (°C)
Figure 18. Slew Rate vs. Temperature
Figure 19. Gain Bandwidth Product vs.
Temperature
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7
125
NCS2001, NCV2001
0
−135
VS = ±2.5 V
−20
−40
10 k
−180
RL = 10 k
TA = 25°C
100 k
1.0 M
20
0
25
50
75
100
Phase Margin
Phase Margin
60
50
VCC = 2.5 V
VEE = −2.5 V
RL = 10 k
CL = 10 pF
TA = 25°C
40
30
Gain Margin
20
10
0
100 k
80
80
AV = 100
VCC = 2.5 V
VEE = −2.5 V
RL = 10 k to GND
TA = 25°C
60
40
60
40
Gain Margin
20
0
1.0
20
0
1000
Rt, Differential Source Resistance (W)
10
100
CL, Output Load Capacitance (pF)
Figure 22. Gain and Phase Margin vs.
Differential Source Resistance
Figure 23. Gain and Phase Margin vs.
Output Load Capacitance
100
1.0 k
10 k
100
Am, Gain Margin (dB)
8.0
6.0
4.0
RL = 10 k
TA = 25°C
Split Supplies
2.0
0.5
1.0
1.5
2.0
2.5
3.0
0
125
100
100
70
0
10
VOUT, Output Volltage (Vpp)
−25
20
Figure 21. Gain and Phase Margin vs.
Temperature
10
0
0
Gain Margin
20
Figure 20. Voltage Gain and Phase vs.
Frequency
Am, Gain Margin (dB)
AV, Gain Margin (dB)
30
40
TA, Ambient Temperature (°C)
60
40
VCC = 2.5 V 60
VEE = −2.5 V
RL = 10 k
40
CL = 10 pF
60
f, Frequency (Hz)
70
50
Phase Margin
0
−50
−225
100 M
10 M
80
Fm, Phase Margin (°)
20
80
100
Phase Margin
80
80
60
60
RL = 10 k
CL = 10 pF
TA = 25°C
40
40
Gain Margin
20
0
3.5
0
0.5
1.0
1.5
2.0
20
2.5
3.0
VS, Supply Voltage (V)
VS, Supply Voltage (V)
Figure 24. Output Voltage Swing vs.
Supply Voltage
Figure 25. Gain and Phase Margin vs.
Supply Voltage
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Fm, Phase Margin (°)
VS = ±0.5 V
Fm, Phase Margin (°)
AVOL, Gain (dB)
40
Am, Gain Margin (dB)
−90
Fm, Excess Phase (°)
VS = ±2.5 V
60
100
100
−45
0
3.5
Fm, Phase Margin (°)
80
NCS2001, NCV2001
20
50
VIO, Input Offset Voltage (mV)
AVOL, Open Loop Gain (dB)
60
RL = 10 k
RL = 2.0 k
40
30
20
TA = 25°C
10
0
0.0
0.5
1.0
1.5
2.0
15
10
5
VS = ±2.5 V
RL = ∞
CL = 0
AV = 1.0
TA = 25°C
0
−5
−10
−15
−20
−3.0
2.5
−2.0
VIO, Input Offset Voltage (mV)
20
5
VS = ±2.5 V
RL = ∞
CL = 0
AV = 1.0
TA = 25°C
0
−5
−10
−15
−20
−0.5 −0.4 −0.3 −0.2 −0.1
0
0.1
0.2
1.0
2.0
3.0
Figure 27. Input Offset Voltage vs. Common
Mode Input Voltage Range VS = +2.5 V
0.3
0.4
0.5
VCM, Common Mode Input Voltage Range (V)
Figure 26. Open Loop Voltage Gain vs.
Supply Voltage
10
0
VCM, Common Mode Input Voltage Range (V)
VS, Supply Voltage (V)
15
−1.0
3.5
2.5
1.5
D Vio = 5.0 mV
RL = ∞
CL = 0
AV = 1.0
TA = 25°C
0.5
−0.5
−1.5
−2.5
−3.5
0.0
VCM, Common Mode Input Voltage Range (V)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VS, Supply Voltage (V)
Figure 28. Input Offset Voltage vs. Common
Mode Input Voltage Range, VS = +0.45 V
Figure 29. Common−Mode Input Voltage Range
vs. Power Supply Voltage
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9
NCS2001, NCV2001
APPLICATION INFORMATION AND OPERATING DESCRIPTION
GENERAL INFORMATION
The NCS2001 is an industry first rail−to−rail input,
rail−to−rail output amplifier that features guaranteed
sub−one voltage operation. This unique feature set is
achieved with the use of a modified analog CMOS process
that allows the implementation of depletion MOSFET
devices. The amplifier has a 1.0 MHz gain bandwidth
product, 2.2 V/ms slew rate and is operational over a power
supply range less than 0.9 V to as high as 7.0 V.
Cfb
Rfb
Input
Cin
+
Output
Cin = Input and printed circuit board capacitance
Figure 30. Input Capacitance Pole Cancellation
Inputs
The input topology chosen for this device series is
unconventional when compared to most low voltage
operational amplifiers. It consists of an N−Channel
depletion mode differential transistor pair that drives a
folded cascade stage and current mirror. This configuration
extends the input common mode voltage range to
encompass the VEE and VCC power supply rails, even when
powered from a combined total of less than 0.9 V. Figures 27
and 28 show the input common mode voltage range versus
power supply voltage.
The differential input stage is laser trimmed in order to
minimize offset voltage. The N−Channel depletion mode
MOSFET input stage exhibits an extremely low input bias
current of less than 10 pA. The input bias current versus
temperature is shown in Figure 4. Either one or both inputs
can be biased as low as VEE minus 300 mV to as high as
7.0 V without causing damage to the device. If the input
common mode voltage range is exceeded, the output will not
display a phase reversal. If the maximum input positive or
negative voltage ratings are to be exceeded, a series resistor
must be used to limit the input current to less than 2.0 mA.
The ultra low input bias current of the NCS2001 allows
the use of extremely high value source and feedback resistor
without reducing the amplifier’s gain accuracy. These high
value resistors, in conjunction with the device input and
printed circuit board parasitic capacitances Cin, will add an
additional pole to the single pole amplifier in Figure 30. If
low enough in frequency, this additional pole can reduce the
phase margin and significantly increase the output settling
time. The effects of Cin, can be canceled by placing a zero
into the feedback loop. This is accomplished with the
addition of capacitor Cfb. An approximate value for Cfb can
be calculated by:
Cfb +
Rin
Output
The output stage consists of complementary P and
N−Channel devices connected to provide rail−to−rail output
drive. With a 2.0 k load, the output can swing within 50 mV
of either rail. It is also capable of supplying over 75 mA
when powered from 5.0 V and 1.0 mA when powered from
0.9 V.
When connected as a unity gain follower, the NCS2001 can
directly drive capacitive loads in excess of 820 pF at room
temperature without oscillating but with significantly
reduced phase margin. The unity gain follower configuration
exhibits the highest bandwidth and is most prone to
oscillations when driving a high value capacitive load. The
capacitive load in combination with the amplifier’s output
impedance, creates a phase lag that can result in an
under−damped pulse response or a continuous oscillation.
Figure 32 shows the effect of driving a large capacitive load
in a voltage follower type of setup. When driving capacitive
loads exceeding 820 pF, it is recommended to place a low
value isolation resistor between the output of the op amp and
the load, as shown in Figure 31. The series resistor isolates the
capacitive load from the output and enhances the phase
margin. Refer to Figure 33. Larger values of R will result in
a cleaner output waveform but excessively large values will
degrade the large signal rise and fall time and reduce the
output amplitude. Depending upon the capacitor
characteristics, the isolation resistor value will typically be
between 50 to 500 W. The output drive capability for resistive
and capacitive loads is shown in Figures 2, 3, and 23.
Input
Rin Cin
Rfb
+
-
R
Output
CL
Isolation resistor R = 50 to 500
Figure 31. Capacitance Load Isolation
Note that the lowest phase margin is observed at cold
temperature and low supply voltage.
www.onsemi.com
10
NCS2001, NCV2001
Vin
VS = ±0.45 V
Vin = 0.8 Vpp
R=0
CL = 820 pF
AV = 1.0
TA = 25°C
Vout
Figure 32. Small Signal Transient Response with Large Capacitive Load
Vin
VS = ±0.45 V
Vin = 0.8 Vpp
R = 51
CL = 820 pF
AV = 1.0
TA = 25°C
Vout
Figure 33. Small Signal Transient Response with Large
Capacitive Load and Isolation Resistor
www.onsemi.com
11
NCS2001, NCV2001
RT
470 k
VCC
Output Voltage
0
0.9 V
CT
1.0 nF
Timing Capacitor
Voltage
-
The non−inverting input threshold levels are set so that
the capacitor voltage oscillates between 1/3 and 2/3 of
VCC. This requires the resistors R1a, R1b and R2 to be of
equal value. The following formula can be used to approximate the output frequency.
R1a
470 k
R2
470 k
R1b
470 k
0.33 VCC
fO = 1.5 kHz
+
0.9 V
0.67 VCC
1
f +
O 1.39 R TC T
Figure 34. 0.9 V Square Wave Oscillator
cww
10 k
D1
1N4148
10 k
D2
1N4148
VCC
Output Voltage
0
1.0 M
Timing Capacitor
Voltage
0.67 VCC
0.33 VCC
cw
Clock−wise, Low Duty Cycle
VCC
CT
1.0 nF
VCC
Output Voltage
-
fO
+
0
Timing Capacitor
Voltage
R1a
470 k
0.67 VCC
0.33 VCC
Counter−Clock−wise, High Duty Cycle
VCC
R1b
470 k
R2
470 k
The timing capacitor CT will charge through diode D2 and discharge
through diode D1, allowing a variable duty cycle. The pulse width of the
signal can be programmed by adjusting the value of the trimpot. The capacitor voltage will oscillate between 1/3 and 2/3 of VCC, since all the
resistors at the non−inverting input are of equal value.
Figure 35. Variable Duty Cycle Pulse Generator
www.onsemi.com
12
NCS2001, NCV2001
R1
1.0 M
2.5 V
R3
1.0 k
+
≈
10,000 mF
-
Cin
10 mF
−2.5 V
Ceff. +
R2
1.0 M
R1
C
R3 in
Figure 36. Positive Capacitance Multiplier
Af
Cf
400 pF
Rf
100 k
fL
R2
10 k
0.5 V
+
Vin
1
f +
[ 200 Hz
L 2pR C
1 1
VO
C1
80 nF
fH
R1
10 k −0.5 V
1
f +
[ 4.0 kHz
H 2pRC
f f
R
A + 1 ) f + 11
f
R2
Figure 37. 1.0 V Voiceband Filter
www.onsemi.com
13
NCS2001, NCV2001
Vsupply
VCC
Vin
+
I
-
V
in
+
sink R sense
Rsense
Figure 38. High Compliance Current Sink
Is
VL
Rsense
R1
1.0 k
RL
1.0 V
R3
1.0 k
R4
1.0 k
+
R5
-
2.4 k
VO
75
Is
VO
435 mA
34.7 mV
212 mA
36.9 mV
R6
For best performance, use low
tolerance resistors.
R2
3.3 k
Figure 39. High Side Current Sense
ORDERING INFORMATION
Device
Marking
NCS2001SN1T1G
AAG
NCS2001SN2T1G
AAH
NCV2001SN2T1G*
MBB
NCS2001SQ2T2G
AAJ
NCV2001SQ2T2G*
AAJ
Package
Shipping†
SOT23−5
(Pb−Free)
3000 / Tape & 7” Reel
SC70−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DATE 17 JAN 2013
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
mm Ǔ
ǒinches
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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