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45 mV Offset, 0.4 mV/5C,
Zero-Drift Operational
Amplifier
NCS21871, NCV21871,
NCS21872, NCV21872,
NCS21874, NCV21874
www.onsemi.com
The NCS21871, NCS21872 and NCS21874 family of zero−drift op
amps feature offset voltage as low as 45 mV over the 1.8 V to 5.5 V
supply voltage range. The zero−drift architecture reduces the offset
drift to as low as 0.4 mV/°C and enables high precision measurements
over both time and temperature. This family has low power
consumption over a wide dynamic range and is available in space
saving packages. These features make it well suited for signal
conditioning circuits in portable, industrial, automotive, medical and
consumer markets.
1
SOT23−5
SN SUFFIX
CASE 483
Features
•
•
•
•
•
•
•
•
•
1
SC70−5
SQ SUFFIX
CASE 419A
1
Gain−Bandwidth Product: 270 kHz to 350 kHz
Low Supply Current: 17 mA (typ at 3.3 V)
Low Offset Voltage: 45 mV max
Low Offset Drift: 0.4 mV/°C max
Wide Supply Range: 1.8 V to 5.5 V
Wide Temperature Range: −40°C to +125°C
Rail−to−Rail Input and Output
Available in Single, Dual and Quad Packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Applications
•
•
•
•
•
•
•
5
5
Automotive
Battery Powered/ Portable Application
Sensor Signal Conditioning
Low Voltage Current Sensing
Filter Circuits
Bridge Circuits
Medical Instrumentation
UDFN8
MU SUFFIX
CASE 517AW
MSOP−8
DM SUFFIX
CASE 846A−02
8
14
1
SOIC−8
D SUFFIX
CASE 751
1
SOIC−14
D SUFFIX
CASE 751A
14
1
TSSOP−14 WB
DT SUFFIX
CASE 948G
ECP5
FCT SUFFIX
CASE 971BE
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 2 of this data sheet.
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
April, 2021 − Rev. 2
1
Publication Order Number:
NCS21871/D
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
DEVICE MARKING INFORMATION
Single Channel Configuration
NCS21871, NCV21871
7AAYWG
G
7CMG
G
XXX
AYW
G
TSOP−5/SOT23−5
CASE 483
SC70−5
CASE 419A
ECP5
CASE 971BE
Dual Channel Configuration
NCS21872, NCV21872
8
1
8
2187
AYWG
G
72
YM
1
1
UDFN8, 2x2, 0.5P
CASE 517AW
Micro8/MSOP8
CASE 846A−02
21872
ALYW
G
SOIC−8
CASE 751
Quad Channel Configuration
NCS21874, NCV21874
14
14
N874
ALYWG
G
N874G
AWLYWW
1
1
SOIC−14
CASE 751A
N874
A
Y
W
M
G or G
TSSOP−14 WB
CASE 948G
N874
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Date Code
= Pb−Free Package
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
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2
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PIN CONNECTIONS
Single Channel Configuration
NCS21871, NCV21871
OUT
1
VSS
2
IN+
3
IN+
1
VSS
2
IN−
3
5 VDD
4
IN−
5 VDD
4 OUT
Dual Channel Configuration
NCS21872, NCV21872
1
IN− 1
2
−
IN+ 1
3
+
VSS
4
C3
VDD
C1
IN−
A1
IN+
B2
VSS
SC70−5 / SC−88−5 / SOT−353−5
SOT23−5 / TSOP−5
OUT 1
OUT
A3
ECP5 (Top View)
Quad Channel Configuration
NCS21874, NCV21874
OUT 1
1
OUT 2
IN− 1
2
−
−
13 IN− 4
6
IN− 2
IN+ 1
3
+
+
12 IN+ 4
5
IN+ 2
VDD
4
IN+ 2
5
+
+
10 IN+ 3
IN− 2
6
−
−
9 IN− 3
OUT 2
7
8
VDD
7
−
+
UDFN8* / Micro8 / SOIC−8
*The exposed pad of the UDFN8 package
can be floated or connected to VSS.
14 OUT 4
11 VSS
8 OUT 3
SOIC−14, TSSOP−14
ORDERING INFORMATION
Temperature
Channels
Package
Device Part Number
Shipping †
SOT23*5 / TSOP*5
NCS21871SN2T1G
3000 / Tape & Reel
SC70*5 / SC*88*5 /
SOT*353*5
NCS21871SQ3T2G
ECP5
NCS21871FCTTAG*
MICRO*8
NCS21872DMR2G
4000 / Tape & Reel
SOIC−8
NCS21872DR2G
3000 / Tape & Reel
COMMERCIAL AND INDUSTRIAL
−40°C to 125°C
Single
Dual
Quad
UDFN−8
NCS21872MUTBG*
SOIC−14
NCS21874DR2G
TSSOP−14
NCS21874DTBR2G
SOT23*5 / TSOP*5
NCV21871SN2T1G
SC70*5 / SC*88*5 /
SOT*353*5
NCV21871SQ3T2G
MICRO*8
NCV21872DMR2G
4000 / Tape & Reel
SOIC−8
NCV21872DR2G
3000 / Tape & Reel
SOIC−14
NCV21874DR2G
2500 / Tape & Reel
TSSOP−14
NCV21874DTBR2G
2500 / Tape & Reel
AUTOMOTIVE
−40°C to 125°C
Single
Dual
Quad
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*In Development. Contact local sales office for more information.
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3
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
ABSOLUTE MAXIMUM RATINGS
Over operating free−air temperature, unless otherwise stated.
Parameter
Supply Voltage
Rating
Unit
6
V
INPUT AND OUTPUT PINS
Input Voltage (Note 1)
(VSS) − 0.3 to (VDD) + 0.3
V
Input Current (Note 1)
±10
mA
Output Short Circuit Current (Note 2)
Continuous
TEMPERATURE
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−65 to +150
°C
+150
°C
Human Body Model (HBM)
±4000
V
Charged Device Model (CDM)
±2000
V
100
mA
Junction Temperature
ESD RATINGS (Note 3)
OTHER RATINGS
Latch−up Current (Note 4)
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less
2. Short−circuit to ground.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JESD22−C101 (AEC−Q100−011)
4. Latch−up Current tested per JEDEC standard: JESD78.
THERMAL INFORMATION (Note 5)
Parameter
Thermal Resistance,
Junction to Ambient
Symbol
Value
Unit
°C/W
SOT23−5 / TSOP5
290
SC70−5 / SC−88−5 / SOT−353−5
290
ECP5
157
Micro8 / MSOP8
298
SOIC−8
250
UDFN8
228
SOIC−14
216
TSSOP−14
155
qJA
mounted on an 80x80x1.5 mm FR4 PCB with 650 mm2
5. As
51.2, 51.3 test guidelines
Package
and 2 oz (0.07 mm) thick copper heat spreader. Following JEDEC JESD/EIA 51.1,
RECOMMENDED OPERATING CONDITIONS
Symbol
Range
Unit
Supply Voltage (VDD − VSS)
Parameter
VS
1.8 to 5.5
V
Specified Operating Temperature Range
TA
−40 to 125
°C
VCM
VSS−0.1 to VDD+0.1
V
Input Common Mode Voltage Range
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
VOS
Min
Typ
Max
Unit
VS = +5 V
6
45
mV
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift vs Temp
DVOS/DT
VS = 5 V
0.1
0.4
mV/°C
Offset Voltage Drift vs Supply
DVOS/DVS
TA = +25°C
0.4
8
mV/V
Full temperature range
Input Bias Current
(Note 6)
IIB
Input Offset Current
(Note 6)
Common Mode Rejection Ratio
(Note 7)
TA = +25°C
±60
Full temperature range
+400
IOS
TA = +25°C
±50
CMRR
VS = 1.8 V
111
VS = 3.3 V
118
VS = 5.0 V
Input Capacitance
12.6
102
pA
±800
pA
dB
123
VS = 5.5 V
127
Differential
4.1
Common Mode
7.9
CIN
±400
pF
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
(Note 6)
Open Loop Output Impedance
AVOL
Zout−OL
Output Voltage High,
Referenced to VDD
VOH
Output Voltage Low,
Referenced to VSS
VOL
TA = +25°C
106
145
dB
See Figure 18
W
10
Full temperature range
TA = +25°C
10
mV
80
mV
80
Sinking Current
11
Sourcing Current
5.0
CL
80
80
Full temperature range
IO
Capacitive Load Drive
VSS + 100 mV < VO < VDD − 100 mV
mA
See Figure 14
NOISE PERFORMANCE
Voltage Noise Density
Voltage Noise
Current Noise Density
eN
fIN = 1 kHz
62
nV / √Hz
eP−P
fIN = 0.1 Hz to 10 Hz
1.1
mVPP
fIN = 0.01 Hz to 1 Hz
0.5
fIN = 10 Hz
350
fA / √Hz
NCS21872, NCS21874
135
dB
NCS21871, NCS21874
350
kHz
NCS21872
270
iN
Channel Separation
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBWP
CL = 100 pF
Gain Margin
AM
CL = 100 pF
18
dB
Phase Margin
fM
CL = 100 pF
55
°
Slew Rate
SR
G = 1, VDD = 5.5 V
0.1
V/ms
G = 1, VDD = 1.8 V
0.05
6. Guaranteed by characterization and/or design
7. Specified over the full common mode range: VSS − 0.1 < VCM < VDD + 0.1
8. No load, per channel
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5
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
PSRR
TA = +25°C
106
130
dB
Full temperature range
98
ms
POWER SUPPLY
Power Supply Rejection Ratio
Turn−on Time
tON
VS = 5 V
100
Quiescent Current
(Note 8)
IQ
1.8 V ≤ VS ≤ 3.3 V
20
40
mA
40
3.3 V < VS ≤ 5.5 V
28
45
45
6. Guaranteed by characterization and/or design
7. Specified over the full common mode range: VSS − 0.1 < VCM < VDD + 0.1
8. No load, per channel
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
TYPICAL CHARACTERISTICS
120
100
105
GAIN (dB)
60
90
75
Gain
40
60
20
45
CL = 100 pF
RL = 10 kW
TA = 25°C
0
−20
−40
10
100
30
100
PHASE MARGIN (°)
Phase Margin
80
120
110
CMRR (dB)
120
1k
10k
100k
FREQUENCY (Hz)
0
1M
70
60
50
40
30
20
10
0
15
TA = 25°C
90
80
10
100
Figure 1. Open Loop Gain and Phase Margin
vs. Frequency
3
TA = 25°C
2
OUTPUT VOLTAGE (V)
PSRR (dB)
100
80
+PSRR
60
−PSRR
40
20
1M
TA = −40 °C
TA = 25 °C
TA = 125 °C
VOH
VDD = 2.75 V
VSS = −2.75 V
1
0
−1
VOL
−2
10
100
1k
10k
100k
1M
−3
0
FREQUENCY (Hz)
0.8
VOH
0.6
TA = −40 °C
TA = 25 °C
TA = 125 °C
0.2
0
−0.2
−0.4
VOL
−0.6
−0.8
8
10
12
14
16
18
2
4
6
8
OUTPUT CURRENT (mA)
TA = 25°C
VS = 1.8 V
150
100
50
IIB+
0
IIB−
−50
−100
−150
−200
−0.2 0
−1
0
6
200
VDD = 0.9 V
VSS = −0.9 V
0.4
4
Figure 4. Output Voltage Swing vs. Output
Current at VS = 5.5 V
INPUT BIAS CURRENT (pA)
1
2
OUTPUT CURRENT (mA)
Figure 3. PSRR vs. Frequency
OUTPUT VOLTAGE (V)
100k
Figure 2. CMRR vs. Frequency
120
0
1k
10k
FREQUENCY (Hz)
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4
1.6 1.8
COMMON MODE VOLTAGE (V)
Figure 5. Output Voltage Swing vs. Output
Current at VS = 1.8 V
Figure 6. Input Bias Current vs. Common
Mode Voltage
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7
2.0
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
TYPICAL CHARACTERISTICS
30
150
100
VS = 5.0 V
50
IQ (mA)
IIB+
IIB−
0
−50
0
20
40
60
80
VS = 3.3 V
15
VS = 1.8 V
5
−150
−20
20
10
TA = 25°C
VS = 5 V
−100
−200
−40
0
−40
100
Per Channel
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Input Bias Current vs. Temperature
Figure 8. Quiescent Current vs. Temperature
3
Input
2
1
5
0.20
4
0.15
3
2
Output
0
1
−1
0
VS = 5.0 V
AV = +1
RL = 10 kW
−2
−3
Input
0.10
0.05
VS = 5.0 V
AV = −1
RL = 10 kW
0
−0.05
−1
−4
INPUT AND OUTPUT (V)
4
INPUT (V)
VS = 5.5 V
25
OUTPUT (V)
INPUT BIAS CURRENT (pA)
200
−2
−0.10
−3
−0.15
Output
TIME (50 ms/div)
TIME (5 ms/div)
Figure 10. Small Signal Step Response
Figure 9. Large Signal Step Response
1.0
0.5
Input
0
−0.5
−1.0
Output
−1.5
VS = 5.0 V
AV = −10
RL = 10 kW
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
−2.5
−0.5 −0.5
−3.0
−1.0 −1.0
TIME (50 ms/div)
0.5
Output
0
−0.5
Input
0
−2.0
INPUT (V)
1.0
VS = 5.0 V
AV = −10
RL = 10 kW
−1.5
−2.0
−2.5
−3.0
INPUT (V)
OUTPUT (V)
−1.0
OUTPUT (V)
TIME (50 ms/div)
Figure 12. Negative Overvoltage Recovery
Figure 11. Positive Overvoltage Recovery
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8
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
TYPICAL CHARACTERISTICS
500
TA = 25°C
RL = 10 kW
OVERSHOOT (%)
SETTLING TIME (ms)
400
300
200
100
0
1
10
100
1000
Figure 14. Small−Signal Overshoot vs. Load
Capacitance
VOLTAGE NOISE DENSITY (nV/√Hz)
VOLTAGE (nV)
100
Figure 13. Setting Time to 0.1% vs.
Closed−Loop Gain
VCM = VS/2
RL = 10 kW
TA = 25°C
1000
500
0
−500
−1000
−1500
1
2
3
4
5
6
7
9
8
10
1000
TA = 25°C
100
10
1
10
100
1000
10,000
TIME (s)
FREQUENCY (Hz)
Figure 15. 0.1 Hz to 10 Hz Noise
Figure 16. Voltage Noise Density vs.
Frequency
10k
1000
TA = 25°C
OUPUT IMPEDANCE (W)
CURRENT NOISE DENSITY (fA/√Hz)
10
LOAD CAPACITANCE (pF)
1500
0
TA = 25°C
GAIN (V/V)
2000
−2000
65
60
55
50
45
40
35
30
25
20
15
10
5
0
100
10
1
10
100
1000
1k
100
10
10,000
FREQUENCY (Hz)
Figure 17. Current Noise Density vs.
Frequency
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 18. Open Loop Output Impedance vs.
Frequency
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9
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
APPLICATIONS INFORMATION
OVERVIEW
The NCS21871, NCS21872, and NCS21874 precision op
amps provide low offset voltage and zero drift over
temperature. The input common mode voltage range
extends 100 mV beyond the supply rails to allow for sensing
near ground or VDD. These features make the NCS21871
series well−suited for applications where precision is
required, such as current sensing and interfacing with
sensors.
The NCS21871 series of precision op amps uses a
chopper−stabilized architecture, which provides the
advantage of minimizing offset voltage drift over
temperature and time. The simplified block diagram is
shown in Figure 19. Unlike the classical chopper
architecture, the chopper stabilized architecture has two
signal paths.
Main amp
IN+
+
IN−
− +
+
−
Chopper
−
O
−
+
Chopper
RC notch filter
RC notch filter
Figure 19. Simplified NCS21871 Block Diagram
cascaded, symmetrical, RC notch filters tuned to the
chopper frequency and its fifth harmonic to reduce aliasing
effects.
The chopper−stabilized architecture also benefits from
the feed−forward path, which is shown as the upper signal
path of the block diagram in Figure 19. This is the high speed
signal path that extends the gain bandwidth up to 350 kHz.
Not only does this help retain high frequency components of
the input signal, but it also improves the loop gain at low
frequencies. This is especially useful for low−side current
sensing and sensor interface applications where the signal is
low frequency and the differential voltage is relatively
small.
In Figure 19, the lower signal path is where the chopper
samples the input offset voltage, which is then used to
correct the offset at the output. The offset correction occurs
at a frequency of 125 kHz. The chopper−stabilized
architecture is optimized for best performance at
frequencies up to the related Nyquist frequency (1/2 of the
offset correction frequency). As the signal frequency
exceeds the Nyquist frequency, 62.5 kHz, aliasing may
occur at the output. This is an inherent limitation of all
chopper
and
chopper−stabilized
architectures.
Nevertheless, the NCS21871 op amps have minimal
aliasing up to 125 kHz and low aliasing up to 190 kHz when
compared to competitor parts from other manufacturers.
ON Semiconductor’s patented approach utilizes two
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10
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
APPLICATION CIRCUITS
sense resistor is less than 100 mW to reduce power loss
across the resistor. The op amp amplifies the voltage drop
across the sense resistor with a gain set by external resistors
R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision
resistors are required for high accuracy, and the gain is set
to utilize the full scale of the ADC for the highest resolution.
Low−Side Current Sensing
Low−side current sensing is used to monitor the current
through a load. This method can be used to detect
over−current conditions and is often used in feedback
control, as shown in Figure 20. A sense resistor is placed in
series with the load to ground. Typically, the value of the
R3
VLOAD
VDD
VDD
Load
R1
VDD
Microcontroller
+
ADC
RSENSE
control
−
R2
R4
Figure 20. Low−Side Current Sensing
Differential Amplifier for Bridged Circuits
produced is relatively small and needs to be amplified before
going into an ADC. Precision amplifiers are recommended
in these types of applications due to their high gain, low
noise, and low offset voltage.
Sensors to measure strain, pressure, and temperature are
often configured in a Wheatstone bridge circuit as shown in
Figure 21. In the measurement, the voltage change that is
VDD
VDD
−
+
Figure 21. Bridge Circuit Amplification
EMI Susceptibility and Input Filtering
General Layout Guidelines
Op amps have varying amounts of EMI susceptibility.
Semiconductor junctions can pick up and rectify EMI
signals, creating an EMI−induced voltage offset at the
output, adding another component to the total error. Input
pins are the most sensitive to EMI. The NCS21871 op amp
family integrates low−pass filters to decrease sensitivity to
EMI.
To ensure optimum device performance, it is important to
follow good PCB design practices. Place 0.1 mF decoupling
capacitors as close as possible to the supply pins. Keep traces
short, utilize a ground plane, choose surface−mount
components, and place components as close as possible to
the device pins. These techniques will reduce susceptibility
to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric−coefficients and prevent
temperature gradients from heat sources or cooling fans.
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11
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
UDFN8 Package Guidelines
center pad can be electrically connected to VSS or it may be
left floating. When connected to VSS, the center pad acts as
a heat sink, improving the thermal resistance of the part.
The UDFN8 package has an exposed leadframe die pad on
the underside of the package. This pad should be soldered to
the PCB, as shown in the recommended soldering footprint
in the Package Dimensions section of this datasheet. The
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12
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
A
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
M
N
J
C
K
H
SOLDER FOOTPRINT
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
13
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE K
D 5X
NOTE 5
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
0.10 T
M
2X
0.20 T
B
5
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
SIDE VIEW
C
SEATING
PLANE
END VIEW
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
14
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PACKAGE DIMENSIONS
UDFN8, 2x2
CASE 517AW
ISSUE A
A
D
PIN ONE
REFERENCE
2X
B
L1
ÇÇ
ÇÇ
E
DETAIL A
ALTERNATE
CONSTRUCTIONS
0.10 C
2X
0.10 C
TOP VIEW
A
0.10 C
NOTE 4
A3
A1
A1
SIDE VIEW
C
D2
DETAIL A
1
ÇÇ
ÇÇ
ÉÉ
MOLD CMPD
EXPOSED Cu
DETAIL B
0.08 C
8X
4
SEATING
PLANE
DETAIL B
5
e
e/2
8X
RECOMMENDED
SOLDERING FOOTPRINT*
L
1.73
PACKAGE
OUTLINE
b
8X
0.50
2.30
1.00
0.10 C A B
0.05 C
A3
ALTERNATE
CONSTRUCTION
E2
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINALS AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL
TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
MILLIMETERS
DIM MIN
MAX
A
0.45
0.55
A1
0.00
0.05
A3
0.13 REF
b
0.18
0.30
D
2.00 BSC
D2
1.50
1.70
E
2.00 BSC
E2
0.80
1.00
e
0.50 BSC
L
0.20
0.45
L1
−−−
0.15
L
L
NOTE 3
BOTTOM VIEW
1
0.50
PITCH
8X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
15
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE J
D
HE
PIN 1 ID
−T−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
E
e
b 8 PL
0.08 (0.003)
M
T B
S
A
DIM
A
A1
b
c
D
E
e
L
HE
S
SEATING
PLANE
A
0.038 (0.0015)
A1
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
L
c
RECOMMENDED
SOLDERING FOOTPRINT*
8X
8X
0.48
0.80
5.25
0.65
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
16
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.021
0.016
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
17
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PACKAGE DIMENSIONS
D
SOIC−14 NB
CASE 751A−03
ISSUE K
A
B
14
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
C A
M
S
B
DIM
A
A1
A3
b
D
E
e
H
h
L
M
S
DETAIL A
h
A
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
X 45 _
M
A1
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
18
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PACKAGE DIMENSIONS
ECP5, 1.116x0.822x0.58
CASE 971BE
ISSUE O
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19
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
www.onsemi.com
20
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
NCS21871, NCV21871, NCS21872, NCV21872, NCS21874, NCV21874
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