NDF11N50Z
N-Channel Power MOSFET
500 V, 0.52 W
Features
•
•
•
•
•
Low ON Resistance
Low Gate Charge
ESD Diode−Protected Gate
100% Avalanche Tested
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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VDSS
RDS(ON) (MAX) @ 4.5 A
500 V
0.52 W
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
NDF
Unit
VDSS
500
V
Continuous Drain Current, RqJC (Note 1)
ID
12
A
Continuous Drain Current
TA = 100°C, RqJC (Note 1)
ID
7.4
A
Pulsed Drain Current,
tP = 10 ms
IDM
44
A
Power Dissipation, RqJC
PD
39
W
Gate−to−Source Voltage
VGS
±30
V
Single Pulse Avalanche
Energy, ID = 10 A
EAS
420
mJ
ESD (HBM) (JESD22−A114)
Vesd
4000
V
RMS Isolation Voltage
(t = 0.3 sec., R.H. ≤ 30%,
TA = 25°C) (Figure 14)
VISO
4500
V
Peak Diode Recovery (Note 2)
dv/dt
4.5
V/ns
MOSFET dV/dt
Rating
Drain−to−Source Voltage
dV/dt
60
V/ns
Continuous Source Current (Body
Diode)
IS
12
A
Maximum Temperature for
Soldering Leads
TL
260
°C
Operating Junction and
Storage Temperature Range
TJ, Tstg
−55 to 150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Limited by maximum junction temperature
2. Id ≤ 10.5 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, TJ ≤ 150°C.
N−Channel
D (2)
G (1)
S (3)
MARKING
DIAGRAM
NDF11N50ZG
NDF11N50ZH
TO−220FP
CASE 221AH
NDF11N50ZG
or
NDF11N50ZH
AYWW
Gate
Source
Drain
A
Y
WW
G, H
= Location Code
= Year
= Work Week
= Pb−Free, Halogen−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 6
1
Publication Order Number:
NDF11N50Z/D
NDF11N50Z
THERMAL RESISTANCE
Symbol
NDF11N50Z
Unit
Junction−to−Case (Drain)
Parameter
RqJC
3.2
°C/W
Junction−to−Ambient Steady State (Note 3)
RqJA
50
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Test Conditions
Symbol
Min
Drain−to−Source Breakdown Voltage
VGS = 0 V, ID = 1 mA
BVDSS
500
Breakdown Voltage Temperature Coefficient
Reference to 25°C,
ID = 1 mA
DBVDSS/
DTJ
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Leakage Current
25°C
VDS = 500 V, VGS = 0 V
0.6
IDSS
V/°C
1
125°C
mA
50
VGS = ±20 V
IGSS
Static Drain−to−Source
On−Resistance
VGS = 10 V, ID = 4.5 A
RDS(on)
Gate Threshold Voltage
VDS = VGS, ID = 100 mA
VGS(th)
VDS = 15 V, ID = 4.5 A
gFS
Gate−to−Source Forward Leakage
V
±10
mA
0.48
0.52
W
3.9
4.5
V
ON CHARACTERISTICS (Note 4)
Forward Transconductance
3.0
7.7
S
DYNAMIC CHARACTERISTICS
Input Capacitance (Note 5)
Output Capacitance (Note 5)
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance
(Note 5)
Total Gate Charge (Note 5)
Gate−to−Source Charge (Note 5)
VDD = 250 V, ID = 10.5 A,
VGS = 10 V
Gate−to−Drain (“Miller”) Charge
(Note 5)
Ciss
1097
1375
1645
Coss
132
166
199
Crss
30
40
50
Qg
23
46
69
Qgs
4.5
8.7
13
Qgd
12.5
25
37.5
pF
nC
Plateau Voltage
VGP
6.2
V
Gate Resistance
Rg
1.4
W
td(on)
15
ns
RESISTIVE SWITCHING CHARACTERISTICS
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
VDD = 250 V, ID = 10.5 A,
VGS = 10 V, RG = 5 Ω
Fall Time
tr
32
td(off)
40
tf
23
SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C unless otherwise noted)
Diode Forward Voltage
IS = 10.5 A, VGS = 0 V
VSD
Reverse Recovery Time
VGS = 0 V, VDD = 30 V
IS = 10.5 A, di/dt = 100 A/ms
trr
310
ns
Qrr
2.5
mC
Reverse Recovery Charge
1.6
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Insertion mounted
4. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%.
5. Guaranteed by design.
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2
NDF11N50Z
TYPICAL CHARACTERISTICS
25
25
VDS = 25 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VGS = 10 V
20
7.0 V
15
6.5 V
10
6.0 V
5
20
15
10
TJ = 25°C
TJ = 150°C
5
TJ = −55°C
5.5 V
5.0 V
0
5
10
15
20
5
6
7
8
9
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 4.5 A
TJ = 25°C
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
1.00
0.95
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0
1
2
3
4
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Region versus Gate−to−Source
Voltage
Figure 4. On−Resistance versus Drain
Current and Gate Voltage
ID = 4.5 A
VGS = 10 V
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
10
VGS = 10 V
TJ = 25°C
0.90
10.0
2.75
0.25
−50
4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.95
2.50
3
Figure 1. On−Region Characteristics
1.00
0.40
5.5
0
25
BVDSS, NORMALIZED BREAKDOWN VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
1.15
ID = 1 mA
1.10
1.05
1.00
0.95
0.90
50
Figure 5. On−Resistance Variation with
Temperature
25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. BVDSS Variation with Temperature
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3
11
150
NDF11N50Z
TYPICAL CHARACTERISTICS
10
C, CAPACITANCE (pF)
TJ = 150°C
TJ = 125°C
1
0.1
50
100 150 200 250 300 350 400 450 500
TJ = 25°C
VGS = 0 V
f = 1 MHz
Ciss
Coss
Crss
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Drain−to−Source Leakage Current
versus Voltage
Figure 8. Capacitance Variation
VGS, GATE−TO−SOURCE VOLTAGE (V)
0
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
0.01
300
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
QT
250
VDS
200
VGS
QGS
150
QGD
100
VDS = 250 V
ID = 10.5 A
TJ = 25°C
0
5
10 15 20 25 30 35 40
Qg, TOTAL GATE CHARGE (nC)
45
50
0
50
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
IDSS, LEAKAGE (mA)
100
Figure 9. Gate−to−Source Voltage and
Drain−to−Source Voltage versus Total Charge
1000
t, TIME (ns)
IS, SOURCE CURRENT (A)
20
VDD = 250 V
ID = 10.5 A
VGS = 10 V
td(off)
tr
tf
100
td(on)
10
1
10
TJ = 150°C
1
125°C
25°C
−55°C
0.1
1
10
RG, GATE RESISTANCE (W)
100
0.3
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 11. Diode Forward Voltage versus
Current
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4
1.2
NDF11N50Z
TYPICAL CHARACTERISTICS
ID, DRAIN CURRENT (A)
100
100 ms 10 ms
1 ms
10 ms
VGS v 30 V
SINGLE PULSE
TC = 25°C
10
dc
1
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
Figure 12. Maximum Rated Forward Biased
Safe Operating Area NDF11N50Z
10
DUTY CYCLE = 0.5
R(t) (C/W)
1
0.1
0.2
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
1E−06
1E−05
RqJC = 3.2°C/W
Steady State
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
PULSE TIME (s)
Figure 13. Thermal Impedance (Junction−to−Case) for NDF11N50Z
LEADS
HEATSINK
0.110″ MIN
Figure 14. Isolation Test Diagram
Measurement made between leads and heatsink with all leads shorted together.
*For additional mounting information, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
5
1E+02
1E+03
NDF11N50Z
ORDERING INFORMATION
Package
Shipping
NDF11N50ZG
Order Number
TO−220FP
(Pb−Free, Halogen−Free)
50 Units / Rail
NDF11N50ZH
TO−220FP
(Pb−Free, Halogen−Free)
50 Units / Rail
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220 FULLPACK, 3−LEAD
CASE 221AH
ISSUE F
A
E
B
P
E/2
0.14
SCALE 1:1
Q
D
M
B A
A
H1
M
A1
C
NOTE 3
1 2 3
L
L1
3X
3X
SEATING
PLANE
b2
c
b
0.25
M
B A
M
C
A2
e
SIDE VIEW
FRONT VIEW
SECTION D−D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. CONTOUR UNCONTROLLED IN THIS AREA.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH AND GATE
PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO
EXCEED 0.13 PER SIDE. THESE DIMENSIONS ARE TO BE MEA
SURED AT OUTERMOST EXTREME OF THE PLASTIC BODY.
5. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION.
LEAD WIDTH INCLUDING PROTRUSION SHALL NOT EXCEED 2.00.
6. CONTOURS AND FEATURES OF THE MOLDED PACKAGE BODY
MAY VARY WITHIN THE ENVELOP DEFINED BY DIMENSIONS A1
AND H1 FOR MANUFACTURING PURPOSES.
MILLIMETERS
MIN
MAX
4.30
4.70
2.50
2.90
2.50
2.90
0.54
0.84
1.10
1.40
0.49
0.79
14.70
15.30
9.70
10.30
2.54 BSC
6.60
7.10
12.50
14.73
--2.80
3.00
3.40
2.80
3.20
DIM
A
A1
A2
b
b2
c
D
E
e
H1
L
L1
P
Q
GENERIC
MARKING DIAGRAM*
A
NOTE 6
DATE 30 SEP 2014
NOTE 6
H1
D
D
XX
XXXXXXXXX
AWLYWWG
A
SECTION A−A
ALTERNATE CONSTRUCTION
1
STYLE 1:
PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 2
3. GATE
STYLE 2:
PIN 1. CATHODE
2. ANODE
3. GATE
DOCUMENT NUMBER:
98AON52577E
DESCRIPTION:
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
TO−220 FULLPACK, 3−LEAD
PAGE 1 OF 1
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