DATA SHEET
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SPM 49 Series
Smart Power Module (SPM)
Inverter, 650 V, 50 A
NFAL5065L4BT
General Description
The NFAL5065L4BT is a smart power module providing
a fully-featured, high-performance inverter output stage for AC
induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built-in IGBTs to minimize EMI and
losses, while also providing multiple on-module protection features:
under-voltage lockouts, over-current shutdown, temperature sensing,
and fault reporting. The built-in, high-speed HVIC requires only
a single supply voltage and translates the incoming logic-level gate
inputs to high-voltage, high-current drive signals to properly drive the
module’s internal IGBTs. Separate negative IGBT terminals are
available for each phase to support the widest variety of control
algorithms.
3D Package Drawing
(Click to Activate 3D Content)
SPM49−CAB
CASE MODGQ
MARKING DIAGRAM
Features
• UL Certified No. 209204 (UL1557)
• 650 V – 50 A 3-Phase IGBT Inverter, Including Control ICs for
•
•
•
•
•
•
•
•
Gate Drive and Protections
Low-Loss, Short-Circuit-Rated IGBTs
Very Low Thermal Resistance Using Al2O3 DBC Substrate
Built-In Bootstrap Diodes/Resistors
Separate Open-Emitter Pins from Low-Side IGBTs for
Three-Phase Current Sensing
Built−In NTC Thermistor for Temperature Monitoring and
Management
Adjustable Over-Current Protection via Integrated Sense-IGBTs
Isolation Rating of 2500 Vrms/1 min
These Devices are RoHS Compliant
Typical Applications
ON
NFAL5065L4BT
ZZZ
AT
Y
WW
NNNNNNN
NFAL5065L4BT
ZZZ ATYWW
NNNNNNN
= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
ORDERING INFORMATION
• Motion Control − Industrial Motor (AC 200 V Class)
See detailed ordering and shipping information on page 10 of
this data sheet.
Integrated Power Functions
• 650 V – 50 A IGBT Inverter for Three-Phase DC/AC Power
Conversion (Refer to Figure 2)
Integrated Drive, Protection, and System Control Functions
• For Inverter High-Side IGBTs: gate-drive circuit, high-voltage
•
•
•
isolated high-speed level-shifting control circuit, Under-Voltage
Lock-Out Protection (UVLO), Available bootstrap circuit example is
given in Figures 4 and 16
For Inverter Low-Side IGBTs: gate-drive circuit, Short-Circuit
Protection (SCP) control circuit, Under-Voltage Lock-Out Protection
(UVLO)
Fault Signaling: corresponding to UV (low-side supply) and SC
faults
Input Interface: active-HIGH interface, works with 3.3 V/5 V logic,
Schmitt-trigger input
© Semiconductor Components Industries, LLC, 2019
October, 2021 − Rev. 3
1
Publication Order Number:
NFAL5065L4BT/D
NFAL5065L4BT
PIN CONFIGURATION
(31) LIN(W)
(30) LIN(V)
NW (1)
(29) LIN(U)
(28) VFO
(27) CFOD
(26) CIN
NV (2)
(25) VTS
(24) VSS(L)
(23) VDD(L)
NU (3)
(22) RSC
(21) VS(W)
W (4)
(20) VB(W)
Case Temperature (Tc)
Detecting Point
(19) VSS(H)
(18) VDD(WH)
V (5)
(17) HIN(W)
(16) VS(V)
(15) VB(V)
44.20
U (6)
(14) VDD(VH)
(13) HIN(V)
P (7)
(12) VS(U)
(11) VB(U)
(10) VDD(UH)
RTH (8)
(9) HIN(U)
17.15
Figure 1. Pin Configuration − Top View
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NFAL5065L4BT
PIN DESCRIPTION
Pin Number
Pin Name
Pin Description
1
NW
Negative DC-Link Input for W Phase
2
NV
Negative DC-Link Input for V Phase
3
NU
Negative DC-Link Input for U Phase
4
W
Output for W Phase
5
V
Output for V Phase
6
U
Output for U Phase
7
P
Positive DC-Link Input
8
RTH
9
HIN(U)
10
VDD(UH)
11
VB(U)
High-Side Bias Voltage for U Phase IGBT Driving
12
VS(U)
High-Side Bias Voltage GND for U Phase IGBT Driving
13
HIN(V)
Signal Input for High-Side V Phase
14
VDD(VH)
15
VB(V)
High-Side Bias Voltage for V Phase IGBT Driving
16
VS(V)
High-Side Bias Voltage GND for V Phase IGBT Driving
17
HIN(W)
18
VDD(WH)
19
VSS(H)
High-Side Common Supply Ground, connected to HVIC
20
VB(W)
High-Side Bias Voltage for W Phase IGBT Driving
21
VS(W)
High-Side Bias Voltage GND for W Phase IGBT Driving
Series Resistor for Thermistor (Temperature Detection)
Signal Input for High-Side U Phase
High-Side Bias Voltage for U Phase IC
High-Side Bias Voltage for V Phase IC
Signal Input for High-Side W Phase
High-Side Bias Voltage for W Phase IC
22
RSC
23
VDD(L)
Resistor for Over and Short-Circuit Current Detection
Low-Side Bias Voltage for IC and IGBTs Driving
24
VSS(L)
Low-Side Common Supply Ground, connected to LVIC
25
VTS
Voltage Output for LVIC Temperature Sensing Unit
26
CIN
Input for Current Protection
27
CFOD
Capacitor for Fault Output Duration Selection
28
VFO
29
LIN(U)
Fault Output
Signal Input for Low-Side U Phase
30
LIN(V)
Signal Input for Low-Side V Phase
31
LIN(W)
Signal Input for Low-Side W Phase
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NFAL5065L4BT
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
(8) RTH
P (7)
Thermistor
(11) VB(U)
(10) VDD(UH)
VB
VDD
HVIC
OUT
VSS
(9) HIN(U)
IN
VS
(12) VS(U)
(15) VB(V)
(14) VDD(VH)
U (6)
VB
VDD
VSS
(13) HIN(V)
HVIC
OUT
IN
VS
V (5)
(16) VS(V)
(20) VB(W)
(18) VDD(WH)
(19) VSS(H)
(17) HIN(W)
VB
VDD
HVIC
OUT
VSS
VS
IN
W (4)
(21) VS(W)
(25) VTS
VTS
(26) CIN
CIN
(27) CFOD
(28) VFO
OUT1
NU (3)
CFOD
VFO
(29) LIN(U)
IN1
(30) LIN(V)
IN2
(31) LIN(W)
IN3
(23) VDD(L)
VDD
(24) VSS(L)
VSS
OUT2
LVIC
NV (2)
OUT3
NW (1)
(22) RSC
NOTES:
1. Inverter high-side is composed of three normal-IGBTs, freewheeling diodes, and one control IC for each IGBT.
2. Inverter low-side is composed of three sense-IGBTs, freewheeling diodes, and one control IC for each IGBT. It has gate drive and
protection functions.
3. Inverter power side is composed of four inverter DC-link input terminals and three inverter output terminals.
Figure 2. Internal Block Diagram
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NFAL5065L4BT
ABSOLUTE MAXIMUM RATINGS (Tj = 25°C unless otherwise noted)
Symbol
Rating
Conditions
Rating
Unit
INVERTER PART
VPN
VPN(surge)
Vces
Supply Voltage
Applied between P − NU, NV, NW
450
V
Supply Voltage (Surge)
Applied between P − NU, NV, NW
550
V
650
V
Collector-Emitter Voltage
±Ic
Each IGBT Collector Current
Tc = 25°C, Tj ≤ 150°C
50
A
±Icp
Each IGBT Collector Current (Peak)
Tc = 25°C, Tj ≤ 150°C, Under 1 ms
Pulse Width (Note 4)
100
A
Pc
Collector Dissipation
Tc = 25°C per One Chip (Note 4)
192
W
Tj
Operating Junction Temperature
−40~150
°C
CONTROL PART
VDD
Control Supply Voltage
Applied between VDD(H), VDD(L) − VSS
20
V
VBS
High-Side Control Bias Voltage
Applied between VB(U) − VS(U),
VB(V) − VS(V), VB(W) − VS(W)
20
V
VIN
Input Signal Voltage
Applied between HIN(U), HIN(V), HIN(W),
LIN(U), LIN(V), LIN(W) − VSS
−0.5~VDD+0.5
V
VFO
Fault Output Supply Voltage
Applied between VFO − VSS
−0.5~VDD+0.5
V
IFO
Fault Output Current
Sink Current at VFO pin
5
mA
Current Sensing Input Voltage
Applied between CIN − VSS
−0.5~VDD+0.5
V
−40~150
°C
650
V
−40~150
°C
400
V
−40~125
°C
−40~125
°C
2500
Vrms
VCIN
Tj
Operating Junction Temperature
BOOSTSTRAP DIODE PART
VRRM
Tj
Maximum Repetitive Reverse
Voltage
Operating Junction Temperature
TOTAL SYSTEM
VPN(PROT)
Tc
Self-Protection Supply Voltage Limit
(Short-Circuit Protection Capability)
VDD = VBS = 13.5~16.5 V, Tj = 150°C,
Vces < 650 V, Non-Repetitive, < 2 ms
Module Case Operation
Temperature
See Figure 1
Tstg
Storage Temperature
Viso
Isolation Voltage
60 Hz, Sinusoidal, AC 1 Minute, Connection
Pins to Heat Sink Plate
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. These values had been made an acquisition by the calculation considered to design factor.
THERMAL RESISTANCE
Symbol
Rth(j-c)Q
Rth(j-c)F
Parameter
Junction-to-Case Thermal
Resistance (Note 5)
Conditions
Min
Typ
Max
Unit
Inverter IGBT Part (per 1/6 module)
−
−
0.65
°C/W
Inverter FWDi Part (per 1/6 module)
−
−
0.96
°C/W
5. For the measurement point of case temperature (Tc), please refer to Figure 1. DBC discoloration and Picker Circle Printing allowed, please
refer to application note AN−9190 (Impact of DBC Oxidation on SPM® Module Performance).
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NFAL5065L4BT
ELECTRICAL CHARACTERISTICS (Tj = 25°C unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
INVERTER PART
VCE(sat)
VF
HS
ton
Collector-Emitter
Saturation Voltage
VDD = VBS = 15 V
IN = 5 V
Ic = 50 A, Tj = 25°C
−
1.55
2.05
V
FWDi Forward Voltage
IN = 0 V
Ic = 50 A, Tj = 25°C
−
1.70
2.20
V
Switching Times
VPN = 300 V, VDD = 15 V, Ic = 50 A
Tj = 25°C
IN = 0 V ´ 5 V, Inductive Load
See Figure 3
(Note 6)
1.10
1.70
2.30
ms
−
0.25
0.55
ms
−
1.70
2.30
ms
−
0.16
0.46
ms
−
0.10
−
ms
1.00
1.60
2.20
ms
−
0.25
0.55
ms
−
2.00
2.60
ms
−
0.18
0.48
ms
−
0.10
−
ms
−
−
1
mA
tc(on)
toff
tc(off)
trr
LS
VPN = 300 V, VDD = 15 V, Ic = 50 A
Tj = 25°C
IN = 0 V ´ 5 V, Inductive Load
See Figure 3
(Note 6)
ton
tc(on)
toff
tc(off)
trr
Ices
Collector-Emitter Leakage
Current
Vce = Vces
CONTROL PART
IQDDH
Quiescent VDD Supply
Current
IQDDL
IPDDH
Operating VDD Supply
Current
IPDDL
VDD(UH,VH,WH) = 15 V,
HIN(U,V,W) = 0 V
VDD(UH) − VSS(H),
VDD(VH) − VSS(H),
VDD(WH) − VSS(H)
−
−
0.30
mA
VDD(L) = 15 V,
LIN(U,V,W) = 0 V
VDD(L) − VSS(L)
−
−
3.50
mA
VDD(UH,VH,WH) = 15 V,
FPWM = 20 kHz,
Duty = 50%, Applied to one
PWM Signal
Input for High-Side
VDD(UH) − VSS(H),
VDD(VH) − VSS(H),
VDD(WH) − VSS(H)
−
−
0.40
mA
VDD(L) = 15 V,
FPWM = 20 kHz,
Duty = 50%, Applied to one
PWM Signal Input for
Low-Side
VDD(L) − VSS(L)
−
−
6.00
mA
IQBS
Quiescent VBS Supply
Current
VDD = VBS = 15 V,
HIN(U,V,W) = 0 V
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
−
−
0.30
mA
IPBS
Operating VBS Supply
Current
VDD = VBS = 15 V,
FPWM = 20 kHz,
Duty = 50%, Applied to one
PWM Signal Input for
High-Side
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
−
−
5.00
mA
VFOH
Fault Output Voltage
VDD = 15 V, CIN = 0 V,
VFO Circuit: 10 kW to 5 V Pull−up
4.90
−
−
V
VDD = 15 V, CIN = 1 V, IFO = 1 mA
−
−
0.95
V
Sensing Current of Each
Sense IGBT
VDD = 15 V, LIN = 5 V,
Rsc = 0 W,
No Connection of Shunt
Resistor at NU, NV, NW
Terminal
Ic = 50 A
−
17.0
−
mA
Short Circuit Trip Level
VDD = 15 V
CIN − VSS(L)
0.46
0.48
0.50
V
Short Circuit Current Level
for Trip
Rsc = 24 W (±1%), No Connection of Shunt Resistor
at NU, NV, NW Terminal (Note 7)
75
−
−
A
VFOL
ISEN
VSC(ref)
ISC
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NFAL5065L4BT
ELECTRICAL CHARACTERISTICS (Tj = 25°C unless otherwise specified.) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
10.3
−
12.5
V
UVDDR
Supply Circuit Under-Voltage Detection Level
Protection
Reset Level
10.8
−
13.0
V
UVBSD
Detection Level
10.0
−
12.0
V
UVBSR
Reset Level
10.5
−
12.5
V
CONTROL PART
UVDDD
VIN(ON)
ON Threshold Voltage
VIN(OFF)
OFF Threshold Voltage
Applied between HIN(U,V,W) − VSS(H),
LIN(U,V,W) − VSS(L)
VTS
Voltage Output for LVIC
Temperature Sensing Unit
VDD(L) = 15 V, TLVIC = 25°C
See Figure 6 and 7 (Note 8)
tFOD
Fault-Out Pulse Width
CFOD = 22 nF (Note 9)
RTH
Resistance of Thermistor
At TTH = 25°C
At TTH = 100°C
−
−
2.6
V
0.8
−
−
V
0.909
1.030
1.151
V
1.6
−
−
ms
See Figure 8
(Note 10)
−
47
−
kW
−
2.9
−
kW
See Figure 9
2.1
2.5
2.9
V
12.5
15.5
18.5
W
BOOTSTRAP DIODE/RESISTOR PART
VF
RBOOT
Forward Voltage
If = 0.1 A, Tj = 25°C
Bootstrap Resistor
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. ton and toff include the propagation delay of the internal drive IC. tc(on) and tc(off) are the switching times of IGBT under the given gate-driving
condition internally. For the detailed information, please see Figure 3.
7. Short-circuit current protection functions only at the low-sides because the sense current is divided from main current at low-side IGBTs.
Inserting the shunt resistor for monitoring the phase current at NU, NV, NW terminal, the trip level of the short-circuit current is changed.
8. TLVIC is the temperature of LVIC itself. VTS is only for sensing temperature of LVIC and cannot shutdown IGBTs automatically. The
relationship between VTS voltage output and LVIC temperature is described in Figure 6. It is recommended to add a ceramic capacitor of
10 nF or more between VTS and VSS (Signal Ground) to make the VTS more stable as described in Figure 7. Refer to the application note
for this products about usage of VTS.
9. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation:
tFOD = 0.1 × 106 × CFOD [s].
10. TTH is the temperature of thermistor itself. To know case temperature (Tc), conduct experiments considering the application.
100% Ic 100% Ic
trr
Vce
Ic
Ic
VIN
VIN
ton
10% Ic
VIN(ON)
Vce
toff
tc(on)
90% Ic
VIN(OFF)
10% Vce
(a) turn-on
tc(off)
10% Vce
(b) turn-off
Figure 3. Switching Time Definition
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7
10% Ic
NFAL5065L4BT
One−Leg Diagram of SPM
IC
P
CBS
VDD
VB
VSS
OUT
LS Switching
VS
IN
HS Switching
LS Switching
VDD
0V
V
VSS
15 V
300 V
HS Switching
OUT
CFOD
CIN
10 kΩ
V
Inductor
IN
VDD
VFO
VIN
5V
VPN
U,V,W
NU, NV, NW
V
RSC
5V
Figure 4. Example Circuit of Switching Test
Inductive Load, VPN = 300 V, VDD = 15 V, Tj = 1505C
Inductive Load, VPN = 300 V, VDD = 15 V, Tj = 255C
4800
4400
4000
3600
IGBT Turn-off, Eoff
3200
FWD Turn-off, Erec
Switching Loss, Esw [mJ]
IGBT Turn-on, Eon
2800
2400
2000
1600
1200
800
4400
IGBT Turn-on, Eon
4000
3600
IGBT Turn-off, Eoff
3200
FWD Turn-off, Erec
2800
2400
2000
1600
1200
800
400
400
0
0
0
5
10
15
20
25
30
35
40
45
50
0
55
5
10
15
20
25
30
35
40
Collector Current, Ic [A]
Collector Current, Ic [A]
Figure 5. Switching Loss Characteristics
4.0
3.5
VTS Output Voltage (V)
Switching Loss, Esw [mJ]
4800
3.0
2.687
2.566
2.445
2.5
2.0
1.5
1.0
40
45
50
55
60
65
70
75
80
85
90
95
100
105
LVIC Temperature (5C)
Figure 6. Temperature Profile of VTS
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110
115
120
125
130
45
50
55
NFAL5065L4BT
VDD
VDD
Temperature
Sensing
Voltage
2.5 kW
+
−
VTS
A/D
> 10 nF is
recommended
MCU
100 kW
5.2 V
2.5 kW
SPM
GND
VSS
Figure 7. Internal Block Diagram and Interface Circuit of VTS
R−T Curve
600
550
16
Resistance (kW)
450
Resistance (kW)
R−T Curve in 50~1255C
20
500
400
350
300
12
8
250
4
200
0
50
150
60
70
80
90
100
110
120
Temperature TTH (5C)
100
50
0
−20 −10 0
10
20
30
40
50
60
70
80
90 100 110 120
Temperature TTH (5C)
Figure 8. R−T Curve of Built-in Thermistor
0.8
0.05
0.7
0.04
0.6
0.03
If [A]
If [A]
0.5
0.4
0.02
0.3
0.2
0.01
0.1
0.00
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
15
0.2
0.4
0.6
0.8
1
1.2
VF [V]
VF [V]
Figure 9. Characteristics of Bootstrap Diode/Resistor (Right Figure is Enlarged Figure)
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9
1.4
1.6
1.8
NFAL5065L4BT
RECOMMENDED OPERATING RANGES
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−
300
400
V
VPN
Supply Voltage
Applied between P−NU, NV, NW
VDD
Control Supply Voltage
Applied between VDD(UH,VH,WH)−VSS(H), VDD(L)−VSS(L)
13.5
15.0
16.5
V
VBS
High-Side Control Bias
Voltage
Applied between VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W)
13.0
15.0
18.5
V
−1
−
+1
V/ms
1.5
−
−
ms
−
−
20
kHz
FPWM = 5 kHz
−
−
27
Arms
FPWM = 15 kHz
−
−
20
dVDD/dt,
dVBS/dt
Control Supply Variation
tdead
Blanking Time for
Preventing Arm − Short
For Each Input Signal
FPWM
PWM Input Signal
−40°C ≤ Tc ≤ 125°C, −40°C ≤ Tj ≤ 150°C
Allowable r.m.s.
Output Current
VPN = 300 V, VDD = VBS = 15 V,
P.F = 0.8, Sinusoidal PWM
Tc ≤ 125°C, Tj ≤ 150°C (Note 11)
Voltage for Current
Sensing
Applied between NU, NV, NW−VSS
(Including Surge Voltage)
−5.0
−
+5.0
V
(Note 12)
1.1
−
−
ms
VDD = VBS = 15 V, IC ≤ 100 A, Wiring Inductance between
NU, NV, NW and DC Link N < 10 nH (Note 12)
2.0
−
−
−40
−
+150
Io
VSEN
PWIN(ON) Minimum Input Pulse
Width
PWIN(OFF)
Tj
Junction Temperature
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
11. This allowable output current value is the reference data for the safe operation of this product. This may be different from the actual application
and operating condition.
12. This product might not make output response if input pulse width is less than the recommended value.
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Shipping
NFAL5065L4BT
NFAL5065L4BT
SPM49−CAB
6 Units/Tube
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NFAL5065L4BT
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Conditions
Device Flatness
See Figure 10
Mounting Torque
Mounting Screw: M4
See Figure 11
Min
Typ
Max
Unit
−50
−
100
mm
Recommended 1.18 N ⋅ m
0.98
1.18
1.47
N⋅m
Recommended 12.03 kg ⋅ cm
10.00
12.03
14.98
kg ⋅ cm
Terminal Pulling Strength
Load 19.6 N
10
−
−
s
Terminal Bending Strength
Load 9.8 N, 90 degrees Bend
2
−
−
times
−
44.5
−
g
Weight
Figure 10. Flatness Measurement Position
NOTES:
13. Do not over torque when mounting screws. Too much mounting torque may cause DBC cracks, as well as bolts and Al heat-sink
destruction.
14. Avoid one-sided tightening stress. Figure 11 shows the recommended torque order for the mounting screws. Uneven mounting can cause
the DBC substrate of package to be damaged. The pre-screwing torque is set to 20~30% of maximum torque rating.
Figure 11. Mounting Screws Torque Order
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NFAL5065L4BT
TIME CHARTS OF SPMs PROTECTIVE FUNCTION
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVDDR
a1
Control
Supply Voltage
a6
UVDDD
a3
a2
a7
a4
Output Current
a5
Fault Output Signal
a1: Control supply voltage rises: after the voltage rises UVDDR, the circuits start to operate when the next input is applied.
a2: Normal operation: IGBT ON and carrying current.
a3: Under-voltage detection (UVDDD).
a4: IGBT OFF in spite of control input condition.
a5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
a6: Under-voltage reset (UVDDR).
a7: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 12. Under-voltage Protection (Low-side)
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVBSR
Control
Supply Voltage
b1
b5
UVBSD
b3
b6
b2
b4
Output Current
Fault Output Signal
High−level (no fault output)
b1: Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when the next input is applied.
b2: Normal operation: IGBT ON and carrying current.
b3: Under-voltage detection (UVBSD).
b4: IGBT OFF in spite of control input condition, but there is no fault output signal.
b5: Under-voltage reset (UVBSR).
b6: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 13. Under-voltage Protection (High-side)
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12
NFAL5065L4BT
Lower Arms
Control Input
c6
Protection
Circuit state
SET
c7
RESET
c4
Internal IGBT
Gate−Emitter
Input Voltage
c3
c2
Internal delay
at protection circuit
SC current trip level
c8
Output Current
c1
SC reference voltage
Sensing Voltage
of Sense Resistor
RC filter circuit
time constant
delay
Fault Output Signal
c5
(With the external sense resistance and RC filter connection)
c1: Normal operation: IGBT ON and carrying current.
c2: Short-circuit current detection (SC trigger).
c3: All low-side IGBTs gate are hard interrupted.
c4: All low-side IGBTs turn OFF.
c5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
c6: Input HIGH − IGBT ON state, but during the active period of fault output, the IGBT doesn’t turn ON.
c7: Fault output operation finishes, but IGBT doesn’t turn on until triggering the next signal from LOW to HIGH.
c8: Normal operation: IGBT ON and carrying current.
Figure 14. Short-circuit Current Protection (Low-side Operation Only)
INPUT/OUTPUT INTERFACE CIRCUIT
+5V (MCU or control power)
10 kW
SPM
HIN(U), HIN(V), HIN(W)
LIN(U), LIN(V), LIN(W)
MCU
VFO
VSS
NOTE:
15. RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance of the
application’s printed circuit board. The input signal section of the SPM49 product integrates 5 kW (typ.) pull-down resistor. Therefore, when
using an external filtering resistor, please pay attention to the signal voltage drop at input terminal.
Figure 15. Recommended MCU I/O Interface Circuit
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13
NFAL5065L4BT
5V line
R6
Temp.
Monitoring 1
(8) RTH Thermistor
R1
Gating UH
(9) HIN(U)
(10) VDD(UH)
C4
(11) VB(U)
R1
Gating VH
(13) HIN(V)
(14) VDD(VH)
C4
(15) VB(V)
R1
Gating WH
(17) HIN(W)
(18) VDD(WH)
(19) VSS(H)
C4
M
C
U
C1 C1 C1
(20) VB(W)
C3
OUT
VS
IN
VDD
VSS
HVIC
U (6)
OUT
VB
(16) VS(V)
C4
C3
HVIC
VB
(12) VS(U)
C4
C3
P (7)
IN
VDD
VSS
VS
IN
VDD
VSS
V (5)
C8
HVIC
VDC
OUT
VB
VS
W (4)
(21) VS(W)
C4
M
5V line
Gating VL
Gating WL
C6
(27) CFOD
(28) VFO
C1
C1
Gating UL
R2
R1
Fault
R1
(29) LIN(U)
R1
(30) LIN(V)
R1
(31) LIN(W)
15V line
C1 C1 C1
C2
C4
(23) VDD(L)
(24) VSS(L)
(25) VTS
Temp.
Monitoring 2
OUT1
CFOD
NU (3)
VFO
A
R3
IN1
IN2
IN3
OUT2
LVIC
NV (2)
VDD
R3
E
Shunt
Resistor
VSS
Power
GND Line
OUT3
VTS
NW (1)
C7
CIN
RSC (22)
(26) CIN
R4
Sense
Resistor
D
C5
R3
R5
B
C
U−Phase Current
V−Phase Current
W−Phase Current
Control
GND Line
NOTES:
16. To avoid malfunction, the wiring of each input should be as short as possible (less than 2−3 cm).
17. VFO output is an open-drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
that makes IFO up to 1 mA. Please refer to Figure 15.
18. Fault out pulse width can be adjusted by capacitor C6 connected to the CFOD terminal.
19. Input signal is active-HIGH type. There is a 5 kW resistor inside the IC to pull-down each input signal line to GND. RC coupling circuits
should be adopted for the prevention of input signal oscillation. R1C1 time constant should be selected in the range 50~150 ns
(recommended R1 = 100 W, C1 = 1 nF).
20. Each wiring pattern inductance of point A should be minimized (recommend less than 10 nH). Use the shunt resistor R3 of surface mounted
(SMD) type to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the shunt resistor
R3 as close as possible.
21. To insert the shunt resistor to measure each phase current at NU, NV, NW terminal, it makes to change the trip level ISC about the
short-circuit current.
22. To prevent errors of the protection function, the wiring of points B, C, and D should be as short as possible. The wiring of B between CIN
filter and RSC terminal should be divided at the point that is close to the terminal of sense resistor R4.
23. For stable protection function, use the sense resistor R4 with resistance variation within 1% and low inductance value.
24. In the short-circuit protection circuit, select the R5C5 time constant in the range 2.0~2.5 ms. R5 should be selected with a minimum of 10
times larger resistance than sense resistor R4. Do enough evaluation on the real system because short-circuit protection time may vary
wiring pattern layout and value of the R5C5 time constant.
25. Each capacitor should be mounted as close to the pins of the SPM product as possible.
26. To prevent surge destruction, the wiring between the smoothing capacitor C8 and the P & GND pins should be as short as possible. The
use of a high-frequency non-inductive capacitor of around 0.1~0.22 mF between the P & GND pins is recommended.
27. Relays are used in most systems of electrical equipment in industrial application. In these cases, there should be sufficient distance
between the MCU and the relays.
28. The Zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each
pair of control supply terminals (recommended Zener diode is 22 V/1 W, which has the lower Zener impedance characteristic than about
15 W).
29. C2 of around seven times larger than bootstrap capacitor C3 is recommended.
30. Please choose the electrolytic capacitor with good temperature characteristic in C3. Choose 0.1~0.2 mF R-category ceramic capacitors
with good temperature and frequency characteristics in C4.
Figure 16. Typical Application Circuit
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DIP31, 79x30/SPM49 CAB
CASE MODGQ
ISSUE O
DATE 06 DEC 2018
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
DOCUMENT NUMBER:
DESCRIPTION:
XXXX
ZZZ
AT
Y
W
NNN
= Specific Device Code
= Assembly Lot Code
= Assembly & Test Location
= Year
= Work Week
= Serial Number
98AON98538G
DIP31, 79x30/SPM49 CAB
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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