NTD4806N, NVD4806N
Power MOSFET
30 V, 76 A, Single N−Channel, DPAK/IPAK
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
AEC−Q101 Qualified and PPAP Capable − NVD4806N
These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
RDS(on) MAX
V(BR)DSS
6.0 mW @ 10 V
30 V
Applications
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Parameter
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
"20
V
ID
15.6
A
N−Channel
G
S
Continuous Drain
Current (RqJA) (Note 1)
TA = 25°C
Power Dissipation
(RqJA) (Note 1)
TA = 25°C
PD
2.65
W
Continuous Drain
Current (RqJA) (Note 2)
TA = 25°C
ID
11.3
A
3
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
4
12
4
1 2
TA = 85°C
8.8
PD
1.4
W
Continuous Drain
Current (RqJC)
(Note 1)
TC = 25°C
ID
79
A
Power Dissipation
(RqJC) (Note 1)
TC = 25°C
TC = 85°C
61
PD
68
W
TA = 25°C
IDM
150
A
TA = 25°C
IDmaxPkg
45
A
TJ, Tstg
−55 to
175
°C
IS
50
A
Drain to Source dV/dt
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
L = 1.0 mH, IL(pk) = 21 A, RG = 25 W)
EAS
220
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
tp=10ms
Current Limited by Package
Operating Junction and Storage Temperature
Source Current (Body Diode)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
2 3
IPAK
CASE 369AD
(Straight Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
AYWW
48
06NG
Steady
State
1
AYWW
48
06NG
TA = 85°C
TA = 25°C
Pulsed Drain Current
76 A
9.4 mW @ 4.5 V
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
Power Dissipation
(RqJA) (Note 2)
ID MAX
2
1 Drain 3
Gate Source
A
Y
WW
4806N
G
1 2 3
Gate Drain Source
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location Code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package bottom (molding ejecter
pin), the front side assembly code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
April, 2017 − Rev. 11
1
Publication Order Number:
NTD4806N/D
NTD4806N, NVD4806N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
RqJC
2.2
°C/W
Junction−to−Case (Drain)
Junction−to−Tab (Drain)
RqJC−TAB
3.5
Junction−to−Ambient − Steady State (Note 1)
RqJA
56.7
Junction−to−Ambient − Steady State (Note 2)
RqJA
106.8
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
27
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = "20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
"100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
6.0
VGS = 10 to 11.5 V
VGS = 4.5 V
Forward Transconductance
gFS
1.5
ID = 30 A
4.9
ID = 15 A
4.8
ID = 30 A
7.9
ID = 15 A
7.5
VDS = 15 V, ID = 15 A
mV/°C
6.0
mW
9.4
14
S
2142
pF
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz,
VDS = 12 V
480
251
15
VGS = 4.5 V, VDS = 15 V,
ID = 30 A
23
nC
3.0
7.0
7.0
VGS = 11.5 V, VDS = 15 V,
ID = 30 A
37
nC
13.9
ns
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
29.7
18.3
7.8
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
www.onsemi.com
2
NTD4806N, NVD4806N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
ns
8.5
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
23.8
26
4.7
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V,
IS = 30 A
TJ = 25°C
0.9
TJ = 125°C
0.8
26
VGS = 0 V, dIs/dt= 100 A/ms,
IS = 30 A
QRR
1.2
V
ns
13
13
16
nC
nH
PACKAGE PARASITIC VALUES
Source Inductance
LS
2.49
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK
LD
Gate Inductance
LG
3.46
Gate Resistance
RG
1.0
TA = 25°C
1.88
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
www.onsemi.com
3
NTD4806N, NVD4806N
TYPICAL PERFORMANCE CURVES
80
70
4.2 V
4V
60
50
3.8 V
40
30
3.6 V
20
3.4 V
10
0
3.2 V
0
1
4
3
2
5
VDS ≥ 10 V
TJ = 125°C
TJ = 25°C
TJ = −55°C
0
1
2
3
4
6
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
TJ = 25°C
0.043
0.038
0.033
0.028
0.023
0.018
0.013
0.008
0.003
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.048
3
4
5
6
7
8
9
10
0.015
TJ = 25°C
VGS = 4.5 V
0.010
VGS = 11.5 V
0.005
0
50
55
60
65
70
75
80
85
90
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
2.0
VGS = 0 V
ID = 30 A
VGS = 10 V
TJ = 175°C
10,000
1.5
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
6V
5V
4.5 V
10 V
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
90
ID, DRAIN CURRENT (AMPS)
100
1.0
0.5
0
−50 −25
1000
TJ = 125°C
100
10
0
25
50
75
100
125
150
175
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
www.onsemi.com
4
25
NTD4806N, NVD4806N
C, CAPACITANCE (pF)
4000
VDS = 0 V VGS = 0 V
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES
TJ = 25°C
Ciss
3000
Ciss
2000
Crss
1000
Coss
0
10
Crss
5
VGS
0
VDS
5
10
15
20
25
8
6
4
0
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
tr
td(off)
td(on)
tf
1
1
0
10
RG, GATE RESISTANCE (OHMS)
15
10
5
10
1 ms
100 ms
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D, DRAIN CURRENT (AMPS)
0.7
0.8
1.0
0.9
Figure 10. Diode Forward Voltage vs. Current
10 ms
0.1
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
100
0.1
TJ = 25°C
20
0
0.5
100
1000
1
20
VGS = 0 V
25
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
VGS = 20 V
SINGLE PULSE
TC = 25°C
15
5
10
QG, TOTAL GATE CHARGE (nC)
30
VDD = 15 V
ID = 30 A
VGS = 11.5 V
10
ID = 30 A
VGS = 4.5 V
TJ = 25°C
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
100
VGS
Q2
2
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
QT
Q1
250
ID = 21 A
200
150
100
50
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
www.onsemi.com
5
175
NTD4806N, NVD4806N
TYPICAL PERFORMANCE CURVES
I D, DRAIN CURRENT (AMPS)
100
100°C
125°C
25°C
10
1
1
100
10
PULSE WIDTH (ms)
1000
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
Figure 13. Avalanche Characteristics
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
1.0E-05
1.0E-04
t1
t2
DUTY CYCLE, D = t1/t2
1.0E-03
1.0E-02
t, TIME (ms)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E-01
1.0E+00
1.0E+01
Figure 14. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD4806NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD4806N−35G
IPAK Trimmed Lead
(3.5 ± 0.15 mm)
(Pb−Free)
75 Units / Rail
NVD4806NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NVD4806NT4G−VF01
DPAK
(Pb−Free)
2500 / Tape & Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
3.5 MM IPAK, STRAIGHT LEAD
CASE 369AD
ISSUE B
DATE 18 APR 2013
SCALE 1:1
E
E3
L2
E2
A1
D2
D
L1
L
T
SEATING
PLANE
NOTES:
1.. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2.. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM TERMINAL TIP.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD GATE OR MOLD FLASH.
A
A1
b1
2X
e
A2
3X
E2
b
0.13
M
T
D2
DIM
A
A1
A2
b
b1
D
D2
E
E2
E3
e
L
L1
L2
MILLIMETERS
MIN
MAX
2.19
2.38
0.46
0.60
0.87
1.10
0.69
0.89
0.77
1.10
5.97
6.22
4.80
−−−
6.35
6.73
4.57
5.45
4.45
5.46
2.28 BSC
3.40
3.60
−−−
2.10
0.89
1.27
GENERIC MARKING
DIAGRAMS*
OPTIONAL
CONSTRUCTION
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
Discrete
AYWW
XXX
XXXXXG
XXXXXX
A
L
Y
WW
G
Integrated
Circuits
XXXXXXG
ALYWW
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON23319D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
3.5 MM IPAK, STRAIGHT LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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