NTLJD4150P_07

NTLJD4150P Power MOSFET −30 V, −3.4 A, mCoolt Dual P−Channel, 2x2 mm WDFN Package Features • WDFN 2x2 mm Package Provides Exposed Drain Pad for • • • • Excellent Thermal Conduction Footprint Same as SC−88 Package Low Profile (< 0.8 mm) for Easy Fit in Thin Environments Bidirectional Current Flow with Common Source Configuration This is a Pb−Free Device V(BR)DSS −30 V http://onsemi.com RDS(on) Max 135 mW @ 10 V 200 mW @ 4.5 V S1 ID Max (Note 1) −3.4 A S2 Applications • Li−Ion Battery Charging and Protection Circuits • LED Backlight, Flashlight • Dual−High Side Load Switch MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (Note 1) Steady State t≤5s Power Dissipation (Note 1) Steady State t≤5s Continuous Drain Current (Note 2) Power Dissipation (Note 2) Pulsed Drain Current TA = 25°C Steady State TA = 85°C TA = 25°C PD IDM TJ, TSTG IS TL ID TA = 25°C TA = 85°C TA = 25°C PD TA = 25°C 2.3 −1.8 −1.4 0.7 −14 −55 to 150 −1.8 260 W A °C A °C A Symbol VDSS VGS ID Value −30 ±20 −2.7 −2.0 −3.4 1.5 W Unit V V A G1 G2 D1 P−CHANNEL MOSFET D2 D2 P−CHANNEL MOSFET D1 MARKING DIAGRAM 1 2 3 JE M G 6 5 G 4 Pin 1 JE M G WDFN6 CASE 506AN = Specific Device Code = Date Code = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS D1 S1 G1 D2 1 2 D2 3 4 S2 6 5 D1 G2 t p = 10 m s Operating Junction and Storage Temperature Source Current (Body Diode) (Note 2) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface Mounted on FR4 Board using the minimum recommended pad size. (Top View) ORDERING INFORMATION Device NTLJD4150PTBG Package WDFN6 (Pb−Free) Shipping † 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D © Semiconductor Components Industries, LLC, 2007 1 January, 2007 − Rev. 0 Publication Order Number: NTLJD4150P/D NTLJD4150P THERMAL RESISTANCE RATINGS Parameter SINGLE OPERATION (SELF−HEATED) Junction−to−Ambient – Steady State (Note 3) Junction−to−Ambient – Steady State Min Pad (Note 4) Junction−to−Ambient – t ≤ 5 s (Note 3) DUAL OPERATION (EQUALLY HEATED) Junction−to−Ambient – Steady State (Note 3) Junction−to−Ambient – Steady State Min Pad (Note 3) Junction−to−Ambient – t ≤ 5 s (Note 3) RqJA RqJA RqJA 58 133 40 °C/W RqJA RqJA RqJA 83 177 54 °C/W Symbol Max Unit 3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu). MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS VGS = 0 V, ID = −250 mA ID = −250 mA, Ref to 25°C TJ = 25°C TJ = 85°C −30.0 1.9 −1.0 −5.0 ±100 nA V mV/°C mA Symbol Test Conditions Min Typ Max Unit VDS = −24 V, VGS = 0 V Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Gate Threshold Temperature Coefficient Drain−to−Source On−Resistance IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS(TH)/TJ RDS(on) VGS = VDS, ID = −250 mA −1.0 −1.5 0.4 −2.0 V mV/°C VGS = −10 V, ID = −4.0 A VGS = −4.5 V, ID = −3.0 A 95 156 1.5 135 200 mW mW S Forward Transconductance gFS VDS = −10 V, ID = −1.0 A CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Gate Resistance SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) tf VGS = −4.5 V, VDD = −24 V, ID = −3.0 A, RG = 2 W 7.0 16.2 11.8 8.8 ns CISS COSS CRSS QG(TOT) QG(TH) QGS QGD RG VGS =−4.5 V, VDS = −15 V, ID = −2.0 A VGS = 0 V, f = 1 MHz, VDS = −15 V 300 50 30 3.6 0.44 0.79 1.54 10.6 W 4.5 nC pF 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTLJD4150P MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued) Parameter Symbol Test Conditions Min Typ Max Unit DRAIN−SOURCE DIODE CHARACTERISTICS Forward Recovery Voltage VSD VGS = 0 V, IS = −2.0 A TJ = 25°C TJ = 85°C −0.85 −0.77 8.9 VGS = 0 V, dISD/dt = 100 A/ms, IS = −2.0 A 6.2 2.9 3.0 nC ns −1.0 V Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time tRR ta tb QRR 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTLJD4150P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 10 −ID, DRAIN CURRENT (AMPS) −10V 9 to 8 −7V 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −2.6 V −3.4 V −3.0 V −6 V −4.8 V TJ = 25°C −ID, DRAIN CURRENT (AMPS) −4.6 V −4.2 V −3.8 V 8 VDS ≥ 10 V 7 6 5 4 3 2 1 0 1 2 TJ = 125°C TJ = 85°C TJ = 25°C TJ = −55°C 3 4 5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 1.0 2.0 3.0 TJ = 125°C TJ = 85°C TJ = 25°C TJ = −55°C 4.0 VGS = −10 V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 5 6 7 8 9 10 VGS = −4.5 V VGS = −10 V TJ = 25°C −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current and Gate Voltage 1000 VGS = 0 V −IDSS, LEAKAGE (nA) 100 TJ = 125°C TJ = 100°C 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.6 I = −3.0 A 1.5 D VGS = −10 V 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 −50 −25 0 25 50 75 100 125 150 1 TJ = 85°C 0.1 0 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 NTLJD4150P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS = 0 V TJ = 25°C Ciss −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 500 6 5 4 QGS 3 8 2 1 0 4 0 0 0.2 0.40.60.8 1 1.21.41.61.8 2 2.2 2.4 2.62.8 3 3.23.43.6 QG, TOTAL GATE CHARGE (nC) ID = −3.0 A TJ = 25°C QGD VGS VDS QT 20 −VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) 400 16 300 12 200 Coss 100 0 0 Crss 5 10 15 20 25 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 30 Figure 7. Capacitance Variation Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 100 −Is, SOURCE CURRENT (AMPS) VDD = −24 V ID = −3.0 A VGS = −4.5 V t, TIME (ns) tr td(off) tf td(on) 4 VGS = 0 V TJ = 25°C 3 10 2 1 1 1 10 RG, GATE RESISTANCE (OHMS) 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 10 −ID, DRAIN CURRENT (AMPS) 10 ms 100 ms 1 *See Note 2 on Page 1 TC = 25°C TJ = 150°C SINGLE PULSE dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 ms 10 ms 0.1 0.01 Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 5 NTLJD4150P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) EFFECTIVE TRANSIENT THERMAL RESISTANCE 1000 100 D = 0.5 0.2 0.1 *See Note 2 on Page 1 P(pk) D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TA = P(pk) RqJA(t) 10 0.05 0.02 1 0.01 SINGLE PULSE 0.1 0.000001 0.00001 0.0001 0.001 t1 t2 DUTY CYCLE, D = t1/t2 0.01 0.1 t, TIME (s) 1 10 100 1000 Figure 12. Thermal Response http://onsemi.com 6 NTLJD4150P PACKAGE DIMENSIONS WDFN6 2x2 CASE 506AN−01 ISSUE C D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L J MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 2.00 BSC 0.57 0.77 2.00 BSC 0.90 1.10 0.65 BSC 0.25 REF 0.20 0.30 0.15 REF PIN ONE REFERENCE E 2X 0.10 C 2X 0.10 C 0.10 C 6X 0.08 C 6X L 1 3 6X K ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ÍÍÍ ÍÍÍ A3 A1 D2 D2 e 2X E2 6 4 A C SEATING PLANE 6X SOLDERMASK DEFINED MOUNTING FOOTPRINT* 2.30 6X 0.35 4X 0.43 1 0.65 PITCH b 6X 0.25 B 2X 6X J 0.10 C A 0.05 C BOTTOM VIEW NOTE 3 0.72 1.05 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NTLJD4150P/D