NVD5407NT4G

NTD5407N, STD5407N, NVD5407N MOSFET – Power, Single, N-Channel, DPAK 40 V, 38 A www.onsemi.com Features • • • • • Low RDS(on) High Current Capability Low Gate Charge STD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable* These Devices are Pb−Free and are RoHS Compliant V(BR)DSS RDS(ON) TYP ID MAX (Note 1) 40 V 21 m @ 10 V 38 A N−Channel D 4 Applications 1 2 3 DPAK CASE 369C STYLE 2 • Electronic Brake Systems • Electronic Power Steering • Bridge Circuits G S MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS ±20 V ID 38 A Continuous Drain Current − RJC Steady State Power Dissipation − RJC Steady State TC = 25°C PD 75 W Continuous Drain Current RJA (Note 1) Steady State TA = 25°C ID 7.6 A Power Dissipation − RJA (Note 1) Steady State Pulsed Drain Current TC = 25°C TC = 100°C 27 TA = 100°C TA = 25°C tp = 10 s Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to Source Avalanche Energy − (VDD = 50 V, VGS = 10 V, IPK = 17 A, L = 1 mH, RG = 25 ) Lead Temperature for Soldering Purposes (1/8” from case for 10 s) 5.3 PD 2.9 W IDM 75 A TJ, TSTG −55 to 175 °C IS 36 A EAS 150 mJ TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 2014 June, 2019 − Rev. 7 1 MARKING DIAGRAM 1 A Y WW 5407N G AYWW 54 07NG = Assembly Location* = Year = Work Week = Specific Device Code = Pb−Free Device * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION Device Package Shipping† NTD5407NT4G DPAK (Pb−Free) 2500 / Tape & Reel STD5407NT4G* DPAK (Pb−Free) 2500 / Tape & Reel NVD5407NT4G* DPAK (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NTD5407N/D NTD5407N, STD5407N, NVD5407N THERMAL RESISTANCE RATINGS (Note 1) Parameter Symbol Max Unit Junction−to−Case (Drain) RθJC 2.0 °C/W Junction−to−Ambient (Note 1) RθJA 52 °C/W 1. Surface mounted on FR4 board using 1 sq in pad size, (Cu Area 1.127 sq in [2 oz] including traces). www.onsemi.com 2 NTD5407N, STD5407N, NVD5407N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise stated) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 A 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current V 39 IDSS VGS = 0 V, VDS = 40 V mV/°C TJ = 25°C 1.0 TJ = 100°C 10 IGSS VDS = 0 V, VGS = ±30 V VGS(TH) VGS = VDS, ID = 250 A ±100 A nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Gate Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ 1.5 3.5 −6.0 RDS(on) gFS V mV/°C VGS = 10 V, ID = 20 A 21 26 VGS = 5.0 V, ID = 10 A 32 40 VGS = 10 V, ID = 18 A 15 m S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Total Gate Charge 615 VGS = 0 V, f = 1.0 MHz, VDS = 32 V 173 VGS = 10 V, VDS = 32 V, ID = 38 A 2.25 QG(TOT) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 1000 pF 80 nC 20 10.5 SWITCHING CHARACTERISTICS, VGS = 10 V (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) ns 6.8 tr VGS = 10 V, VDD = 32 V, ID = 38 A, RG = 2.5  td(OFF) tf 17 66 51 SWITCHING CHARACTERISTICS, VGS = 5 V (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) ns 10 tr VGS = 5 V, VDD = 20 V, ID = 20 A, RG = 2.5  td(OFF) tf 175 13 23 DRAIN−SOURCE DIODE CHARACTERISTICS (Note 2) Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 5.0 A TJ = 25°C 0.9 TJ = 125°C 0.75 tRR ta tb 38 VGS = 0 V, dIS/dt = 100 A/s, IS = 15 A QRR 1.1 V ns 20.5 17 40 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: pulse width ≤ 300 s, duty cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 3 NTD5407N, STD5407N, NVD5407N TYPICAL PERFORMANCE CURVES VGS = 7 V to 10 V 60 TJ = 25°C VDS ≥ 10 V 6V 50 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 60 5.5 V 40 5V 30 4.5 V 20 4V 10 50 40 30 20 TJ = 100°C 10 TJ = 25°C 3.5 V 0 0 2 1 3 6 5 4 7 8 9 TJ = −55°C 0 10 0 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.08 ID = 38 A TJ = 25°C 0.07 0.06 0.05 0.04 0.03 0.02 0.01 3 5 4 6 7 8 9 10 11 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 12 0.105 0.085 0.075 0.065 VGS = 5 V 0.055 0.045 0.035 VGS = 10 V 0.025 0.015 0.005 10 20 15 10000 ID = 20 A VGS = 10 V 1.2 1 VGS = 0 V 1000 100 10 TJ = 100°C 0.8 0 40 TJ = 175°C 1.4 −25 35 30 Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.6 0.6 −50 25 ID, DRAIN CURRENT (AMPS) IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.8 TJ = 25°C 0.095 Figure 3. On−Resistance vs. Gate−to−Source Voltage 2 8 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE () RDS(on), DRAIN−TO−SOURCE RESISTANCE () Figure 1. On−Region Characteristics 3 5 6 7 1 2 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 25 50 75 100 125 150 175 1 5 10 15 20 25 30 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 4 40 NTD5407N, STD5407N, NVD5407N TYPICAL PERFORMANCE CURVES VGS = 0 V TJ = 25°C VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) VDS = 0 V Ciss 1200 Crss Ciss 600 Coss 0 10 Crss 5 VGS 0 VDS 5 15 10 20 25 30 15 35 12 28 QT 9 VDS 6 QGS 0 ID = 36 A TJ = 25°C 0 IS, SOURCE CURRENT (AMPS) 100 tr td(on) 10 1 1 10 RG, GATE RESISTANCE (OHMS) 100 15 14 VGS = 0 V 13 TJ = 25°C 12 11 10 9 8 7 6 5 4 3 2 1 0 0.3 0.9 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance VGS = 10 V SINGLE PULSE TC = 25°C 100 10 s 100 s 10 1 ms 10 ms dc 1 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0 20 1.2 Figure 10. Diode Forward Voltage vs. Current 1000 ID, DRAIN CURRENT (A) t, TIME (ns) td(off) tf 5 10 15 QG, TOTAL GATE CHARGE (nC) 7 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge Figure 7. Capacitance Variation 1000 21 14 QGD 3 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) VDS = 32 V ID = 38 A VGS = 10 V VGS 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area www.onsemi.com 5 V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1800 100 NTD5407N, STD5407N, NVD5407N r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE TYPICAL PERFORMANCE CURVES 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 P(pk) 0.01 SINGLE PULSE t1 t2 DUTY CYCLE, D = t1/t2 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) Figure 12. Thermal Response www.onsemi.com 6 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RJC(t) 0.1 1 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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