PIC24FJ128GL306 FAMILY
16-Bit eXtreme Low-Power Microcontrollers with
LCD Controller in Low Pin Count Packages
High-Performance CPU
Functional Safety and Security Peripherals
•
•
•
•
•
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• Power-on Reset (POR), Brown-out Reset (BOR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Programmable High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with
RC Oscillator for Reliable Operation
• Deadman Timer (DMT) for Monitoring Health
of Software
• Programmable 32-Bit Cyclic Redundancy Check
(CRC) Generator
• Flash OTP by ICSP™ Write Inhibit
• CodeGuard™ Security
• ECC Flash Memory (128 Kbytes) with Fault
Injection:
- Single Error Correction (SEC)
- Double Error Detection (DED)
• Customer OTP Memory
• Unique Device Identifier (UDID)
•
•
•
•
Modified Harvard Architecture
128 Kbytes Flash Memory
8 Kbytes SRAM
Up to 16 MIPS Operation @ 32 MHz
17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
32-Bit by 16-Bit Hardware Divider
16-Bit x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
Two Address Generation Units (AGUs) for Separate
Read and Write Addressing of Data Memory
LCD Display Controller
•
•
•
•
32x8 with Up to 256 Pixels
LCD Charge Pump
Core-Independent LCD Animation
Operation in Sleep mode
Analog Features
• Up to 17-Channel, Software-Selectable, 10/12-Bit
Analog-to-Digital Converter:
- 12-bit, 350K samples/second conversion rate
(single Sample-and-Hold)
- 10-bit, 400K samples/second conversion rate
(single Sample-and-Hold)
- Sleep mode operation
- Low-voltage boost for input
- Band gap reference input feature
- Core-independent windowed threshold
compare feature
- Auto-scan feature
• Three Analog Comparators with Input Multiplexing:
- Programmable reference voltage for comparators
eXtreme Low-Power Features
• Sleep and Idle modes Selectively Shut Down
Peripherals and/or Core for Substantial Power
Reduction and Fast Wake-up
• Doze mode Allows CPU to Run at a Lower Clock
Speed than Peripherals
• Alternate Clock modes Allow On-the-Fly
Switching to a Lower Clock Speed for Selective
Power Reduction
• Retention Sleep with On-Chip Ultra Low-Power
Retention Regulator
2019-2020 Microchip Technology Inc.
Special Microcontroller Features
• Supply Voltage Range of 2.0V to 3.6V
• Operating Ambient Temperature Range of
-40°C to +125°C
• On-Chip Voltage Regulators (1.8V) for
Low-Power Operation
• Flash Memory:
- 10,000 erase/write cycle endurance, typical
- Data retention: 20 years minimum
- Self-programmable under software control
- Flash OTP emulation
• 8 MHz Fast RC Internal Oscillator:
- Multiple clock divide options
- Fast start-up
• 96 MHz PLL Option
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via Two Pins
• JTAG Boundary Scan Support
DS30010198B-page 1
PIC24FJ128GL306 FAMILY
Peripheral Features
• Four UART modules:
- LIN/J2602 bus support (auto-wake-up,
Auto-Baud Detect, Break character support)
- RS-232 and RS-485 support
- IrDA® mode (hardware encoder/decoder
functions)
• Five External Interrupt Pins
• Hardware Real-Time Clock and Calendar (RTCC)
• Peripheral Pin Select (PPS) allows Independent
I/O Mapping of Many Peripherals
• Configurable Interrupt-on-Change on All I/O Pins:
- Each pin is independently configurable for
rising edge or falling edge change detection
• Reference Clock Output with Programmable
Divider
• Four Configurable Logic Cell (CLC) Blocks:
- Two inputs and one output, all mappable to
peripherals or I/O pins
- AND/OR/XOR logic and D/JK flip-flop
functions
• Independent, Low-Power 32 kHz Timer Oscillator
• Six-Channel DMA Controller:
- Minimizes CPU overhead and increases data
throughput
• Timer1: 16-Bit Timer/Counter with External Crystal
Oscillator; Timer1 can Provide an A/D Trigger
• Timer2,3,4,5: 16-Bit Timer/Counter can Create
32-Bit Timer; Timer3 and Timer5 can Provide an
A/D Trigger
• Five MCCP modules, Each with a Dedicated
16/32-Bit Timer:
- One 6-output MCCP module
- Four 2-output MCCP modules
• Two Variable Width, Serial Peripheral Interface (SPI)
Ports on All Devices; Three Operation modes:
- 3-wire SPI (supports all four SPI modes)
- Up to 32-byte deep FIFO buffer
- I2S mode
- Speed up to 25 MHz
• Two I2C Master and Slave w/Address Masking,
PMBus™ and IPMI Support
Qualification
• AEC-Q100 REVG (Grade 1: -40°C to +125°C)
Compliant
PIC24FJ128GL306 FAMILY DEVICES
Variable Width SPI
UART w/IrDA®
CLC
RTCC
6
I2C
32/33
16-Bit Timers
DMA Channels
54
MCCP 6-Output/2-Output
Remappable I/O (PPS)
(Output/Input)
64
CRC
GPIO
8K
Comparators
Pins
128K
10/12-Bit A/D Channels
SRAM
(bytes)
PIC24FJ128GL306
Program
(bytes)
Device
17
3
Yes
1/4
5
2
2
4
4
Yes
LCD Pixels
Peripherals
Memory
JTAG
TABLE 1:
Yes
256
PIC24FJ128GL305
128K
8K
48
39
24/25
6
12
3
Yes
1/4
5
2
2
4
4
Yes
Yes
152
PIC24FJ128GL303
128K
8K
36
29
15/16
6
11
3
Yes
1/4
5
2
2
4
4
Yes
Yes
80
PIC24FJ128GL302
128K
8K
28
21
13/14
6
9
3
Yes
1/4
5
2
2
4
4
Yes
Yes
42
PIC24FJ64GL306
64K
8K
64
54
32/33
6
17
3
Yes
1/4
5
2
2
4
4
Yes
Yes
256
PIC24FJ64GL305
64K
8K
48
39
24/25
6
12
3
Yes
1/4
5
2
2
4
4
Yes
Yes
152
PIC24FJ64GL303
64K
8K
36
29
15/16
6
11
3
Yes
1/4
5
2
2
4
4
Yes
Yes
80
PIC24FJ64GL302
64K
8K
28
21
13/14
6
9
3
Yes
1/4
5
2
2
4
4
Yes
Yes
42
DS30010198B-page 2
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams
VCAP
RF1
VSS
RE2
RE1
RE0
RE3
28-Pin QFN/UQFN
28 27 26 25 24 23 22
RG7
1
RG8
MCLR
RB5
2
21
20
19
3
4
RB4
5
RB1
RB0
6
7
PIC24FJXXXGL302
18
17
16
15
RC14
RC13
VSS
RC15(4)
RC12
VDD
RG3
Note 1:
2:
3:
4:
TABLE 2:
RB14
RB15
RB7
AVDD/VDD
AVss/Vss
RB10(3)
RB6
8 9 10 11 12 13 14
See Table 2 for a complete description of pin functions.
Shaded pins are up to 5.5 VDC tolerant.
There is an internal pull-up resistor connected to the TMS pin during POR and programming.
RC15/OSCO will toggle during programming or debugging time.
28-PIN QFN/UQFN COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
VLCAP1/C1INC/C2INC/C3INC/RP26/RG7
15 TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3
2
VLCAP2/C2IND/RP19/RG8
16 VDD
17 OSCI/CLKI/RC12
3
MCLR
4
PGC3/SEG2/AN5/C1INA/RP18/ASCL1(1)/OCM1A/RB5
18 OSCO/CLKO/RC15
5
PGD3/SEG3/AN4/C1INB/RP28/ASDA1(1)/OCM1B/RB4
19 VSS
6
PGC1/SEG6/CVREF-/AN1/AN1-/C2INA/RP1/RB1
20 SOSCI/RC13
7
PGD1/SEG7/VREF+/CVREF+/AN0/C2INB/RP0/RB0
21 SOSCO/SCLKI/RPI37/PWRLCLK/RC14
8
PGC2/LCDBIAS3/AN6/RP6/RB6
22 VCAP
9
PGD2/AN7/RP7/T1CK/RB7
23 VSS
10 AVDD/VDD
24 COM4/SEG48/RP2/SCL1/OCM1E/RF1
11 AVSS/VSS
25 COM3/RE0
12 TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
26 COM2/C3INA/RE1
13 TCK/SEG8/AN14/RP14/SDA2/OCM1C/RB14
27 COM1/C3IND/RE2
14 TDI/SEG9/AN15/RP29/SCL2/OCM1D/RB15
28 COM0/HLVDIN/RE3
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
2019-2020 Microchip Technology Inc.
DS30010198B-page 3
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
RF1
RE0
RE1
RE2
RE3
RG7
RG8
MCLR
RB5
RB4
RB1
RB0
RB6
RB7
Note 1:
2:
3:
4:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC24FJXXXGL302
28-Pin SOIC/SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
VCAP
RC14
RC13
VSS
RC15(4)
RC12
VDD
RG3
RB15
RB14
RB10(3)
AVSS/VSS
AVDD/VDD
See Table 3 for a complete description of pin functions.
Shaded pins are up to 5.5 VDC tolerant.
There is an internal pull-up resistor connected to the TMS pin during POR and programming.
RC15/OSCO will toggle during programming or debugging time.
TABLE 3:
28-PIN SOIC/SSOP COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
COM4/SEG48/RP2/SCL1/OCM1E/RF1
15
AVDD/VDD
2
COM3/RE0
16
AVSS/VSS
3
COM2/C3INA/RE1
17
TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
4
COM1/C3IND/RE2
18
TCK/SEG8/AN14/RP14/SDA2/OCM1C/RB14
5
COM0/HLVDIN/RE3
19
TDI/SEG9/AN15/RP29/SCL2/OCM1D/RB15
6
VLCAP1/C1INC/C2INC/C3INC/RP26/RG7
20
TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3
VDD
7
VLCAP2/C2IND/RP19/RG8
21
8
MCLR
22
OSCI/CLKI/RC12
9
PGC3/SEG2/AN5/C1INA/RP18/ASCL1(1)/OCM1A/RB5
23
OSCO/CLKO/RC15
10
PGD3/SEG3/AN4/C1INB/RP28/ASDA1(1)/OCM1B/RB4
24
VSS
11
PGC1/SEG6/CVREF-/AN1/AN1-/C2INA/RP1/RB1
25
SOSCI/RC13
12
PGD1/SEG7/VREF+/CVREF+/AN0/C2INB/RP0/RB0
26
SOSCO/SCLKI/RPI37/PWRLCLK/RC14
13
PGC2/LCDBIAS3/AN6/RP6/RB6
27
VCAP
14
PGD2/AN7/RP7/T1CK/RB7
28
VSS
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
DS30010198B-page 4
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
Note 1:
2:
3:
4:
RE3
RE2
RE1
RE0
RF1
VSS
VCAP
RD7
RD6
36
35
34
33
32
31
30
29
28
36-Pin UQFN
RE5
1
27
RC14
RE6
2
26
RC13
RE7
3
25
Vss
RG7
4
24
RC15(4)
RG8
5
23
RC12
MCLR
6
22
VDD
RB5
7
21
RG2
RB4
8
20
RG3
RB1
9
19
RB15
12
13
14
15
16
17
18
RB7
AVSS/VSS
RB8
RB9
RB10(3)
RB14
11
RB6
AVDD/VDD
10
RB0
PIC24FJXXXGL303
See Table 4 for a complete description of pin functions.
Shaded pins are up to 5.5 VDC tolerant.
There is an internal pull-up resistor connected to the TMS pin during POR and programming.
RC15/OSCO will toggle during programming or debugging time.
2019-2020 Microchip Technology Inc.
DS30010198B-page 5
PIC24FJ128GL306 FAMILY
TABLE 4:
36-PIN UQFN COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
LCDBIAS2/RE5
19
2
LCDBIAS1/RE6
20
TDI/SEG9/AN15/RP29/SCL2/OCM1D/RB15
TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3
3
LCDBIAS0/RE7
21
SEG28/SCL1/RG2
4
VLCAP1/C1INC/C2INC/C3INC/RP26/RG7
22
VDD
5
VLCAP2/C2IND/RP19/RG8
23
OSCI/CLKI/RC12
6
MCLR
24
OSCO/CLKO/RC15
7
PGC3/SEG2/AN5/C1INA/RP18/ASCL1(1)/OCM1A/RB5
25
VSS
8
PGD3/SEG3/AN4/C1INB/RP28/ASDA1(1)/OCM1B/RB4
26
SOSCI/RC13
9
PGC1/SEG6/CVREF-/AN1/AN1-/C2INA/RP1/RB1
27
SOSCO/SCLKI/RPI37/PWRLCLK/RC14
10
PGD1/SEG7/VREF+//CVREF+/AN0/C2INB/RP0/RB0
28
SEG25/C3INB/RD6
11
PGC2/LCDBIAS3/AN6/RP6/RB6
29
SEG26/C3INA/RD7
12
PGD2/AN7/RP7/T1CK/RB7
30
VCAP
13
AVDD/VDD
31
VSS
14
AVSS/VSS
32
COM4/SEG48/RP2/OCM1E/RF1
15
COM7/SEG31/AN8/RP8/RB8
33
COM3/RE0
16
COM6/SEG30/AN9/RP9/RB9
34
COM2/RE1
17
TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
35
COM1/C3IND/RE2
18
TCK/SEG8/AN14/RP14/SDA2/OCM1C/RB14
36
COM0/HLVDIN/RE3
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
DS30010198B-page 6
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
RD3
RD4
RD5
RD6
RD7
VCAP
VSS
RF1
RE0
RE1
RE2
RE3
48-Pin TQFP/UQFN
48 47 46 45 44 43 42 41 40 39 38 37
RE5
1
36
RC14
RE6
2
35
RC13
RE7
3
34
RD0
RG7
4
33
RD11
RG8
5
32
RD10
MCLR
6
31
VSS
VSS
7
30
RC15(4)
VDD
8
29
RC12
RB5
9
28
VDD
RB4
10
27
RG2
RB1
11
26
RG3
RB0
12
25
RF3
PIC24FJXXXGL305
Note 1:
2:
3:
4:
RF5
RF4
RB15
RB14
RB11
RB9
RB10(3)
RB8
AVss
AVDD
RB7
RB6
13 14 15 16 17 18 19 20 21 22 23 24
See Table 5 for a complete description of pin functions.
Shaded pins are up to 5.5 VDC tolerant.
There is an internal pull-up resistor connected to the TMS pin during POR and programming.
RC15/OSCO will toggle during programming or debugging time.
2019-2020 Microchip Technology Inc.
DS30010198B-page 7
PIC24FJ128GL306 FAMILY
TABLE 5:
48-PIN TQFP/UQFN COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
LCDBIAS2/RE5
25
SEG12/RP16/RF3
2
LCDBIAS1/RE6
26
SEG47/RP31/SDA1/OCM1F/INT0/RG3
3
LCDBIAS0/RE7
27
SEG28/SCL1/RG2
4
VLCAP1/C1INC/C2INC/C3INC(2)/RP26/RG7
28
VDD
5
VLCAP2/AN19/C2IND/RP19/RG8
29
OSCI/CLKI/RC12
6
MCLR
30
OSCO/CLKO/RC15
7
VSS
31
VSS
8
VDD
32
SEG15/C3IND/RP3/RD10
9
PGC3/SEG2/AN5/C1INA/RP18/SCL1(1)/OCM1A/RB5
33
SEG16/C3INC/RP12/RD11
10 PGD3/SEG3/AN4/C1INB/RP28/SDA1(1)/OCM1B/RB4
34
SEG17/RP11/RD0
11
PGC1/SEG6/CVREF-/AN1/AN1-/C2INA/RP1/RB1
35
SOSCI/RC13
12 PGD1/SEG7/VREF+/CVREF+/AN0/C2INB/RP0/RB0
36
SOSCO/SCLKI/RPI37/PWRLCLK/RC14
13 PGC2/LCDBIAS3/AN6/C1IND/RP6/RB6
37
SEG22/RP22/RD3
14 PGD2/AN7/RP7/T1CK/RB7
38
SEG23/RP25/RD4
15 AVDD
39
SEG24/RP20/RD5
SEG25/C3INB/RD6
16 AVSS
40
17 COM7/SEG31/AN8/RP8/RB8
41
SEG26/C3INA/RD7
18 COM6/SEG30/AN9/RP9/RB9
42
VCAP
19 TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
43
VSS
20 TDO/AN11/RB11
44
COM4/SEG48/RP2/OCM1E/RF1
21 TCK/SEG8/AN14/RP14/OCM1C/RB14
45
COM3/RE0
22 TDI/SEG9/AN15/RP29/OCM1D/RB15
46
COM2/RE1
23 SEG10/RP10/SDA2/RF4
47
COM1/RE2
24 SEG11/RP17/SCL2/RF5
48
COM0/HLVDIN/RE3
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
2: Alternate pin assignments for C3INC as determined by the ALTCMPI Configuration bit.
DS30010198B-page 8
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RE4
RE3
RE2
RE1
RE0
RF1
RF0
RA0
VCAP
RD7
RD6
RD5
RD4
RD3
RD2
RD1
64-Pin TQFP/QFN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24FJXXXGL306
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RC14
RC13
RD0
RD11
RD10
RD9
RD8
VSS
RC15(4)
RC12
VDD
RG2
RG3
RF6
RF2
RF3
RB6
RB7
AVDD
AVSS
RB8
RB9
RB10(3)
RB11
VSS
VDD
RB12
RB13
RB14
RB15
RF4
RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RE5
RE6
RE7
RG6
RG7
RG8
MCLR
RG9
VSS
VDD
RB5
RB4
RB3
RB2
RB1
RB0
Note 1:
2:
3:
4:
See Table 6 for a complete description of pin functions.
Shaded pins are up to 5.5 VDC tolerant.
There is an internal pull-up resistor connected to the TMS pin during POR and programming.
RC15/OSCO will toggle during programming or debugging time.
2019-2020 Microchip Technology Inc.
DS30010198B-page 9
PIC24FJ128GL306 FAMILY
TABLE 6:
64-PIN TQFP/QFN COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
1
Function
LCDBIAS2/RE5
Pin
Function
33
SEG12/RP16/RF3
SEG40/RP30/RF2
2
LCDBIAS1/RE6
34
3
LCDBIAS0/RE7
35
RP5/INT0/RF6
4
SEG0/C1IND/RP21/RG6
36
SEG47/RP31/SDA1/OCM1F/RG3
5
VLCAP1/C1INC/C2INC(2)/C3INC(2)/RP26/RG7
37
SEG28/SCL1/RG2
6
VLCAP2/C2IND/RP19/RG8
38
VDD
7
MCLR
39
OSCI/CLKI/RC12
8
SEG1/C2INC/RP27/RG9
40
OSCO/CLKO/RC15
9
VSS
41
VSS
10
VDD
42
SEG13/RP2/RD8
11
PGC3/SEG2/AN5/C1INA/RP18/ASCL1(1)/OCM1A/RB5
43
SEG14/RP4/RD9
12
PGD3/SEG3/AN4/C1INB/RP28/ASDA1(1)/OCM1B/RB4
44
SEG15/C3IND/RP3/RD10
13
SEG4/AN3/C2INA/RB3
45
SEG16/C3INC/RP12/RD11
14
SEG5/AN2/C2INB/RP13/RB2
46
SEG17/RP11/RD0
15
PGC1/SEG6/CVREF-/AN1/AN1-/RP1/RB1
47
SOSCI/RC13
SOSCO/SCLKI/RPI37/PWRLCLK/RC14
16
PGD1/SEG7/VREF+/CVREF+/AN0/RP0/RB0
48
17
PGC2/LCDBIAS3/AN6/RP6/RB6
49
SEG20/RP24/RD1
18
PGD2/AN7/RP7/T1CK/RB7
50
SEG21/RP23/RD2
19
AVDD
51
SEG22/RP22/RD3
20
AVSS
52
SEG23/RP25/RD4
21
COM7/SEG31/AN8/RP8/RB8
53
SEG24/RP20/RD5
22
COM6/SEG30/AN9/RP9/RB9
54
SEG25/C3INB/RD6
23
TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
55
SEG26/C3INA/RD7
24
TDO/AN11/RB11
56
VCAP
25
VSS
57
AN16/RA0
26
VDD
58
SEG27/RF0
27
TCK/SEG18/AN12/RB12
59
COM4/SEG48/OCM1E/RF1
28
TDI/SEG19/AN13/RB13
60
COM3/RE0
29
SEG8/AN14/RP14/OCM1C/RB14
61
COM2/RE1
30
SEG9/AN15/RP29/OCM1D/RB15
62
COM1/RE2
31
SEG10/RP10/SDA2/RF4
63
COM0/RE3
32
SEG11/RP17/SCL2/RF5
64
SEG63/HLVDIN/RE4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
2: Alternate pin assignments for C2INC and C3INC as determined by the ALTCMPI Configuration bit.
DS30010198B-page 10
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 21
3.0 CPU............................................................................................................................................................................................ 27
4.0 Memory Organization ................................................................................................................................................................. 33
5.0 Direct Memory Access Controller (DMA) ................................................................................................................................... 53
6.0 Flash Program Memory.............................................................................................................................................................. 61
7.0 Resets ........................................................................................................................................................................................ 75
8.0 Interrupt Controller ..................................................................................................................................................................... 81
9.0 Oscillator Configuration .............................................................................................................................................................. 95
10.0 Power-Saving Features............................................................................................................................................................ 113
11.0 I/O Ports ................................................................................................................................................................................... 125
12.0 Timer1 ...................................................................................................................................................................................... 157
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................. 159
14.0 Capture/Compare/PWM/Timer Modules (MCCP) .................................................................................................................... 165
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 181
16.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 201
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 209
18.0 Liquid Crystal Display (LCD) Controller.................................................................................................................................... 219
19.0 Real-Time Clock and Calendar (RTCC) with Timestamp......................................................................................................... 235
20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 255
21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 261
22.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 271
23.0 Triple Comparator Module........................................................................................................................................................ 289
24.0 Comparator Voltage Reference................................................................................................................................................ 295
25.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 297
26.0 Deadman Timer (DMT) ............................................................................................................................................................ 299
27.0 Special Features ...................................................................................................................................................................... 307
28.0 Instruction Set Summary .......................................................................................................................................................... 329
29.0 Development Support............................................................................................................................................................... 337
30.0 Electrical Characteristics .......................................................................................................................................................... 339
31.0 Packaging Information.............................................................................................................................................................. 381
Appendix A: Revision History............................................................................................................................................................. 411
Index ................................................................................................................................................................................................. 413
The Microchip Website ...................................................................................................................................................................... 419
Customer Change Notification Service .............................................................................................................................................. 419
Customer Support .............................................................................................................................................................................. 419
Product Identification System ............................................................................................................................................................ 421
2019-2020 Microchip Technology Inc.
DS30010198B-page 11
PIC24FJ128GL306 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS30010198B-page 12
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of the
PIC24FJ128GL306 product page of the
Microchip website (www.microchip.com) or
select a family reference manual section
from the following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“CPU with Extended Data Space (EDS)” (www.microchip.com/DS39732)
“Direct Memory Access Controller (DMA)” (www.microchip.com/DS30009742)
“PIC24F Flash Program Memory” (www.microchip.com/DS30009715)
“Data Memory with Extended Data Space (EDS)” (www.microchip.com/DS39733)
“Reset” (www.microchip.com/DS39712)
“Interrupts” (www.microchip.com/DS70000600)
“Oscillator” (www.microchip.com/DS39700)
“Power-Saving Features with Deep Sleep” (www.microchip.com/DS39727)
“I/O Ports with Peripheral Pin Select (PPS)” (www.microchip.com/DS30009711)
“Timers” (www.microchip.com/DS39704)
“Capture/Compare/PWM/Timer (MCCP and SCCP)” (www.microchip.com/DS30003035)
“Serial Peripheral Interface (SPI) with Audio Codec Support” (www.microchip.com/DS70005136)
“Inter-Integrated Circuit (I2C)” (www.microchip.com/DS70000195)
“Universal Asynchronous Receiver Transmitter (UART)” (www.microchip.com/DS70000582)
“RTCC with Timestamp” (www.microchip.com/DS70005193)
“32-Bit Programmable Cyclic Redundancy Check (CRC)” (www.microchip.com/DS30009729)
“Configurable Logic Cell (CLC)” (www.microchip.com/DS70005298)
“12-Bit A/D Converter with Threshold Detect” (www.microchip.com/DS39739)
“Scalable Comparator Module” (www.microchip.com/DS39734)
“Dual Comparator Module” (www.microchip.com/DS39710)
“High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (www.microchip.com/DS39725)
“Watchdog Timer (WDT)” (www.microchip.com/DS39697)
“CodeGuard™ Intermediate Security” (www.microchip.com/DS70005182)
“High-Level Device Integration” (www.microchip.com/DS39719)
“Programming and Diagnostics” (www.microchip.com/DS39716)
“Comparator Voltage Reference Module” (www.microchip.com/DS39709)
“Deadman Timer” (www.microchip.com/DS70005155)
“Liquid Crystal Display (LCD)” (www.microchip.com/DS30009740)
2019-2020 Microchip Technology Inc.
DS30010198B-page 13
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 14
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ128GL306
• PIC24FJ64GL306
• PIC24FJ128GL305
• PIC24FJ64GL305
• PIC24FJ128GL303
• PIC24FJ64GL303
• PIC24FJ128GL302
• PIC24FJ64GL302
The PIC24FJ128GL306 family introduces eXtreme
low-power microcontrollers with LCD controller in low pin
count packages. This is a 16-bit microcontroller family
with a broad peripheral feature set and enhanced
computational performance. This family also offers a
new migration option for those high-performance
applications which may be outgrowing their 8-bit
platforms, but do not require the numerical processing
power of a Digital Signal Processor (DSP).
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
1.1
1.1.1
Core Features
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements,
such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes
(program space) and 32 Kbytes (data)
• A 16-element Working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2
POWER-SAVING TECHNOLOGY
This new low-power mode also supports the continuous
operation of the low-power, on-chip Real-Time Clock/
Calendar (RTCC), making it possible for an application
to keep time while the device is otherwise asleep.
Aside from this new feature, PIC24FJ128GL306 family
devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
of a lower power clock during run time
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of the Idle and Sleep modes
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ128GL306 family offer
six different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes
• External Clock (EC) mode
• A Phase-Locked Loop (PLL) frequency multiplier,
which allows processor speeds up to 32 MHz
• An internal Fast RC Oscillator (FRC), a nominal
8 MHz output with multiple frequency divider options
• A separate internal Low-Power RC Oscillator
(LPRC), 32 kHz nominal for low-power,
timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor (FSCM).
This option constantly monitors the main clock source
against a reference signal provided by the internal oscillator and enables the controller to switch to the internal
oscillator, allowing for continued low-speed operation
or a safe application shutdown.
1.1.4
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger device.
The PIC24FJ128GL306 family of devices includes
Retention Sleep, a low-power mode with essential
circuits being powered from a separate low-voltage
regulator.
2020 Microchip Technology Inc.
DS30010198B-page 15
PIC24FJ128GL306 FAMILY
1.2
DMA Controller
PIC24FJ128GL306 family devices have a Direct Memory
Access (DMA) Controller. This module acts in concert
with the CPU, allowing data to move between data
memory and peripherals without the intervention of the
CPU, increasing data throughput and decreasing execution time overhead. Six independently programmable
channels make it possible to service multiple peripherals
at virtually the same time, with each channel peripheral
performing a different operation. Many types of data
transfer operations are supported.
1.3
LCD Controller
The versatile on-chip LCD controller includes many
features that make the integration of displays in lowpower applications easier. These include an integrated
voltage regulator with charge pump and an integrated
internal resistor ladder that allows contrast control in
software, and display operation above the device VDD.
Core-independent automatic display features:
• Dual display memory
• Blink mode of individual pixels or the complete
pixels
• Blank of individual pixels or the complete pixels
• Timing schedule can be changed without core
intervention, based on user configurations
1.4
Other Special Features
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Configurable Logic Cell: The Configurable
Logic Cell (CLC) module allows the user to
specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins.
• Timing Modules: The PIC24FJ128GL306 family
provides five independent, general purpose, 16-bit
timers (four of which can be combined
into two 32-bit timers). The devices also include
five multiple output advanced
Capture/Compare/PWM/Timer peripherals.
DS30010198B-page 16
• Communications: The PIC24FJ128GL306 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I2C
modules that support both Master and Slave
modes of operation. Devices also have, through
the PPS feature, four independent UARTs with
built-in IrDA® encoders/decoders, LIN support and
two SPI modules.
• Analog Features: All members of the
PIC24FJ128GL306 family include a 12-bit A/D
Converter (A/D) module and a triple comparator
module. The A/D module incorporates a range of
new features that allow the converter to assess
and make decisions on incoming data, reducing
CPU overhead for routine A/D conversions. The
comparator module includes three analog
comparators that are configurable for a wide
range of operations.
• Real-Time Clock and Calendar (RTCC): This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
• Deadman Timer (DMT): This module is provided
to interrupt the processor in the event of a
software malfunction.
1.5
Details of Individual Family
Members
Devices in the PIC24FJ128GL306 family are available
in 28-pin, 36-pin, 48-pin and 64-pin packages. The
general block diagram for all devices is shown in
Figure 1-1.
A list of the pin features available on the
PIC24FJ128GL306 family devices, sorted by function,
is shown in Table 1-1. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the “Pin Diagrams” section in the beginning of this data sheet. Multiplexed features are sorted
by the priority given to a feature, with the highest
priority peripheral being listed first.
2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 1-1:
PIC24FJ128GL306 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
PORTA(1)
16
(1 I/O)
16
16
8
Data Latch
EDS and
Table Data
Access Control
23
Stack
Control
Logic
PORTB(1)
DMA
Controller
Data RAM
PCH
PCL
Program Counter
(16 I/Os)
Address
Latch
Repeat
Control
Logic
PORTC(1)
16
23
16
(4 I/Os)
16
Read AGU
Write AGU
Address Latch
Program Memory/
Extended Data
Space
PORTD(1)
(12 I/Os)
Data Latch
Address Bus
PORTE(1)
EA MUX
(8 I/Os)
24
16
Inst Latch
Inst Register
OSCO/CLKO
OSCI/CLKI
REFO
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Watchdog
Timer
Voltage
Regulators
HLVD and
BOR(2)
Timer1
VDD, VSS
(7 I/Os)
DMA
Data Bus
PORTG(1)
(6 I/Os)
16
Divide
Support
16 x 16
W Reg Array
17x17
Multiplier
16-Bit ALU
16
MCLR
Timer2/3(3)
and 4/5
DMT
Note 1:
2:
3:
PORTF(1)
Power-on
Reset
VCAP
MCCP
1/4
Literal
Data
Instruction
Decode and
Control
Control Signals
SOSCO/SOSCI
16
IOCs(1)
RTCC
12-Bit
A/D
Comparators(3)
CLC1-4(1)
SPI
1-2(3)
I2C1-2
UART
1-4(3)
LCD
Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count.
Some peripheral I/Os are only accessible through remappable pins.
These peripheral I/Os are only accessible through remappable pins.
2020 Microchip Technology Inc.
DS30010198B-page 17
PIC24FJ128GL306 FAMILY
TABLE 1-1:
PIC24FJ128GL306 FAMILY PINOUT DESCRIPTION
Pin
Type
Buffer Type
PPS
AN0-AN16
I
Analog
No
A/D Analog Inputs
AVDD
P
—
No
Positive Supply for Analog Modules
AVSS
P
—
No
Ground Reference for Analog Modules
C1INA-C1IND
C1OUT
I
O
Analog
DIG
No Comparator 1 Inputs A through D
Yes Comparator 1 Output
C2INA-C2IND
C2OUT
I
O
Analog
DIG
No Comparator 2 Inputs A through D
Yes Comparator 2 Output
C3INA-C3IND
C3OUT
I
O
Analog
DIG
No Comparator 3 Inputs A through D
Yes Comparator 3 Output
CLKI
CLKO
—
O
—
DIG
No
No
Main Clock Input Connection
System Clock Output
COM0-COM7
LCDBIAS0-LCDBIAS3
VLCAP1
VLCAP2
SEG0-SEG31
SEG40
SEG47
SEG48
SEG63
O
O
O
O
O
O
O
O
O
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
No
No
No
No
No
No
No
No
No
LCD Driver Common Outputs 0 through 7
Bias Inputs 0 through 3 for LCD Driver Charge Pump
LCD Drive Charge Pump Capacitor Input 1
LCD Drive Charge Pump Capacitor Input 2
LCD Driver Segment Outputs 0 through 31
LCD Driver Segment Output 40
LCD Driver Segment Output 47
LCD Driver Segment Output 48
LCD Driver Segment Output 63
CVREF
O
Analog
No
Comparator Voltage Reference Output
CVREF+
I
Analog
No
Comparator Voltage Reference (high) Input
CVREF-
I
Analog
No
Comparator Voltage Reference (low) Input
INT0
INT1-INT4
I
I
ST
ST
HLVDIN
I
Analog
No
High/Low-Voltage Detect Input
MCLR
I
ST
No
Master Clear (device Reset) Input
This line is brought low to cause a Reset.
ICM1-ICM5
TCKIA-TCKIB
OCFA-OCFB
OCM1A-OCM1F
OCM2A-OCM2B
OCM3A-OCM3B
OCM4A-OCM4B
OCM5A-OCM5B
I
I
I
O
O
O
O
O
ST
ST
ST
DIG
DIG
DIG
DIG
DIG
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
MCCP Capture Inputs 1 through 5
MCCP Timer Clock Inputs A through B
MCCP Fault Inputs A through B
MCCP1 Outputs A through F
MCCP2 Outputs A through B
MCCP3 Outputs A through B
MCCP4 Outputs A through B
MCCP5 Outputs A through B
CLCINA-CLCIND
CLC1OUT-CLC4OUT
I
O
ST
DIG
Yes CLC Inputs A through D
Yes CLC Outputs 1 through 4
OSCI
OSCO
I
O
Analog/ST
REFO
REFI
O
I
—
ST
Pin Name
Legend: TTL = TTL input buffer
I2C = I2C/SMBus input buffer
DS30010198B-page 18
Description
No External Interrupt Input 0
Yes External Interrupt Inputs 1 through 4
No
Main Oscillator Input Connection
Main Oscillator Output Connection
Yes Reference Clock Output
Yes Reference Clock Input
ST = Schmitt Trigger input buffer
Analog = Analog level input/output
DIG = Digital input/output
SMB3 = SMBus Version 3
2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 1-1:
PIC24FJ128GL306 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin
Type
Buffer Type
PPS
PGC1
PGD1
PGC2
PGD2
PGC3
PGD3
I
I/O
I
I/O
I
I/O
ST
DIG/ST
ST
DIG/ST
ST
DIG/ST
No
No
No
No
No
No
ICSP™ Programming Clock 1
ICSP Programming Data 1
ICSP Programming Clock 2
ICSP Programming Data 2
ICSP Programming Clock 3
ICSP Programming Data 3
PWRLCLK
TMPRN
PWRGT
RTCC
I
I
O
O
ST
ST
DIG
DIG
No
Yes
Yes
Yes
Real-Time Clock 50/60 Hz Clock Input
Tamper Detect
RTCC Power Control
RTCC Clock Output
RA0
I/O
DIG/ST
No
PORTA Digital I/O
Pin Name
Description
RB0-RB15
I/O
DIG/ST
No
PORTB Digital I/Os
RC12-RC15
I/O
DIG/ST
No
PORTC Digital I/Os
RD0-RD11
I/O
DIG/ST
No
PORTD Digital I/Os
RE0-RE7
I/O
DIG/ST
No
PORTE Digital I/Os
RF0-RF6
I/O
DIG/ST
No
PORTF Digital I/Os
RG2-RG3, RG6-RG9
I/O
DIG/ST
No
PORTG Digital I/Os
RP0-RP31
I/O
DIG/ST
No
Remappable Peripherals (input or output)
RPI37
I
ST
No
Remappable Peripheral (input only)
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
DIG
ST
Yes
Yes
Yes
Yes
Synchronous Serial Clock Input/Output for SPI1
SPI1 Data In
SPI1 Data Out
SPI1 Slave Synchronization or Frame Pulse I/O
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
ST
ST
DIG
ST
Yes
Yes
Yes
Yes
Synchronous Serial Clock Input/Output for SPI2
SPI2 Data In
SPI2 Data Out
SPI2 Slave Synchronization or Frame Pulse I/O
SCL1
SDA1
ASCL1
ASDA1
I/O
DIG/I2C/SMB3
No
I2C1 Synchronous Serial Clock Input/Output
I2C1 Data Input/Output
Alternate I2C1 Synchronous Serial Clock Input/Output
Alternate I2C1 Data Input/Output
SCL2
SDA2
I/O
DIG/I2C/SMB3
No
I2C2 Synchronous Serial Clock Input/Output
I2C2 Data Input/Output
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
DIG
ST
DIG
Yes
Yes
Yes
Yes
UART1 Clear-to-Send
UART1 Request-to-Send
UART1 Receive
UART1 Transmit
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
ST
DIG
ST
DIG
Yes
Yes
Yes
Yes
UART2 Clear-to-Send
UART2 Request-to-Send
UART2 Receive
UART2 Transmit
U3CTS
U3RTS
U3RX
U3TX
I
O
I
O
ST
DIG
ST
DIG
Yes
Yes
Yes
Yes
UART3 Clear-to-Send
UART3 Request-to-Send
UART3 Receive
UART3 Transmit
Legend: TTL = TTL input buffer
I2C = I2C/SMBus input buffer
2020 Microchip Technology Inc.
ST = Schmitt Trigger input buffer
Analog = Analog level input/output
DIG = Digital input/output
SMB3 = SMBus Version 3
DS30010198B-page 19
PIC24FJ128GL306 FAMILY
TABLE 1-1:
PIC24FJ128GL306 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin
Type
Buffer Type
PPS
U4CTS
U4RTS
U4RX
U4TX
I
O
I
O
ST
DIG
ST
DIG
Yes
Yes
Yes
Yes
UART4 Clear-to-Send
UART4 Request-to-Send
UART4 Receive
UART4 Transmit
SOSCI
SOSCO
SCLKI
—
—
I
—
—
ST
—
No
No
Secondary Oscillator/Timer1 Clock Input
Secondary Oscillator/Timer1 Clock Output
Secondary Clock Digital Input
T1CK
T2CK-T5CK
TxCK
I
I
I
ST
ST
ST
No Timer1 Clock
Yes Timer2 through Timer5 Clock
Yes Timer External Clock
TCK
TDI
TDO
TMS
I
I
O
I
ST
ST
DIG
ST
No
No
No
No
JTAG Test Clock/Programming Clock Input
JTAG Test Data/Programming Data Input
JTAG Test Data Output
JTAG Test Mode Select Input
VCAP
P
—
No
External Filter Capacitor Connection (regulator enabled)
VDD
P
—
No
Positive Supply for Peripheral Digital Logic and I/O Pins
VREF+
I
Analog
No
Comparator and A/D Reference Voltage (high) Input
VSS
P
—
No
Ground Reference for Peripheral Digital Logic and I/O Pins
Pin Name
Legend: TTL = TTL input buffer
I2C = I2C/SMBus input buffer
DS30010198B-page 20
Description
ST = Schmitt Trigger input buffer
Analog = Analog level input/output
DIG = Digital input/output
SMB3 = SMBus Version 3
2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• VCAP pin
(see Section 2.4 “Voltage Regulator Pin (VCAP)”)
VDD
VSS
R1
R2
VCAP(1)
MCLR
C1
C7
PIC24FJXXX
C6(2)
VSS
VDD
VDD
VSS
C3(2)
C4(2)
C5(2)
These pins must also be connected if they are being
used in the end application:
Key (all values are recommendations):
• PGCx/PGDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.4.2 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.5 “External Oscillator Pins”)
C7: 10 µF, 16V or greater, ceramic
Additionally, the following pins may be required:
• VREF+ pin used when external voltage reference
for analog modules is implemented
Note:
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
VSS
The following pins must always be connected:
C2(2)
VDD
Getting started with the PIC24FJ128GL306 family of
16-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
RECOMMENDED
MINIMUM CONNECTIONS
VDD
Basic Connection Requirements
FIGURE 2-1:
AVSS
2.1
GUIDELINES FOR GETTING
STARTED WITH
16-BIT MICROCONTROLLERS
AVDD
2.0
C1 through C6: 0.1 µF, 50V ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1:
2:
See Section 2.4 “Voltage Regulator Pin
(VCAP)” for an explanation of voltage
regulator pin connections.
The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
The minimum mandatory connections are shown in
Figure 2-1.
2019-2020 Microchip Technology Inc.
DS30010198B-page 21
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2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 µF (100 nF),
25V-50V capacitor is recommended. The capacitor
should be a low-ESR device with a self-resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic-type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 µF in parallel with 0.001 µF).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
BULK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a bulk
capacitance of 10 µF or greater located near the MCU.
The value of the capacitor should be determined based
on the trace resistance that connects the power supply
source to the device, and the maximum current drawn
by the device in the application. Typical values range
from 10 µF to 47 µF. The capacitor should be ceramic
and have a voltage rating of 25V or more to reduce DC
bias effects (see Section 2.4.1 “Considerations for
Ceramic Capacitors”).
DS30010198B-page 22
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions:
device Reset, and device programming and debugging. If programming and debugging are not required
in the end application, a direct connection to VDD
may be all that is required. The addition of other
components, to help increase the application’s
resistance to spurious Resets from voltage sags, may
be beneficial. A typical configuration is shown in
Figure 2-1. Other circuit designs may be implemented
depending on the application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The
jumper is replaced for normal run-time operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R1
R2
JP
MCLR
PIC24FJXXX
C1
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2:
R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of a MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
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PIC24FJ128GL306 FAMILY
2.4
Voltage Regulator Pin (VCAP)
Note:
FIGURE 2-3:
This section applies only to PIC24FJ
devices with an on-chip voltage regulator.
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
10
Refer to Section 27.3 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.
1
ESR ()
A low-ESR (< 5Ω) capacitor is required on the VCAP pin
to stabilize the voltage regulator output voltage. The
VCAP pin must not be connected to VDD and must use a
capacitor of 10 µF connected to ground. The type can be
ceramic or tantalum. Suitable examples of capacitors
are shown in Table 2-1. Capacitors with equivalent
specifications can be used.
0.1
0.01
0.001
Designers may use Figure 2-3 to evaluate the ESR
equivalence of candidate devices.
0.01
0.1
1
10
100
Frequency (MHz)
1000 10,000
Note: Typical data measurement at +25°C, 0V DC bias.
The placement of this capacitor should be close to VCAP.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 30.0 “Electrical
Characteristics” for additional information.
.
TABLE 2-1:
Make
SUITABLE CAPACITOR EQUIVALENTS (0805 CASE SIZE)
Part #
Nominal
Capacitance
Base Tolerance
Rated Voltage
TDK
C2012X5R1E106K085AC
10 µF
±10%
25V
TDK
C2012X5R1C106K085AC
10 µF
±10%
16V
Kemet
C0805C106M4PACTU
10 µF
±10%
16V
Murata
GRM21BR61E106KA3L
10 µF
±10%
25V
Murata
GRM21BR61C106KE15
10 µF
±10%
16V
2019-2020 Microchip Technology Inc.
DS30010198B-page 23
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CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
Typical low-cost, 10 µF ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance
specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R) or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit
will also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 µF nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very significant, but is often overlooked or is not always
documented.
A typical DC bias voltage vs. capacitance graph for
X7R type capacitors is shown in Figure 2-4.
FIGURE 2-4:
Capacitance Change (%)
2.4.1
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
10
0
-10
16V Capacitor
-20
-30
-40
10V Capacitor
-50
-60
-70
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC Bias Voltage (VDC)
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating so that the operating voltage is a
small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at
a minimum of 16V for the 1.8V core voltage. Suggested
capacitors are shown in Table 2-1.
2.4.2
ICSP PINS
The PGCx and PGDx pins are used for In-Circuit Serial
Programming (ICSP) and debugging purposes. It is
recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGCx and PGDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits, and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” pins (i.e., PGCx/PGDx) programmed
into the device match the physical connections for the
ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 29.0 “Development Support”.
DS30010198B-page 24
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PIC24FJ128GL306 FAMILY
2.5
External Oscillator Pins
FIGURE 2-5:
Many microcontrollers have options for at least two
oscillators: a high-frequency Primary Oscillator and
a low-frequency Secondary Oscillator (refer to
Section 9.0 “Oscillator Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be
placed next to the oscillator itself, on the same side of
the board.
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Single-Sided and In-Line Layouts:
Copper Pour
(tied to ground)
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate website
(www.microchip.com):
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
• AN1798, “Crystal Selection for Low-Power
Secondary Oscillator”
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
OSCI
C1
`
OSCO
GND
C2
`
SOSCO
SOSCI
Secondary
Oscillator
Crystal
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
`
Sec Oscillator: C1
Sec Oscillator: C2
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
OSCO
C2
Oscillator
Crystal
GND
C1
OSCI
DEVICE PINS
2019-2020 Microchip Technology Inc.
DS30010198B-page 25
PIC24FJ128GL306 FAMILY
2.6
Configuration of Analog and
Digital Pins During ICSP
Operations
If an ICSP compliant emulator is selected as a debugger,
it automatically initializes all of the A/D input pins (ANx)
as “digital” pins. This is done by clearing all bits in the
ANSELx registers. Refer to Section 11.2 “Configuring Analog Port Pins (ANSELx)” for more specific
information.
The bits in these registers that correspond to the A/D
pins that initialized the emulator must not be changed
by the user application firmware; otherwise, communication errors will result between the debugger and the
device.
When a Microchip debugger/emulator is used as a programmer, the user application firmware must correctly
configure the ANSELx registers. Automatic initialization of these registers is only done during debugger
operation. Failure to correctly configure the register(s)
will result in all A/D pins being recognized as analog
input pins, resulting in the port value being read as a
logic ‘0’, which may affect user application functionality.
2.7
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the A/D module, as follows:
• Set the bits corresponding to the pin(s) to be
configured as analog. Do not change any other
bits, particularly those corresponding to the
PGCx/PGDx pair, at any time.
DS30010198B-page 26
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PIC24FJ128GL306 FAMILY
3.0
Note:
CPU
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “CPU with Extended Data
Space (EDS)” (www.microchip.com/
DS39732) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in
this data sheet supersedes the information
in the FRM.
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEAT instructions, which are interruptible
at any point.
PIC24F devices have sixteen, 16-bit Working registers
in the programmer’s model. Each of the Working
registers can act as a Data, Address or Address Offset
register. The 16th Working register (W15) operates as
a Software Stack Pointer (SSP) for interrupts and calls.
The lower 32 Kbytes of the Data Space (DS) can be
accessed linearly. The upper 32 Kbytes of the Data
Space are referred to as Extended Data Space (EDS),
to which the extended data RAM, EPMP memory
space or program memory can be mapped.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibility.
All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
2019-2020 Microchip Technology Inc.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct Addressing modes along with
three groups of addressing modes. All modes support
Register Direct and various Register Indirect modes.
Each group offers up to seven addressing modes.
Instructions are associated with predefined addressing
modes depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a Working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing trinary operations (for example, A + B = C) to
be executed in a single cycle.
A high-speed, 17-bit x 17-bit multiplier has been included
to significantly enhance the core arithmetic capability and
throughput. The multiplier supports Signed, Unsigned
and Mixed mode, 16-bit x 16-bit or 8-bit x 8-bit, integer
multiplication. All multiply instructions execute in a single
cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or 16-bit),
divided by 16-bit, integer signed and unsigned division.
All divide operations require 19 cycles to complete but
are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up
to eight sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.
A block diagram of the CPU is shown in Figure 3-1.
3.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in
Figure 3-2. All registers in the programmer’s model are
memory-mapped and can be manipulated directly by
instructions.
A description of each register is provided in Table 3-1.
All registers associated with the programmer’s model
are memory-mapped.
DS30010198B-page 27
PIC24FJ128GL306 FAMILY
FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
EDS and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
8
16
16
Data Latch
23
Data RAM
Up to 0x7FFF
PCH
PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
16
Address
Latch
23
16
RAGU
WAGU
Address Latch
Program Memory/
Extended Data
Space
EA MUX
Address Bus
Data Latch
ROM Latch
24
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
Hardware
Multiplier
Divide
Support
16
Literal Data
16
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
TABLE 3-1:
CPU CORE REGISTERS
Register(s) Name
W0 through W15
PC
SR
SPLIM
TBLPAG
RCOUNT
CORCON
DISICNT
DSRPAG
DSWPAG
DS30010198B-page 28
Description
Working Register Array
23-Bit Program Counter
ALU STATUS Register
Stack Pointer Limit Value Register
Table Memory Page Address Register
REPEAT Loop Counter Register
CPU Control Register
Disable Interrupt Count Register
Data Space Read Page Register
Data Space Write Page Register
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PIC24FJ128GL306 FAMILY
FIGURE 3-2:
PROGRAMMER’S MODEL
15
Divider Working Registers
0
W0 (WREG)
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
Frame Pointer
W15
Stack Pointer
0
SPLIM
0
22
0
0
PC
7
0
TBLPAG
9
Program Counter
Table Memory Page
Address Register
0
Data Space Read Page Register
DSRPAG
8
0
Data Space Write Page Register
DSWPAG
15
0
RCOUNT
15
Stack Pointer Limit
Value Register
SRH
SRL
0
— — — — — — — DC 2 IPL
1 0 RA N OV Z C
0
15
— — — — — — — — — — — — IPL3 — — —
13
REPEAT Loop Counter
Register
ALU STATUS Register (SR)
CPU Control Register (CORCON)
0
DISICNT
Disable Interrupt Count Register
Registers or bits are shadowed for PUSH.S and POP.S instructions.
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DS30010198B-page 29
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3.2
CPU Control Registers
REGISTER 3-1:
SR: ALU STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DC
bit 15
bit 8
R/W-0(1)
IPL2
R/W-0(1)
(2)
(2)
IPL1
R/W-0(1)
IPL0
(2)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DC: ALU Half Carry/Borrow bit
1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL[2:0]: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3
N: ALU Negative bit
1 = Result was negative
0 = Result was not negative (zero or positive)
bit 2
OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1
Z: ALU Zero bit
1 = An operation, which affects the Z bit, has set it at some time in the past
0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result)
bit 0
C: ALU Carry/Borrow bit
1 = A carry out from the Most Significant bit (MSb) of the result occurred
0 = No carry out from the Most Significant bit of the result occurred
Note 1:
2:
The IPLx Status bits are read-only when NSTDIS (INTCON1[15]) = 1.
The IPLx Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt
Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
DS30010198B-page 30
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REGISTER 3-2:
CORCON: CPU CORE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
R/W-1
U-0
U-0
—
—
—
—
IPL3(1)
PSV(2)
—
—
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2
PSV: Program Space Visibility (PSV) in Data Space Enable bit(2)
1 = Program space is visible in Data Space
0 = Program space is not visible in Data Space
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level; see
Register 3-1 for bit description.
If PSV = 0, any reads from data memory at 0x8000 and above will cause an address trap error instead of
reading from the PSV section of program memory. This bit is not individually addressable.
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DS30010198B-page 31
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3.3
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
for 16-bit divisor division.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
•
•
•
•
•
•
•
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
TABLE 3-2:
3.3.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
•
•
•
•
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. The 16-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.3.3
MULTIBIT SHIFT SUPPORT
The PIC24F ALU supports both single-bit and singlecycle, multibit arithmetic and logic shifts. Multibit shifts
are implemented using a shifter block, capable of
performing up to a 15-bit arithmetic right shift, or up to
a 15-bit left shift, in a single cycle. All multibit shift
instructions only support Register Direct Addressing for
both the operand source and result destination.
A full summary of instructions that use the shift
operation is provided in Table 3-2.
INSTRUCTIONS THAT USE THE SINGLE-BIT AND MULTIBIT SHIFT OPERATION
Instruction
Description
ASR
Arithmetic Shift Right Source register by one or more bits.
SL
Shift Left Source register by one or more bits.
LSR
Logical Shift Right Source register by one or more bits.
DS30010198B-page 32
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
4.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive reference source. For more information, refer
to “PIC24F Flash Program Memory”
(www.microchip.com/DS30009715) in the
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory
spaces and buses. This architecture also allows direct
access of program memory from the Data Space (DS)
during code execution.
2019-2020 Microchip Technology Inc.
4.1
Program Memory Space
The program address memory space of the
PIC24FJ128GL306 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during program execution, or from table operation or Data Space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG[7] to permit access to
the Configuration bits and customer OTP sections of
the configuration memory space.
The memory map for the PIC24FJ128GL306 family of
devices is shown in Figure 4-1.
DS30010198B-page 33
PIC24FJ128GL306 FAMILY
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GL306 DEVICES
PIC24FJ64GL30X
PIC24FJ128GL30X
GOTO Instruction
Reset Address
GOTO Instruction
Reset Address
Interrupt Vector Table
Interrupt Vector Table
User Flash Program Memory
(22K Instructions)
User Flash Program Memory
(44K Instructions)
User Memory Space
Flash Config Words
000000h
000002h
000004h
0000FEh
000100h
00AFFEh
00B000h
Flash Config Words
015FFEh
016000h
Unimplemented
Read ‘0’
Configuration Memory Space
Unimplemented
Read ‘0’
7FFFFFh
800000h
Reserved
Reserved
Executive Code Memory
Executive Code Memory
Reserved
Reserved
OTP Memory
OTP Memory
Reserved
Reserved
Flash Write Latches
Flash Write Latches
Reserved
Reserved
DEVID (2)
Reserved
DEVID (2)
Reserved
800100h
800FFEh
801000h
8016FEh
801700h
8017FEh
801800h
F9FFFEh
FA0000h
FA00FEh
FA0100h
FEFFFEh
FF0000h
FF0004h
FFFFFFh
Legend: Memory areas are not shown to scale.
Note:
TABLE 4-1:
Exact boundary addresses are determined by the size of the implemented program memory (Table 4-1).
PROGRAM MEMORY SIZES AND BOUNDARIES(2)
Device
Program Memory
Upper Boundary
(Instruction Words)
Write Blocks(1)
Erase Blocks(1)
PIC24FJ128GL30X
015FFEh (45,056 x 24)
352
44
PIC24FJ64GL30X
00AFFEh (22,528 x 24)
176
22
Note 1:
2:
One Write Block = 128 Instruction Words; One Erase Block (Page) = 1024 Instruction Words.
To maintain integer page sizes, the memory sizes are not exactly half of each other.
DS30010198B-page 34
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
000000h and 000200h for hard-coded program execution vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the PC
on a device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
The PIC24FJ128GL306 devices can have up to two
Interrupt Vector Tables (IVT). The first is located from
addresses, 000004h to 0000FFh. The Alternate Interrupt Vector Table (AIVT) can be enabled by the AIVTDIS
Configuration bit if the Boot Segment (BS) is present. If
the user has configured a Boot Segment, the AIVT will
be located at the address: (BSLIM[12:0] – 1) x 0x800.
These vector tables allow each of the many device
interrupt sources to be handled by separate ISRs. A
more detailed discussion of the Interrupt Vector Tables is
provided in Section 8.1 “Interrupt Vector Table”.
2019-2020 Microchip Technology Inc.
4.1.3
CONFIGURATION BITS OVERVIEW
The Configuration bits are stored in the last page location of implemented program memory. These bits can be
set or cleared to select various device configurations.
There are two types of Configuration bits: system operation bits and code-protect bits. The system operation
bits determine the power-on settings for system-level
components, such as the oscillator and the Watchdog
Timer. The code-protect bits prevent program memory
from being read and written.
Refer to Section 27.0 “Special Features” for the full
Configuration register description for each specific
device.
4.1.4
CODE-PROTECT CONFIGURATION
BITS
The device implements intermediate security features
defined by the FSEC register. The Boot Segment (BS)
is the higher privileged segment and the General Segment (GS) is the lower privileged segment. The total
user code memory can be split into BS or GS. The size
of the segments is determined by the BSLIM[12:0] bits.
The relative location of the segments within user space
does not change, such that BS (if present) occupies the
memory area just after the Interrupt Vector Table (IVT)
and the GS occupies the space just after the BS (or if
the Alternate IVT is enabled, just after it).
The Configuration Segment (CS) is a small segment
(less than a page, typically just one row) within user
Flash address space. It contains all user configuration
data that are loaded by the NVM Controller during the
Reset sequence.
DS30010198B-page 35
PIC24FJ128GL306 FAMILY
4.2
Data Memory Space
Note:
The 16-bit wide data addresses in the data memory
space point to bytes within the Data Space (DS). This
gives a DS address range of 64 Kbytes or 32K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference source. For more information, refer
to “Data Memory with Extended Data
Space (EDS)” (www.microchip.com/
DS39733) in the “dsPIC33/PIC24 Family
Reference Manual”, . The information in
this data sheet supersedes the information
in the FRM.
The upper half of data memory address space (8000h to
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in
Section 4.2.5 “Extended Data Space (EDS)”.
4.2.1
The PIC24F core has a 16-bit wide data memory space,
addressable as a single linear range. The Data Space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The Data Space
memory map is shown in Figure 4-2.
FIGURE 4-2:
DATA SPACE WIDTH
The data memory space is organized in byteaddressable, 16-bit wide blocks. Data are aligned in
data memory and registers as 16-bit words, but all Data
Space EAs resolve to bytes. The Least Significant Bytes
(LSBs) of each word have even addresses, while the
Most Significant Bytes (MSBs) have odd addresses.
DATA SPACE MEMORY MAP FOR PIC24FJ128GL306 DEVICES
MSB
Address
0001h
07FFh
0801h
1FFFh
2001h
Lower 32 Kbytes
Data Space
MSB
LSB
SFR Space
8 Kbytes Data RAM
27FFh
2801h
LSB
Address
0000h
SFR
07FEh Space
0800h
1FFEh
2000h
Near
Data Space
27FEh
2800h
Unimplemented
7FFFh
8001h
7FFEh
8000h
EDS Window
Upper 32 Kbytes
Data Space
FFFFh
FFFEh
Note: Memory areas are not shown to scale.
DS30010198B-page 36
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCUs and
improve Data Space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recognizes
that Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel, byte-wide
entities with shared (word) address decode, but
separate write lines. Data byte writes only write to the
corresponding side of the array or register which
matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
LSB. The Most Significant Byte (MSB) is not modified.
2019-2020 Microchip Technology Inc.
A Sign-Extend (SE) instruction is provided to allow users
to translate 8-bit signed data to 16-bit signed values.
Alternatively, for 16-bit unsigned data, users can clear
the MSB of any W register by executing a Zero-Extend
(ZE) instruction on the appropriate address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3
NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the Data Space is addressable indirectly.
Additionally, the whole Data Space is addressable
using MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.
4.2.4
SPECIAL FUNCTION REGISTER
(SFR) SPACE
The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. Each implemented area indicates
a 32-byte region where at least one address is
implemented as an SFR. A complete list of implemented SFRs, including their addresses, is shown in
Table 4-2 through Table 4-9. These tables contain all
registers applicable to the PIC24FJ128GL306 family.
Not all registers are present on all device variants. Refer
to Table 1 for peripheral availability. Refer to Table 11-3
through Table 11-9 for detailed port availability for the
different package options.
DS30010198B-page 37
PIC24FJ128GL306 FAMILY
TABLE 4-2:
SFR MAP: 0000h BLOCK
Address(1)
All Resets(2)
WREG0
0000h
0000000000000000
IFS3
008Eh
000-00---00--00-
WREG1
0002h
0000000000000000
IFS4
0090h
-------0----0000
WREG2
0004h
0000000000000000
IFS5
0092h
00----000-00000-
WREG3
0006h
0000000000000000
IFS6
0094h
-0-000----000000
WREG4
0008h
0000000000000000
IFS7
0096h
----------0-----
WREG5
000Ah
0000000000000000
IEC0
0098h
000000000--00000
WREG6
000Ch
0000000000000000
IEC1
009Ah
00000--0-0-00000
WREG7
000Eh
0000000000000000
IEC2
009Ch
00-00------0--00
WREG8
0010h
0000000000000000
IEC3
009Eh
000-00---00--00-
WREG9
0012h
0000000000000000
IEC4
00A0h
-------0----0000
WREG10
0014h
0000000000000000
IEC5
00A2h
00----000-00000-
WREG11
0016h
0000000000000000
IEC6
00A4h
-0-000----000000
WREG12
0018h
0000000000000000
IEC7
00A6h
----------0-----
WREG13
001Ah
0000000000000000
IPC0
00A8h
-100-100-100-100
WREG14
001Ch
0000000000000000
IPC1
00AAh
-100---------100
WREG15
001Eh
0000100000000000
IPC2
00ACh
-100-100-100-100
SPLIM
0020h
xxxxxxxxxxxxxxxx
IPC3
00AEh
-100-100-100-100
PCL
002Eh
0000000000000000
IPC4
00B0h
-100-100-100-100
PCH
0030h
--------00000000
IPC5
00B2h
------100----100
DSRPAG
0032h
------0000000000
IPC6
00B4h
-100---------100
DSWPAG
0034h
-------000000000
IPC7
00B6h
-100-100-100-100
RCOUNT
0036h
xxxxxxxxxxxxxxxx
IPC8
00B8h
---------100-100
SR
0042h
-------000000000
IPC9
00BAh
-------------100
CORCON
0044h
------------01--
IPC10
00BCh
-100------------
DISICNT
0052h
--xxxxxxxxxxxxxx
IPC11
00BEh
-100-100-----100
TBLPAG
0054h
--------00000000
IPC12
00C0h
-----100-100----
IPC13
00C2h
-----100-100----
DMTCON
005Ch
0000000000000000
IPC14
00C4h
-100-100--------
DMTPRECLR
0060h
00000000--------
IPC15
00C6h
-100-100-100----
DMTCLR
0064h
0000000000000000
IPC16
00C8h
-100-100-100-100
DMTSTAT
0068h
0000000000000000
IPC17
00CAh
----------------
DMTCNTL
006Ch
0000000000000000
IPC18
00CCh
-------------100
DMTCNTH
006Eh
0000000000000000
IPC19
00CEh
----------------
DMTHOLDREG
0070h
0000000000000000
IPC20
00D0h
-100-100-100----
DMTPSCNTL
0074h
0000000000000000
IPC21
00D2h
-100-----100-100
DMTPSCNTH
0076h
0000000000000000
IPC22
00D4h
---------100-100
DMTPSINTVL
0078h
0000000000000000
IPC23
00D6h
-100-100--------
DMTPSINTVH
007Ah
0000000000000000
IPC24
00D8h
-100-100-100-100
IPC25
00DAh
---------100-100
Register
CPU Core
Register
Address(1)
All Resets(2)
Interrupt Controller (Continued)
Deadman Timer
Interrupt Controller
INTCON1
0080h
0----------0000-
IPC26
00DCh
-100-100--------
INTCON2
0082h
100----0---00000
IPC27
00DEh
-----100-----100
INTCON3
0084h
0000000000000000
IPC28
00E0h
----------------
INTCON4
0086h
--------------00
IPC29
00E2h
---------100----
IFS0
0088h
000000000--00000
INTTREG
00E4h
0-0-000000000000
IFS1
008Ah
00000--0-0-00000
IFS2
008Ch
00-00------0--00
Legend: x = unknown or indeterminate value; - = unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
DS30010198B-page 38
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 4-3:
Register
SFR MAP: 0100h BLOCK
Address(1)
All Resets(2)
Oscillator and Reset
Register
Address(1)
All Resets(2)
Timers (Continued)
OSCCON
0100h
-qqq-qqq00q00000
TMR2
0196h
0000000000000000
CLKDIV
0102h
0011000000q-----
TMR3HLD
0198h
0000000000000000
OSCTUN
0106h
0000000000000000
TMR3
019Ah
0000000000000000
OSCDIV
010Ch
-000000000000001
PR2
019Ch
1111111111111111
OSCFDIV
010Eh
000000000-------
PR3
019Eh
1111111111111111
RCON
0110h
0010--0000000011
T2CON
01A0h
0-0---xx-0000-0-
T3CON
01A2h
0-0---xx-000--0-
0114h
0-0-xxxx----0000
TMR4
01A4h
0000000000000000
TMR5HLD
01A6h
0000000000000000
01A8h
0000000000000000
HLVD
HLVDCON
CRC
CRCCON1
0158h
0-00000001x00---
TMR5
CRCCON2
015Ah
---00000---00000
PR4
01AAh
1111111111111111
CRCXORL
015Ch
000000000000000-
PR5
01ACh
1111111111111111
CRCXORH
015Eh
0000000000000000
T4CON
01AEh
0-0---xx-0000-0-
CRCDATL
0160h
xxxxxxxxxxxxxxxx
T5CON
01B0h
0-0---xx-000--0-
CRCDATH
0162h
xxxxxxxxxxxxxxxx
Real-Time Clock and Calendar (RTCC)
CRCWDATL
0164h
xxxxxxxxxxxxxxxx
RTCCON1L
01CCh
0---00000000---0
CRCWDATH
0166h
xxxxxxxxxxxxxxxx
RTCCON1H
01CEh
00--000000000000
RTCCON2L
01D0h
10000---0000--00
REFO
REFOCONL
0168h
0-000-00----0000
RTCCON2H
01D2h
0011111111111111
REFOCONH
016Ah
-000000000000000
RTCCON3L
01D4h
0000000000000000
RTCSTATL
01D8h
----------0-0000
PMD
PMD1
0178h
00000---00000--0
TIMEL
01DCh
-0000000--------
PMD2
017Ah
----------------
TIMEH
01DEh
--000000-0000000
PMD3
017Ch
-----00-0---0-0-
DATEL
01E0h
--000001-----110
PMD4
017Eh
------------000-
DATEH
01E2h
00000000---00001
PMD5
0180h
-----------xxxxx
ALMTIMEL
01E4h
-0000000--------
PMD6
0182h
---------------0
ALMTIMEH
01E6h
--000000-0000000
PMD7
0184h
----------00----
ALMDATEL
01E8h
--000001-----110
PMD8
0186h
------------00--
ALMDATEH
01EAh
00000000---00001
TSATIMEL
01ECh
-0000000--------
Timers
TMR1
0190h
0000000000000000
TSATIMEH
01EEh
--000000-0000000
PR1
0192h
1111111111111111
TSADATEL
01F0h
--000000-----000
T1CON
0194h
0-0---00-000-00-
TSADATEH
01F2h
00000000---00000
Legend: x = unknown or indeterminate value; - = unimplemented bits; q = value set by Configuration bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
2019-2020 Microchip Technology Inc.
DS30010198B-page 39
PIC24FJ128GL306 FAMILY
TABLE 4-4:
Register
SFR MAP: 0200h BLOCK
Address(1)
All Resets(2)
Register
Address(1)
All Resets(2)
Multiple Output Capture/Compare/PWM
Multiple Output Capture/Compare/PWM (Continued)
CCP1CON1L
026Ch
0000000000000000
CCP2RBL
02ACh
0000000000000000
CCP1CON1H
026Eh
0000000000000000
CCP2BUFL
02B0h
0000000000000000
CCP1CON2L
0270h
0000000000000000
CCP2BUFH
02B2h
0000000000000000
CCP1CON2H
0272h
0000000100000000
CCP3CON1L
02B4h
0000000000000000
CCP1CON3L
0274h
----------000000
CCP3CON1H
02B6h
0000000000000000
CCP1CON3H
0276h
0000000000000000
CCP3CON2L
02B8h
0000000000000000
CCP1STATL
0278h
0000000000000000
CCP3CON2H
02BAh
0000000100000000
CCP1TMRL
027Ch
0000000000000000
CCP3CON3L
02BCh
----------000000
CCP1TMRH
027Eh
0000000000000000
CCP3CON3H
02BEh
0000000000000000
CCP1PRL
0280h
1111111111111111
CCP3STATL
02C0h
0000000000000000
CCP1PRH
0282h
1111111111111111
CCP3TMRL
02C4h
0000000000000000
CCP1RAL
0284h
0000000000000000
CCP3TMRH
02C6h
0000000000000000
CCP1RBL
0288h
0000000000000000
CCP3PRL
02C8h
0000000000000000
CCP1BUFL
028Ch
0000000000000000
CCP3PRH
02CAh
0000000000000000
CCP1BUFH
028Eh
0000000000000000
CCP3RAL
02CCh
0000000000000000
CCP2CON1L
0290h
0000000000000000
CCP3RBL
02D0h
0000000000000000
CCP2CON1H
0292h
0000000000000000
CCP3BUFL
02D4h
0000000000000000
CCP2CON2L
0294h
0000000000000000
CCP3BUFH
02D6h
0000000000000000
CCP2CON2H
0296h
0000000100000000
Comparator
CCP2CON3L
0298h
----------000000
CMSTAT
02E6h
0----000-----000
CCP2CON3H
029Ah
0000000000000000
CVRCON
02E8h
-----00000000000
CCP2STATL
029Ch
0000000000000000
CM1CON
02EAh
000---0000-0--00
CCP2TMRL
02A0h
0000000000000000
CM2CON
02ECh
000---0000-0--00
CCP2TMRH
02A2h
0000000000000000
CM3CON
02EEh
000---0000-0--00
CCP2PRL
02A4h
0000000000000000
ANCFG
02F4h
-------------000
CCP2PRH
02A6h
0000000000000000
CCP2RAL
02A8h
0000000000000000
Legend: x = unknown or indeterminate value; - = unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
DS30010198B-page 40
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 4-5:
Register
SFR MAP: 0300h BLOCK
Address(1)
All Resets(2)
Register
Address(1)
All Resets(2)
Multiple Output Capture/Compare/PWM
UART
CCP4CON1L
0300h
0000000000000000
U1MODE
0398h
0-000-0000000000
CCP4CON1H
0302h
0000000000000000
U1STA
039Ah
0000000100010000
CCP4CON2L
0304h
0000000000000000
U1TXREG
039Ch
x------xxxxxxxxx
CCP4CON2H
0306h
0000000100000000
U1RXREG
039Eh
-------000000000
CCP4CON3L
0308h
----------000000
U1BRG
03A0h
0000000000000000
CCP4CON3H
030Ah
0000000000000000
U1ADMD
03A2h
0000000000000000
CCP4STATL
030Ch
0000000000000000
U2MODE
03AEh
0-000-0000000000
CCP4TMRL
0310h
0000000000000000
U2STA
03B0h
0000000100010000
CCP4TMRH
0312h
0000000000000000
U2TXREG
03B2h
x------xxxxxxxxx
CCP4PRL
0314h
0000000000000000
U2RXREG
03B4h
-------000000000
CCP4PRH
0316h
0000000000000000
U2BRG
03B6h
0000000000000000
CCP4RAL
0318h
0000000000000000
U2ADMD
03B8h
0000000000000000
CCP4RBL
031Ch
0000000000000000
U3MODE
03C4h
0-000-0000000000
CCP4BUFL
0320h
0000000000000000
U3STA
03C6h
0000000100010000
CCP4BUFH
0322h
0000000000000000
U3TXREG
03C8h
x------xxxxxxxxx
CCP5CON1L
0324h
0000000000000000
U3RXREG
03CAh
-------000000000
CCP5CON1H
0326h
0000000000000000
U3BRG
03CCh
0000000000000000
CCP5CON2L
0328h
0000000000000000
U3ADMD
03CEh
0000000000000000
CCP5CON2H
032Ah
0000000100000000
U4MODE
03D0h
0-000-0000000000
CCP5CON3L
032Ch
----------000000
U4STA
03D2h
0000000100010000
CCP5CON3H
032Eh
0000000000000000
U4TXREG
03D4h
x------xxxxxxxxx
CCP5STATL
0330h
0000000000000000
U4RXREG
03D6h
-------000000000
CCP5TMRL
0334h
0000000000000000
U4BRG
03D8h
0000000000000000
CCP5TMRH
0336h
0000000000000000
U4ADMD
03DAh
0000000000000000
CCP5PRL
0338h
0000000000000000
SPI
CCP5PRH
033Ah
0000000000000000
SPI1CON1L
03F4h
0-00000000000000
CCP5RAL
033Ch
0000000000000000
SPI1CON1H
03F6h
0000000000000000
CCP5RBL
0340h
0000000000000000
SPI1CON2L
03F8h
-----------00000
CCP5BUFL
0344h
0000000000000000
SPI1STATL
03FCh
---00--0001-1-00
CCP5BUFH
0346h
0000000000000000
SPI1STATH
03FEh
--000000--000000
Legend: x = unknown or indeterminate value; - = unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
2019-2020 Microchip Technology Inc.
DS30010198B-page 41
PIC24FJ128GL306 FAMILY
TABLE 4-6:
Register
SFR MAP: 0400h BLOCK
Address(1)
All Resets(2)
Register
Address(1)
All Resets(2)
I2C (Continued)
SPI (Continued)
SPI1BUFL
0400h
0000000000000000
I2C1CONL
049Ah
0-01000000000000
SPI1BUFH
0402h
0000000000000000
I2C1CONH
049Ch
---------0000000
SPI1BRGL
0404h
---xxxxxxxxxxxxx
I2C1STAT
049Eh
000--00000000000
SPI1IMSKL
0408h
---00--0000-0-00
I2C1ADD
04A0h
------0000000000
SPI1IMSKH
040Ah
0-0000000-000000
I2C1MSK
04A2h
------0000000000
SPI1URDTL
040Ch
0000000000000000
I2C2RCV
04A4h
--------00000000
SPI1URDTH
040Eh
0000000000000000
I2C2TRN
04A6h
--------11111111
SPI2CON1L
0410h
0-00000000000000
I2C2BRG
04A8h
0000000000000000
SPI2CON1H
0412h
0000000000000000
I2C2CONL
04AAh
0-01000000000000
SPI2CON2L
0414h
-----------00000
I2C2CONH
04ACh
---------0000000
SPI2STATL
0418h
---00--0001-1-00
I2C2STAT
04AEh
000--00000000000
SPI2STATH
041Ah
--000000--000000
I2C2ADD
04B0h
------0000000000
SPI2BUFL
041Ch
0000000000000000
I2C2MSK
04B2h
------0000000000
SPI2BUFH
041Eh
0000000000000000
DMA
SPI2BRGL
0420h
---xxxxxxxxxxxxx
DMACON
04C4h
0--------------0
SPI2IMSKL
0424h
---00--0000-0-00
DMABUF
04C6h
0000000000000000
SPI2IMSKH
0426h
0-0000000-000000
DMAL
04C8h
0000000000000000
SPI2URDTL
0428h
0000000000000000
DMAH
04CAh
0000000000000000
SPI2URDTH
042Ah
0000000000000000
DMACH0
04CCh
---0-00000000000
DMAINT0
04CEh
0000000000000--0
Configurable Logic Cell (CLC)
CLC1CONL
0464h
0---00--000--000
DMASRC0
04D0h
0000000000000000
CLC1CONH
0466h
------------0000
DMADST0
04D2h
0000000000000000
CLC1SEL
0468h
-000-000-000-000
DMACNT0
04D4h
0000000000000001
CLC1GLSL
046Ch
0000000000000000
DMACH1
04D6h
---0-00000000000
CLC1GLSH
046Eh
0000000000000000
DMAINT1
04D8h
0000000000000--0
CLC2CONL
0470h
0---00--000--000
DMASRC1
04DAh
0000000000000000
CLC2CONH
0472h
------------0000
DMADST1
04DCh
0000000000000000
CLC2SELL
0474h
-000-000-000-000
DMACNT1
04DEh
0000000000000001
CLC2GLSL
0478h
0000000000000000
DMACH2
04E0h
---0-00000000000
CLC2GLSH
047Ah
0000000000000000
DMAINT2
04E2h
0000000000000--0
CLC3CONL
047Ch
0---00--000--000
DMASRC2
04E4h
0000000000000000
CLC3CONH
047Eh
------------0000
DMADST2
04E6h
0000000000000000
CLC3SELL
0480h
-000-000-000-000
DMACNT2
04E8h
0000000000000001
CLC3GLSL
0484h
0000000000000000
DMACH3
04EAh
---0-00000000000
CLC3GLSH
0486h
0000000000000000
DMAINT3
04ECh
0000000000000--0
CLC4CONL
0488h
0---00--000--000
DMASRC3
04EEh
0000000000000000
CLC4CONH
048Ah
------------0000
DMADST3
04F0h
0000000000000000
CLC4SELL
048Ch
-000-000-000-000
DMACNT3
04F2h
0000000000000001
CLC4GLSL
0490h
0000000000000000
DMACH4
04F4h
---0-00000000000
CLC4GLSH
0492h
0000000000000000
I2C
DMAINT4
04F6h
0000000000000--0
DMASRC4
04F8h
0000000000000000
I2C1RCV
0494h
--------00000000
DMADST4
04FAh
0000000000000000
I2C1TRN
0496h
--------11111111
DMACNT4
04FCh
0000000000000001
I2C1BRG
0498h
0000000000000000
DMACH5
04FEh
---0-00000000000
Legend: x = unknown or indeterminate value; - = unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
DS30010198B-page 42
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 4-7:
SFR MAP: 0500h BLOCK
Address(1)
All Resets(2)
DMAINT5
0500h
0000000000000--0
LCDSE2
058Ah
xxxxxxxxxxxxxxxx
DMASRC5
0502h
0000000000000000
LCDSE3
058Ch
xxxxxxxxxxxxxxxx
Register
DMA (Continued)
Register
Address(1)
All Resets(2)
LCD (Continued)
DMADST5
0504h
0000000000000000
LCDREG
058Eh
0-------------00
DMACNT5
0506h
0000000000000001
LCDACTRL
0590h
0000000000000000
LCDASTAT
0592h
0000000000000000
LCDCON
0540h
0000000000000000
LCDFC0
0594h
0000000000000001
LCDREF
0542h
0000000000000000
LCDFC1
0596h
0000000000000001
LCDPS
0544h
0000000000000000
LCDFC2
0598h
0000000000000001
LCD
LCDDATA0
0546h
xxxxxxxxxxxxxxxx
LCDTEVNT
059Ah
0000000000000001
LCDDATA1
0548h
xxxxxxxxxxxxxxxx
LCDSDATA0
059Ch
xxxxxxxxxxxxxxxx
LCDDATA2
054Ah
xxxxxxxxxxxxxxxx
LCDSDATA1
059Eh
xxxxxxxxxxxxxxxx
LCDDATA3
054Ch
xxxxxxxxxxxxxxxx
LCDSDATA2
05A0h
xxxxxxxxxxxxxxxx
LCDDATA4
054Eh
xxxxxxxxxxxxxxxx
LCDSDATA3
05A2h
xxxxxxxxxxxxxxxx
LCDDATA5
0550h
xxxxxxxxxxxxxxxx
LCDSDATA4
05A4h
xxxxxxxxxxxxxxxx
LCDDATA6
0552h
xxxxxxxxxxxxxxxx
LCDSDATA5
05A6h
xxxxxxxxxxxxxxxx
LCDDATA7
0554h
xxxxxxxxxxxxxxxx
LCDSDATA6
05A8h
xxxxxxxxxxxxxxxx
LCDDATA8
0556h
xxxxxxxxxxxxxxxx
LCDSDATA7
05AAh
xxxxxxxxxxxxxxxx
LCDDATA9
0558h
xxxxxxxxxxxxxxxx
LCDSDATA8
05ACh
xxxxxxxxxxxxxxxx
LCDDATA10
055Ah
xxxxxxxxxxxxxxxx
LCDSDATA9
05AEh
xxxxxxxxxxxxxxxx
LCDDATA11
055Ch
xxxxxxxxxxxxxxxx
LCDSDATA10
05B0h
xxxxxxxxxxxxxxxx
LCDDATA12
055Eh
xxxxxxxxxxxxxxxx
LCDSDATA11
05B2h
xxxxxxxxxxxxxxxx
LCDDATA13
0560h
xxxxxxxxxxxxxxxx
LCDSDATA12
05B4h
xxxxxxxxxxxxxxxx
LCDDATA14
0562h
xxxxxxxxxxxxxxxx
LCDSDATA13
05B6h
xxxxxxxxxxxxxxxx
LCDDATA15
0564h
xxxxxxxxxxxxxxxx
LCDSDATA14
05B8h
xxxxxxxxxxxxxxxx
LCDDATA16
0566h
xxxxxxxxxxxxxxxx
LCDSDATA15
05BAh
xxxxxxxxxxxxxxxx
LCDDATA17
0568h
xxxxxxxxxxxxxxxx
LCDSDATA16
05BCh
xxxxxxxxxxxxxxxx
LCDDATA18
056Ah
xxxxxxxxxxxxxxxx
LCDSDATA17
05BEh
xxxxxxxxxxxxxxxx
LCDDATA19
056Ch
xxxxxxxxxxxxxxxx
LCDSDATA18
05C0h
xxxxxxxxxxxxxxxx
LCDDATA20
056Eh
xxxxxxxxxxxxxxxx
LCDSDATA19
05C2h
xxxxxxxxxxxxxxxx
LCDDATA21
0570h
xxxxxxxxxxxxxxxx
LCDSDATA20
05C4h
xxxxxxxxxxxxxxxx
LCDDATA22
0572h
xxxxxxxxxxxxxxxx
LCDSDATA21
05C6h
xxxxxxxxxxxxxxxx
LCDDATA23
0574h
xxxxxxxxxxxxxxxx
LCDSDATA22
05C8h
xxxxxxxxxxxxxxxx
LCDDATA24
0576h
xxxxxxxxxxxxxxxx
LCDSDATA23
05CAh
xxxxxxxxxxxxxxxx
LCDDATA25
0578h
xxxxxxxxxxxxxxxx
LCDSDATA24
05CCh
xxxxxxxxxxxxxxxx
LCDDATA26
057Ah
xxxxxxxxxxxxxxxx
LCDSDATA25
05CEh
xxxxxxxxxxxxxxxx
LCDDATA27
057Ch
xxxxxxxxxxxxxxxx
LCDSDATA26
05D0h
xxxxxxxxxxxxxxxx
LCDDATA28
057Eh
xxxxxxxxxxxxxxxx
LCDSDATA27
05D2h
xxxxxxxxxxxxxxxx
LCDDATA29
0580h
xxxxxxxxxxxxxxxx
LCDSDATA28
05D4h
xxxxxxxxxxxxxxxx
LCDDATA30
0582h
xxxxxxxxxxxxxxxx
LCDSDATA29
05D6h
xxxxxxxxxxxxxxxx
LCDDATA31
0584h
xxxxxxxxxxxxxxxx
LCDSDATA30
05D8h
xxxxxxxxxxxxxxxx
LCDSDATA31
05DAh
xxxxxxxxxxxxxxxx
LCDSE0
0586h
xxxxxxxxxxxxxxxx
LCDSE1
0588h
xxxxxxxxxxxxxxxx
Legend: x = unknown or indeterminate value; - = unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
2019-2020 Microchip Technology Inc.
DS30010198B-page 43
PIC24FJ128GL306 FAMILY
TABLE 4-8:
SFR MAP: 0600h BLOCK
Address(1)
All Resets(2)
Address(1)
All Resets(2)
PADCON
065Ch
0---------------
ODCD
06A2h
----000000000000
ANSELD
06A4h
IOCSTAT
065Eh
----------000000
----11--11------
IOCPD
06A6h
----000000000000
TRISA
0660h
---------------1
IOCND
06A8h
----000000000000
IOCFD
06AAh
PORTA
0662h
----000000000000
---------------0
IOCPUD
06ACh
LATA
----000000000000
0664h
---------------0
IOCPDD
06AEh
----000000000000
ODCA
0666h
---------------0
PORTE
ANSELA
0668h
---------------1
TRISE
06B0h
--------11111111
IOCPA
066Ah
---------------0
PORTE
06B2h
--------00000000
IOCNA
066Ch
---------------0
LATE
06B4h
--------00000000
IOCFA
066Eh
---------------0
ODCE
06B6h
--------00000000
IOCPUA
0670h
---------------0
ANSELE
06B8h
-----------1111-
IOCPDA
0672h
---------------0
IOCPE
06BAh
--------00000000
IOCNE
06BCh
--------00000000
Register
I/O
PORTA
PORTB
Register
TRISB
0674h
1111111111111111
IOCFE
06BEh
--------00000000
PORTB
0676h
0000000000000000
IOCPUE
06C0h
--------00000000
LATB
0678h
0000000000000000
IOCPDE
06C2h
--------00000000
ODCB
067Ah
0000000000000000
PORTF
ANSELB
067Ch
1111111111111111
TRISF
06C4h
---------1111111
IOCPB
067Eh
0000000000000000
PORTF
06C6h
---------0000000
IOCNB
0680h
0000000000000000
LATF
06C8h
---------0000000
IOCFB
0682h
0000000000000000
ODCF
06CAh
---------0000000
IOCPUB
0684h
0000000000000000
ANSELF
06CCH
----------------
IOCPDB
0686h
0000000000000000
IOCPF
06CEh
---------0000000
IOCNF
06D0h
---------0000000
PORTC
TRISC
0688h
1111------------
IOCFF
06D2h
---------0000000
PORTC
068Ah
0000------------
IOCPUF
06D4h
---------0000000
LATC
068Ch
0000------------
IOCPDF
06D6h
---------0000000
ODCC
068Eh
0000------------
PORTG
ANSELC
0690h
1111------------
TRISG
06D8h
------1111--11--
IOCPC
0692h
0000------------
PORTG
06DAh
------0000--00--
IOCNC
0694h
0000------------
LATG
06DCh
------0000--00--
IOCFC
0696h
0000------------
ODCG
06DEh
------0000--00--
IOCPUC
0698h
0000------------
ANSELG
06E0h
------1111------
IOCPDC
069Ah
0000------------
IOCPG
06E2h
------0000--00--
IOCNG
06E4h
------0000--00--
PORTD
TRISD
069Ch
----111111111111
IOCFG
06E6h
------0000--00--
PORTD
069Eh
----000000000000
IOCPUF
06E8h
------0000--00--
LATD
06A0h
----000000000000
IOCPDG
06EAh
------0000--00--
Legend: x = unknown or indeterminate value; - = unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
DS30010198B-page 44
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 4-9:
SFR MAP: 0700h BLOCK
Address(1)
All Resets(2)
ADC1BUF0
0700h
xxxxxxxxxxxxxxxx
RPINR0
0790h
--111111--------
ADC1BUF1
0702h
xxxxxxxxxxxxxxxx
RPINR1
0792h
--111111--111111
ADC1BUF2
0704h
xxxxxxxxxxxxxxxx
RPINR2
0794h
----------111111
ADC1BUF3
0706h
xxxxxxxxxxxxxxxx
RPINR3
0796h
--xxxxxx--111111
ADC1BUF4
0708h
xxxxxxxxxxxxxxxx
RPINR4
0798h
--111111--111111
ADC1BUF5
070Ah
xxxxxxxxxxxxxxxx
RPINR5
079Ah
--111111--111111
ADC1BUF6
070Ch
xxxxxxxxxxxxxxxx
RPINR6
079Ch
--111111--111111
ADC1BUF7
070Eh
xxxxxxxxxxxxxxxx
RPINR11
07A6h
--111111--111111
ADC1BUF8
0710h
xxxxxxxxxxxxxxxx
RPINR12
07A8h
--111111--111111
ADC1BUF9
0712h
xxxxxxxxxxxxxxxx
RPINR13
07AAh
--111111--111111
ADC1BUF10
0714h
xxxxxxxxxxxxxxxx
RPINR14
07ACh
----------111111
ADC1BUF11
0716h
xxxxxxxxxxxxxxxx
RPINR17
07B2h
--111111--------
ADC1BUF12
0718h
xxxxxxxxxxxxxxxx
RPINR18
07B4h
--111111--111111
ADC1BUF13
071Ah
xxxxxxxxxxxxxxxx
RPINR19
07B6h
--111111--111111
ADC1BUF14
071Ch
xxxxxxxxxxxxxxxx
RPINR20
07B8h
--111111--111111
ADC1BUF15
071Eh
xxxxxxxxxxxxxxxx
RPINR21
07BAh
--111111--111111
ADC1BUF16
0720h
xxxxxxxxxxxxxxxx
RPINR22
07BCh
--111111--111111
AD1CON1
0734h
0-0000000000-000
RPINR23
07BEh
--111111--111111
AD1CON2
0736h
000000--00000000
RPINR25
07C2h
--111111--111111
AD1CON3
0738h
0000000000000000
RPINR26
07C4h
--111111--111111
AD1CHS
073Ah
0000000000000000
RPINR27
07C6h
--111111--111111
AD1CSSH
073Ch
-000------------
RPOR0
07D4h
-0000000-0000000
AD1CSSL
073Eh
0000000000000000
RPOR1
07D6h
-0000000-0000000
AD1CON4
0740h
-------------000
RPOR2
07D8h
-0000000-0000000
AD1CON5
0742h
0000--00----0000
RPOR3
07DAh
-0000000-0000000
AD1CHITH
0744h
0000000000000000
RPOR4
07DCh
-0000000-0000000
AD1CHITL
0746h
0000000000000000
RPOR5
07DEh
-0000000-0000000
AD1RESDMA
074Ch
xxxxxxxxxxxxxxxx
RPOR6
07E0h
-0000000-0000000
RPOR7
07E2h
-0000000-0000000
Register
ADC
Register
Address(1)
All Resets(2)
Peripheral Pin Select (PPS)
NVM
NVMCON
0760h
000000------0000
RPOR8
07E4h
-0000000-0000000
NVMADR
0762h
0000000000000000
RPOR9
07E6h
-0000000-0000000
NVMADRU
0764h
--------00000000
RPOR10
07E8h
-0000000-0000000
NVMKEY
0766h
--------00000000
RPOR11
07EAh
-0000000-0000000
RPOR12
07ECh
-0000000-0000000
ECCCONL
076Ch
0000000000000000
RPOR13
07EEh
-0000000-0000000
ECCCONH
076Eh
0000000000000000
RPOR14
07F0h
-0000000-0000000
ECCADDRL
0770h
0000000000000000
RPOR15
07F2h
-0000000-0000000
ECCADDRH
0772h
0000000000000000
ECCSTATL
0774h
0000000000000000
ECCSTATH
0776h
0000000000000000
ECC
Legend: x = unknown or indeterminate value; - = unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
2019-2020 Microchip Technology Inc.
DS30010198B-page 45
PIC24FJ128GL306 FAMILY
4.2.5
EXTENDED DATA SPACE (EDS)
The Extended Data Space (EDS) allows PIC24F
devices to address a much larger range of data than
would otherwise be possible with a 16-bit address
range.
EDS allows read access to the program memory
space. This feature is called Program Space Visibility
(PSV) and is discussed in detail in Section 4.3.3
“Reading Data from Program Memory Using EDS”.
particular EDS page is selected through the Data
Space Read Page register (DSRPAG) or the Data
Space Write Page register (DSWPAG). For PSV, only
the DSRPAG register is used. The combination of the
DSRPAG register value and the 16-bit wide data
address forms a 24-bit Effective Address (EA).
Note:
Accessing Page 0 in the EDS window will
generate an address error trap as Page 0
is the base data memory (data locations,
0800h to 7FFFh, in the lower Data Space).
Figure 4-3 displays the entire EDS space. The EDS is
organized as pages, called EDS pages, with one page
equal to the size of the EDS window (32 Kbytes). A
FIGURE 4-3:
EXTENDED DATA SPACE
Special
Function
Registers
0000h
0800h
Internal
Data
Memory
Space
047FEh
04800h
Unimplemented
EDS Pages
8000h
32-Kbyte
EDS
Window
FFFEh
000000h
7F8000h
000001h
7F8001h
Program
Space
Access
(Lower
Word)
Program
Space
Access
(Lower
Word)
Program
Space
Access
(Upper
Word)
Program
Space
Access
(Upper
Word)
007FFEh
7FFFFEh
007FFFh
7FFFFFh
DSRPAG
= 200h
DSRPAG
= 2FFh
DSRPAG
= 300h
DSRPAG
= 3FFh
Program Memory
DS30010198B-page 46
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
4.2.6
4.3
SOFTWARE STACK
Apart from its use as a Working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer (SSP). The pointer always points to the
first available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and postincrements for stack pushes, as shown in Figure 4-4.
Note that for a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
ensuring that the MSB is always clear.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
The Stack Pointer Limit Value register (SPLIM), associated with the Stack Pointer, sets an upper address
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM[0] is forced
to ‘0’ as all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the
Stack Pointer (W15) and the SPLIM register are equal,
and a push operation is performed, a stack error trap
will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 2000h in RAM, initialize the
SPLIM with the value, 1FFEh.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the SFR space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-4:
Stack Grows Towards
Higher Address
0000h
CALL STACK FRAME
15
0
PC[15:0]
000000000 PC[22:16]
[Free Word]
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
Interfacing Program and Data
Memory Spaces
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide Data Space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use these
data successfully, they must be accessed in a way that
preserves the alignment of information in both spaces.
Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the Data Space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look-ups from a
large table of static data. It can only access the least
significant word of the program word.
4.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the MSBs of TBLPAG are
used to determine if the operation occurs in the user
memory (TBLPAG[7] = 0) or the configuration memory
(TBLPAG[7] = 1).
For remapping operations, the 10-bit Extended Data
Space Read register (DSRPAG) is used to define a
16K word page in the program space. When the Most
Significant bit (MSb) of the EA is ‘1’, and the MSb (bit 9)
of DSRPAG is ‘1’, the lower 8 bits of DSRPAG are
concatenated with the lower 15 bits of the EA to form a
23-bit program space address. The DSRPAG[8] bit
decides whether the lower word (when the bit is ‘0’) or
the higher word (when the bit is ‘1’) of program memory
is mapped. Unlike table operations, this strictly limits
remapping operations to the user memory area.
Table 4-10 and Figure 4-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P[23:0] refers to a program
space word, whereas D[15:0] refers to a Data Space
word.
2019-2020 Microchip Technology Inc.
DS30010198B-page 47
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TABLE 4-10:
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Program Space Address
[23]
[22:16]
[15]
[14:1]
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
TBLPAG[7:0]
Data EA[15:0]
0xxx xxxx
xxxx xxxx xxxx xxxx
Configuration
TBLPAG[7:0]
Data EA[15:0]
1xxx xxxx
xxxx xxxx xxxx xxxx
2:
PC[22:1]
0
0
0xx xxxx xxxx xxxx xxxx xxx0
Program Space Visibility
(Block Remap/Read)
Note 1:
[0]
User
0
DSRPAG[7:0](2)
Data EA[14:0](1)
0
xxxx xxxx
xxx xxxx xxxx xxxx
Data EA[15] is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is DSRPAG[0].
DSRPAG[9] is always ‘1’ in this case. DSRPAG[8] decides whether the lower word or higher word of
program memory is read. When DSRPAG[8] is ‘0’, the lower word is read, and when it is ‘1’, the higher
word is read.
FIGURE 4-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter
Program Counter
0
0
23 Bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 Bits
16 Bits
24 Bits
Select
Program Space
(Remapping)
Visibility(1)
0
1
EA
1/0
DSRPAG[7:0]
1-Bit
8 Bits
15 Bits
23 Bits
User/Configuration
Space Select
Byte Select
Note 1: DSRPAG[8] acts as word select. DSRPAG[9] should always be ‘1’ to map program memory to data memory.
2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is
accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the
lower word. Table Read operations are permitted in the configuration memory space.
DS30010198B-page 48
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4.3.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
2.
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going through
Data Space. The TBLRDH and TBLWTH instructions are
the only method to read or write the upper eight bits of a
program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to Data Space addresses.
Program memory can thus be regarded as two, 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P[15:0]) to a data address (D[15:0]).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-6:
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P[23:16]) to a data address. Note that D[15:8],
the ‘phantom’ byte, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D[7:0] of the data address,
as above. Note that the data will always be ‘0’
when the upper ‘phantom’ byte is selected (byte
select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are described in Section 6.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address (TBLPAG) register. TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG[7] = 0, the table page is located in the user
memory space. When TBLPAG[7] = 1, the page is
located in configuration space.
Note:
Only Table Read operations will execute
in the configuration memory space where
Device IDs are located. Table Write
operations are not allowed.
ACCESS PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
Data EA[15:0]
23
15
0
000000h
23
16
8
0
00000000
020000h
030000h
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn[0] = 0)
TBLRDL.B (Wn[0] = 1)
TBLRDL.B (Wn[0] = 0)
TBLRDL.W
800000h
2019-2020 Microchip Technology Inc.
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
DS30010198B-page 49
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4.3.3
READING DATA FROM PROGRAM
MEMORY USING EDS
The upper 32 Kbytes of Data Space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the Data Space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the Data Space occurs
when the MSb of EA is ‘1’ and the DSRPAG[9] bit is
also ‘1’. The lower eight bits of DSRPAG are concatenated to the Wn[14:0] bits to form a 23-bit EA to access
program memory. The DSRPAG[8] decides which word
should be addressed; when the bit is ‘0’, the lower
word, and when ‘1’, the upper word of the program
memory is accessed.
The entire program memory is divided into 512 EDS
pages, from 200h to 3FFh, each consisting of 16K words
of data. Pages, 200h to 2FFh, correspond to the lower
words of the program memory, while 300h to 3FFh
correspond to the upper words of the program memory.
Using this EDS technique, the entire program memory
can be accessed. Previously, the access to the upper
word of the program memory was not supported.
TABLE 4-11:
For operations that use PSV and are executed outside a
REPEAT loop, the MOV and MOV.D instructions will require
one instruction cycle in addition to the specified execution
time. All other instructions will require two instruction
cycles in addition to the specified execution time.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES
DSRPAG
(Data Space Read Register)
Source Address while
Indirect Addressing
200h
•
•
•
2FFh
300h
•
•
•
3FFh
000h
Note 1:
Table 4-11 provides the corresponding 23-bit EDS
address for program memory with EDS page and
source addresses.
8000h to FFFFh
23-Bit EA Pointing
to EDS
Comment
000000h to 007FFEh
•
•
•
7F8000h to 7FFFFEh
Lower words of 4M program
instructions (8 Mbytes) for
read operations only.
000001h to 007FFFh
•
•
•
7F8001h to 7FFFFFh
Upper words of 4M program
instructions (4 Mbytes remaining;
4 Mbytes are phantom bytes) for
read operations only.
Invalid Address
Address error trap.(1)
When the source/destination address is above 8000h and DSRPAG/DSWPAG is ‘0’, an address error trap
will occur.
EXAMPLE 4-1:
EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY
; Set the EDS page from where the data to be read
mov
#0x0202, w0
mov
w0, DSRPAG
;page 0x202, consisting lower words, is selected for read
mov
#0x000A, w1
;select the location (0x0A) to be read
bset
w1, #15
;set the MSB of the base address, enable EDS mode
;Read a byte from the selected location
mov.b
[w1++], w2
;read Low byte
mov.b
[w1++], w3
;read High byte
;Read a word from the selected location
mov
[w1], w2
;
;Read Double - word from the selected location
mov.d
[w1], w2
;two word read, stored in w2 and w3
DS30010198B-page 50
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PIC24FJ128GL306 FAMILY
FIGURE 4-7:
PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD
When DSRPAG[9:8] = 10 and EA[15] = 1:
Program Space
DSRPAG
202h
23
15
Data Space
0
000000h
0000h
Data EA[14:0]
010000h
017FFEh
The data in the page
designated by DSRPAG
are mapped into the
upper half of the data
memory space....
8000h
EDS Window
... while the lower
15 bits of the EA
specify an exact
FFFFh address within the
EDS area. This corresponds exactly to the
same lower 15 bits of
the actual program
space address.
7FFFFEh
FIGURE 4-8:
PROGRAM SPACE VISIBILITY OPERATION TO ACCESS UPPER WORD
When DSRPAG[9:8] = 11 and EA[15] = 1:
Program Space
DSRPAG
302h
23
15
Data Space
0
000000h
0000h
Data EA[14:0]
010001h
017FFFh
The data in the page
designated by DSRPAG
are mapped into the
upper half of the data
memory space....
8000h
EDS Window
7FFFFEh
2019-2020 Microchip Technology Inc.
... while the lower
15 bits of the EA
specify an exact
FFFFh address within the
EDS area. This corresponds exactly to the
same lower 15 bits of
the actual program
space address.
DS30010198B-page 51
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NOTES:
DS30010198B-page 52
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5.0
DIRECT MEMORY ACCESS
CONTROLLER (DMA)
Note:
The controller also monitors CPU instruction processing directly, allowing it to be aware of when the CPU
requires access to peripherals on the DMA bus and
automatically relinquishing control to the CPU as
needed. This increases the effective bandwidth for
handling data without DMA operations causing a
processor Stall. This makes the controller essentially
transparent to the user.
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. To complement the information in this data sheet, refer to “Direct
Memory Access Controller (DMA)”
(www.microchip.com/DS30009742) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The DMA Controller has these features:
• Six Independent and Independently
Programmable Channels
• Concurrent Operation with the CPU (no DMA
caused Wait states)
• DMA Bus Arbitration
• Five Programmable Address modes
• Four Programmable Transfer modes
• Four Flexible Internal Data Transfer modes
• Byte or Word Support for Data Transfer
• 16-Bit Source and Destination Address Register
for Each Channel, Dynamically Updated and
Reloadable
• 16-Bit Transaction Count Register, Dynamically
Updated and Reloadable
• Upper and Lower Address Limit Registers
• Counter Half-Full Level Interrupt
• Software Triggered Transfer
• Null Write mode for Symmetric Buffer Operations
The Direct Memory Access (DMA) Controller is designed
to service high throughput data peripherals operating on
the SFR bus, allowing them to access data memory
directly and alleviating the need for CPU-intensive management. By allowing these data-intensive peripherals to
share their own data path, the main data bus is also
deloaded, resulting in additional power savings.
The DMA Controller functions both as a peripheral and a
direct extension of the CPU. It is located on the microcontroller data bus, between the CPU and DMA-enabled
peripherals, with direct access to SRAM. This partitions
the SFR bus into two buses, allowing the DMA Controller
access to the DMA-capable peripherals located on the
new DMA SFR bus. The controller serves as a Master
device on the DMA SFR bus, controlling data flow from
DMA-capable peripherals.
FIGURE 5-1:
A simplified block diagram of the DMA Controller is
shown in Figure 5-1.
DMA FUNCTIONAL BLOCK DIAGRAM
CPU Execution Monitoring
To DMA-Enabled
Peripherals
To I/O Ports
and Peripherals
Control
Logic
DMACON
DMAH
DMAL
DMABUF
Data
Bus
DMACH0
DMAINT0
DMASRC0
DMADST0
DMACNT0
DMACH1
DMAINT1
DMASRC1
DMADST1
DMACNT1
DMACH4
DMAINT4
DMASRC4
DMADST4
DMACNT4
DMACH5
DMAINT5
DMASRC5
DMADST5
DMACNT5
Channel 0
Channel 1
Channel 4
Channel 5
Data RAM
2019-2020 Microchip Technology Inc.
Data RAM
Address Generation
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5.1
Summary of DMA Operations
The DMA Controller is capable of moving data between
addresses according to a number of different parameters.
Each of these parameters can be independently
configured for any transaction; in addition, any or all of
the DMA channels can independently perform a different transaction at the same time. Transactions are
classified by these parameters:
•
•
•
•
Source and destination (SFRs and data RAM)
Data size (byte or word)
Trigger source
Transfer mode (One-Shot, Repeated or
Continuous)
• Addressing modes (Fixed Address or Address
Blocks, with or without Address Increment/
Decrement)
In addition, the DMA Controller provides channel priority
arbitration for all channels.
5.1.1
SOURCE AND DESTINATION
Using the DMA Controller, data may be moved between
any two addresses in the Data Space. The SFR space
(0000h to 07FFh), or the data RAM space (0800h to
FFFFh), can serve as either the source or the destination. Data can be moved between these areas in either
direction or between addresses in either area. The four
different combinations are shown in Figure 5-2.
If it is necessary to protect areas of data RAM, the DMA
Controller allows the user to set upper and lower address
boundaries for operations in the Data Space above the
SFR space. The boundaries are set by the DMAH and
DMAL Limit registers. If a DMA channel attempts an
operation outside of the address boundaries, the
transaction is terminated and an interrupt is generated.
5.1.2
DATA SIZE
The DMA Controller can handle both 8-bit and 16-bit
transactions. Size is user-selectable using the SIZE bit
(DMACHn[1]). By default, each channel is configured
for word-sized transactions. When byte-sized transactions are chosen, the LSb of the source and/or
destination address determines if the data represent
the upper or lower byte of the data RAM location.
5.1.3
TRIGGER SOURCE
The DMA Controller can use any one of the device’s
interrupt sources to initiate a transaction. The DMA
trigger sources are listed in reverse order of their
natural interrupt priority and are shown in Table 5-1.
5.1.4
TRANSFER MODE
The DMA Controller supports four types of data
transfers, based on the volume of data to be moved for
each trigger.
• One-Shot: A single transaction occurs for each
trigger.
• Continuous: A series of back-to-back transactions
occur for each trigger; the number of transactions
is determined by the DMACNTn transaction
counter.
• Repeated One-Shot: A single transaction is
performed repeatedly, once per trigger, until the
DMA channel is disabled.
• Repeated Continuous: A series of transactions
are performed repeatedly, one cycle per trigger,
until the DMA channel is disabled.
All transfer modes allow the option to have the source
and destination addresses, and counter value, automatically reloaded after the completion of a transaction.
Repeated mode transfers do this automatically.
5.1.5
ADDRESSING MODES
The DMA Controller also supports transfers between
single addresses or address ranges. The four basic
options are:
• Fixed-to-Fixed: Between two constant addresses
• Fixed-to-Block: From a constant source address
to a range of destination addresses
• Block-to-Fixed: From a range of source addresses
to a single, constant destination address
• Block-to-Block: From a range of source
addresses to a range of destination addresses
The option to select auto-increment or auto-decrement
of source and/or destination addresses is available for
Block Addressing modes.
In addition to the four basic modes, the DMA Controller
also supports Peripheral Indirect Addressing (PIA)
mode, where the source or destination address is generated jointly by the DMA Controller and a PIA-capable
peripheral. When enabled, the DMA channel provides
a base source and/or destination address, while the
peripheral provides a fixed range offset address.
For PIC24FJ128GL306 family devices, the 12-bit A/D
Converter module is the only PIA-capable peripheral.
Details for its use in PIA mode are provided in
Section 22.0 “12-Bit A/D Converter with Threshold
Detect”.
Since the source and destination addresses for any
transaction can be programmed independently of the
trigger source, the DMA Controller can use any trigger
to perform an operation on any peripheral. This also
allows DMA channels to be cascaded to perform more
complex transfer operations.
DS30010198B-page 54
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FIGURE 5-2:
TYPES OF DMA DATA TRANSFERS
Peripheral to Memory
Memory to Peripheral
SFR Area
SFR Area
Data RAM
DMASRCn
DMADSTn
07FFh
0800h
07FFh
0800h
DMAL
DMA RAM Area
Data RAM
DMA RAM Area
DMAL
DMADSTn
DMASRCn
DMAH
DMAH
Peripheral to Peripheral
Memory to Memory
SFR Area
SFR Area
DMASRCn
DMADSTn
Data RAM
DMA RAM Area
07FFh
0800h
DMAL
Data RAM
DMA RAM Area
07FFh
0800h
DMAL
DMASRCn
DMADSTn
DMAH
DMAH
Note: Relative sizes of memory areas are not shown to scale.
2019-2020 Microchip Technology Inc.
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5.1.6
CHANNEL PRIORITY
Each DMA channel functions independently of the
others, but also competes with the others for access to
the data and DMA buses. When access collisions
occur, the DMA Controller arbitrates between the
channels using a user-selectable priority scheme. Two
schemes are available:
• Round-Robin: When two or more channels
collide, the lower numbered channel receives
priority on the first collision. On subsequent collisions, the higher numbered channels each
receive priority, based on their channel number.
• Fixed: When two or more channels collide, the
lowest numbered channel always receives
priority, regardless of past history; however, any
channel being actively processed is not available
for an immediate retrigger. If a higher priority
channel is continually requesting service, it will be
scheduled for service after the next lower priority
channel with a pending request.
5.2
Typical Setup
To set up a DMA channel for a basic data transfer:
1.
Enable the DMA Controller (DMAEN = 1) and
select an appropriate channel priority scheme
by setting or clearing PRSSEL.
2. Program DMAH and DMAL with the appropriate
upper and lower address boundaries for data
RAM operations.
3. Select the DMA channel to be used and disable
its operation (CHEN = 0).
4. Program the appropriate source and destination
addresses for the transaction into the channel’s
DMASRCn and DMADSTn registers. For PIA
mode addressing, use the base address value.
5. Program the DMACNTn register for the number
of triggers per transfer (One-Shot or Continuous
modes) or the number of words (bytes) to be
transferred (Repeated modes).
6. Set or clear the SIZE bit to select the data size.
7. Program the TRMODE[1:0] bits to select the
Data Transfer mode.
8. Program the SAMODE[1:0] and DAMODE[1:0]
bits to select the addressing mode.
9. Enable the DMA channel by setting CHEN.
10. Enable the trigger source interrupt.
DS30010198B-page 56
5.3
Peripheral Module Disable
Unlike other peripheral modules, the channels of the
DMA Controller cannot be individually powered down
using the Peripheral Module Disable (PMD) registers.
Instead, the channels are controlled as two groups. The
DMA0MD bit (PMD7[4]) selectively controls DMACH0
through DMACH3. The DMA1MD bit (PMD7[5])
controls DMACH4 and DMACH5. Setting both bits
effectively disables the DMA Controller.
5.4
DMA Registers
The DMA Controller uses a number of registers to control its operation. The number of registers depends on
the number of channels implemented for a particular
device.
There are always four module-level registers (one
control and three buffer/address):
• DMACON: DMA Engine Control Register
(Register 5-1)
• DMAH and DMAL: DMA High and Low Address
Limit Registers
• DMABUF: DMA Data Buffer
Each of the DMA channels implements five registers
(two control and three buffer/address):
• DMACHn: DMA Channel n Control Register
(Register 5-2)
• DMAINTn: DMA Channel n Interrupt Register
(Register 5-3)
• DMASRCn: DMA Data Source Address Pointer
for Channel n
• DMADSTn: DMA Data Destination Address Pointer
for Channel n
• DMACNTn: DMA Transaction Counter for
Channel n
For PIC24FJ128GL306 family devices, there are a total
of 34 registers.
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REGISTER 5-1:
DMACON: DMA ENGINE CONTROL REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
DMAEN
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PRSSEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
DMAEN: DMA Module Enable bit
1 = Enables module
0 = Disables module and terminates all active DMA operation(s)
bit 14-1
Unimplemented: Read as ‘0’
bit 0
PRSSEL: Channel Priority Scheme Selection bit
1 = Round-robin scheme
0 = Fixed priority scheme
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 57
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REGISTER 5-2:
DMACHn: DMA CHANNEL n CONTROL REGISTER
U-0
—
U-0
—
U-0
—
r-0
—
U-0
—
R/W-0
NULLW
R/W-0
RELOAD(1)
R/W-0
CHREQ(3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SAMODE1
bit 7
SAMODE0
DAMODE1
DAMODE0
TRMODE1
TRMODE0
SIZE
CHEN
bit 0
Legend:
R = Readable bit
r = Reserved bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 11
bit 10
Unimplemented: Read as ‘0’
NULLW: Null Write Mode bit
1 = A dummy write is initiated to DMASRCn for every write to DMADSTn
0 = No dummy write is initiated
bit 9
RELOAD: Address and Count Reload bit(1)
1 = DMASRCn, DMADSTn and DMACNTn registers are reloaded to their previous values upon the
start of the next operation
0 = DMASRCn, DMADSTn and DMACNTn are not reloaded on the start of the next operation(2)
CHREQ: DMA Channel Software Request bit(3)
1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0 = No DMA request is pending
bit 8
bit 7-6
SAMODE[1:0]: Source Address Mode Selection bits
11 = DMASRCn is used in Peripheral Indirect Addressing and remains unchanged
10 = DMASRCn is decremented based on the SIZE bit after a transfer completion
01 = DMASRCn is incremented based on the SIZE bit after a transfer completion
00 = DMASRCn remains unchanged after a transfer completion
DAMODE[1:0]: Destination Address Mode Selection bits
11 = DMADSTn is used in Peripheral Indirect Addressing and remains unchanged
10 = DMADSTn is decremented based on the SIZE bit after a transfer completion
01 = DMADSTn is incremented based on the SIZE bit after a transfer completion
00 = DMADSTn remains unchanged after a transfer completion
TRMODE[1:0]: Transfer Mode Selection bits
11 = Repeated Continuous mode
10 = Continuous mode
01 = Repeated One-Shot mode
00 = One-Shot mode
SIZE: Data Size Selection bit
1 = Byte (8-bit)
0 = Word (16-bit)
bit 5-4
bit 3-2
bit 1
bit 0
CHEN: DMA Channel Enable bit
1 = The corresponding channel is enabled
0 = The corresponding channel is disabled
Note 1:
2:
3:
Only the original DMACNTn is required to be stored to recover the original DMASRCn and DMADSTn.
DMASRCn, DMADSTn and DMACNTn are always reloaded in Repeated mode transfers
(DMACHn[2] = 1), regardless of the state of the RELOAD bit.
The number of transfers executed while CHREQ is set depends on the configuration of TRMODE[1:0].
DS30010198B-page 58
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REGISTER 5-3:
DMAINTn: DMA CHANNEL n INTERRUPT REGISTER
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DBUFWF(1)
CHSEL6
CHSEL5
CHSEL4
CHSEL3
CHSEL2
CHSEL1
CHSEL0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
HIGHIF(1,2)
LOWIF(1,2)
DONEIF(1)
HALFIF(1)
OVRUNIF(1)
—
—
HALFEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
DBUFWF: DMA Buffered Data Write Flag bit(1)
1 = The content of the DMA buffer has not been written to the location specified in DMADSTn or
DMASRCn in Null Write mode
0 = The content of the DMA buffer has been written to the location specified in DMADSTn or DMASRCn
in Null Write mode
bit 14-8
CHSEL[6:0]: DMA Channel Trigger Selection bits
See Table 5-1 for a complete list.
bit 7
HIGHIF: DMA High Address Limit Interrupt Flag bit(1,2)
1 = The DMA channel has attempted to access an address higher than DMAH or the upper limit of the
data RAM space
0 = The DMA channel has not invoked the high address limit interrupt
bit 6
LOWIF: DMA Low Address Limit Interrupt Flag bit(1,2)
1 = The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above
the SFR range (07FFh)
0 = The DMA channel has not invoked the low address limit interrupt
bit 5
DONEIF: DMA Complete Operation Interrupt Flag bit(1)
If CHEN = 1:
1 = The previous DMA session has ended with completion
0 = The current DMA session has not yet completed
If CHEN = 0:
1 = The previous DMA session has ended with completion
0 = The previous DMA session has ended without completion
bit 4
HALFIF: DMA 50% Watermark Level Interrupt Flag bit(1)
1 = DMACNTn has reached the halfway point to 0000h
0 = DMACNTn has not reached the halfway point
bit 3
OVRUNIF: DMA Channel Overrun Flag bit(1)
1 = The DMA channel is triggered while it is still completing the operation based on the previous trigger
0 = The overrun condition has not occurred
bit 2-1
Unimplemented: Read as ‘0’
bit 0
HALFEN: Halfway Completion Watermark bit
1 = Interrupts are invoked when DMACNTn has reached its halfway point and at completion
0 = An interrupt is invoked only at the completion of the transfer
Note 1:
2:
Setting these flags in software does not generate an interrupt.
Testing for address limit violations (DMASRCn or DMADSTn is either greater than DMAH or less than
DMAL) is NOT done before the actual access.
2019-2020 Microchip Technology Inc.
DS30010198B-page 59
PIC24FJ128GL306 FAMILY
TABLE 5-1:
DMA TRIGGER SOURCES
CHSEL[6:0]
0000000
Trigger (Interrupt)
0h
0000001
1h
...
...
0000110
6h
0000111
7h
0001000
8h
0001001
0001010
0001011
Bh
Off
CHSEL[6:0]
1000101
Trigger (Interrupt)
45h
UART1 RX Interrupt
UART1 Error Interrupt
1000110
46h
1000111
47h
...
...
MCCP5 IC/OC Interrupt
1001010
4Ah
MCCP5 Timer Interrupt
1001011
4Bh
DMACHA5 Interrupt
9h
MCCP4 IC/OC Interrupt
1001100
4Ch
DMACHA4 Interrupt
Ah
MCCP4 Timer Interrupt
1001101
4Dh
DMACHA3 Interrupt
MCCP3 IC/OC Interrupt
1001110
4Eh
DMACHA2 Interrupt
Reserved
Reserved
0001100
Ch
MCCP3 Timer Interrupt
1001111
4Fh
DMACHA1 Interrupt
0001101
Dh
MCCP2 IC/OC Interrupt
1010000
50h
DMACHA0 Interrupt
0001110
Eh
MCCP2 Timer Interrupt
1010001
51h
ADC Interrupt
0001111
Fh
MCCP1 IC/OC Interrupt
1010010
52h
0010000
10h
MCCP1 Timer Interrupt
...
...
0010001
11h
...
...
0100010
22h
0100011
23h
0100100
24h
0100101
25h
0100110
0100111
Reserved
1010011
53h
1010100
54h
HLVD Interrupt
1010101
55h
CRC Interrupt
SPI2 Receive Interrupt
1010110
56h
LCD Interrupt
SPI2 Transmit Interrupt
1010111
57h
LCD Automation Interrupt
SPI2 General Interrupt
1011000
58h
Reserved
26h
SPI1 Receive Interrupt
1011001
59h
CLC4 Out
27h
SPI1 Transmit Interrupt
1011010
5Ah
CLC3 Out
0101000
28h
SPI1 General Interrupt
1011011
5Bh
CLC2 Out
0101001
29h
1011100
5Ch
CLC1 Out
...
...
1011101
5Dh
Reserved
0101110
2Eh
1011110
5Eh
RTCC Alarm Interrupt
0101111
2Fh
I2C2 Slave Interrupt
1011111
5Fh
TMR5 Interrupt
0110000
30h
I2C2 Master Interrupt
1100000
60h
TMR4 Interrupt
0110001
31h
I2C2 Collision Interrupt
1100001
61h
TMR3 Interrupt
0110010
32h
I2C1 Slave Interrupt
1100010
62h
TMR2 Interrupt
0110011
33h
I2C1 Master Interrupt
1100011
63h
TMR1 Interrupt
0110100
34h
I2C1 Collision Interrupt
1100100
64h
0110101
35h
...
...
1100110
66h
1100111
67h
Comparator Interrupt
68h
INT4 Interrupt
Reserved
Reserved
Reserved
Reserved
...
...
0111010
3Ah
0111011
3Bh
UART4 TX Interrupt
1101000
0111100
3Ch
UART4 RX Interrupt
1101001
69h
INT3 Interrupt
0111101
3Dh
UART4 Error Interrupt
1101010
6Ah
INT2 Interrupt
0111110
3Eh
UART3 TX Interrupt
1101011
6Bh
INT1 Interrupt
0111111
3Fh
UART3 RX Interrupt
1101100
6Ch
INT0 Interrupt
1000000
40h
UART3 Error Interrupt
1101101
6Dh
Interrupt-on-Change (IOC) Interrupt
1000001
41h
UART2 TX Interrupt
1101110
6Eh
1000010
42h
UART2 RX Interrupt
...
...
1000011
43h
UART2 Error Interrupt
1111111
7Fh
1000100
44h
UART1 TX Interrupt
DS30010198B-page 60
Reserved
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
6.0
Note:
FLASH PROGRAM MEMORY
RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
may write program memory data in blocks of
128 instructions (384 bytes) at a time and erase
program memory in blocks of 1024 instructions
(3072 bytes) at a time.
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive reference source. For more information, refer
to “PIC24F Flash Program Memory”
(www.microchip.com/DS30009715) in the
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data
sheet supersedes the information in the
FRM.
The device implements a 7-bit Error Correcting Code
(ECC). The NVM block contains a logic to write and
read ECC bits to and from the Flash memory. The
Flash is programmed at the same time as the
corresponding ECC parity bits. The ECC provides
improved resistance to Flash errors. ECC single-bit
errors can be transparently corrected; ECC double-bit
errors generate an interrupt.
The PIC24FJ128GL306 family of devices contains
internal Flash program memory for storing and executing application code. The program memory is readable,
writable and erasable. The Flash memory can be
programmed in four ways:
•
•
•
•
6.1
In-Circuit Serial Programming™ (ICSP™)
Run-Time Self-Programming (RTSP)
JTAG
Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using the TBLPAG[7:0] bits and the Effective
Address (EA) from a W register, specified in the table
instruction, as shown in Figure 6-1.
ICSP allows a PIC24FJ128GL306 family device to be
serially programmed while in the end application circuit.
This is simply done with two lines for the programming
clock and programming data (named PGCx and PGDx,
respectively), and three other lines for power (VDD),
ground (VSS) and Master Clear (MCLR). This allows
customers to manufacture boards with unprogrammed
devices and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be
programmed.
FIGURE 6-1:
Table Instructions and Flash
Programming
The TBLRDL and the TBLWTL instructions are used to
read or write to bits[15:0] of program memory. TBLRDL
and TBLWTL can access program memory in both
Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits[23:16] of program memory. TBLRDH and
TBLWTH can also access program memory in Word or
Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program
Counter
Program Counter
0
0
Working Reg EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 Bits
User/Configuration
Space Select
2019-2020 Microchip Technology Inc.
16 Bits
24-Bit EA
Byte
Select
DS30010198B-page 61
PIC24FJ128GL306 FAMILY
6.2
RTSP Operation
The PIC24F Flash program memory array is organized
into rows of 128 instructions or 384 bytes. RTSP allows
the user to erase blocks of eight rows (1024 instructions) at a time and to program one row at a time. It is
also possible to program two instruction word blocks.
The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory, on
boundaries of 3072 bytes and 384 bytes, respectively.
When data are written to program memory using
TBLWT instructions, the data are not written directly to
memory. Instead, data written using Table Writes are
stored in holding latches until the programming
sequence is executed.
6.2.2
The user can program one row of Flash program memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
process is:
1.
2.
3.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
128 TBLWT instructions are required to write the full row
of memory.
To ensure that no data are corrupted during a write, any
unused address should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.
The basic sequence for RTSP programming is to set
the Table Pointer to point to the programming latches,
do a series of TBLWT instructions to load the buffers
and set the NVMADRU/NVMADR registers to point to
the destination. Programming is performed by setting
the control bits in the NVMCON register.
4.
5.
6.
Data can be loaded in any order and the holding
registers can be written to multiple times before performing a write operation. Subsequent writes, however, will
wipe out any previous writes.
Note:
Writing to a location multiple times without
erasing is not recommended.
All of the Table Write operations are single-word writes
(two instruction cycles), because only the buffers
are written. A programming cycle is required for
programming each row.
6.2.1
PROGRAMMING OPERATIONS
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON[15]) starts the operation
and the WR bit is automatically cleared when the
operation is finished.
DS30010198B-page 62
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
7.
Read eight rows of program memory
(1024 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 6-1):
a) Set the NVMOP[3:0] bits (NVMCON[3:0]) to
‘0011’ to configure for block erase. Set the
WREN (NVMCON[14]) bit.
b) Write the starting address of the block to
be erased into the NVMADRU/NVMADR
registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
e) Set the WR bit (NVMCON[15]). The erase
cycle begins and the CPU stalls for the
duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
Update the TBLPAG register to point to the
programming latches on the device. Update the
NVMADRU/NVMADR registers to point to the
destination in the program memory.
Write the first 128 instructions from data RAM into
the program memory buffers (see Table 6-1).
Write the program block to Flash memory:
a) Set the NVMOPx bits to ‘0010’ to configure
for row programming. Set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration
of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
Repeat Steps 4 through 6, using the next
available 128 instructions from the block in data
RAM, by incrementing the value in NVMADRU/
NVMADR until all 1024 instructions are written
back to Flash memory.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 6-2.
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 6-1:
EXAMPLE PAGE ERASE
Step 1: Set the NVMCON register to erase a page.
MOV
MOV
#0x4003, W0
W0, NVMCON
Step 2: Load the address of the page to be erased into the NVMADRU/NVMADR register pair.
MOV
MOV
MOV
MOV
#PAGE_ADDR_LO, W0
W0, NVMADR
#PAGE_ADDR_HI, W0
W0, NVMADRU
Step 3: Set the WR bit.
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
EXAMPLE 6-1:
ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE)
// C example using MPLAB XC16
unsigned
long progAddr = 0xXXXXXX;
// Address of row to write
unsigned
int offset;
//Set up pointer to the first memory location to be written
NVMADRU = progAddr>>16;
// Initialize PM Page Boundary SFR
NVMADR = progAddr & 0xFFFF;
// Initialize lower word of address
NVMCON = 0x4003;
// Initialize NVMCON
asm("DISI #5");
// Block all interrupts with priority 16;
// Initialize PM Page Boundary SFR
NVMADR = progAddr & 0xFFFF;
// Initialize lower word of address
//Perform TBLWT instructions to write latches
__builtin_tblwtl(0, progData1L);
// Write word 1 to address low word
__builtin_tblwth(0, progData2H);
// Write word 1 to upper byte
__builtin_tblwtl(1, progData2L);
// Write word 2 to address low word
__builtin_tblwth(1, progData2H);
// Write word 2 to upper byte
asm(“DISI #5”);
// Block interrupts with priority W0
; W0 has '1' for each bit set in IOCFx
; IOCFx & W0 ->IOCFx
PORT READ/WRITE IN ASSEMBLY
;
;
;
;
Configure PORTB[15:8] as inputs
and PORTB[7:0] as outputs
Delay 1 cycle
Next Instruction
PORT READ/WRITE IN ‘C’
TRISB = 0xFF00;
Nop();
If (PORTBbits.RB13){ };
2019-2020 Microchip Technology Inc.
// Configure PORTB[15:8] as inputs and PORTB[7:0] as outputs
// Delay 1 cycle
// Next Instruction
DS30010198B-page 129
PIC24FJ128GL306 FAMILY
11.4
I/O Port Control Registers
REGISTER 11-1:
PADCON: PORT CONFIGURATION REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
IOCON
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
IOCON: Interrupt-on-Change Enable bit
1 = Interrupt-on-change functionality is enabled
0 = Interrupt-on-change functionality is disabled
bit 14-0
Unimplemented: Read as ‘0’
DS30010198B-page 130
x = Bit is unknown
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PIC24FJ128GL306 FAMILY
REGISTER 11-2:
IOCSTAT: INTERRUPT-ON-CHANGE STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
—
IOCPGF
IOCPFF
IOCPEF
IOCPDF
IOCPCF
IOCPBF
IOCPAF
bit 7
bit 0
Legend:
HS = Hardware Settable bit
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6
IOCPGF: Interrupt-on-Change PORTG Flag bit
1 = A change was detected on an IOC-enabled pin on PORTG
0 = No change was detected or the user has cleared all detected changes
bit 5
IOCPFF: Interrupt-on-Change PORTF Flag bit
1 = A change was detected on an IOC-enabled pin on PORTF
0 = No change was detected or the user has cleared all detected changes
bit 4
IOCPEF: Interrupt-on-Change PORTE Flag bit
1 = A change was detected on an IOC-enabled pin on PORTE
0 = No change was detected or the user has cleared all detected changes
bit 3
IOCPDF: Interrupt-on-Change PORTD Flag bit
1 = A change was detected on an IOC-enabled pin on PORTD
0 = No change was detected or the user has cleared all detected changes
bit 2
IOCPCF: Interrupt-on-Change PORTC Flag bit
1 = A change was detected on an IOC-enabled pin on PORTC
0 = No change was detected or the user has cleared all detected changes
bit 1
IOCPBF: Interrupt-on-Change PORTB Flag bit
1 = A change was detected on an IOC-enabled pin on PORTB
0 = No change was detected or the user has cleared all detected changes
bit 0
IOCPAF: Interrupt-on-Change PORTA Flag bit
1 = A change was detected on an IOC-enabled pin on PORTA
0 = No change was detected, or the user has cleared all detected change
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 131
PIC24FJ128GL306 FAMILY
TRISx: OUTPUT ENABLE FOR PORTx REGISTER(1)
REGISTER 11-3:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISx[15:8]
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
TRISx[15:0]: Output Enable for PORTx bits
1 = LATx[n] is not driven on the PORTx[n] pin
0 = LATx[n] is driven on the PORTx[n] pin
See Table 11-3 through Table 11-9 for individual bit availability in this register.
PORTx: INPUT DATA FOR PORTx REGISTER(1)
REGISTER 11-4:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PORTx[15:8]
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PORTx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PORTx[15:0]: PORTx Data Input Value bits
See Table 11-3 through Table 11-9 for individual bit availability in this register.
DS30010198B-page 132
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PIC24FJ128GL306 FAMILY
REGISTER 11-5:
R/W-x
LATx: OUTPUT DATA FOR PORTx REGISTER(1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
LATx[15:8]
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
LATx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
LATx[15:0]: PORTx Data Output Value bits
See Table 11-3 through Table 11-9 for individual bit availability in this register.
REGISTER 11-6:
R/W-0
ODCx: OPEN-DRAIN ENABLE FOR PORTx REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ODCx[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ODCx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
ODCx[15:0]: PORTx Open-Drain Enable bits
1 = Open-drain is enabled on the PORTx pin
0 = Open-drain is disabled on the PORTx pin
See Table 11-3 through Table 11-9 for individual bit availability in this register.
2019-2020 Microchip Technology Inc.
DS30010198B-page 133
PIC24FJ128GL306 FAMILY
ANSELx: ANALOG SELECT FOR PORTx REGISTER(1)
REGISTER 11-7:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSELx[15:8]
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSELx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
ANSELx[15:0]: Analog Select for PORTx bits
1 = Analog input is enabled and digital input is disabled on the PORTx[n] pin
0 = Analog input is disabled and digital input is enabled on the PORTx[n] pin
See Table 11-3 through Table 11-9 for individual bit availability in this register.
REGISTER 11-8:
R/W-0
IOCPx: INTERRUPT-ON-CHANGE POSITIVE EDGE x REGISTER(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCPx[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCPx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
IOCPx[15:0]: Interrupt-on-Change Positive Edge x Enable bits
1 = Interrupt-on-change is enabled on the IOCx pin for a positive going edge; the associated status bit
and interrupt flag will be set upon detecting an edge
0 = Interrupt-on-change is disabled on the IOCx pin for a positive going edge
Setting both IOCPx and IOCNx will enable the IOCx pin for both edges, while clearing both registers will
disable the functionality.
Changing the value of this register while the module is enabled (IOCON = 1) may cause a spurious IOC
event. The corresponding interrupt must be ignored, cleared (using IOCFx) or masked (within the interrupt
controller), or this module must be enabled (IOCON = 0) when changing this register.
See Table 11-3 through Table 11-9 for individual bit availability in this register.
DS30010198B-page 134
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PIC24FJ128GL306 FAMILY
REGISTER 11-9:
R/W-0
IOCNx: INTERRUPT-ON-CHANGE NEGATIVE EDGE x REGISTER(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCNx[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCNx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
IOCNx[15:0]: Interrupt-on-Change Negative Edge x Enable bits
1 = Interrupt-on-change is enabled on the IOCx pin for a negative going edge; the associated status bit
and interrupt flag will be set upon detecting an edge
0 = Interrupt-on-change is disabled on the IOCx pin for a negative going edge
Setting both IOCPx and IOCNx will enable the IOCx pin for both edges, while clearing both registers will
disable the functionality.
Changing the value of this register while the module is enabled (IOCON = 1) may cause a spurious IOC
event. The corresponding interrupt must be ignored, cleared (using IOCFx) or masked (within the interrupt
controller), or this module must be enabled (IOCON = 0) when changing this register.
See Table 11-3 through Table 11-9 for individual bit availability in this register.
2019-2020 Microchip Technology Inc.
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REGISTER 11-10: IOCFx: INTERRUPT-ON-CHANGE FLAG x REGISTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCFx[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCFx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
IOCFx[15:0]: Interrupt-on-Change Flag x bits
1 = An enabled change was detected on the associated pin; set when IOCPx = 1 and a positive edge was
detected on the IOCx pin, or when IOCNx = 1 and a negative edge was detected on the IOCx pin
0 = No change was detected or the user cleared the detected change
It is not possible to set the IOCFx register bits with software writes (as this would require the addition of
significant logic). To test IOC interrupts, it is recommended to enable the IOC functionality on one or more
GPIO pins and then use the corresponding LATx register bit(s) to trigger an IOC interrupt.
See Table 11-3 through Table 11-9 for individual bit availability in this register.
REGISTER 11-11: IOCPUx: INTERRUPT-ON-CHANGE PULL-UP ENABLE x REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCPUx[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCPUx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
IOCPUx[15:0]: Interrupt-on-Change Pull-up Enable x bits
1 = Pull-up is enabled
0 = Pull-up is disabled
See Table 11-3 through Table 11-9 for individual bit availability in this register.
DS30010198B-page 136
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 11-12: IOCPDx: INTERRUPT-ON-CHANGE PULL-DOWN ENABLE x REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCPDx[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCPDx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
IOCPDx[15:0]: Interrupt-on-Change Pull-Down Enable x bits
1 = Pull-down is enabled
0 = Pull-down is disabled
See Table 11-3 through Table 11-9 for individual bit availability in this register.
2019-2020 Microchip Technology Inc.
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PIC24FJ128GL306 FAMILY
11.5
Peripheral Pin Select (PPS)
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. In an
application that needs to use more than one peripheral
multiplexed on a single pin, inconvenient work arounds
in application code, or a complete redesign, may be the
only option.
The Peripheral Pin Select (PPS) feature provides an
alternative to these choices by enabling the user’s
peripheral set selection and its placement on a wide
range of I/O pins. By increasing the pinout options
available on a particular device, users can better tailor
the microcontroller to their entire application, rather
than trimming the application to fit the device.
The Peripheral Pin Select feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of any one of many digital
peripherals to any one of these I/O pins. PPS is performed in software and generally does not require the
device to be reprogrammed. Hardware safeguards are
included that prevent accidental or spurious changes to
the peripheral mapping once it has been established.
11.5.1
AVAILABLE PINS
The number of available pins is dependent on the particular device and its pin count. Pins that support the
Peripheral Pin Select feature include the designation,
“RPn” or “RPIn”, in their full pin designation, where “n”
is the remappable pin number. “RP” is used to designate pins that support both remappable input and
output functions, while “RPI” indicates pins that support
remappable input functions only.
PIC24FJ128GL306 family devices support a larger
number of remappable input/output pins than remappable input only pins. In this device family, there are up
to 33 remappable input/output pins, depending on the
pin count of the particular device selected. These pins
are numbered, RP0 through RP31 and RPI37.
See Table 1-1 for a summary of pinout options in each
package offering.
11.5.2
PPS is not available for these peripherals:
•
•
•
•
I2C (input and output)
Input Change Notifications
Analog (inputs and outputs)
INT0
A key difference between pin select and non-pin select
peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non-pin select peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
11.5.2.1
Peripheral Pin Select Function
Priority
Pin-selectable peripheral outputs (e.g., output compare, UART transmit) will take priority over general
purpose digital functions on a pin, such as port I/O.
Specialized digital outputs will take priority over PPS
outputs on the same pin. The pin diagrams list
peripheral outputs in the order of priority. Refer to them
for priority concerns on a particular pin.
Unlike PIC24F devices with fixed peripherals, pinselectable peripheral inputs will never take ownership
of a pin. The pin’s output buffer will be controlled by the
TRISx setting or by a fixed peripheral on the pin. If the
pin is configured in Digital mode, then the PPS input will
operate correctly. If an analog function is enabled on
the pin, the PPS input will be disabled.
11.5.3
CONTROLLING PERIPHERAL PIN
SELECT
PPS features are controlled through two sets of Special
Function Registers (SFRs): one to map peripheral
inputs and one to map outputs. Because they are
separately controlled, a particular peripheral’s input
and output (if the peripheral has both) can be placed on
any selectable function pin without constraint.
The association of a peripheral to a peripheral-selectable
pin is handled in two different ways, depending on if an
input or an output is being mapped.
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digital
only peripherals. These include general serial communications (UART and SPI), general purpose timer clock
inputs, timer related peripherals (input capture and
output compare) and external interrupt inputs. Also
included are the outputs of the comparator module,
since these are discrete digital signals.
DS30010198B-page 138
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
11.5.3.1
Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-13
through Register 11-33).
Each register contains one or two sets of 6-bit fields,
with each set associated with one of the pin-selectable
peripherals. Programming a given peripheral’s bit field
with an appropriate 6-bit value maps the RPn/RPIn pin
with that value to that peripheral. For any given device,
the valid range of values for any of the bit fields corresponds to the maximum number of Peripheral Pin
Selections supported by the device.
TABLE 11-10: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Function Name
Register
Function Mapping
Bits
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
Timer2 External Clock
Timer3 External Clock
Timer4 External Clock
Timer5 External Clock
CCP Capture 1
CCP Capture 2
CCP Capture 3
CCP Capture 4
Output Compare Fault A
Output Compare Fault B
CCP Clock Input A
CCP Clock Input B
Reference Clock Input
INT1
INT2
INT3
INT4
T2CK
T3CK
T4CK
T5CK
ICM1
ICM2
ICM3
ICM4
OCFA
OCFB
TCKIA
TCKIB
REFI
RPINR0[13:8]
RPINR1[5:0]
RPINR1[13:8]
RPINR2[5:0]
RPINR3[5:0]
RPINR3[13:8]
RPINR4[5:0]
RPINR4[13:8]
RPINR5[5:0]
RPINR5[13:8]
RPINR6[5:0]
RPINR6[13:8]
RPINR11[5:0]
RPINR11[13:8]
RPINR12[5:0]
RPINR12[13:8]
RPINR13[5:0]
INT1R[5:0]
INT2R[5:0]
INT3R[5:0]
INT4R[5:0]
T2CKR[5:0]
T3CKR[5:0]
T4CKR[5:0]
T5CKR[5:0]
ICM1R[5:0]
ICM2R[5:0]
ICM3R[5:0]
ICM4R[5:0]
OCFAR[5:0]
OCFBR[5:0]
TCKIAR[5:0]
TCKIBR[5:0]
REFIR[5:0]
Tamper Detect
CCP Capture 5
UART3 Receive
UART1 Receive
TMPRN
ICM5
U3RX
U1RX
RPINR13[13:8]
RPINR14[5:0]
RPINR17[13:8]
RPINR18[5:0]
TMPRNR[5:0]
ICM5R[5:0]
U3RXR[5:0]
U1RXR[5:0]
UART1 Clear-to-Send
UART2 Receive
U1CTS
U2RX
RPINR18[13:8]
RPINR19[5:0]
U1CTSR[5:0]
U2RXR[5:0]
UART2 Clear-to-Send
SPI1 Data Input
SPI1 Clock Input
SPI1 Slave Select Input
U2CTS
SDI1
SCK1IN
SS1IN
RPINR19[13:8]
RPINR20[5:0]
RPINR20[13:8]
RPINR21[5:0]
U2CTSR[5:0]
SDI1R[5:0]
SCK1R[5:0]
SS1R[5:0]
UART3 Clear-to-Send
SPI2 Data Input
SPI2 Clock Input
SPI2 Slave Select Input
Generic Timer External Clock
CLC Input A
CLC Input B
CLC Input C
CLC Input D
UART4 Receive
U3CTS
SDI2
SCK2IN
SS2IN
TxCK
CLCINA
CLCINB
CLCINC
CLCIND
U4RX
RPINR21[13:8]
RPINR22[5:0]
RPINR22[13:8]
RPINR23[5:0]
RPINR23[13:8]
RPINR25[5:0]
RPINR25[13:8]
RPINR26[5:0]
RPINR26[13:8]
RPINR27[5:0]
U3CTSR[5:0]
SDI2R[5:0]
SCK2R[5:0]
SS2R[5:0]
TXCKR[5:0]
CLCINAR[5:0]
CLCINBR[5:0]
CLCINCR[5:0]
CLCINDR[5:0]
U4RXR[5:0]
Input Name
UART4 Clear-to-Send
U4CTS
RPINR27[13:8]
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.
2019-2020 Microchip Technology Inc.
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DS30010198B-page 139
PIC24FJ128GL306 FAMILY
11.5.3.2
Output Mapping
value of the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see
Table 11-11).
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In this
case, a control register associated with a particular pin
dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Each register contains two 6-bit fields, with each field
being associated with either one RPa pin or one RPb pin
(see Register 11-34, Table 11-13 and Table 11-14). The
Because of the mapping technique, the list of peripherals
for output mapping also includes a null value of ‘000000’.
This permits any given pin to remain disconnected from
the output of any of the pin-selectable peripherals.
TABLE 11-11: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)
Output Function Number
Function
Output Name
0
None (Pin Disabled)
—
1
C1OUT
Comparator 1 Output
2
C2OUT
Comparator 2 Output
3
U1TX
4
U1RTS
UART1 Transmit
5
U2TX
6
U2RTS
UART2 Request-to-Send
7
SDO1
SPI1 Data Output
8
SCK1OUT
SPI1 Clock Output
9
SS1OUT
UART1 Request-to-Send
UART2 Transmit
SPI1 Slave Select Output
10
SDO2
SPI2 Data Output
11
SCK2OUT
SPI2 Clock Output
12
SS2OUT
SPI2 Slave Select Output
16
OCM2A
CCP2A Output Compare
17
OCM2B
CCP2B Output Compare
18
OCM3A
CCP3A Output Compare
19
OCM3B
CCP3B Output Compare
20
OCM4A
CCP4A Output Compare
21
OCM4B
22
U3TX
23
U3RTS
24
U4TX
25
U4RTS
UART4 Request-to-Send
26
C3OUT
Comparator 3 Output
27
PWRGT
RTCC Power Control
CCP4B Output Compare
UART3 Transmit
UART3 Request-to-Send
UART4 Transmit
28
REFO
29
CLC1OUT
30
CLC2OUT
CLC2 Output
31
CLC3OUT
CLC3 Output
32
CLC4OUT
CLC4 Output
33
RTCC
34
OCM5B
CCP5B Output Compare
35
OCM5A
CCP5A Output Compare
DS30010198B-page 140
Reference Clock Output
CLC1 Output
RTCC Clock Output
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
11.5.3.3
Mapping Limitations
11.5.4.1
The control schema of the Peripheral Pin Select is
extremely flexible. Other than systematic blocks that
prevent signal contention, caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lockouts. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
11.5.3.4
To set or clear IOLOCK, a specific command sequence
must be executed:
Mapping Exceptions for Family
Devices
1.
2.
3.
The differences in available remappable pins are
summarized in Table 11-12.
Write 46h to OSCCON[7:0].
Write 57h to OSCCON[7:0].
Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence, followed by an update
to all control registers, then locked with a second lock
sequence.
When developing applications that use remappable
pins, users should also keep these things in mind:
• For the RPINRx registers, bit combinations corresponding to an unimplemented pin for a particular
device are treated as invalid; the corresponding
module will not have an input mapped to it.
• For RPORx registers, the bit fields corresponding
to an unimplemented pin will also be
unimplemented; writing to these fields will have
no effect.
11.5.4
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON[6]).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
11.5.4.2
Continuous State Monitoring
In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly
monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell
disturbances caused by ESD or other external events), a
Configuration Mismatch Reset will be triggered.
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
11.5.4.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY (FOSC[5])
Configuration bit blocks the IOLOCK bit from being
cleared after it has been set once. If IOLOCK remains
set, the register unlock procedure will not execute and
the Peripheral Pin Select Control registers cannot be
written to. The only way to clear the bit and re-enable
peripheral remapping is to perform a device Reset.
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the Peripheral
Pin Select registers.
TABLE 11-12: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GL306 FAMILY DEVICES
Device
RPn Pins (I/O)
RPIn Pins
Total
Unimplemented
Total
Unimplemented
PIC24FJXXXGL306
32
—
1
—
PIC24FJXXXGL305
24
—
1
—
PIC24FJXXXGL303
15
—
1
—
PIC24FJXXXGL302
13
—
1
—
2019-2020 Microchip Technology Inc.
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PIC24FJ128GL306 FAMILY
11.5.5
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
The ability to control Peripheral Pin Selection introduces several considerations into application design
that could be overlooked. This is particularly true for
several common peripherals that are available only as
remappable peripherals.
The main consideration is that the Peripheral Pin
Selects are not available on default pins in the device’s
default (Reset) state. Since all RPINRx registers reset
to ‘111111’ and all RPORx registers reset to ‘000000’,
all Peripheral Pin Select inputs are tied to VSS, and all
Peripheral Pin Select outputs are disconnected.
This situation requires the user to initialize the device
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK
bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
come out of Reset. For application safety, however, it is
best to set IOLOCK and lock the configuration after
writing to the control registers.
Because the unlock sequence is timing-critical, it must
be executed as an assembly language routine in the
same manner as changes to the oscillator configuration. If the bulk of the application is written in ‘C’, or
another high-level language, the unlock sequence
should be performed by writing in-line assembly.
Choosing the configuration requires the review of all
Peripheral Pin Selects and their pin assignments,
especially those that will not be used in the application.
In all cases, unused pin-selectable peripherals should
be disabled completely. Unused peripherals should
have their inputs assigned to an unused RPn/RPIn pin
function. I/O pins with unused RPn functions should be
configured with the null peripheral output.
The assignment of a peripheral to a particular pin does
not automatically perform any other configuration of the
pin’s I/O circuitry. In theory, this means adding a pinselectable output to a pin may mean inadvertently
driving an existing peripheral input when the output is
driven. Users must be familiar with the behavior of
other fixed peripherals that share a remappable pin and
know when to enable or disable them. To be safe, fixed
digital peripherals that share the same pin should be
disabled when not in use.
Along these lines, configuring a remappable pin for a
specific peripheral does not automatically turn that
feature on. The peripheral must be specifically configured for operation and enabled as if it were tied to a
fixed pin. Where this happens in the application code
(immediately following a device Reset and peripheral
configuration or inside the main application routine)
depends on the peripheral and its use in the
application.
DS30010198B-page 142
A final consideration is that Peripheral Pin Select functions neither override analog inputs nor reconfigure
pins with analog functions for digital I/Os. If a pin is
configured as an analog input on a device Reset, it
must be explicitly reconfigured as a digital I/O when
used with a Peripheral Pin Select.
Example 11-4 shows a configuration for bidirectional
communication with flow control using UART1. The
following input and output functions are used:
• Input Functions: U1RX, U1CTS
• Output Functions: U1TX, U1RTS
EXAMPLE 11-4:
CONFIGURING UART1
INPUT AND OUTPUT
FUNCTIONS
// Unlock Registers
asm volatile
("MOV
"MOV
"MOV
"MOV.b
"MOV.b
"BCLR
#OSCCON, w1
#0x46, w2
#0x57, w3
w2, [w1]
w3, [w1]
OSCCON, #6")
\n"
\n"
\n"
\n"
\n"
;
//
//
or use XC16 built-in macro:
__builtin_write_OSCCONL(OSCCON & 0xbf);
//
Configure Input Functions (Table 11-10)
// Assign U1RX To Pin RP0
RPINR18bits.U1RXR = 0;
// Assign U1CTS To Pin RP1
RPINR18bits.U1CTSR = 1;
//
Configure Output Functions (Table 11-11)
// Assign U1TX To Pin RP2
RPOR1bits.RP2R = 3;
// Assign U1RTS To Pin RP3
RPOR1bits.RP3R = 4;
// Lock Registers
asm volatile
("MOV
"MOV
"MOV
"MOV.b
"MOV.b
"BSET
//
//
#OSCCON, w1
#0x46, w2
#0x57, w3
w2, [w1]
w3, [w1]
OSCCON, #6")
\n"
\n"
\n"
\n"
\n"
;
or use XC16 built-in macro:
__builtin_write_OSCCONL(OSCCON | 0x40);
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
11.5.6
PERIPHERAL PIN SELECT
REGISTERS
Note:
The PIC24FJ128GL306 family of devices implements a
total of 36 registers for remappable peripheral
configuration:
Input and Output register values can only
be changed if IOLOCK (OSCCON[6]) = 0.
See Section 11.5.4.1 “Control Register
Lock” for a specific command sequence.
• Input Remappable Peripheral Registers (21)
• Output Remappable Peripheral Registers (15)
REGISTER 11-13: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT1R5
INT1R4
INT1R3
INT1R2
INT1R1
INT1R0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
INT1R[5:0]: Assign External Interrupt 1 (INT1) to the Corresponding RPn or RPIn Pin bits
bit 7-0
Unimplemented: Read as ‘0’
REGISTER 11-14: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT3R5
INT3R4
INT3R3
INT3R2
INT3R1
INT3R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT2R5
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
x = Bit is unknown
Unimplemented: Read as ‘0’
bit 13-8
INT3R[5:0]: Assign External Interrupt 3 (INT3) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
INT2R[5:0]: Assign External Interrupt 2 (INT2) to the Corresponding RPn or RPIn Pin bits
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REGISTER 11-15: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT4R5
INT4R4
INT4R3
INT4R2
INT4R1
INT4R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
INT4R[5:0]: Assign External Interrupt 4 (INT4) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-16: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T3CKR5
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T2CKR5
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
T3CKR[5:0]: Assign Timer3 Clock (T3CK) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
T2CKR[5:0]: Assign Timer2 Clock to (T2CK) the Corresponding RPn or RPIn Pin bits
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REGISTER 11-17: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T5CKR5
T5CKR4
T5CKR3
T5CKR2
T5CKR1
T5CKR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T4CKR5
T4CKR4
T4CKR3
T4CKR2
T4CKR1
T4CKR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
T5CKR[5:0]: Assign Timer5 Clock (T5CK) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
T4CKR[5:0]: Assign Timer4 Clock (T4CK) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-18: RPINR5: PERIPHERAL PIN SELECT INPUT REGISTER 5
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
ICM2R5
ICM2R4
ICM2R3
ICM2R2
ICM2R1
ICM2R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
ICM1R5
ICM1R4
ICM1R3
ICM1R2
ICM1R1
ICM1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
ICM2R[5:0]: Assign CCP2 Capture Mode (ICM2) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
ICM1R[5:0]: Assign CCP1 Capture Mode (ICM1) to the Corresponding RPn or RPIn Pin bits
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REGISTER 11-19: RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
ICM4R5
ICM4R4
ICM4R3
ICM4R2
ICM4R1
ICM4R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
ICM3R5
ICM3R4
ICM3R3
ICM3R2
ICM3R1
ICM3R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
ICM4R[5:0]: Assign CCP4 Capture Mode (ICM4) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
ICM3R[5:0]: Assign CCP3 Capture Mode (ICM3) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-20: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
OCFBR5
OCFBR4
OCFBR3
OCFBR2
OCFBR1
OCFBR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
OCFAR5
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
OCFBR[5:0]: Assign Output Compare Fault B (OCFB) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
OCFAR[5:0]: Assign Output Compare Fault A (OCFA) to the Corresponding RPn or RPIn Pin bits
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REGISTER 11-21: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
TCKIBR5
TCKIBR4
TCKIBR3
TCKIBR2
TCKIBR1
TCKIBR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
TCKIAR5
TCKIAR4
TCKIAR3
TCKIAR2
TCKIAR1
TCKIAR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
TCKIBR[5:0]: Assign MCCP Clock Input B (TCKIB) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
TCKIAR[5:0]: Assign MCCP Clock Input A (TCKIA) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-22: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
TMPRNR5
TMPRNR4
TMPRNR3
TMPRNR2
TMPRNR1
TMPRNR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
REFIR5
REFIR4
REFIR3
REFIR2
REFIR1
REFIR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
TMPRNR[5:0]: Assign Tamper Detect (TMPRN) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
REFIR[5:0]: Assign Reference Clock Input (REFI) to the Corresponding RPn or RPIn Pin bits
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REGISTER 11-23: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
ICM5R5
ICM5R4
ICM5R3
ICM5R2
ICM5R1
ICM5R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
ICM5R[5:0]: Assign CCP5 Capture Mode (ICM5) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-24: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U3RXR5
U3RXR4
U3RXR3
U3RXR2
U3RXR1
U3RXR0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
U3RXR[5:0]: Assign UART3 Receive (U3RX) to the Corresponding RPn or RPIn Pin bits
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 11-25: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U1CTSR5
U1CTSR4
U1CTSR3
U1CTSR2
U1CTSR1
U1CTSR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U1RXR5
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
U1CTSR[5:0]: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
U1RXR[5:0]: Assign UART1 Receive (U1RX) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-26: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U2CTSR5
U2CTSR4
U2CTSR3
U2CTSR2
U2CTSR1
U2CTSR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U2RXR5
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
U2CTSR[5:0]: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
U2RXR[5:0]: Assign UART2 Receive (U2RX) to the Corresponding RPn or RPIn Pin bits
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REGISTER 11-27: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SCK1R5
SCK1R4
SCK1R3
SCK1R2
SCK1R1
SCK1R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SDI1R5
SDI1R4
SDI1R3
SDI1R2
SDI1R1
SDI1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
SCK1R[5:0]: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
SDI1R[5:0]: Assign SPI1 Data Input (SDI1) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-28: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U3CTSR5
U3CTSR4
U3CTSR3
U3CTSR2
U3CTSR1
U3CTSR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SS1R5
SS1R4
SS1R3
SS1R2
SS1R1
SS1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
x = Bit is unknown
Unimplemented: Read as ‘0’
bit
U3CTSR[5:0]: Assign UART3 Receive (U3CTS) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
SS1R[5:0]: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn or RPIn Pin bits
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REGISTER 11-29: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SCK2R5
SCK2R4
SCK2R3
SCK2R2
SCK2R1
SCK2R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SDI2R5
SDI2R4
SDI2R3
SDI2R2
SDI2R1
SDI2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
SCK2R[5:0]: Assign SPI2 Clock Input (SCK2IN) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
SDI2R[5:0]: Assign SPI2 Data Input (SDI2) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-30: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
TXCKR5
TXCKR4
TXCKR3
TXCKR2
TXCKR1
TXCKR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SS2R5
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
TXCKR[5:0]: Assign Generic Timer External Clock (TxCK) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
SS2R[5:0]: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn or RPIn Pin bits
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REGISTER 11-31: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
CLCINBR5
CLCINBR4
CLCINBR3
CLCINBR2
CLCINBR1
CLCINBR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
CLCINAR5
CLCINAR4
CLCINAR3
CLCINAR2
CLCINAR1
CLCINAR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
CLCINBR[5:0]: Assign CLC Input B (CLCINB) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
CLCINAR[5:0]: Assign CLC Input A (CLCINA) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-32: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
CLCINDR5
CLCINDR4
CLCINDR3
CLCINDR2
CLCINDR1
CLCINDR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
CLCINCR5
CLCINCR4
CLCINCR3
CLCINCR2
CLCINCR1
CLCINCR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
CLCINDR[5:0]: Assign CLC Input D (CLCIND) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
CLCINCR[5:0]: Assign CLC Input C (CLCINC) to the Corresponding RPn or RPIn Pin bits
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REGISTER 11-33: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U4CTSR5
U4CTSR4
U4CTSR3
U4CTSR2
U4CTSR1
U4CTSR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U4RXR5
U4RXR4
U4RXR3
U4RXR2
U4RXR1
U4RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
U4CTSR[5:0]: Assign UART4 Clear-to-Send (U4CTS) to the Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
U4RXR[5:0]: Assign UART4 Receive (U4RX) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-34: RPORx: PERIPHERAL PIN SELECT OUTPUT REGISTER x
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RPaR5
RPaR4
RPaR3
RPaR2
RPaR1
RPaR0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RPbR5
RPbR4
RPbR3
RPbR2
RPbR1
RPbR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RPaR[5:0]: RPa Output Pin Mapping bits
Peripheral Output Number y is assigned to pin, RPa (see Table 11-11 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RPbR[5:0]: RPb Output Pin Mapping bits
Peripheral Output Number y is assigned to pin, RPb (see Table 11-11 for peripheral function numbers).
2019-2020 Microchip Technology Inc.
DS30010198B-page 153
Register
Address
Bit 15
Bit 14
Bit 13
2019-2020 Microchip Technology Inc.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPINR0
790h
—
—
RPINR1
792h
—
—
INT1R[5:0]
—
—
—
—
—
—
—
—
INT3R[5:0]
—
—
RPINR2
794h
—
—
RPINR3
796h
—
—
T3CKR[5:0]
—
—
INT4R[5:0]
—
—
T2CKR[5:0]
RPINR4
798h
—
—
RPINR5
79Ah
—
—
T5CKR[5:0]
—
—
T4CKR[5:0]
ICM2R[5:0]
—
—
RPINR6
79Ch
—
—
ICM1R[5:0]
ICM4R[5:0]
—
—
RPINR7
79Eh
—
—
—
—
—
—
—
—
—
—
—
—
—
RPINR8
7A0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPINR9
7A2h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPINR10
7A4h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPINR11
7A6h
—
—
—
OCFBR[5:0]
—
—
OCFAR[5:0]
RPINR12
7A8h
—
RPINR13
7AAh
—
—
TCKIBR[5:0]
—
—
TCKIAR[5:0]
—
TMPRNR[5:0]
—
—
RPINR14
7ACh
—
—
—
—
—
—
—
REFI1R[5:0]
—
—
—
RPINR15
7AEh
—
—
—
—
—
—
—
—
—
—
—
—
—
RPINR16
7B0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPINR17
7B2h
—
—
—
U3RXR[5:0]
—
—
—
—
—
—
—
RPINR18
7B4h
—
—
—
U1CTSR[5:0]
—
—
U1RXR[5:0]
RPINR19
7B6h
RPINR20
7B8h
—
—
U2CTSR[5:0]
—
—
U2RXR[5:0]
—
—
SCK1R[5:0]
—
—
RPINR21
SDI1R[5:0]
7BAh
—
—
U3CTSR[5:0]
—
—
SS1R[5:0]
RPINR22
7BCh
—
—
SCK2R[5:0]
—
—
SDI2R[5:0]
RPINR23
7BEh
—
—
—
—
RPINR24
7C0h
—
—
—
—
—
—
RPINR25
7C2h
—
—
CLCINBR[5:0]
—
—
CLCINAR[5:0]
RPINR26
7C4h
—
—
CLCINDR[5:0]
—
—
CLCINCR[5:0]
RPINR27
7C6h
—
—
U4CTSR[5:0]
—
—
U4RXR[5:0]
—
Bit 12
—
Bit 11
—
Bit 10
—
Bit 9
—
Bit 8
—
TXCKR[5:0]
—
—
—
—
—
—
INT2R[5:0]
ICM3R[5:0]
ICM5R[5:0]
SS2R[5:0]
—
—
—
—
PIC24FJ128GL306 FAMILY
DS30010198B-page 154
TABLE 11-13: PPS INPUT CONTROL FOR RPINR REGISTERS
2019-2020 Microchip Technology Inc.
TABLE 11-14: PPS OUTPUT CONTROL FOR RPOR REGISTERS
Register
Address
Bit 15
Bit 14
RPOR0
7D4h
—
—
RPOR1
7D6h
—
—
RPOR2
7D8h
—
RPOR3
7DAh
RPOR4
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RP1R[5:0]
—
—
RP0R[5:0]
RP3R[5:0]
—
—
RP2R[5:0]
—
RP5R[5:0]
—
—
RP4R[5:0]
—
—
RP7R[5:0]
—
—
RP6R[5:0]
7DCh
—
—
RP9R[5:0]
—
—
RP8R[5:0]
RPOR5
7DEh
—
—
RP11R[5:0]
—
—
RP10R[5:0]
RPOR6
7E0h
—
—
RP13R[5:0]
—
—
RP12R[5:0]
RPOR7
7E2h
—
—
RP15R[5:0]
—
—
RP14R[5:0]
RPOR8
7E4h
—
—
RP17R[5:0]
—
—
RP16R[5:0]
RPOR9
7E6h
—
—
RP19R[5:0]
—
—
RP18R[5:0]
RPOR10
7E8h
—
—
RP21R[5:0]
—
—
RP20R[5:0]
RPOR11
7EAh
—
—
RP23R[5:0]
—
—
RP22R[5:0]
RPOR12
7ECh
—
—
RP25R[5:0]
—
—
RP24R[5:0]
RPOR13
7EEh
—
—
RP27R[5:0]
—
—
RP26R[5:0]
RPOR14
7F0h
—
—
RP29R[5:0]
—
—
RP28R[5:0]
RPOR15
7F2h
—
—
RP31R[5:0]
—
—
RP30R[5:0]
Bit 1
Bit 0
PIC24FJ128GL306 FAMILY
DS30010198B-page 155
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 156
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
12.0
TIMER1
Note:
Figure 12-1 presents a block diagram of the 16-bit
timer module.
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive reference source. For more information,
refer to “Timers” (www.microchip.com/
DS39704) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in
this data sheet supersedes the
information in the FRM.
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the Real-Time Clock (RTC) or
operate as a free-running, interval timer/counter.
Timer1 can operate in three modes:
• 16-Bit Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
To configure Timer1 for operation:
1.
2.
3.
4.
5.
6.
Set the TON bit (= 1).
Select the timer prescaler ratio using the
TCKPS[1:0] bits.
Set the Clock and Gating modes using the TCS,
TECS[1:0] and TGATE bits.
Set or clear the TSYNC bit to configure
synchronous or asynchronous operation.
Load the timer period value into the PR1
register.
If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP[2:0], to set
the interrupt priority.
Timer1 also supports these features:
•
•
•
•
Timer Gate Operation
Selectable Prescaler Settings
Timer Operation during CPU Idle and Sleep modes
Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TGATE
LPRC
Clock
Input Select
SOSCO
D
Q
1
CK
Q
0
TMR1
SOSCI
Comparator
SOSCSEL
SOSCEN
Set T1IF
Reset
Equal
PR1
Clock Input Select Detail
SOSC
Input
TECS[1:0]
2
Gate
Output
TON
T1CK Input
LPRC Input
Prescaler
1, 8, 64, 256
Gate
Sync
TxCK Input
0
Sync
TCY
TGATE
TCS
2019-2020 Microchip Technology Inc.
TCKPS[1:0]
2
1
Clock
Output
to TMR1
TSYNC
DS30010198B-page 157
PIC24FJ128GL306 FAMILY
T1CON: TIMER1 CONTROL REGISTER(1)
REGISTER 12-1:
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
TON
—
TSIDL
—
—
—
TECS1
TECS0
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timer1 On bit
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9-8
TECS[1:0]: Timer1 Extended Clock Source Select bits (selected when TCS = 1)
11 = Generic timer (TxCK) external input
10 = LPRC Oscillator
01 = T1CK External Clock input
00 = SOSC
bit 7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS[1:0]: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronizes the External Clock input
0 = Does not synchronize the External Clock input
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer1 Clock Source Select bit
1 = Extended clock is selected by the timer
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
DS30010198B-page 158
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
13.0
Note:
TIMER2/3 AND TIMER4/5
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive reference source. For more information, refer to
“Timers” (www.microchip.com/DS39704)
in the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as independent, 16-bit
timers with selectable operating modes.
To configure Timer2/3 or Timer4/5 for 32-bit operation:
1.
2.
3.
4.
As a 32-bit timer, Timer2/3 or Timer4/5 can operate in
three modes:
• Two Independent 16-Bit Timers with All 16-Bit
Operating modes (except Asynchronous Counter
mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
They also support these features:
•
•
•
•
•
Timer Gate Operation
Selectable Prescaler Settings
Timer Operation during Idle and Sleep modes
Interrupt on a 32-Bit Period Register Match
A/D Event Trigger (on Timer4/5 in 32-bit mode
and Timer5 in 16-bit mode)
Individually, all of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the A/D event trigger.
This trigger is implemented only on Timer4/5 in 32-bit
mode and Timer5 in 16-bit mode. The operating modes
and enabled features are determined by setting the
appropriate bit(s) in the T2CON, T3CON, T4CON and
T5CON registers. T2CON and T4CON are shown in
generic form in Register 13-1; T3CON and T5CON are
shown in Register 13-2.
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word; Timer3 and Timer5 are
the most significant word of the 32-bit timer.
Note:
5.
6.
Set the T32 bit (T2CON[3] = 1 or
T4CON[3] = 1).
Select the prescaler ratio for Timer2 or Timer4
using the TCKPS[1:0] bits.
Set the Clock and Gating modes using the TCS
and TGATE bits. If TCS is set to an External
Clock, RPINRx (TyCK) must be configured to
an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select
(PPS)”.
Load the timer period value. PR3 or PR5 will
contain the most significant word (msw) of the
value, while PR2 or PR4 contains the least
significant word (lsw).
If interrupts are required, set the interrupt enable
bit, T3IE or T5IE. Use the priority bits, T3IP[2:0] or
T5IP[2:0], to set the interrupt priority. Note that
while Timer2 or Timer4 controls the timer, the
interrupt appears as a Timer3 or Timer5 interrupt.
Set the TON bit (= 1).
The timer value, at any point, is stored in the register
pair, TMR[3:2] (or TMR[5:4]). TMR3 (or TMR5) always
contains the most significant word of the count, while
TMR2 (or TMR4) contains the least significant word.
To configure any of the timers for individual 16-bit
operation:
1.
2.
3.
4.
5.
6.
Clear the T32 bit (T2CON[3] for Timer2 and
Timer3 or T4CON[3] for Timer4 and Timer5).
Select the timer prescaler ratio using the
TCKPS[1:0] bits.
Set the Clock and Gating modes using the TCS
and TGATE bits. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
Load the timer period value into the PRx register.
If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP[2:0], to set
the interrupt priority.
Set the TON bit (TxCON[15] = 1).
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clocks, and
gate inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
2019-2020 Microchip Technology Inc.
DS30010198B-page 159
PIC24FJ128GL306 FAMILY
FIGURE 13-1:
TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCY
T2CK (T4CLK)
TCKPS[1:0]
TxCK
2
SOSC Input
LPRC Input
Prescaler
1, 8, 64, 256
Gate
Sync
TECS[1:0]
TGATE(2)
TCS(2)
TGATE
1
Q
0
Q
D
Set T3IF (T5IF)
PR3
(PR5)
Equal
A/D Event
CK
PR2
(PR4)
Comparator
Trigger(3)
MSB
LSB
TMR3
(TMR5)
Reset
TMR2
(TMR4)
Sync
16
Read TMR2 (TMR4)
(1)
Write TMR2 (TMR4)(1)
16
TMR3HLD
(TMR5HLD)
16
Data Bus[15:0]
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
3: The A/D event trigger is available only on Timer4/5 in 32-bit mode and Timer4 in 16-bit mode.
DS30010198B-page 160
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 13-2:
TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCY
T2CK (T4CLK)
TxCK
TON
TCKPS[1:0]
2
SOSC Input
LPRC Input
Prescaler
1, 8, 64, 256
Gate
Sync
TECS[1:0]
TGATE(1)
TCS(1)
TGATE
1
Q
D
0
Q
CK
Set T2IF (T4IF)
Reset
Equal
Sync
TMR2 (TMR4)
Comparator
PR2 (PR4)
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
FIGURE 13-3:
TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TCY
T3CK (T5CLK)
TxCK
TON
TCKPS[1:0]
2
SOSC Input
LPRC Input
Prescaler
1, 8, 64, 256
Gate
Sync
TGATE
TECS[1:0]
1
Set T3IF (T5IF)
0
Reset
A/D Event Trigger(2)
Equal
TGATE(1)
TCS(1)
Q
D
Q
CK
TMR3 (TMR5)
Comparator
PR3 (PR5)
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
2: The A/D event trigger is available only on Timer5.
2019-2020 Microchip Technology Inc.
DS30010198B-page 161
PIC24FJ128GL306 FAMILY
TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1)
REGISTER 13-1:
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
TON
—
TSIDL
—
—
—
TECS1(2)
TECS0(2)
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
T32(3)
—
TCS(2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timerx On bit
When TxCON[3] = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When TxCON[3] = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9-8
TECS[1:0]: Timerx Extended Clock Source Select bits (selected when TCS = 1)(2)
When TCS = 1:
11 = Generic timer (TxCK) external input
10 = LPRC Oscillator
01 = TyCK External Clock input
00 = SOSC
When TCS = 0:
These bits are ignored; the timer is clocked from the internal system clock (FOSC/2).
bit 7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS[1:0]: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
Note 1:
2:
3:
Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
If TCS = 1 and TECS[1:0] = x1, the selected external timer input (TxCK or TyCK) must be configured to an
available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
In 32-bit mode, the T3CON and T5CON control bits do not affect 32-bit timer operation.
DS30010198B-page 162
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 13-1:
TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1) (CONTINUED)
bit 3
T32: 32-Bit Timer Mode Select bit(3)
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timerx Clock Source Select bit(2)
1 = Timer source is selected by TECS[1:0]
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
If TCS = 1 and TECS[1:0] = x1, the selected external timer input (TxCK or TyCK) must be configured to an
available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
In 32-bit mode, the T3CON and T5CON control bits do not affect 32-bit timer operation.
2019-2020 Microchip Technology Inc.
DS30010198B-page 163
PIC24FJ128GL306 FAMILY
TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(1)
REGISTER 13-2:
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
TON(2)
—
TSIDL(2)
—
—
—
TECS1(2,3)
TECS0(2,3)
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
—
TGATE(2)
TCKPS1(2)
TCKPS0(2)
—
—
TCS(2,3)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timery On bit(2)
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timery Stop in Idle Mode bit(2)
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9-8
TECS[1:0]: Timery Extended Clock Source Select bits (selected when TCS = 1)(2,3)
11 = Generic timer (TxCK) external input
10 = LPRC Oscillator
01 = TyCK External Clock input
00 = SOSC
bit 7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timery Gated Time Accumulation Enable bit(2)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS[1:0]: Timery Input Clock Prescale Select bits(2)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3-2
Unimplemented: Read as ‘0’
bit 1
TCS: Timery Clock Source Select bit(2,3)
1 = External clock from pin, TyCK (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
When 32-bit operation is enabled (T2CON[3] = 1 or T4CON[3] = 1), this bit has no effect on Timery
operation; all timer functions are set through T2CON and T4CON.
If TCS = 1 and TECS[1:0] = x1, the selected external timer input (TyCK) must be configured to an
available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
DS30010198B-page 164
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PIC24FJ128GL306 FAMILY
14.0
CAPTURE/COMPARE/PWM/
TIMER MODULES (MCCP)
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “Capture/Compare/PWM/Timer
(MCCP and SCCP)” (www.microchip.com/
DS30003035) in the “dsPIC33/PIC24 Family Reference Manual”. The information in
this data sheet supersedes the information
in the FRM.
PIC24FJ128GL306 family devices include several
Capture/Compare/PWM/Timer base modules, which
provide the functionality of three different peripherals of
earlier PIC24F devices. The module can operate in one
of three major modes:
• General Purpose Timer
• Input Capture
• Output Compare/PWM
This family of devices features five instances of the
MCCP module. MCCP1 provides up to six outputs and
an extended range of power control features, whereas
MCCP2-MCCP5 support two outputs.
The MCCPx modules can be operated only in one of
the three major modes at any time. The other modes
are not available unless the module is reconfigured for
the new mode.
FIGURE 14-1:
A conceptual block diagram for the module is shown in
Figure 14-1. All three modules share a time base generator and a common Timer register pair (CCPxTMRH/L);
other shared hardware components are added as a
particular mode requires.
Each module has a total of eight control and status
registers:
•
•
•
•
•
•
•
CCPxCON1L (Register 14-1)
CCPxCON1H (Register 14-2)
CCPxCON2L (Register 14-3)
CCPxCON2H (Register 14-4)
CCPxCON3L (Register 14-5)
CCPxCON3H (Register 14-6)
CCPxSTATL (Register 14-7)
Each module also includes eight buffer/counter
registers that serve as Timer Value registers or data
holding buffers:
• CCPxTMRH/CCPxTMRL (CCPx Timer High/Low
Counters)
• CCPxPRH/CCPxPRL (CCPx Timer Period High/
Low)
• CCPxRAH/CCPxRAL (CCPx Primary Output
Compare Data High/Low Buffers)
• CCPxRBH/CCPxRBL (CCPx Secondary Output
Compare Data High/Low Buffers)
• CCPxBUFH/CCPxBUFL (CCPx Input Capture
High/Low Buffers)
MCCPx CONCEPTUAL BLOCK DIAGRAM
CCPxIF
CCTxIF
External
Capture Input
Clock
Sources
Time Base
Generator
Input Capture
Special Trigger (to A/D)
CCPxTMRH/L
T32
CCSEL
MOD[3:0]
Sync and
Gating
Sources
Sync/Trigger Out
Compare/PWM
Output(s)
16/32-Bit
Timer
2019-2020 Microchip Technology Inc.
Output
Compare/PWM
OCFA/OCFB
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PIC24FJ128GL306 FAMILY
14.1
Time Base Generator
The Timer Clock Generator (TCG) generates a clock
for the module’s internal time base using one of the
clock signals already available on the microcontroller.
This is used as the time reference for the module in its
three major modes. The internal time base is shown in
Figure 14-2.
FIGURE 14-2:
There are eight inputs available to the clock generator,
which are selected using the CLKSEL[2:0] bits
(CCPxCON1L[10:8]). Available sources include the FRC
and LPRC, the Secondary Oscillator and the TCLKI
External Clock inputs. The system clock is the default
source (CLKSEL[2:0] = 000). On PIC24FJ128GL306
family devices, clock sources to the MCCPx modules
must be synchronized with the system clock. As a result,
when clock sources are selected, clock input timing
restrictions or module operating restrictions may exist.
TIMER CLOCK GENERATOR
Clock
Sources
TMRPS[1:0]
TMRSYNC
SSDG
Prescaler
Clock
Synchronizer
Gate(1)
To Rest
of Module
CLKSEL[2:0]
Note 1: Gating is available in Timer modes only.
DS30010198B-page 166
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PIC24FJ128GL306 FAMILY
14.2
General Purpose Timer
Timer mode is selected when CCSEL = 0 and
MOD[3:0] = 0000. The timer can function as a 32-bit
timer or a dual 16-bit timer, depending on the setting of
the T32 bit (Table 14-1).
TABLE 14-1:
TIMER OPERATION MODE
T32
(CCPxCON1L[5])
Operating Mode
0
Dual Timer Mode (16-bit)
1
Timer Mode (32-bit)
Dual 16-Bit Timer mode provides a simple timer function
with two independent 16-bit timer/counters. The primary
timer uses the CCPxTMRL and CCPxPRL registers.
Only the primary timer can interact with other modules
on the device. It generates the MCCPx Sync out signals
for use by other MCCPx modules. It can also use the
SYNC[4:0] bits’ signal generated by other modules.
The secondary timer uses the CCPxTMRH and
CCPxPRH registers. It is intended to be used only as a
periodic interrupt source for scheduling CPU events. It
does not generate an output Sync/trigger signal like the
primary time base. In Dual Timer mode, the CCPx Timer
Period High register, CCPxPRH, generates the MCCPx
compare event (CCPxIF) used by many other modules
on the device.
The 32-Bit Timer mode uses the CCPxTMRL and
CCPxTMRH registers, together, as a single 32-bit timer.
When CCPxTMRL overflows, CCPxTMRH increments
FIGURE 14-3:
by one. This mode provides a simple timer function
when it is important to track long time periods. Note that
the T32 bit (CCPxCON1L[5]) should be set before the
CCPxTMRL or CCPxPRH registers are written to
initialize the 32-bit timer.
14.2.1
SYNC AND TRIGGER OPERATION
In both 16-bit and 32-bit modes, the timer can also
function in either Synchronization (“Sync”) or Trigger
mode operation. Both use the SYNC[4:0] bits
(CCPxCON1H[4:0]) to determine the input signal source.
The difference is how that signal affects the timer.
In Sync operation, the Timer Reset or clear occurs when
the input selected by SYNC[4:0] is asserted. The timer
immediately begins to count again from zero unless it is
held for some other reason. Sync operation is used whenever the TRIGEN bit (CCPxCON1H[7]) is cleared. The
SYNC[4:0] bits can have any value except ‘11111’.
In Trigger mode operation, the timer is held in Reset
until the input selected by SYNC[4:0] is asserted; when
it occurs, the timer starts counting. Trigger operation is
used whenever the TRIGEN bit is set. In Trigger mode,
the timer will continue running after a trigger event as
long as the CCPTRIG bit (CCPxSTATL[7]) is set. To
clear CCPTRIG, the TRCLR bit (CCPxSTATL[5]) must
be set to clear the trigger event, reset the timer and
hold it at zero until another trigger event occurs. On
PIC24FJ128GL306 family devices, Trigger mode
operation can only be used when the system clock is
the time base source (CLKSEL[2:0] = 000).
DUAL 16-BIT TIMER MODE
CCPxPRL
Comparator
SYNC[4:0]
Sync/
Trigger
Control
CCPxTMRL
Comparator
Clock
Sources
Set CCTxIF
Special Event Trigger
Time Base
Generator
CCPxRB
CCPxTMRH
Comparator
Set CCPxIF
CCPxPRH
2019-2020 Microchip Technology Inc.
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FIGURE 14-4:
32-BIT TIMER MODE
SYNC[4:0]
Clock
Sources
Sync/
Trigger
Control
Time Base
Generator
CCPxTMRH
CCPxTMRL
Set CCTxIF
Comparator
CCPxPRH
14.3
Output Compare Mode
Output Compare mode compares the Timer register
value with the value of one or two Compare registers,
depending on its mode of operation. The Output
Compare x module, on compare match events, has the
ability to generate a single output transition or a train of
TABLE 14-2:
CCPxPRL
output pulses. Like most PIC® MCU peripherals, the
Output Compare x module can also generate interrupts
on a compare match event.
Table 14-2 shows the various modes available in
Output Compare modes.
OUTPUT COMPARE/PWM MODES
MOD[3:0]
(CCPxCON1L[3:0])
T32
(CCPxCON1L[5])
0001
0
Output High on Compare (16-bit)
0001
1
Output High on Compare (32-bit)
0010
0
Output Low on Compare (16-bit)
0010
1
Output Low on Compare (32-bit)
0011
0
Output Toggle on Compare (16-bit)
0011
1
Output Toggle on Compare (32-bit)
0100
0
Dual Edge Compare (16-bit)
0101
0
Dual Edge Compare (16-bit buffered)
PWM Mode
0110
0
Center-Aligned Pulse (16-bit buffered)(1)
Center PWM Mode
0111
0
Variable Frequency Pulse (16-bit)(1)
1111
0
External Input Source Mode (16-bit)
Note 1:
Operating Mode
Single Edge Mode
Dual Edge Mode
Available only on the MCCP1 module.
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PIC24FJ128GL306 FAMILY
FIGURE 14-5:
OUTPUT COMPARE x BLOCK DIAGRAM
CCPxCON1H/L
CCPxCON2H/L
CCPxPRL
CCPxCON3H/L
Comparator
CCPxRAH/L
Rollover/Reset
CCPxRA Buffer
Comparator
OCx Clock
Sources
Time Base
Generator
Increment
CCPxTMRH/L
Reset
Trigger and
Sync Sources
Trigger and
Sync Logic
Match Event
Comparator
Match
Event
Rollover
Match
Event
Edge
Detect
OCx Output,
Auto-Shutdown
and Polarity
Control
CCPx Pin(s)
OCFA/OCFB
Fault Logic
CCPxRB Buffer
Rollover/Reset
CCPxRBH/L
Reset
2019-2020 Microchip Technology Inc.
Output Compare
Interrupt
DS30010198B-page 169
PIC24FJ128GL306 FAMILY
14.4
Input Capture Mode
Input Capture mode is used to capture a timer value
from an independent timer base upon an event on an
input pin or other internal Trigger source. The input
capture features are useful in applications requiring
frequency (time period) and pulse measurement.
Figure 14-6 depicts a simplified block diagram of the
Input Capture mode.
TABLE 14-3:
Input Capture mode uses a dedicated 16/32-bit, synchronous, up counting timer for the capture function. The timer
value is written to the FIFO when a capture event occurs.
The internal value may be read (with a synchronization
delay) using the CCPxTMRH/L registers.
To use Input Capture mode, the CCSEL bit
(CCPxCON1L[4]) must be set. The T32 and MOD[3:0]
bits are used to select the proper Capture mode, as
shown in Table 14-3.
INPUT CAPTURE MODES
MOD[3:0]
(CCPxCON1L[3:0])
T32
(CCPxCON1L[5])
Operating Mode
0000
0
Edge Detect (16-bit capture)
0000
1
Edge Detect (32-bit capture)
0001
0
Every Rising (16-bit capture)
0001
1
Every Rising (32-bit capture)
0010
0
Every Falling (16-bit capture)
0010
1
Every Falling (32-bit capture)
0011
0
Every Rise/Fall (16-bit capture)
0011
1
Every Rise/Fall (32-bit capture)
0100
0
Every 4th Rising (16-bit capture)
0100
1
Every 4th Rising (32-bit capture)
0101
0
Every 16th Rising (16-bit capture)
0101
1
Every 16th Rising (32-bit capture)
FIGURE 14-6:
INPUT CAPTURE x BLOCK DIAGRAM
ICS[2:0]
Clock
Select
ICx Clock
Sources
MOD[3:0]
OPS[3:0]
Edge Detect Logic
and
Clock Synchronizer
Event and
Interrupt
Logic
Set CCPxIF
Increment
Reset
Trigger and
Sync Sources
Trigger and
Sync Logic
16
CCPxTMRH/L
4-Level FIFO Buffer
16
T32
16
CCPxBUFx
System Bus
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PIC24FJ128GL306 FAMILY
14.5
Auxiliary Output
The MCCPx modules have an auxiliary (secondary)
output that provides other peripherals access to internal module signals. The auxiliary output is intended to
connect to other MCCPx modules, or other digital
peripherals, to provide these types of functions:
The type of output signal is selected using the
AUXOUT[1:0] control bits (CCPxCON2H[4:3]). The
type of output signal is also dependent on the module
operating mode.
• Time Base Synchronization
• Peripheral Trigger and Clock Inputs
• Signal Gating
TABLE 14-4:
AUXILIARY OUTPUT
AUXOUT[1:0]
CCSEL
MOD[3:0]
Comments
00
x
xxxx
Auxiliary Output Disabled
No Output
01
0
0000
Time Base Modes
Time Base Period Reset or Rollover
Special Event Trigger Output
10
No Output
11
01
0
10
11
01
Signal Description
1
0001
through
1111
xxxx
Output Compare Modes
Time Base Period Reset or Rollover
Output Compare Event Signal
Output Compare Signal
Input Capture Modes
Time Base Period Reset or Rollover
10
Reflects the Value of the ICDIS bit
11
Input Capture Event Signal
2019-2020 Microchip Technology Inc.
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REGISTER 14-1:
CCPxCON1L: CCPx CONTROL 1 LOW REGISTERS
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCPON
—
CCPSIDL
CCPSLP
TMRSYNC
CLKSEL2
CLKSEL1
CLKSEL0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMRPS1
TMRPS0
T32
CCSEL
MOD3
MOD2
MOD1
MOD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CCPON: CCPx Module Enable bit
1 = Module is enabled with an operating mode specified by the MOD[3:0] control bits
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CCPSIDL: CCPx Stop in Idle Mode Bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
CCPSLP: CCPx Sleep Mode Enable bit
1 = Module continues to operate in Sleep modes
0 = Module does not operate in Sleep modes
bit 11
TMRSYNC: Time Base Clock Synchronization bit
1 = Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0 = Module time base clock is not synchronized to the internal system clocks
bit 10-8
CLKSEL[2:0]: CCPx Time Base Clock Select bits
111 = TCKIA pin
110 = TCKIB pin
101 = PLL clock
100 = 2x system clock
010 = SOSC clock
001 = Reference clock output
000 = System clock
For MCCP1 and MCCP5:
011 = CLC1 output
For MCCP2:
011 = CLC2 output
For MCCP3:
011 = CLC3 output
For MCCP4:
011 = CLC4 output
bit 7-6
TMRPS[1:0]: Time Base Prescale Select bits
11 = 1:64 Prescaler
10 = 1:16 Prescaler
01 = 1:4 Prescaler
00 = 1:1 Prescaler
Note 1:
Available only on the MCCP1 module.
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REGISTER 14-1:
CCPxCON1L: CCPx CONTROL 1 LOW REGISTERS (CONTINUED)
bit 5
T32: 32-Bit Time Base Select bit
1 = Uses 32-bit time base for timer, single edge output compare or input capture function
0 = Uses 16-bit time base for timer, single edge output compare or input capture function
bit 4
CCSEL: Capture/Compare Mode Select bit
1 = Input capture peripheral
0 = Output compare/PWM/timer peripheral (exact function is selected by the MOD[3:0] bits)
bit 3-0
MOD[3:0]: CCPx Mode Select bits
For CCSEL = 1 (Input Capture modes):
1xxx = Reserved
011x = Reserved
0101 = Capture every 16th rising edge
0100 = Capture every 4th rising edge
0011 = Capture every rising and falling edge
0010 = Capture every falling edge
0001 = Capture every rising edge
0000 = Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0 (Output Compare/Timer modes):
1111 = External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110 = Reserved
110x = Reserved
10xx = Reserved
0111 = Variable Frequency Pulse mode(1)
0110 = Center-Aligned Pulse Compare mode, buffered(1)
0101 = Dual Edge Compare mode, buffered
0100 = Dual Edge Compare mode
0011 = 16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010 = 16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001 = 16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000 = 16-Bit/32-Bit Timer mode, output functions are disabled
Note 1:
Available only on the MCCP1 module.
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REGISTER 14-2:
CCPxCON1H: CCPx CONTROL 1 HIGH REGISTERS
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
OPSSRC(1)
RTRGEN(2)
—
—
OPS3(3)
OPS2(3)
OPS1(3)
OPS0(3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRIGEN
ONESHOT
ALTSYNC
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OPSSRC: Output Postscaler Source Select bit(1)
1 = Output postscaler scales module trigger output events
0 = Output postscaler scales time base interrupt events
bit 14
RTRGEN: Retrigger Enable bit(2)
1 = Time base can be retriggered when the TRIGEN bit = 1
0 = Time base may not be retriggered when the TRIGEN bit = 1
bit 13-12
Unimplemented: Read as ‘0’
bit 11-8
OPS3[3:0]: CCPx Interrupt Output Postscale Select bits(3)
1111 = Interrupt every 16th time base period match
1110 = Interrupt every 15th time base period match
...
0100 = Interrupt every 5th time base period match
0011 = Interrupt every 4th time base period match or 4th input capture event
0010 = Interrupt every 3rd time base period match or 3rd input capture event
0001 = Interrupt every 2nd time base period match or 2nd input capture event
0000 = Interrupt after each time base period match or input capture event
bit 7
TRIGEN: CCPx Trigger Enable bit
1 = Trigger operation of time base is enabled
0 = Trigger operation of time base is disabled
bit 6
ONESHOT: One-Shot Mode Enable bit
1 = One-Shot Trigger mode is enabled; Trigger mode duration is set by the OSCNT[2:0] bits
0 = One-Shot Trigger mode is disabled
bit 5
ALTSYNC: CCPx Clock Select bit
1 = An alternate signal is used as the module synchronization output signal
0 = The module synchronization output signal is the Time Base Reset/rollover event
bit 4-0
SYNC[4:0]: CCPx Synchronization Source Select bits
See Table 14-5 for the definition of inputs.
Note 1:
2:
3:
This control bit has no function in Input Capture modes.
This control bit has no function when TRIGEN = 0.
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
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TABLE 14-5:
SYNCHRONIZATION SOURCES
SYNC[4:0]
Note 1:
Synchronization Source
11111
None; Timer with Rollover on CCPxPR Match or FFFFh
11110
Reserved
11101
Reserved
11100
Reserved
11011
A/D Start Conversion
11010
CMP3 Trigger
11001
CMP2 Trigger
11000
CMP1 Trigger
10111
Reserved
10110
Reserved
10101
Reserved
10100
Reserved
10011
CLC4 Out
10010
CLC3 Out
10001
CLC2 Out
10000
CLC1 Out
01111
Reserved
01110
Reserved
01101
Reserved
01100
Reserved
01011
INT2 Pad
01010
INT1 Pad
01001
INT0 Pad
01000
Reserved
00111
Reserved
00110
MCCP5 Sync Out
00101
MCCP4 Sync Out
00100
MCCP3 Sync Out
00011
MCCP2 Sync Out
00010
MCCP1 Sync Out
00001
MCCPx Sync Out(1)
00000
MCCPx Timer Sync Out(1)
CCP1 when connected to CCP1, CCP2 when connected to CCP2, etc.
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REGISTER 14-3:
CCPxCON2L: CCPx CONTROL 2 LOW REGISTERS
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
PWMRSEN
ASDGM
—
SSDG
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ASDG7
ASDG6
ASDG5
ASDG4
ASDG3
ASDG2
ASDG1
ASDG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PWMRSEN: CCPx PWM Restart Enable bit
1 = ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input
has ended
0 = ASEVT bit must be cleared in software to resume PWM activity on output pins
bit 14
ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit
1 = Waits until the next Time Base Reset or rollover for shutdown to occur
0 = Shutdown event occurs immediately
bit 13
Unimplemented: Read as ‘0’
bit 12
SSDG: CCPx Software Shutdown/Gate Control bit
1 = Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of
ASDGM bit still applies)
0 = Normal module operation
bit 11-8
Unimplemented: Read as ‘0’
bit 7-0
ASDG[7:0]: CCPx Auto-Shutdown/Gating Source Enable bits
1 = ASDGx Source n is enabled (see Table 14-6 for auto-shutdown/gating sources)
0 = ASDGx Source n is disabled
TABLE 14-6:
ASDG[7:0]
AUTO-SHUTDOWN SOURCES
Auto-Shutdown Source
MCCP1
MCCP2
MCCP3
MCCP4
MCCP5
OCFB
1xxx xxxx
OCFA
x1xx xxxx
xx1x xxxx
CLC1
CLC2
CLC3
CLC4
CLC1
xxx1 xxxx
MCCP2 OCM Out
MCCP1 OCM Out
MCCP1 OCM Out
MCCP1 OCM Out
MCCP1 OCM Out
xxxx 1xxx
MCCP3 OCM Out
MCCP3 OCM Out
MCCP4 OCM Out
MCCP5 OCM Out
MCCP2 OCM Out
xxxx x1xx
CMP3 Out
xxxx xx1x
CMP2 Out
xxxx xxx1
CMP1 Out
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REGISTER 14-4:
CCPxCON2H: CCPx CONTROL 2 HIGH REGISTERS
R/W-0
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0
R/W-1
OENSYNC
—
OCFEN
OCEEN
OCDEN
OCCEN
OCBEN
OCAEN
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ICGSM1
ICGSM0
—
AUXOUT1
AUXOUT0
ICS2
ICS1
ICS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OENSYNC: Output Enable Synchronization bit
1 = Update by output enable bits occurs on the next Time Base Reset or rollover
0 = Update by output enable bits occurs immediately
bit 14
Unimplemented: Read as ‘0’
bit 13-8
OC[F:A]EN: Output Enable/Steering Control bits(1)
1 = OCMnx pin is controlled by the CCPx module and produces an output compare or PWM signal
0 = OCMnx pin is not controlled by the CCPx module; the pin is available to the port logic or another
peripheral multiplexed on the pin
bit 7-6
ICGSM[1:0]: Input Capture Gating Source Mode Control bits
11 = Reserved
10 = One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01 = One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00 = Level-Sensitive mode: A high level from gating source will enable future capture events; a low
level will disable future capture events
bit 5
Unimplemented: Read as ‘0’
bit 4-3
AUXOUT[1:0]: Auxiliary Output Signal on Event Selection bits
11 = Input capture or output compare event; no signal in Timer mode
10 = Signal output is defined by module operating mode (see Table 14-4)
01 = Time base rollover event (all modes)
00 = Disabled
bit 2-0
ICS[2:0]: Input Capture Source Select bits
111 = CLC4 output
110 = CLC3 output
101 = CLC2 output
100 = CLC1 output
011 = Comparator 3 output
010 = Comparator 2 output
001 = Comparator 1 output
000 = Input Capture x (ICMx) I/O pin
Note 1:
The OC[F:C]EN bits are available only on the MCCP1 module.
2019-2020 Microchip Technology Inc.
DS30010198B-page 177
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REGISTER 14-5:
CCPxCON3L: CCPx CONTROL 3 LOW REGISTERS
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DT[5:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
DT[5:0]: CCPx Dead-Time Select bits
111111 = Inserts 63 dead-time delay periods between complementary output signals
111110 = Inserts 62 dead-time delay periods between complementary output signals
...
000010 = Inserts 2 dead-time delay periods between complementary output signals
000001 = Inserts 1 dead-time delay period between complementary output signals
000000 = Dead-time logic is disabled
DS30010198B-page 178
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PIC24FJ128GL306 FAMILY
REGISTER 14-6:
CCPxCON3H: CCPx CONTROL 3 HIGH REGISTERS
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
OETRIG
OSCNT2
OSCNT1
OSCNT0
—
OUTM2
OUTM1
OUTM0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
POLACE
POLBDF
PSSACE1
PSSACE0
PSSBDF1
PSSBDF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OETRIG: CCPx Dead-Time Select bit
1 = For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0 = Normal output pin operation
bit 14-12
OSCNT[2:0]: One-Shot Event Count bits
111 = Extends one-shot event by 7 time base periods (8 time base periods total)
110 = Extends one-shot event by 6 time base periods (7 time base periods total)
101 = Extends one-shot event by 5 time base periods (6 time base periods total)
100 = Extends one-shot event by 4 time base periods (5 time base periods total)
011 = Extends one-shot event by 3 time base periods (4 time base periods total)
010 = Extends one-shot event by 2 time base periods (3 time base periods total)
001 = Extends one-shot event by 1 time base period (2 time base periods total)
000 = Does not extend one-shot trigger event
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OUTM[2:0]: PWMx Output Mode Control bits
111 = Reserved
110 = Output Scan mode
101 = Brush DC Output mode, forward
100 = Brush DC Output mode, reverse
011 = Reserved
010 = Half-Bridge Output mode
001 = Push-Pull Output mode
000 = Steerable Single Output mode
bit 7-6
Unimplemented: Read as ‘0’
bit 5
POLACE: CCPx Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
1 = Output pin polarity is active-low
0 = Output pin polarity is active-high
bit 4
POLBDF: CCPx Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
1 = Output pin polarity is active-low
0 = Output pin polarity is active-high
bit 3-2
PSSACE[1:0]: PWMx Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
11 = Pins are driven active when a shutdown event occurs
10 = Pins are driven inactive when a shutdown event occurs
0x = Pins are tri-stated when a shutdown event occurs
bit 1-0
PSSBDF[1:0]: PWMx Output Pins, OCMxB, OCMxD, and OCMxF, Shutdown State Control bits
11 = Pins are driven active when a shutdown event occurs
10 = Pins are driven inactive when a shutdown event occurs
0x = Pins are in a high-impedance state when a shutdown event occurs
2019-2020 Microchip Technology Inc.
DS30010198B-page 179
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REGISTER 14-7:
CCPxSTATL: CCPx STATUS REGISTER LOW
U-0
U-0
U-0
U-0
U-0
W-0
U-0
U-0
—
—
—
—
—
ICGARM
—
—
bit 15
bit 8
R-0
W1-0
W1-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
CCPTRIG
TRSET
TRCLR
ASEVT
SCEVT
ICDIS
ICOV
ICBNE
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
R = Readable bit
W1 = Write ‘1’ Only bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10
ICGARM: Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when
ICGSM[1:0] = 01 or 10; read as ‘0’.
bit 9-8
Unimplemented: Read as ‘0’
bit 7
CCPTRIG: CCPx Trigger Status bit
1 = Timer has been triggered and is running
0 = Timer has not been triggered and is held in Reset
bit 6
TRSET: CCPx Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
bit 5
TRCLR: CCPx Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
bit 4
ASEVT: CCPx Auto-Shutdown Event Status/Control bit
1 = A shutdown event is in progress; CCPx outputs are in the Shutdown state
0 = CCPx outputs operate normally
bit 3
SCEVT: Single Edge Compare Event Status bit
1 = A single edge compare event has occurred
0 = A single edge compare event has not occurred
bit 2
ICDIS: Input Capture x Disable bit
1 = Event on Input Capture x pin (ICMx) does not generate a capture event
0 = Event on Input Capture x pin will generate a capture event
bit 1
ICOV: Input Capture x Buffer Overflow Status bit
1 = The Input Capture x FIFO buffer has overflowed
0 = The Input Capture x FIFO buffer has not overflowed
bit 0
ICBNE: Input Capture x Buffer Status bit
1 = Input Capture x buffer has data available
0 = Input Capture x buffer is empty
DS30010198B-page 180
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PIC24FJ128GL306 FAMILY
15.0
Note:
SERIAL PERIPHERAL
INTERFACE (SPI)
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. To complement the information in this data sheet, refer to “Serial
Peripheral Interface (SPI) with Audio
Codec Support” (www.microchip.com/
DS70005136) in the “dsPIC33/PIC24
Family Reference Manual”. The information in this data sheet supersedes the
information in the FRM.
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift
registers, display drivers, A/D Converters, etc. The SPI
module is compatible with the Motorola® SPI and SIOP
interfaces. All devices in the PIC24FJ128GL306 family
include two SPI modules.
The module supports operation in two buffer modes. In
Standard Buffer mode, datum is shifted through a
single serial buffer. In Enhanced Buffer mode, data are
shifted through a FIFO buffer. The FIFO level depends
on the configured mode.
Note:
The SPI serial interface consists of four pins:
•
•
•
•
The SPI module can be configured to operate using
two, three or four pins. In the 3-pin mode, SSx is not
used. In the 2-pin mode, both SDOx and SSx are not
used.
The SPI module has the ability to generate three interrupts reflecting the events that occur during the data
communication. The following types of interrupts can
be generated:
1.
2.
FIFO depth for this device is 32 (in 8-Bit
Data mode).
Do not perform Read-Modify-Write operations (such as bit-oriented instructions) on
the SPIxBUF register in either Standard or
Enhanced Buffer mode.
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
The module also supports Audio modes. Four different
Audio modes are available.
•
•
•
•
I2S mode
Left Justified mode
Right Justified mode
PCM/DSP mode
In each of these modes, the serial clock is free-running
and audio data are always transferred.
If an audio protocol data transfer takes place between
two devices, then usually one device is the Master and
the other is the Slave. However, audio data can be
transferred between two Slaves. Because the audio
protocols require free-running clocks, the Master can
be a third party controller. In either case, the Master
generates two free-running clocks: SCKx and LRC
(Left, Right Channel Clock/SSx/FSYNC).
2019-2020 Microchip Technology Inc.
Receive interrupts are signalled by SPIxRXIF.
This event occurs when:
- RX watermark interrupt
- SPIROV = 1
- SPIRBF = 1
- SPIRBE = 1
provided the respective mask bits are enabled in
SPIxIMSKL/H.
Variable length data can be transmitted and received
from 2 to 32 bits.
Note:
SDIx: Serial Data Input
SDOx: Serial Data Output
SCKx: Shift Clock Input or Output
SSx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
Transmit interrupts are signalled by SPIxTXIF.
This event occurs when:
- TX watermark interrupt
- SPITUR = 1
- SPITBF = 1
- SPITBE = 1
provided the respective mask bits are enabled in
SPIxIMSKL/H.
3.
General interrupts are signalled by SPIxIF. This
event occurs when
- FRMERR = 1
- SPIBUSY = 1
- SRMT = 1
provided the respective mask bits are enabled in
SPIxIMSKL/H.
A block diagram of the module in Enhanced Buffer mode
is shown in Figure 15-1.
Note:
In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1 or SPI2. Special Function Registers will follow a similar notation. For
example, SPIxCON1 and SPIxCON2
refer to the control registers for either of
the two SPI modules.
DS30010198B-page 181
PIC24FJ128GL306 FAMILY
15.1
Master Mode Operation
Perform the following steps to set up the SPIx module
for Master mode operation:
1.
Disable the SPIx interrupts in the respective
IECx register.
2. Stop and reset the SPIx module by clearing the
SPIEN bit.
3. Clear the receive buffer.
4. Clear the ENHBUF bit (SPIxCON1L[0]) if using
Standard Buffer mode or set the bit if using
Enhanced Buffer mode.
5. If SPIx interrupts are not going to be used, skip
this step. Otherwise, the following additional
steps are performed:
a) Clear the SPIx interrupt flags/events in the
respective IFSx register.
b) Write the SPIx interrupt priority and
sub-priority bits in the respective IPCx
register.
c) Set the SPIx interrupt enable bits in the
respective IECx register.
6. Write the Baud Rate register, SPIxBRGL.
7. Clear the SPIROV bit (SPIxSTATL[6]).
8. Write the desired settings to the SPIxCON1L
register with MSTEN (SPIxCON1L[5]) = 1.
9. Enable SPI operation by setting the SPIEN bit
(SPIxCON1L[15]).
10. Write the data to be transmitted to the
SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data
are written to the SPIxBUFL/H registers.
15.2
Slave Mode Operation
The following steps are used to set up the SPIx module
for the Slave mode of operation:
1.
2.
3.
4.
5.
If using interrupts, disable the SPIx interrupts in
the respective IECx register.
Stop and reset the SPIx module by clearing the
SPIEN bit.
Clear the receive buffer.
Clear the ENHBUF bit (SPIxCON1L[0]) if using
Standard Buffer mode or set the bit if using
Enhanced Buffer mode.
If using interrupts, the following additional steps
are performed:
a) Clear the SPIx interrupt flags/events in the
respective IFSx register.
b) Write the SPIx interrupt priority and
sub-priority bits in the respective IPCx
register.
c) Set the SPIx interrupt enable bits in the
respective IECx register.
DS30010198B-page 182
6.
7.
8.
9.
Clear the SPIROV bit (SPIxSTATL[6]).
Write the desired settings to the SPIxCON1L
register with MSTEN (SPIxCON1L[5]) = 0.
Enable SPI operation by setting the SPIEN bit
(SPIxCON1L[15]).
Transmission (and reception) will start as soon
as the Master provides the serial clock.
The following additional features are provided in
Slave mode:
• Slave Select Synchronization:
The SSx pin allows a Synchronous Slave mode. If
the SSEN bit (SPIxCON1L[7]) is set, transmission
and reception are enabled in Slave mode only if
the SSx pin is driven to a low state. The port output or other peripheral outputs must not be driven
in order to allow the SSx pin to function as an
input. If the SSEN bit is set and the SSx pin is
driven high, the SDOx pin is no longer driven and
will tri-state, even if the module is in the middle of
a transmission. An aborted transmission will be
tried again the next time the SSx pin is driven low
using the data held in the SPIxTXB register. If the
SSEN bit is not set, the SSx pin does not affect
the module operation in Slave mode.
• SPITBE Status Flag Operation:
The SPITBE bit (SPIxSTATL[3]) has a different
function in the Slave mode of operation. The
following describes the function of SPITBE for
various settings of the Slave mode of operation:
- If SSEN (SPIxCON1L[7]) is cleared, the
SPITBE bit is cleared when SPIxBUF is
loaded by the user code. It is set when the
module transfers SPIxTXB to SPIxTXSR.
This is similar to the SPITBE bit function in
Master mode.
- If SSEN is set, SPITBE is cleared when
SPIxBUF is loaded by the user code. However, it is set only when the SPIx module
completes data transmission. A transmission
will be aborted when the SSx pin goes high
and may be retried at a later time. So, each
data word is held in SPIxTXB until all bits are
transmitted to the receiver.
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 15-1:
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Internal
Data Bus
Write
Read
SPIxRXB
SPIxTXB
SPIxURDT
MSB
Transmit
Receive
SPIxTXSR
SPIxRXSR
SDIx
MSB
0
Shift
Control
SDOx
SSx/FSYNC
SSx and
FSYNC Control
Clock
Control
1
TXELM[5:0] = 6’b0
URDTEN
Edge
Select
MCLKEN
Baud Rate
Generator
SCKx
Edge
Select
15.3
Clock
Control
Audio Mode Operation
To initialize the SPIx module for Audio mode, follow the
steps to initialize it for Master/Slave mode, but also set the
AUDEN bit (SPIxCON1H[15]). In Master+Audio mode:
• This mode enables the device to generate SCKx
and LRC pulses as long as the SPIEN bit
(SPIxCON1L[15]) = 1.
• The SPIx module generates LRC and SCKx
continuously, in all cases, regardless of the
transmit data while in Master mode.
• The SPIx module drives the leading edge of LRC
and SCKx within one SCKx period, and the serial
data shift in and out continuously, even when the
TX FIFO is empty.
2019-2020 Microchip Technology Inc.
REFO
Peripheral Clock
Enable Master Clock
In Slave+Audio mode:
• This mode enables the device to receive SCKx
and LRC pulses as long as the SPIEN bit
(SPIxCON1L[15]) = 1.
• The SPIx module drives zeros out of SDOx, but
does not shift data out or in (SDIx) until the
module receives the LRC (i.e., the edge that
precedes the left channel).
• Once the module receives the leading edge
of LRC, it starts receiving data if
DISSDI (SPIxCON1L[4]) = 0 and the serial data
shift out continuously, even when the TX FIFO is
empty.
DS30010198B-page 183
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15.4
SPI Control Registers
REGISTER 15-1:
R/W-0
SPIxCON1L: SPIx CONTROL REGISTER 1 LOW
U-0
—
SPIEN
R/W-0
SPISIDL
R/W-0
DISSDO
R/W-0
MODE32
(1,4)
R/W-0
MODE16
(1,4)
R/W-0
R/W-0
SMP
CKE(1)
bit 15
bit 8
R/W-0
R/W-0
(2)
CKP
SSEN
R/W-0
MSTEN
R/W-0
DISSDI
R/W-0
R/W-0
R/W-0
R/W-0
DISSCK
MCLKEN(3)
SPIFE
ENHBUF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
SPIEN: SPIx On bit
1 = Enables module
0 = Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
bit 14
Unimplemented: Read as ‘0’
bit 13
SPISIDL: SPIx Stop in Idle Mode bit
1 = Halts in CPU Idle mode
0 = Continues to operate in CPU Idle mode
bit 12
DISSDO: Disable SDOx Output Port bit
1 = SDOx pin is not used by the module; pin is controlled by the port function
0 = SDOx pin is controlled by the module
bit 11-10
MODE[32,16]: Serial Word Length bits(1,4)
AUDEN = 0:
MODE32 MODE16
COMMUNICATION FIFO DEPTH
1
x
32-Bit
8
0
1
16-Bit
16
0
0
8-Bit
32
AUDEN = 1:
MODE32 MODE16
COMMUNICATION
1
1
24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
1
0
32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
0
1
16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame
0
0
16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame
bit 9
SMP: SPIx Data Input Sample Phase bit
Master Mode:
1 = Input datum is sampled at the end of data output time
0 = Input datum is sampled at the middle of data output time
Slave Mode:
Input datum is always sampled at the middle of data output time, regardless of the SMP setting.
Note 1:
2:
3:
4:
When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
When FRMEN = 1, SSEN is not used.
MCLKEN can only be written when the SPIEN bit = 0.
This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
DS30010198B-page 184
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PIC24FJ128GL306 FAMILY
REGISTER 15-1:
SPIxCON1L: SPIx CONTROL REGISTER 1 LOW (CONTINUED)
bit 8
CKE: SPIx Clock Edge Select bit(1)
1 = Transmit happens on transition from active clock state to Idle clock state
0 = Transmit happens on transition from Idle clock state to active clock state
bit 7
SSEN: Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used by the macro in Slave mode; SSx pin is used as the Slave select input
0 = SSx pin is not used by the macro (SSx pin will be controlled by the port I/O)
bit 6
CKP: SPIx Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
bit 4
DISSDI: Disable SDIx Input Port bit
1 = SDIx pin is not used by the module; pin is controlled by the port function
0 = SDIx pin is controlled by the module
bit 3
DISSCK: Disable SCKx Output Port bit
1 = SCKx pin is not used by the module; pin is controlled by the port function
0 = SCKx pin is controlled by the module
bit 2
MCLKEN: Master Clock Enable bit(3)
1 = REFO is used by the BRG
0 = Peripheral clock is used by the BRG
bit 1
SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0 = Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
bit 0
ENHBUF: Enhanced Buffer Mode Enable bit
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
Note 1:
2:
3:
4:
When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
When FRMEN = 1, SSEN is not used.
MCLKEN can only be written when the SPIEN bit = 0.
This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
2019-2020 Microchip Technology Inc.
DS30010198B-page 185
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REGISTER 15-2:
R/W-0
R/W-0
(1)
AUDEN
SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH
SPISGNEXT
R/W-0
IGNROV
R/W-0
IGNTUR
R/W-0
R/W-0
(2)
AUDMONO
URDTEN
R/W-0
(3)
R/W-0
(4)
AUDMOD1
AUDMOD0(4)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
FRMCNT2
FRMCNT1
FRMCNT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
AUDEN: Audio Codec Support Enable bit(1)
1 = Audio protocol is enabled; MSTEN controls the direction of both the SCKx and frame (a.k.a. LRC),
and this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT[2:0] = 001 and
SMP = 0, regardless of their actual values
0 = Audio protocol is disabled
bit 14
SPISGNEXT: SPIx Sign-Extend RX FIFO Read Data Enable bit
1 = Data from RX FIFO are sign-extended
0 = Data from RX FIFO are not sign-extended
bit 13
IGNROV: Ignore Receive Overflow bit
1 = A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO are not overwritten
by the receive data
0 = A ROV is a critical error that stops SPI operation
bit 12
IGNTUR: Ignore Transmit Underrun bit
1 = A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN are transmitted
until the SPIxTXB is not empty
0 = A TUR is a critical error that stops SPI operation
bit 11
AUDMONO: Audio Data Format Transmit bit(2)
1 = Audio data are mono (i.e., each data word is transmitted on both left and right channels)
0 = Audio data are stereo
bit 10
URDTEN: Transmit Underrun Data Enable bit(3)
1 = Transmits data out of the SPIxURDTL/H registers during Transmit Underrun conditions
0 = Transmits the last received data during Transmit Underrun conditions
bit 9-8
AUDMOD[1:0]: Audio Protocol Mode Selection bits(4)
11 = PCM/DSP mode
10 = Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01 = Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
00 = I2S mode: This module functions as if SPIFE = 0, regardless of its actual value
bit 7
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output)
0 = Framed SPIx support is disabled
Note 1:
2:
3:
4:
AUDEN can only be written when the SPIEN bit = 0.
AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
URDTEN is only valid when IGNTUR = 1.
AUDMOD[1:0] bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1. When
NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
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REGISTER 15-2:
SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH (CONTINUED)
bit 6
FRMSYNC: Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (Slave)
0 = Frame Sync pulse output (Master)
bit 5
FRMPOL: Frame Sync/Slave Select Polarity bit
1 = Frame Sync pulse/Slave select is active-high
0 = Frame Sync pulse/Slave select is active-low
bit 4
MSSEN: Master Mode Slave Select Enable bit
1 = SPIx Slave select support is enabled with polarity determined by FRMPOL (SSx pin is automatically
driven during transmission in Master mode)
0 = SPIx Slave select support is disabled (SSx pin will be controlled by port I/O)
bit 3
FRMSYPW: Frame Sync Pulse-Width bit
1 = Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0])
0 = Frame Sync pulse is one clock (SCKx) wide
bit 2-0
FRMCNT[2:0]: Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
111 = Reserved
110 = Reserved
101 = Generates a Frame Sync pulse on every 32 serial words
100 = Generates a Frame Sync pulse on every 16 serial words
011 = Generates a Frame Sync pulse on every 8 serial words
010 = Generates a Frame Sync pulse on every 4 serial words
001 = Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000 = Generates a Frame Sync pulse on each serial word
Note 1:
2:
3:
4:
AUDEN can only be written when the SPIEN bit = 0.
AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
URDTEN is only valid when IGNTUR = 1.
AUDMOD[1:0] bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1. When
NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
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REGISTER 15-3:
SPIxCON2L: SPIx CONTROL REGISTER 2 LOW
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WLENGTH[4:0](1,2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
WLENGTH[4:0]: Variable Word Length bits(1,2)
11111 = 32-bit data
11110 = 31-bit data
11101 = 30-bit data
11100 = 29-bit data
11011 = 28-bit data
11010 = 27-bit data
11001 = 26-bit data
11000 = 25-bit data
10111 = 24-bit data
10110 = 23-bit data
10101 = 22-bit data
10100 = 21-bit data
10011 = 20-bit data
10010 = 19-bit data
10001 = 18-bit data
10000 = 17-bit data
01111 = 16-bit data
01110 = 15-bit data
01101 = 14-bit data
01100 = 13-bit data
01011 = 12-bit data
01010 = 11-bit data
01001 = 10-bit data
01000 = 9-bit data
00111 = 8-bit data
00110 = 7-bit data
00101 = 6-bit data
00100 = 5-bit data
00011 = 4-bit data
00010 = 3-bit data
00001 = 2-bit data
00000 = See MODE[32,16] bits in SPIxCON1L[11:10]
Note 1:
2:
x = Bit is unknown
These bits are effective when AUDEN = 0 only.
Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.
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REGISTER 15-4:
SPIxSTATL: SPIx STATUS REGISTER LOW
U-0
U-0
U-0
HS/R/C-0
HSC/R-0
U-0
U-0
HSC/R-0
—
—
—
FRMERR
SPIBUSY
—
—
SPITUR(1)
bit 15
bit 8
HSC/R-0
HS/R/C-0
HSC/R-1
U-0
HSC/R-1
U-0
HSC/R-0
HSC/R-0
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
x = Bit is unknown
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-13
Unimplemented: Read as ‘0’
bit 12
FRMERR: SPIx Frame Error Status bit
1 = Frame error is detected
0 = No frame error is detected
bit 11
SPIBUSY: SPIx Activity Status bit
1 = Module is currently busy with some transactions
0 = No ongoing transactions (at time of read)
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPITUR: SPIx Transmit Underrun Status bit(1)
1 = Transmit buffer has encountered a Transmit Underrun (TUR) condition
0 = Transmit buffer does not have a Transmit Underrun condition
bit 7
SRMT: Shift Register Empty Status bit
1 = No current or pending transactions (i.e., neither SPIxTXB or SPIxTXSR contains data to transmit)
0 = Current or pending transactions
bit 6
SPIROV: SPIx Receive Overflow Status bit
1 = A new byte/half-word/word has been completely received when the SPIxRXB is full
0 = No overflow
bit 5
SPIRBE: SPIx RX Buffer Empty Status bit
1 = RX buffer is empty
0 = RX buffer is not empty
Standard Buffer Mode:
Automatically set in hardware when SPIxBUF is read from, reading SPIxRXB. Automatically cleared in
hardware when SPIx transfers data from SPIxRXSR to SPIxRXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 6’b000000.
bit 4
Unimplemented: Read as ‘0’
bit 3
SPITBE: SPIx Transmit Buffer Empty Status bit
1 = SPIxTXB is empty
0 = SPIxTXB is not empty
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Automatically
cleared in hardware when SPIxBUF is written, loading SPIxTXB.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 6’b000000.
Note 1:
SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit
Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
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REGISTER 15-4:
SPIxSTATL: SPIx STATUS REGISTER LOW (CONTINUED)
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = SPIxTXB is full
0 = SPIxTXB not full
Standard Buffer Mode:
Automatically set in hardware when SPIxBUF is written, loading SPIxTXB. Automatically cleared in
hardware when SPIx transfers data from SPIxTXB to SPIxTXSR.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 6’b111111.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = SPIxRXB is full
0 = SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Automatically
cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 6’b111111.
Note 1:
SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit
Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
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REGISTER 15-5:
U-0
SPIxSTATH: SPIx STATUS REGISTER HIGH(4)
U-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
—
RXELM5(3)
RXELM4(2)
RXELM3(1)
RXELM2
RXELM1
RXELM0
—
bit 15
U-0
bit 8
U-0
—
—
HSC/R-0
(3)
TXELM5
HSC/R-0
(2)
TXELM4
HSC/R-0
(1)
TXELM3
HSC/R-0
HSC/R-0
HSC/R-0
TXELM2
TXELM1
TXELM0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RXELM[5:0]: Receive Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
TXELM[5:0]: Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3)
Note 1:
2:
3:
4:
RXELM3 and TXELM3 bits are only present when FIFODEPTH = 8 or higher.
RXELM4 and TXELM4 bits are only present when FIFODEPTH = 16 or higher.
RXELM5 and TXELM5 bits are only present when FIFODEPTH = 32.
See the MODE32/16 bits in the SPIxCON1L register.
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REGISTER 15-6:
R/W-0
R/W-0
SPIxBUFL: SPIx BUFFER REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA[15:8]
bit 15
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
DATA[15:0]: SPIx FIFO Data bits
When the MODE[32,16] or WLENGTH[4:0] bits select 16 to 9-bit data, the SPIx only uses DATA[15:0].
When the MODE[32,16] or WLENGTH[4:0] bits select 8 to 2-bit data, the SPIx only uses DATA[7:0].
REGISTER 15-7:
R/W-0
x = Bit is unknown
R/W-0
SPIxBUFH: SPIx BUFFER REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA[31:24]
bit 15
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA[23:16]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
DATA[31:16]: SPIx FIFO Data bits
When the MODE[32,16] or WLENGTH[4:0] bits select 32 to 25-bit data, the SPIx uses DATA[31:16].
When the MODE[32,16] or WLENGTH[4:0] bits select 24 to 17-bit data, the SPIx only uses DATA[23:16].
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REGISTER 15-8:
U-0
U-0
—
—
SPIxBRGL: SPIx BAUD RATE GENERATOR REGISTER LOW
U-0
R/W-0
R/W-0
—
R/W-0
BRG[12:8]
R/W-0
R/W-0
(1)
bit 15
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
BRG[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-0
BRG[12:0]: SPIx Baud Rate Generator Divisor bits(1)
Note 1:
x = Bit is unknown
Changing the BRG value when SPIEN = 1 causes undefined behavior.
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REGISTER 15-9:
SPIxIMSKL: SPIx INTERRUPT MASK REGISTER LOW
U-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
—
—
—
FRMERREN
BUSYEN
—
—
SPITUREN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
R/W-0
R/W-0
SRMTEN
SPIROVEN
SPIRBEN
—
SPITBEN
—
SPITBFEN
SPIRBFEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame error generates an interrupt event
0 = Frame error does not generate an interrupt event
bit 11
BUSYEN: Enable Interrupt Events via SPIBUSY bit
1 = SPIBUSY generates an interrupt event
0 = SPIBUSY does not generate an interrupt event
bit 10-9
Unimplemented: Read as ‘0’
bit 8
SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun (TUR) generates an interrupt event
0 = Transmit Underrun does not generate an interrupt event
bit 7
SRMTEN: Enable Interrupt Events via SRMT bit
1 = Shift Register Empty (SRMT) generates interrupt events
0 = Shift Register Empty does not generate interrupt events
bit 6
SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = SPIx Receive Overflow (ROV) generates an interrupt event
0 = SPIx Receive Overflow does not generate an interrupt event
bit 5
SPIRBEN: Enable Interrupt Events via SPIRBE bit
1 = SPIx receive buffer empty generates an interrupt event
0 = SPIx receive buffer empty does not generate an interrupt event
bit 4
Unimplemented: Read as ‘0’
bit 3
SPITBEN: Enable Interrupt Events via SPITBE bit
1 = SPIx transmit buffer empty generates an interrupt event
0 = SPIx transmit buffer empty does not generate an interrupt event
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBFEN: Enable Interrupt Events via SPITBF bit
1 = SPIx transmit buffer full generates an interrupt event
0 = SPIx transmit buffer full does not generate an interrupt event
bit 0
SPIRBFEN: Enable Interrupt Events via SPIRBF bit
1 = SPIx receive buffer full generates an interrupt event
0 = SPIx receive buffer full does not generate an interrupt event
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REGISTER 15-10: SPIxIMSKH: SPIx INTERRUPT MASK REGISTER HIGH
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXWIEN
—
RXMSK5(1)
RXMSK4(1,4)
RXMSK3(1,3)
RXMSK2(1,2)
RXMSK1(1)
RXMSK0(1)
bit 15
bit 8
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXWIEN
—
TXMSK5(1)
TXMSK4(1,4)
TXMSK3(1,3)
TXMSK2(1,2)
TXMSK1(1)
TXMSK0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
RXWIEN: Receive Watermark Interrupt Enable bit
1 = Triggers receive buffer element watermark interrupt when RXMSK[5:0] RXELM[5:0]
0 = Disables receive buffer element watermark interrupt
bit 14
Unimplemented: Read as ‘0’
bit 13-8
RXMSK[5:0]: RX Buffer Mask bits(1,2,3,4)
RX mask bits; used in conjunction with the RXWIEN bit.
bit 7
TXWIEN: Transmit Watermark Interrupt Enable bit
1 = Triggers transmit buffer element watermark interrupt when TXMSK[5:0] = TXELM[5:0]
0 = Disables transmit buffer element watermark interrupt
bit 6
Unimplemented: Read as ‘0’
bit 5-0
TXMSK[5:0]: TX Buffer Mask bits(1,2,3,4)
TX mask bits; used in conjunction with the TXWIEN bit.
Note 1:
2:
3:
4:
Mask values higher than FIFODEPTH are not valid. The module will not trigger a match for any value in
this case.
RXMSK2 and TXMSK2 bits are only present when FIFODEPTH = 8 or higher.
RXMSK3 and TXMSK3 bits are only present when FIFODEPTH = 16 or higher.
RXMSK4 and TXMSK4 bits are only present when FIFODEPTH = 32.
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REGISTER 15-11: SPIxURDTL: SPIx UNDERRUN DATA REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
URDATA[15:8]
bit 15
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
URDATA[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
URDATA[15:0]: SPIx Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit
Underrun condition occurs.
When the MODE[32,16] or WLENGTH[4:0] bits select 16 to 9-bit data, the SPIx only uses URDATA[15:0].
When the MODE[32,16] or WLENGTH[4:0] bits select 8 to 2-bit data, the SPIx only uses URDATA[7:0].
REGISTER 15-12: SPIxURDTH: SPIx UNDERRUN DATA REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
URDATA[31:24]
bit 15
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
URDATA[23:16]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
URDATA[31:16]: SPIx Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit
Underrun condition occurs.
When the MODE[32,16] or WLENGTH[4:0] bits select 32 to 25-bit data, the SPIx only uses
URDATA[31:16]. When the MODE[32,16] or WLENGTH[4:0] bits select 24 to 17-bit data, the SPIx only
uses URDATA[23:16].
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FIGURE 15-2:
SPIx MASTER/SLAVE CONNECTION (STANDARD MODE)
Processor 2 (SPIx Slave)
Processor 1 (SPIx Master)
SDIx
SDOx
Serial Receive Buffer
(SPIxRXB)(2)
Shift Register
(SPIxRXSR)
LSb
MSb
Serial Transmit Buffer
(SPIxTXB)(2)
SDIx
SDOx
SDOx
SDIx
Shift Register
(SPIxTXSR)
MSb
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
MSb
LSb
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)(2)
SCKx
Serial Clock
SCKx
LSb
Serial Receive Buffer
(SPIxRXB)(2)
SSx(1)
SPIx Buffer
(SPIxBUF)
MSTEN (SPIxCON1L[5]) = 1
Note 1:
2:
SPIx Buffer
(SPIxBUF)
MSSEN (SPIxCON1H[4]) = 1 and MSTEN (SPIxCON1L[5]) = 0
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
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FIGURE 15-3:
SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Processor 1 (SPIx Master)
Processor 2 (SPIx Slave)
SDOx
SDIx
Serial Transmit FIFO
(SPIxTXB)(2)
Serial Receive FIFO
(SPIxRXB)(2)
Shift Register
(SPIxRXSR)
LSb
MSb
SDIx
SDOx
SDOx
SDIx
Shift Register
(SPIxTXSR)
MSb
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
MSb
LSb
MSb
LSb
Serial Transmit FIFO
(SPIxTXB)(2)
SCKx
Serial Clock
SCKx
LSb
Serial Receive FIFO
(SPIxRXB)(2)
SSx(1)
SPIx Buffer
(SPIxBUF)
MSTEN (SPIxCON1L[5]) = 1
Note 1:
2:
SPIx Buffer
(SPIxBUF)
MSSEN (SPIxCON1H[4]) = 1 and MSTEN (SPIxCON1L[5]) = 0
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
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FIGURE 15-4:
SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24FJ128GL306
(SPIx Master, Frame Master)
Processor 2
(SPIx Slave, Frame Slave)
Serial Receive Buffer
(SPIxRXB)(3)
Serial Receive Buffer
(SPIxTXB)(3)
Shift Register
(SPIxRXSR)
MSb
LSb
SDIx
SDOx
SDOx
SDIx
Shift Register
(SPIxRXSR)
MSb
Shift Register
(SPIxTXSR)
MSb
Shift Register
(SPIxTXSR)
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)(3)
SCKx
SSx
SPI Buffer
(SPIxBUF)
Note 1:
2:
3:
LSb
Serial Clock
Frame Sync
Pulse(1,2)
SCKx
LSb
Serial Transmit Buffer
(SPIxTXB)(3)
SSx(1)
SPI Buffer
(SPIxBUF)
In Framed SPI modes, the SSx pin is used to transmit/receive the Frame Synchronization pulse.
Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional).
The SPIxTXB and SPIxRXB registers are memory-mapped to the SPIxBUF register.
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FIGURE 15-5:
SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM
Processor 2
PIC24F
SPIx Master, Frame Slave)
SDOx
SDIx
SDIx
SDOx
SCKx
Serial Clock
SSx
FIGURE 15-6:
Frame Sync
Pulse
SCKx
SSx
SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM
Processor 2
PIC24F
(SPIx Slave, Frame Master)
SDOx
SDIx
SDIx
SDOx
SCKx
SSx
FIGURE 15-7:
Serial Clock
Frame Sync.
Pulse
SCKx
SSx
SPIx SLAVE, FRAME SLAVE CONNECTION DIAGRAM
Processor 2
PIC24F
(SPIx Slave, Frame Slave)
SDIx
SDOx
SDOx
SDIx
SCKx
SSx
EQUATION 15-1:
Serial Clock
Frame Sync
Pulse
SCKx
SSx
RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED
Baud Rate =
FPB
(2 * (SPIxBRG + 1))
Where:
FPB is the Peripheral Bus Clock Frequency.
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16.0
Note:
INTER-INTEGRATED CIRCUIT
(I2C)
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive reference source. For more information, refer
to “Inter-Integrated Circuit (I2C)”
(www.microchip.com/DS70000195) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The Inter-Integrated Circuit (I2C) module is a serial
interface useful for communicating with other peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, A/D
Converters, etc.
16.1
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.
2.
3.
4.
5.
6.
The I2C module supports these features:
• Independent Master and Slave Logic
• 7-Bit and 10-Bit Device Addresses
• General Call Address as Defined in the
I2C Protocol
• Clock Stretching to Provide Delays for the
Processor to Respond to a Slave Data Request
• Both 100 kHz, 400 kHz and 1 MHz Bus
Specifications
• Configurable Address Masking
• Multi-Master modes to Prevent Loss of Messages
in Arbitration
• Bus Repeater mode, Allowing the Acceptance of All
Messages as a Slave, regardless of the Address
• Automatic SCL
• PMBus™ Support
Communicating as a Master in a
Single Master Environment
7.
8.
9.
10.
11.
12.
13.
Assert a Start condition on SDAx and SCLx.
Send the I 2C device address byte to the Slave
with a write indication.
Wait for and verify an Acknowledge from the
Slave.
Send the first data byte (sometimes known as
the command) to the Slave.
Wait for and verify an Acknowledge from the
Slave.
Send the serial memory address low byte to the
Slave.
Repeat Steps 4 and 5 until all data bytes are
sent.
Assert a Repeated Start condition on SDAx and
SCLx.
Send the device address byte to the Slave with
a read indication.
Wait for and verify an Acknowledge from the
Slave.
Enable Master reception to receive serial
memory data.
Generate an ACK or NACK condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
A block diagram of the module is shown in Figure 16-1.
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FIGURE 16-1:
I2Cx BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
SCLx
Shift
Clock
I2CxRSR
LSb
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSb
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
TCY/2
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16.2
Setting Baud Rate When Operating
as a Bus Master
16.3
The I2CxMSK register (Register 16-4) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2CxMSK register causes the Slave
module to respond, whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is
set to ‘0010000000’, the Slave module will detect both
addresses, ‘0000000000’ and ‘0010000000’.
To compute the Baud Rate Generator reload value, use
Equation 16-1.
EQUATION 16-1:
COMPUTING BAUD RATE
RELOAD VALUE(1,2,3)
FSCL =
or:
FCY
(I2CxBRG + 2) * 2
I2CxBRG =
Note 1:
2:
3:
[
FCY
–2
(FSCL * 2)
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the STRICT bit (I2CxCONL[11]).
]
Note:
Based on FCY = FOSC/2; Doze mode and
PLL are disabled.
These clock rate values are for guidance
only. The actual clock rate can be
affected by various system-level parameters. The actual clock rate should be
measured in its intended application.
I2CxBRG values of 0 to 3 are forbidden.
TABLE 16-1:
Slave Address Masking
As a result of changes in the I2C protocol,
the addresses in Table 16-2 are reserved
and will not be Acknowledged in Slave
mode. This includes any address mask
settings that include any of these
addresses.
I2Cx CLOCK RATES(1,2)
Required System FSCL
FCY
I2CxBRG Value
(Decimal)
(Hexadecimal)
Actual FSCL
100 kHz
16 MHz
78
4E
100 kHz
100 kHz
8 MHz
38
26
100 kHz
100 kHz
4 MHz
18
12
100 kHz
400 kHz
16 MHz
18
12
400 kHz
400 kHz
8 MHz
8
8
400 kHz
400 kHz
4 MHz
3
3
400 kHz
1 MHz
16 MHz
6
6
1 MHz
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2: These clock rate values are for guidance only. The actual clock rate can be affected by various
system-level parameters. The actual clock rate should be measured in its intended application.
TABLE 16-2:
I2Cx RESERVED ADDRESSES(1)
Slave Address
R/W Bit
0000 000
0
General Call Address(2)
0000 000
1
Start Byte
0000 001
x
C-Bus Address
0000 01x
x
Reserved
0000 1xx
x
HS Mode Master Code
1111 0xx
x
10-Bit Slave Upper Byte(3)
1111 1xx
x
Reserved
Note 1:
2:
3:
Description
The address bits listed here will never cause an address match independent of address mask settings.
This address will be Acknowledged only if GCEN = 1.
A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 16-1:
R/W-0
I2CxCONL: I2Cx CONTROL REGISTER LOW
U-0
I2CEN
—
HC/R/W-0
I2CSIDL
R/W-1
(1)
SCLREL
R/W-0
R/W-0
R/W-0
R/W-0
STRICT
A10M
DISSLW
SMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
HC/R/W-0
HC/R/W-0
HC/R/W-0
HC/R/W-0
HC/R/W-0
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit (writable from software only)
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C pins are controlled by port functions
bit 14
Unimplemented: Read as ‘0’
bit 13
I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (I2C Slave mode only)(1)
Module resets and (I2CEN = 0) sets SCLREL = 1.
If STREN = 0:(2)
1 = Releases clock
0 = Forces clock low (clock stretch)
If STREN = 1:
1 = Releases clock
0 = Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at next SCLx low
bit 11
STRICT: I2Cx Strict Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced (for reserved addresses, refer to Table 16-2)
In Slave Mode: The device does not respond to reserved address space and addresses falling in
that category are NACKed.
In Master Mode: The device is allowed to generate addresses with reserved address space.
0 = Reserved addressing would be Acknowledged
In Slave Mode: The device will respond to an address falling in the reserved address space. When
there is a match with any of the reserved addresses, the device will generate an ACK.
In Master Mode: Reserved.
bit 10
A10M: 10-Bit Slave Address Flag bit
1 = I2CxADD is a 10-bit Slave address
0 = I2CxADD is a 7-bit Slave address
bit 9
DISSLW: Slew Rate Control Disable bit
1 = Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)
0 = Slew rate control is enabled for High-Speed mode (400 kHz)
Note 1:
2:
3:
Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end
of Slave reception. The user software must provide a delay between writing to the transmit buffer and setting the SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as
specified in Section 30.0 “Electrical Characteristics”.
Automatically cleared to ‘0’ at the beginning of Slave transmission.
SMBus 3.0 specification input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).
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REGISTER 16-1:
I2CxCONL: I2Cx CONTROL REGISTER LOW (CONTINUED)
bit 8
SMEN: SMBus Input Levels Enable bit(3)
1 = Enables input logic so thresholds are compliant with the SMBus specification
0 = Disables SMBus-specific inputs
bit 7
GCEN: General Call Enable bit (I2C Slave mode only)
1 = Enables interrupt when a general call address is received in I2CxRSR; module is enabled for reception
0 = General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit
In I2C Slave mode only; used in conjunction with the SCLREL bit.
1 = Enables clock stretching
0 = Disables clock stretching
bit 5
ACKDT: Acknowledge Data bit
In I2C Master mode during Master Receive mode. The value that will be transmitted when the user
initiates an Acknowledge sequence at the end of a receive.
In I2C Slave mode when AHEN = 1 or DHEN = 1. The value that the Slave will transmit when it initiates
an Acknowledge sequence at the end of an address or data reception.
1 = NACK is sent
0 = ACK is sent
bit 4
ACKEN: Acknowledge Sequence Enable bit
In I2C Master mode only; applicable during Master Receive mode.
1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits the ACKDT data bit
0 = Acknowledge sequence is Idle
bit 3
RCEN: Receive Enable bit (I2C Master mode only)
1 = Enables Receive mode for I2C; automatically cleared by hardware at the end of the 8-bit receive
data byte
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (I2C Master mode only)
1 = Initiates Stop condition on the SDAx and SCLx pins
0 = Stop condition is Idle
bit 1
RSEN: Restart Condition Enable bit (I2C Master mode only)
1 = Initiates Restart condition on the SDAx and SCLx pins
0 = Restart condition is Idle
bit 0
SEN: Start Condition Enable bit (I2C Master mode only)
1 = Initiates Start condition on the SDAx and SCLx pins
0 = Start condition is Idle
Note 1:
2:
3:
Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end
of Slave reception. The user software must provide a delay between writing to the transmit buffer and setting the SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as
specified in Section 30.0 “Electrical Characteristics”.
Automatically cleared to ‘0’ at the beginning of Slave transmission.
SMBus 3.0 specification input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).
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REGISTER 16-2:
I2CxCONH: I2Cx CONTROL REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
—
PCIE
R/W-0
SCIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BOEN
SDAHT(1)
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6
PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 5
SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 4
BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1 = I2CxRCV is updated and an ACK is generated for a received address/data byte, ignoring the state
of the I2COV bit only if the RBF bit = 0
0 = I2CxRCV is only updated when I2COV is clear
bit 3
SDAHT: SDAx Hold Time Selection bit(1)
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit
sequences.
1 = Enables Slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte; the SCLREL bit
(I2CxCONL[12]) will be cleared and SCLx will be held low
0 = Address holding is disabled
bit 0
DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte; Slave hardware clears the SCLREL
bit (I2CxCONL[12]) and SCLx is held low
0 = Data holding is disabled
Note 1:
This bit must be set to ‘0’ for 1 MHz operation.
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REGISTER 16-3:
I2CxSTAT: I2Cx STATUS REGISTER
HSC/R-0
HSC/R-0
HSC/R-0
U-0
U-0
HSC/R/C-0
HSC/R-0
HSC/R-0
ACKSTAT
TRSTAT
ACKTIM
—
—
BCL
GCSTAT
ADD10
bit 15
HS/R/C-0
bit 8
HS/R/C-0
IWCOL
I2COV
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
D/A
P
S
R/W
RBF
TBF
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
‘0’ = Bit is cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
bit 15
ACKSTAT: Acknowledge Status bit (updated in all Master and Slave modes)
1 = Acknowledge was not received from Slave
0 = Acknowledge was received from Slave
bit 14
TRSTAT: Transmit Status bit (when operating as I2C Master; applicable to Master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
bit 13
ACKTIM: Acknowledge Time Status bit (valid in I2C Slave mode only)
1 = Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock
0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock
bit 12-11
Unimplemented: Read as ‘0’
bit 10
BCL: Bus Collision Detect bit (Master/Slave mode; cleared when I2C module is disabled, I2CEN = 0)
1 = A bus collision has been detected during a Master or Slave transmit operation
0 = No bus collision has been detected
bit 9
GCSTAT: General Call Status bit (cleared after Stop detection)
1 = General call address was received
0 = General call address was not received
bit 8
ADD10: 10-Bit Address Status bit (cleared after Stop detection)
1 = 10-bit address was matched
0 = 10-bit address was not matched
bit 7
IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy; must be cleared
in software
0 = No collision
bit 6
I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte; I2COV is a “don’t
care” in Transmit mode, must be cleared in software
0 = No overflow
bit 5
D/A: Data/Address bit (when operating as I2C Slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received or transmitted was an address
bit 4
P: I2Cx Stop bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
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REGISTER 16-3:
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
S: I2Cx Start bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start (or Repeated Start) bit was not detected last
bit 2
R/W: Read/Write Information bit (when operating as I2C Slave)
1 = Read: Indicates the data transfer is output from the Slave
0 = Write: Indicates the data transfer is input to the Slave
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full (8 bits of data)
0 = Transmit is complete, I2CxTRN is empty
REGISTER 16-4:
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
MSK[9:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSK[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
MSK[9:0]: I2Cx Mask for Address Bit x Select bits
1 = Enables masking for bit x of the incoming message address; bit match is not required in this position
0 = Disables masking for bit x; bit match is required in this position
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17.0
Note:
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “Universal Asynchronous
Receiver
Transmitter
(UART)”
(www.microchip.com/DS70000582) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
A simplified block diagram of the UARTx module is
shown in Figure 17-1. The UARTx module consists of
these key important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
Note:
Throughout this section, references to
register and bit names that may be associated with a specific UART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “UxSTA” might refer to the Status
register for either UART1, UART2, UART3
or UART4.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the PIC24F device family. The UART is a full-duplex,
asynchronous system that can communicate with
peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. The module
also supports a hardware flow control option with the
UxCTS and UxRTS pins. The UART module includes
an IrDA® encoder/decoder unit.
The PIC24FJ128GL306 family devices are equipped
with four UART modules, referred to as UART1,
UART2, UART3 and UART4.
The primary features of the UARTx modules are:
• Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with the UxCTS
and UxRTS Pins
• Fully Integrated Baud Rate Generator with
16-Bit Prescaler
• Baud Rates Range from Up to 1 Mbps and Down to
15 Hz at 16 MIPS in 16x mode
• Baud Rates Range from Up to 4 Mbps and Down to
61 Hz at 16 MIPS in 4x mode
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-Bit mode with Address Detect
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Polarity Control for Transmit and Receive Lines
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• Includes DMA Support
• 16x Baud Clock Output for IrDA Support
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FIGURE 17-1:
UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
UxRTS/BCLKx(1)
(1)
UxCTS
UARTx Receiver
UxRX (1)
UARTx Transmitter
UxTX (1)
Note 1: The UART1, UART2, UART3 and UART4 inputs and outputs must all be assigned to available RPn/RPIn pins
before use. See Section 11.5 “Peripheral Pin Select (PPS)” for more information.
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17.1
UARTx Baud Rate Generator (BRG)
The UARTx module includes a dedicated, 16-bit Baud
Rate Generator. The UxBRG register controls the
period of a free-running, 16-bit timer. Equation 17-1
shows the formula for computation of the baud rate
when BRGH = 0.
EQUATION 17-1:
Note 1:
2:
EQUATION 17-2:
FCY
16 • (UxBRG + 1)
FCY
16 • Baud Rate
UxBRG =
Note 1:
–1
FCY denotes the instruction cycle
clock frequency (FOSC/2).
Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
Example 17-1 shows the calculation of the baud rate
error for the following conditions:
• FCY = 4 MHz
• Desired Baud Rate = 9600
UARTx BAUD RATE WITH
BRGH = 1(1,2)
Baud Rate =
UARTx BAUD RATE WITH
BRGH = 0(1,2)
Baud Rate =
UxBRG =
Equation 17-2 shows the formula for computation of
the baud rate when BRGH = 1.
2:
FCY
4 • (UxBRG + 1)
FCY
4 • Baud Rate
–1
FCY denotes the instruction cycle
clock frequency.
Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
The maximum baud rate (BRGH = 1) possible is FCY/4
(for UxBRG = 0) and the minimum baud rate possible
is FCY/(4 * 65536).
Writing a new value to the UxBRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
The maximum baud rate (BRGH = 0) possible is
FCY/16 (for UxBRG = 0) and the minimum baud rate
possible is FCY/(16 * 65536).
EXAMPLE 17-1:
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
Desired Baud Rate
= FCY/(16 (UxBRG + 1))
Solving for UxBRG Value:
UxBRG
UxBRG
UxBRG
= ((FCY/Desired Baud Rate)/16) – 1
= ((4000000/9600)/16) – 1
= 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9615
Error
Note 1:
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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17.2
1.
2.
3.
4.
5.
6.
Set up the UARTx:
a) Write appropriate values for data, parity and
Stop bits.
b) Write appropriate baud rate value to the
UxBRG register.
c) Set up transmit and receive interrupt enable
and priority bits.
Enable the UARTx.
Set the UTXEN bit (causes a transmit interrupt,
two cycles after being set).
Write a data byte to the lower byte of the
UxTXREG word. The value will be immediately
transferred to the Transmit Shift Register (TSR)
and the serial bit stream will start shifting out
with the next rising edge of the baud clock.
Alternatively, the data byte may be transferred
while UTXEN = 0 and then the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
A transmit interrupt will be generated as per
interrupt control bits, UTXISEL[1:0].
17.3
1.
2.
3.
4.
5.
6.
Transmitting in 8-Bit Data Mode
Transmitting in 9-Bit Data Mode
Set up the UARTx (as described in Section 17.2
“Transmitting in 8-Bit Data Mode”).
Enable the UARTx.
Set the UTXEN bit (causes a transmit interrupt).
Write UxTXREG as a 16-bit value only.
A word write to UxTXREG triggers the transfer
of the 9-bit data to the TSR. The serial bit stream
will start shifting out with the first rising edge of
the baud clock.
A transmit interrupt will be generated as per the
setting of control bits, UTXISELx.
17.4
Break and Sync Transmit
Sequence
The following sequence will send a message frame
header, made up of a Break, followed by an auto-baud
Sync byte.
1.
2.
3.
4.
5.
Configure the UARTx for the desired mode.
Set UTXEN and UTXBRK to set up the Break
character.
Load the UxTXREG with a dummy character to
initiate transmission (value is ignored).
Write ‘55h’ to UxTXREG; this loads the Sync
character into the transmit FIFO.
After the Break has been sent, the UTXBRK bit
is reset by hardware. The Sync character now
transmits.
DS30010198B-page 212
17.5
1.
2.
3.
4.
5.
Receiving in 8-Bit or 9-Bit Data
Mode
Set up the UARTx (as described in Section 17.2
“Transmitting in 8-Bit Data Mode”).
Enable the UARTx by setting the URXEN bit
(UxSTA[12]).
A receive interrupt will be generated when one
or more data characters have been received as
per interrupt control bits, URXISEL[1:0].
Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
Read UxRXREG.
The act of reading the UxRXREG character will move
the next character to the top of the receive FIFO,
including a new set of PERR and FERR values.
17.6
Operation of UxCTS and UxRTS
Control Pins
UARTx Clear-to-Send (UxCTS) and Request-to-Send
(UxRTS) are the two hardware controlled pins that are
associated with the UARTx modules. These two pins
allow the UARTx to operate in Simplex and Flow
Control mode. They are implemented to control the
transmission and reception between the Data Terminal
Equipment (DTE). The UEN[1:0] bits in the UxMODE
register configure these pins.
17.7
Infrared Support
The UARTx module provides two types of infrared
UART support: one is the IrDA clock output to support
an external IrDA encoder and decoder device (legacy
module support), and the other is the full implementation of the IrDA encoder and decoder. Note that
because the IrDA modes require a 16x baud clock, they
will only work when the BRGH bit (UxMODE[3]) is ‘0’.
17.7.1
IrDA CLOCK OUTPUT FOR
EXTERNAL IrDA SUPPORT
To support external IrDA encoder and decoder devices,
the BCLKx pin (same as the UxRTS pin) can be
configured to generate the 16x baud clock. When
UEN[1:0] = 11, the BCLKx pin will output the 16x baud
clock if the UARTx module is enabled; it can be used to
support the IrDA codec chip.
17.7.2
BUILT-IN IrDA ENCODER AND
DECODER
The UARTx has full implementation of the IrDA
encoder and decoder as part of the UARTx module.
The built-in IrDA encoder and decoder functionality is
enabled using the IREN bit (UxMODE[12]). When
enabled (IREN = 1), the receive pin (UxRX) acts as the
input from the infrared receiver. The transmit pin
(UxTX) acts as the output to the infrared transmitter.
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 17-1:
UxMODE: UARTx MODE REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
UARTEN(1)
—
USIDL
IREN(2)
RTSMD
—
UEN1
UEN0
bit 15
bit 8
HC/R/W-0
R/W-0
HC/R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN[1:0]
0 = UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption is minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN[1:0]: UARTx Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
port latches
bit 7
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
bit 4
URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
Note 1:
2:
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
This feature is only available for the 16x BRG mode (BRGH = 0).
2019-2020 Microchip Technology Inc.
DS30010198B-page 213
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REGISTER 17-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 3
BRGH: High Baud Rate Enable bit
1 = High-Speed mode (4 BRG clock cycles per bit)
0 = Standard Speed mode (16 BRG clock cycles per bit)
bit 2-1
PDSEL[1:0]: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1:
2:
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
This feature is only available for the 16x BRG mode (BRGH = 0).
DS30010198B-page 214
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PIC24FJ128GL306 FAMILY
REGISTER 17-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
HC/R/W-0
R/W-0
HSC/R-0
HSC/R-1
UTXISEL1
UTXINV(1)
UTXISEL0
—
UTXBRK
UTXEN(2)
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
HSC/R-1
HSC/R-0
HSC/R-0
HS/R/C-0
HSC/R-0
URXISEL1
URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
C = Clearable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
HC = Hardware Clearable bit
x = Bit is unknown
bit 15,13
UTXISEL[1:0]: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14
UTXINV: UARTx IrDA® Encoder Transmit Polarity Inversion bit(1)
IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
IREN = 1:
1 = UxTX Idle state is ‘1’
0 = UxTX Idle state is ‘0’
bit 12
Unimplemented: Read as ‘0’
bit 11
UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10
UTXEN: UARTx Transmit Enable bit(2)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by the port
bit 9
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
Note 1:
2:
The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled
(IREN = 1).
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
2019-2020 Microchip Technology Inc.
DS30010198B-page 215
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REGISTER 17-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 7-6
URXISEL[1:0]: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters)
10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (the character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (the character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset
the receive buffer and the RSR to the empty state)
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
2:
The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled
(IREN = 1).
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
DS30010198B-page 216
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REGISTER 17-3:
UxRXREG: UARTx RECEIVE REGISTER (NORMALLY READ-ONLY)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
UxRXREG8
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
UxRXREG[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-9
Unimplemented: Read as ‘0’
bit 8-0
UxRXREG[8:0]: Data of the Received Character bits
REGISTER 17-4:
x = Bit is unknown
UxTXREG: UARTx TRANSMIT REGISTER (NORMALLY WRITE-ONLY)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
W-x
—
—
—
—
—
—
—
UxTXREG8
bit 15
bit 8
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
UxTXREG[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-9
Unimplemented: Read as ‘0’
bit 8-0
UxTXREG[8:0]: Data of the Transmitted Character bits
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 217
PIC24FJ128GL306 FAMILY
REGISTER 17-5:
R/W-0
UxBRG: UARTx BAUD RATE GENERATOR REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BRG[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BRG[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
BRG[15:0]: Baud Rate Divisor bits
REGISTER 17-6:
UxADMD: UARTx ADDRESS DETECT AND MATCH REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADMMASK7
ADMMASK6
ADMMASK5
ADMMASK4
ADMMASK3
ADMMASK2
ADMMASK1
ADMMASK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADMADDR7
ADMADDR6
ADMADDR5
ADMADDR4
ADMADDR3
ADMADDR2
ADMADDR1
ADMADDR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
ADMMASK[7:0]: ADMADDR[7:0] (UxADMD[7:0]) Masking bits
For ADMMASKx:
1 = ADMADDRx is used to detect the address match
0 = ADMADDRx is not used to detect the address match
bit 7-0
ADMADDR[7:0]: Address Detect Task Off-Load bits
Used with the ADMMASK[7:0] bits (UxADMD[15:8]) to offload the task of detecting the address
character from the processor during Address Detect mode.
DS30010198B-page 218
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PIC24FJ128GL306 FAMILY
18.0
LIQUID CRYSTAL DISPLAY
(LCD) CONTROLLER
Note:
• Up to Eight Commons:
- Static (one common)
- 1/2 multiplex (two commons)
- 1/3 multiplex (three commons)
- 1/4 multiplex (four commons)
- 1/5 multiplex (five commons)
- 1/6 multiplex (six commons)
- 1/7 multiplex (seven commons)
- 1/8 multiplex (eight commons)
• Ability to Drive Up to 9 (in 28-pin devices) or Up to
36 (in 64-pin devices) Segments, Depending on
the Multiplexing Mode Selected; Table 18-1
shows the segment availability
• Static, 1/2 or 1/3 LCD Bias
• On-Chip Bias Generator with Dedicated Charge Pump
to Support a Range of Fixed and Bias Options
• Internal Resistors for Bias Voltage Generation
• Software Contrast Control for LCD Using
Internal Biasing
• Core-Independent Automatic Display Features:
- Dual display memory used to display two
different content displays
- Blink mode of individual pixels or the
complete pixels
- Blanking of individual pixels or the complete pixels
- Timing schedule can be changed without core
intervention based on user configurations
This data sheet summarizes the features
of the PIC24FJ128GL306 family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
“Liquid Crystal Display (LCD)”
(www.microchip.com/DS30009740) in
the “dsPIC33/PIC24 Family Reference
Manual”.
The Liquid Crystal Display (LCD) controller generates
the data and timing control required to directly drive a
static or multiplexed LCD panel. The module can drive
up to eight commons signals on all devices, and from
9 to 36 segments, depending on the specific device.
Note:
To be driven by the LCD controller, pins must
be set as analog inputs. For the port corresponding to the desired common or segment
pin, set TRISx = 1 and ANSELx = 1.
The LCD controller includes these features:
• Direct Driving of LCD Panel
• Three LCD Clock Sources with Selectable
Prescaler
A simplified block diagram of the module is shown in
Figure 18-1.
TABLE 18-1:
LCD SEGMENT AVAILABILITY
Segments
Device
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIC24FJXXXGL306
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PIC24FJXXXGL305
x
x
x
—
—
x
x
x
x
x
x
x
—
—
x
x
—
—
PIC24FJXXXGL303
—
—
—
—
—
—
—
—
x
x
x
x
—
—
x
x
—
—
PIC24FJXXXGL302
—
—
—
—
—
—
—
—
x
x
x
x
—
—
x
x
—
—
Segments
Device
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
63
48
47
40
31
30
29
28
27
26
25
24
23
22
21
20
19
18
PIC24FJXXXGL306
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PIC24FJXXXGL305
—
x
x
—
x
x
x
x
—
x
x
x
x
x
—
—
—
—
PIC24FJXXXGL303
—
x
x
—
x
x
x
x
—
x
x
—
—
—
—
—
—
—
PIC24FJXXXGL302
—
x
x
—
—
—
x
—
—
—
—
—
—
—
—
—
—
—
2019-2020 Microchip Technology Inc.
DS30010198B-page 219
PIC24FJ128GL306 FAMILY
FIGURE 18-1:
LCD CONTROLLER MODULE BLOCK DIAGRAM
Data Bus
LCD DATA
32 x 18 (= 8 x 64)
LCDDATA31
LCDDATA30
..
.
LCDDATA1
16
512
to
64
MUX
64
SEG[62:0]
LCDDATA0
Bias
Voltage
Timing Control
To I/O Pins
8
LCDCON
LCDPS
LCDSEx
LCD BIAS Generation
COMx[7:0]
LCDREG
LCDREF
Resistor Ladder
FRC Oscillator
LPRC Oscillator
SOSC
(Secondary Oscillator)
DS30010198B-page 220
LCD Clock
Source Select
LCD
Charge Pump
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
18.1
LCD Control Registers
REGISTER 18-1:
LCDCON: LCD CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
LCDEN
—
LCDSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/C-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SLPEN
WERR
CS1
CS0
LMUX2
LMUX1
LMUX0
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
LCDEN: LCD Driver Enable bit
1 = LCD driver module is enabled
0 = LCD driver module is not enabled
bit 14
Unimplemented: Read as ‘0’
bit 13
LCDSIDL: Stop LCD Drive in CPU Idle Mode Control bit
1 = LCD driver halts in CPU Idle mode
0 = LCD driver continues to operate in CPU Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
SLPEN: LCD Driver Enable in Sleep Mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
bit 5
WERR: LCD Write Failed Error bit
1 = LCDDATAx register is written while WA (LCDPS[4]) = 0 (must be cleared in software)
0 = No LCD write error
bit 4-3
CS[1:0]: Clock Source Select bits
1x = SOSC
01 = LPRC
00 = FRC
bit 2-0
LMUX[2:0]: LCD Commons Select bits
LMUX[2:0]
Multiplex
111
1/8 MUX (COM[7:0])
1/3
110
1/7 MUX (COM[6:0])
1/3
101
1/6 MUX (COM[5:0])
1/3
100
1/5 MUX (COM[4:0])
1/3
011
1/4 MUX (COM[3:0])
1/3
010
1/3 MUX (COM[2:0])
1/2 or 1/3
001
1/2 MUX (COM[1:0])
1/2 or 1/3
000
Static (COM0)
Static
2019-2020 Microchip Technology Inc.
Bias
DS30010198B-page 221
PIC24FJ128GL306 FAMILY
REGISTER 18-2:
LCDREG: LCD CHARGE PUMP CONTROL REGISTER
RW-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
CPEN
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
RW-0
RW-0
—
—
—
—
—
—
CKSEL1
CKSEL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CPEN: 3.6V Charge Pump Enable bit
1 = The regulator generates the highest (3.6V) voltage
0 = Highest voltage in the system is supplied externally (AVDD)
bit 14-2
Unimplemented: Read as ‘0’
bit 1-0
CLKSEL[1:0]: Regulator Clock Select Control bits
11 = SOSC
10 = 8 MHz FRC
01 = 32 kHz LPRC
00 = Disables regulator and floats regulator voltage output
DS30010198B-page 222
x = Bit is unknown
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REGISTER 18-3:
LCDPS: LCD PHASE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
WFT
BIASMD
LCDA
WA
LP3
LP2
LP1
LP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7
WFT: Waveform Type Select bit
1 = Type-B waveform (phase changes on each frame boundary)
0 = Type-A waveform (phase changes within each common type)
bit 6
BIASMD: Bias Mode Select bit
When LMUX[2:0] = 000 or 011 through 111:
0 = Static Bias mode (do not set this bit to ‘1’)
When LMUX[2:0] = 001 or 010:
1 = 1/2 Bias mode
0 = 1/3 Bias mode
bit 5
LCDA: LCD Active Status bit
1 = LCD driver module is active
0 = LCD driver module is inactive
bit 4
WA: LCD Write Allow Status bit
1 = Write into the LCDDATAx registers is allowed
0 = Write into the LCDDATAx registers is not allowed
bit 3-0
LP[3:0]: LCD Prescaler Select bits
1111 = 1:16
1110 = 1:15
1101 = 1:14
1100 = 1:13
1011 = 1:12
1010 = 1:11
1001 = 1:10
1000 = 1:9
0111 = 1:8
0110 = 1:7
0101 = 1:6
0100 = 1:5
0011 = 1:4
0010 = 1:3
0001 = 1:2
0000 = 1:1
x = Bit is unknown
\
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REGISTER 18-4:
LCDSEx: LCD SEGMENT x ENABLE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n+15)
SE(n+14)
SE(n+13)
SE(n+12)
SE(n+11)
SE(n+10)
SE(n+9)
SE(n+8)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n+7)
SE(n+6)
SE(n+5)
SE(n+4)
SE(n+3)
SE(n+2)
SE(n+1)
SE(n)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
SE(n+15):SE(n): Segment Enable bits
For LCDSE0: n = 0
For LCDSE1: n = 16
For LCDSE2: n = 32
For LCDSE3: n = 48
1 = Segment function of the pin is enabled, digital I/O is disabled
0 = Segment function of the pin is disabled, digital I/O is enabled
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REGISTER 18-5:
LCDDATAx: LCD DATA x REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+15)Cy
S(n+14)Cy
S(n+13)Cy
S(n+12)Cy
S(n+11)Cy
S(n+10)Cy
S(n+9)Cy
S(n+8)Cy
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+7)Cy
S(n+6)Cy
S(n+5)Cy
S(n+4)Cy
S(n+3)Cy
S(n+2)Cy
S(n+1)Cy
S(n)Cy
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
S(n+15)Cy:S(n)Cy: Pixel On bits
For Registers, LCDDATA0 through LCDDATA3: n = (16x), y = 0
For Registers, LCDDATA4 through LCDDATA7: n = (16(x – 4)), y = 1
For Registers, LCDDATA8 through LCDDATA11: n = (16(x – 8)), y = 2
For Registers, LCDDATA12 through LCDDATA15: n = (16(x – 12)), y = 3
For Registers, LCDDATA16 through LCDDATA19: n = (16(x – 16)), y = 4
For Registers, LCDDATA20 through LCDDATA23: n = (16(x – 20)), y = 5
For Registers, LCDDATA24 through LCDDATA27: n = (16(x – 24)), y = 6
For Registers, LCDDATA28 through LCDDATA31: n = (16(x – 28)), y = 7
1 = Pixel is on
0 = Pixel is off
Table 18-2 shows the correlation of each bit in the LCDDATAx registers to the respective common and
segment signals.
TABLE 18-2:
COM Lines
0
1
2
3
4
5
6
7
x = Bit is unknown
LCD DATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
Segments
0 to 15
16 to 31
32 to 47
48 to 64
LCDDATA0
LCDDATA1
LCDDATA2
LCDDATA3
S00C0:S15C0
S16C0:S31C0
S32C0:S47C0
S48C0:S63C0
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
S00C1:S15C1
S16C1:S31C1
S32C1:S47C1
S48C1:S63C1
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
S00C2:S15C2
S16C2:S31C2
S32C2:S47C2
S48C2:S63C2
LCDDATA12
LCDDATA13
LCDDATA14
LCDDATA15
S00C3:S15C3
S16C3:S31C3
S32C3:S47C3
S48C3:S63C3
LCDDATA16
LCDDATA17
LCDDATA18
LCDDATA19
S00C4:S15C4
S16C4:S31C4
S32C4:S47C4
S48C4:S63C4
LCDDATA20
LCDDATA21
LCDDATA22
LCDDATA23
S00C5:S15C5
S16C5:S31C5
S32C5:S47C5
S48C5:S63C5
LCDDATA24
LCDDATA25
LCDDATA26
LCDDATA27
S00C6:S15C6
S16C6:S31C6
S32C6:S47C6
S48C6:S63C6
LCDDATA28
LCDDATA29
LCDDATA30
LCDDATA31
S00C7:S15C7
S16C7:S31C7
S32C7:S47C7
S48C7:S63C7
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REGISTER 18-6:
LCDREF: LCD REFERENCE LADDER CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LCDIRE
—
LCDCST2
LCDCST1
LCDCST0
VLCD3PE
VLCD2PE
VLCD1PE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
LRLAP1
LRLAP0
LRLBP1
LRLBP0
—
LRLAT2
LRLAT1
LRLAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
LCDIRE: LCD Internal Reference Enable bit
1 = Internal LCD reference is enabled and connected to the internal contrast control circuit
0 = Internal LCD reference is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13-11
LCDCST[2:0]: LCD Contrast Control bits
Selects the Resistance of the LCD Contrast Control Resistor Ladder:
111 = Resistor ladder is at maximum resistance (minimum contrast)
110 = Resistor ladder is at 6/7th of maximum resistance
101 = Resistor ladder is at 5/7th of maximum resistance
100 = Resistor ladder is at 4/7th of maximum resistance
011 = Resistor ladder is at 3/7th of maximum resistance
010 = Resistor ladder is at 2/7th of maximum resistance
001 = Resistor ladder is at 1/7th of maximum resistance
000 = Minimum resistance (maximum contrast); resistor ladder is shorted
bit 10
VLCD3PE: LCD Bias 3 Pin Enable bit
1 = Bias 3 level is connected to the external pin, LCDBIAS3
0 = Bias 3 level is internal (internal resistor ladder)
bit 9
VLCD2PE: LCD Bias 2 Pin Enable bit
1 = Bias 2 level is connected to the external pin, LCDBIAS2
0 = Bias 2 level is internal (internal resistor ladder)
bit 8
VLCD1PE: LCD Bias 1 Pin Enable bit
1 = Bias 1 level is connected to the external pin, LCDBIAS1
0 = Bias 1 level is internal (internal resistor ladder)
bit 7-6
LRLAP[1:0]: LCD Reference Ladder A Time Power Control bits
During Time Interval A:
11 = Internal LCD reference ladder is powered in High-Power mode
10 = Internal LCD reference ladder is powered in Medium Power mode
01 = Internal LCD reference ladder is powered in Low-Power mode
00 = Internal LCD reference ladder is powered down and unconnected
bit 5-4
LRLBP[1:0]: LCD Reference Ladder B Time Power Control bits
During Time Interval B:
11 = Internal LCD reference ladder is powered in High-Power mode
10 = Internal LCD reference ladder is powered in Medium Power mode
01 = Internal LCD reference ladder is powered in Low-Power mode
00 = Internal LCD reference ladder is powered down and unconnected
bit 3
Unimplemented: Read as ‘0’
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REGISTER 18-6:
bit 2-0
LCDREF: LCD REFERENCE LADDER CONTROL REGISTER (CONTINUED)
LRLAT[2:0]: LCD Reference Ladder A Time Interval Control bits
Sets the number of 32 clock counts when the A Time Interval Power mode is active.
For Type-A Waveforms (WFT = 0):
111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9 clocks
110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10 clocks
101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11 clocks
100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12 clocks
011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13 clocks
010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14 clocks
001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15 clocks
000 = Internal LCD reference ladder is always in B Power mode
For Type-B Waveforms (WFT = 1):
111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25 clocks
110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26 clocks
101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27 clocks
100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28 clocks
011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29 clocks
010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30 clocks
001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31 clocks
000 = Internal LCD reference ladder is always in B Power mode
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REGISTER 18-7:
R/W-0
LCDACTRL: LCD AUTOMATIC CONTROL REGISTER
R/W-0
R/W-0
R/W-0
SMFCS[2:0](1,2,3,4,5)
R/W-0
R/W-0
BLINKFCS[2:0](4,5,6,7)
R/W-0
R/W-0
BLINKMODE[1:0](8,9)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
BLANKFCS[2:0](3,5,6,7,10,11)
R/W-0
R/W-0
BLANKMODE[1:0]
R/W-0
R/W-0
FCCS[1:0]
R/W-0
ELCDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
x = Bit is unknown
SMFCS[2:0]: Frame Counter Selection for Data Memory Selection bits(1,2,3,4,5)
When DMSEL[1:0] = 10 (one-time switchover from current display memory to another memory):
000 = Reserved
001 = Selects Frame Counter 0 (FC0)
When DMSEL[1:0] = 11 (continues to switch over from one memory to another memory):
000 = Reserved
001 = Selects Frame Counter 0 (FC0)
010 = Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency
given by the time event
011 = Reserved
When DMSEL[1:0] = 11 (continues to switch over from one memory to another with a repeated pattern):
100 = Alternates between FC0 and FC1 at the frequency given by the time event
101 = Reserved
110 = Reserved
111 = Reserved
Note 1:
Secondary memory is selected for pixel enable to Blink or Blank when
BLINKMODE[1:0] = 01 | BLANKMODE[1:0] = 01.
2: Secondary memory is used to store data to display or selects the pixel to Blink or Blank.
3: FC1 is used when Blink mode is not selected (i.e., BLINKMODE[1:0] = 00 | 11).
4: FC2 is used when Blank mode is not selected (i.e., BLANKMODE[1:0] = 00 | 11).
5: Frame counter selection switchover based on time event.
6: Pixel will alternate between ON and OFF state at the frequency given by the selected frame counter.
7: FC0 is used when secondary memory is not selected with switchover function
(i.e., DMSEL[1:0] = 00 or 01).
8: Blink mode ON state is effective to the pixel when Blank mode is off.
9: Blink mode OFF state drives ‘0’ to the pixel.
10: One-time Blank continues to Blank until a user changes the Blank mode to enable or disable the
enhanced LCD feature (clears ELCDEN) or SBLANK is clear.
11: In One-Time Blank Configuration mode, the pixel continues to Blink (to alternate between on and off) until
the timer event happens.
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REGISTER 18-7:
LCDACTRL: LCD AUTOMATIC CONTROL REGISTER (CONTINUED)
bit 12-10
BLINKFCS[2:0]: Frame Counter Selection for Blink Selection bits (BLINKMODE = 01 or 10)(4,5,6,7)
000 = Reserved
001 = Selects Frame Counter 1 (FC1)
010 = Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency
given by the time event
011 = Reserved
100 = Alternates between FC0 and FC1 at the frequency given by the time event (repeated pattern)
101 = Reserved
110 = Reserved
111 = Reserved
bit 9-8
BLINKMODE[1:0]: Blink Mode bits(8,9)
00 = Blink mode is disabled
01 = Blink mode is enabled with selected pixels (when DMSEL[1:0] = 00)
10 = Blink mode is enabled with all pixels
11 = Reserved
bit 7-5
BLANKFCS[2:0]: Blank Operation Selection from Frame Counter Selection bits(3,5,6,7,10,11)
(when BLANKMODE[1:0] = 01 or 10)
000 = Reserved
001 = Selects Frame Counter 2 (FC2)
010 = Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency
given by the time event
011 = Reserved
100 = Alternates between FC0 and FC1 at the frequency given by the time event (repeated pattern)
101 = Reserved
110 = One-time Blank selects Frame Counter 2 (FC2) by the time event(10,11)
111 = Reserved
bit 4-3
BLANKMODE[1:0]: Blank Mode bits
00 = Blank mode is disabled
01 = Blank mode is enabled with selected pixels (when DMSEL[1:0] = 00)
10 = Blank mode is enabled with all pixels
11 = Reserved
bit 2-1
FCCS[1:0]: Clock Source bits
00 = LCD clock
01 = RTCC
10 = CLC1
11 = CLC2
bit 0
ELCDEN: Enhancement LCD Enable bit
1 = Enhancement function is enabled
0 = Enhancement function is disabled
Note 1:
Secondary memory is selected for pixel enable to Blink or Blank when
BLINKMODE[1:0] = 01 | BLANKMODE[1:0] = 01.
2: Secondary memory is used to store data to display or selects the pixel to Blink or Blank.
3: FC1 is used when Blink mode is not selected (i.e., BLINKMODE[1:0] = 00 | 11).
4: FC2 is used when Blank mode is not selected (i.e., BLANKMODE[1:0] = 00 | 11).
5: Frame counter selection switchover based on time event.
6: Pixel will alternate between ON and OFF state at the frequency given by the selected frame counter.
7: FC0 is used when secondary memory is not selected with switchover function
(i.e., DMSEL[1:0] = 00 or 01).
8: Blink mode ON state is effective to the pixel when Blank mode is off.
9: Blink mode OFF state drives ‘0’ to the pixel.
10: One-time Blank continues to Blank until a user changes the Blank mode to enable or disable the
enhanced LCD feature (clears ELCDEN) or SBLANK is clear.
11: In One-Time Blank Configuration mode, the pixel continues to Blink (to alternate between on and off) until
the timer event happens.
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REGISTER 18-8:
LCDASTAT: LCD AUTOMATIC STATUS REGISTER
U-0
R/C-0
R-0
R-0
R/C-0
R/C-0
R/C-0
R/C-0
—
SBLANK(1,2,3,4)
SMEMACT
PMEMACT
TEVENTO
FC2O
FC1O
FC0O
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SMLOCK(7)
SMCLEAR
PMLOCK(5,6)
PMCLEAR
SMEMEN
PMEMDIS
DMSEL1
DMSEL0
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
SBLANK: Blank Status bit(1,2,3,4)
1 = Pixels are in continuous Blank
0 = Pixels are not in continuous Blank
bit 13
SMEMACT: Secondary Memory Active bit
1 = Data display is from secondary memory
0 = Data display is not from secondary memory
bit 12
PMEMACT: Primary Memory Active bit
1 = Data display is from primary memory
0 = Data display is not from primary memory
bit 11
TEVENTO: Time Event Overflow bit
1 = This flag is set when the time event overflows
0 = Timer event does not overflow
bit 10
FC2O: Frame Counter 2 Overflow bit
1 = This flag is set when Frame Counter 2 overflows
0 = Frame Counter 2 does not overflow
bit 9
FC1O: Frame Counter 1 Overflow bit
1 = This flag is set when Frame Counter 1 overflows
0 = Frame Counter 1 does not overflow
bit 8
FC0O: Frame Counter 0 Overflow bit
1 = This flag is set when Frame Counter 0 overflows
0 = Frame Counter 0 does not overflow
Note 1:
2:
3:
4:
5:
6:
7:
x = Bit is unknown
Reflects BLANKFCS[2:0] = 110 status.
It is the user’s responsibility to clear the bit to make LCD active.
This bit is cleared by hardware when the user changes Blank mode = 0 or clears the ELCDEN bit.
This flag bit is used to generate an enhanced feature interrupt.
This bit is effective when SMEMEN = 1; otherwise, the write follows the Write Allow bit, WA (LCDPS[4]).
When the PMLOCK bit is set, it does not allow the user to write to the primary memory.
When the SMLOCK bit is set, it does not allow the user to write to the secondary memory.
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REGISTER 18-8:
LCDASTAT: LCD AUTOMATIC STATUS REGISTER (CONTINUED)
bit 7
SMLOCK: Secondary Memory Lock Enable bit(7)
1 = Secondary memory is locked
0 = Secondary memory is unlocked
bit 6
SMCLEAR: Secondary Memory Clear Enable bit
1 = Secondary memory is cleared immediately
0 = Secondary memory is not cleared
bit 5
PMLOCK: Primary Memory Lock Enable bit(5,6)
1 = Primary memory is locked
0 = Primary memory is unlocked
bit 4
PMCLEAR: Primary Memory Clear Enable bit
1 = Primary memory is cleared immediately
0 = Primary memory is not cleared
bit 3
SMEMEN: Secondary Memory Enable bit
1 = Secondary memory is enabled
0 = Secondary memory is disabled
bit 2
PMEMDIS: Primary Memory Disable bit
1 = Primary memory is disabled
0 = Primary memory is enabled
bit 1-0
DMSEL[1:0]: Data Memory Selection bits
11 = Continues alternating selection between primary and secondary memories based on SMFCS[2:0]
10 = Alternates selection between primary and secondary memories on SMFCS[2:0]
01 = Selects secondary memory as display memory
00 = Selects primary memory as display memory
Note 1:
2:
3:
4:
5:
6:
7:
Reflects BLANKFCS[2:0] = 110 status.
It is the user’s responsibility to clear the bit to make LCD active.
This bit is cleared by hardware when the user changes Blank mode = 0 or clears the ELCDEN bit.
This flag bit is used to generate an enhanced feature interrupt.
This bit is effective when SMEMEN = 1; otherwise, the write follows the Write Allow bit, WA (LCDPS[4]).
When the PMLOCK bit is set, it does not allow the user to write to the primary memory.
When the SMLOCK bit is set, it does not allow the user to write to the secondary memory.
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REGISTER 18-9:
R/W-0
LCDFC0: LCD FRAME COUNTER 0 REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FC0[15:8](1,2,3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FC0[7:0](1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
FC0[15:0]: Time Base Value bits(1,2,3)
These bits define the overflow value.
It is recommended to make the FC0x values to be multiples of the frame frequency.
FC0x value must be greater than two.
FC0x should not be written when ELCDEN = 1.
REGISTER 18-10: LCDFC1: LCD FRAME COUNTER 1 REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FC1[15:8](1,2,3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FC1[7:0](1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
FC1[15:0]: Time Base Value bits(1,2,3)
These bits define the overflow value.
It is recommended to make the FC1x values to be multiples of the frame frequency.
FC1x value must be greater than two.
FC1x should not be written when ELCDEN = 1.
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REGISTER 18-11: LCDFC2: LCD FRAME COUNTER 2 REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FC2[15:8](1,2,3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FC2[7:0](1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
FC2[15:0]: Time Base Value bits(1,2,3)
These bits define the overflow value.
It is recommended to make the FC2x values to be multiples of the frame frequency.
FC2x value must be greater than two.
FC2x should not be written when ELCDEN = 1.
REGISTER 18-12: LCDEVENT: LCD TIME EVENT SELECTION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TEVENT[15:8](1,2,3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TEVENT[7:0](1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15:0
Note 1:
2:
3:
x = Bit is unknown
TEVENT[15:0]: Time Base Event Value bits(1,2,3)
These bits define the time event value.
The TEVENTx value should be multiples of the frame frequency.
The TEVENTx value should be greater than the FCx value.
The overflow is (TEVENTx * 16 ±1); the TEVENTx overflow gets ±1 based on the TEVENTx ratio with the
FCx value.
2019-2020 Microchip Technology Inc.
DS30010198B-page 233
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REGISTER 18-13: LCDSDATAx: LCD SDATA x REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+15)Cy
S(n+14)Cy
S(n+13)Cy
S(n+12)Cy
S(n+11)Cy
S(n+10)Cy
S(n+9)Cy
S(n+8)Cy
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+7)Cy
S(n+6)Cy
S(n+5)Cy
S(n+4)Cy
S(n+3)Cy
S(n+2)Cy
S(n+1)Cy
S(n)Cy
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15:0
TABLE 18-3:
S(n+15)Cy:S(n)Cy: Pixel Blink/Blank Enable bits (Segment x and Common y)
If BLINKMODE[1:0] = 01 or BLANKMODE[1:0] = 01:
1 = Pixel is selected for Blink or Blank
0 = Pixel is not selected for Blink or Blank
Else:
SEGxCOMy: Pixel Data bits (Segment x and Common y)
1 = Pixel on (dark)
0 = Pixel off (clear)
LCD SDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
Segments
COM Lines
0
1
2
3
4
5
6
7
x = Bit is unknown
0 to 15
16 to 31
32 to 47
48 to 64
LCDSDATA0
LCDSDATA1
LCDSDATA2
LCDSDATA3
S00C0:S15C0
S16C0:S31C0
S32C0:S47C0
S48C0:S63C0
LCDSDATA4
LCDSDATA5
LCDSDATA6
LCDSDATA7
S00C1:S15C1
S16C1:S31C1
S32C1:S47C1
S48C1:S63C1
LCDSDATA8
LCDSDATA9
LCDSDATA10
LCDSDATA11
S00C2:S15C2
S16C2:S31C2
S32C2:S47C2
S48C2:S63C2
LCDSDATA12
LCDSDATA13
LCDSDATA14
LCDSDATA15
S00C3:S15C3
S16C3:S31C3
S32C3:S47C3
S48C3:S63C3
LCDSDATA16
LCDSDATA17
LCDSDATA18
LCDSDATA19
S00C4:S15C4
S16C4:S31C4
S32C4:S47C4
S48C4:S63C4
LCDSDATA20
LCDSDATA21
LCDSDATA22
LCDSDATA23
S00C5:S15C5
S16C5:S31C5
S32C5:S47C5
S48C5:S63C5
LCDSDATA24
LCDSDATA25
LCDSDATA26
LCDSDATA27
S00C6:S15C6
S16C6:S31C6
S32C6:S47C6
S48C6:S63C6
LCDSDATA28
LCDSDATA29
LCDSDATA30
LCDSDATA31
S00C7:S15C7
S16C7:S31C7
S32C7:S47C7
S48C7:S63C7
DS30010198B-page 234
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PIC24FJ128GL306 FAMILY
19.0
Note:
REAL-TIME CLOCK AND
CALENDAR (RTCC) WITH
TIMESTAMP
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “RTCC with Timestamp”
(www.microchip.com/DS70005193) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The RTCC provides the user with a Real-Time Clock
and Calendar (RTCC) function that can be calibrated.
Key features of the RTCC module are:
• Selectable Clock Source
• Provides Hours, Minutes and Seconds Using
24-Hour Format
• Visibility of One Half Second Period
• Provides Calendar – Weekday, Date, Month
and Year
• Alarm-Configurable for Half a Second, 1 Second,
10 Seconds, 1 Minute, 10 Minutes, 1 Hour, 1 Day,
1 Week, 1 Month or 1 Year
• Alarm Repeat with Decrementing Counter
• Alarm with Indefinite Repeat Chime
• Year 2000 to 2099 Leap Year Correction
• BCD Format for Smaller Software Overhead
• Optimized for Long-Term Battery Operation
• User Calibration of the 32.768 kHz Clock
Crystal/32 kHz INTRC Frequency with Periodic
Auto-Adjust
• Fractional Second Synchronization
• Calibration to within ±2.64 Seconds Error
per Month
• Calibrates Up to 260 ppm of Crystal Error
• Ability to Periodically Wake-up External Devices
without CPU Intervention (external power control)
• Power Control Output for External Circuit Control
• Calibration takes Effect Every 15 Seconds
• Timestamp Capture Register for Time and Date
• Programmable Prescaler and Clock Divider
Circuit allows Operation with Any Clock Source
Up to 32 MHz, Including 32.768 kHz Crystal,
50/60 Hz Powerline Clock, External Real-Time
Clock (RTC) or 32 kHz LPRC Clock
2019-2020 Microchip Technology Inc.
19.1
RTCC Source Clock
The RTCC clock divider block converts the incoming
oscillator source into accurate 1/2 and 1 second clocks
for the RTCC. The clock divider is optimized to work
with three different oscillator sources:
• 32.768 kHz Crystal Oscillator
• 32 kHz Low-Power RC Oscillator (LPRC)
• External 50 Hz or 60 Hz Powerline Frequency
An asynchronous prescaler, PS[1:0] (RTCCON2L[5:4]), is
provided that allows the RTCC to work with higher
speed clock sources, such as the system clock. Divide
ratios of 1:16, 1:64 or 1:256 may be selected, allowing
sources up to 32 MHz to clock the RTCC.
19.1.1
COARSE FREQUENCY DIVISION
The clock divider block has a 16-bit counter used to
divide the input clock frequency. The divide ratio is set
by the DIV[15:0] register bits (RTCCON2H[15:0]). The
DIV[15:0] bits should be programmed with a value to
produce a nominal 1/2 second clock divider count
period.
19.1.2
FINE FREQUENCY DIVISION
The fine frequency division is set using the FDIV[4:0]
(RTCCON2L[15:11]) bits. Increasing the FDIVx value
will lengthen the overall clock divider period.
If FDIV[4:0] = 00000, the fine frequency division circuit
is effectively disabled. Otherwise, it will optionally
remove a clock pulse from the input of the clock divider
every 1/2 second. This functionality will allow the user to
remove up to 31 pulses over a fixed period of
16 seconds, depending on the value of FDIVx.
The value for DIV[15:0] is calculated as shown in
Equation 19-1. The fractional remainder of the DIV[15:0]
calculation result can be used to calculate the value for
FDIV[4:0].
EQUATION 19-1:
FOUT =
RTCC CLOCK DIVIDER
OUTPUT FREQUENCY
FIN
FDIV[4:0]
2 • (PS[1:0] Prescaler) • (DIV[15:0] + 1) +
32
The DIV[15:0] value is the integer part of this calculation:
DIV[15:0] =
FIN
2 • (PS[1:0] Prescaler)
–1
The FDIV[4:0] value is the fractional part of the DIV[15:0]
calculation, multiplied by 32.
DS30010198B-page 235
PIC24FJ128GL306 FAMILY
FIGURE 19-1:
RTCC BLOCK DIAGRAM
PWCPS[1:0]
Alarm Registers
Power Comparators Repeat
Control
Control
PS[1:0]
Clock
Divider
CLKSEL[1:0]
1/2
Second
RTCOE
RTCC
PPS
Time/Date
Registers
Timestamp Time/
Date Registers
OUTSEL[2:0]
Note 1: In Retention mode, the maximum peripheral output frequency to an I/O pin must be limited to 33 kHz or less.
DS30010198B-page 236
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PIC24FJ128GL306 FAMILY
19.2
RTCC Module Registers
The RTCC module registers are organized into four
categories:
•
•
•
•
RTCC Control Registers
RTCC Value Registers
Alarm Value Registers
Timestamp Registers
19.2.1
Clearing the WRLOCK bit requires an unlock sequence
after it has been written to a ‘1’, writing two bytes consecutively to the NVMKEY register. A sample assembly
sequence is shown in Example 19-1. If WRLOCK is
already cleared, it can be set to ‘1’ without using the
unlock sequence.
Note:
REGISTER MAPPING
Previous RTCC implementations used a Register
Pointer to access the RTCC Time and Date registers,
as well as the Alarm Time and Date registers. These
registers are now mapped to memory and are
individually addressable.
19.2.2
WRITE LOCK
19.2.3
To prevent spurious changes to the Time Control or Time
Value registers, the WRLOCK bit (RTCCON1L[11]) must
be cleared (‘0’). The POR default state is when the
WRLOCK bit is ‘0’ and is cleared on any device Reset
(POR, BOR, MCLR). It is recommended that the
WRLOCK bit be set to ‘1’ after the Date and Time
registers are properly initialized, and after the RTCEN bit
(RTCCON1L[15]) has been set.
Any attempt to write to the RTCEN bit, the RTCCON2L/H
registers, or the Date or Time registers, will be ignored
as long as WRLOCK is ‘1’. The Alarm, Power Control
and Timestamp registers can be changed when
WRLOCK is ‘1’.
EXAMPLE 19-1:
DISI
MOV
MOV
MOV
MOV
MOV
BCLR
To avoid accidental writes to the timer, it is
recommended that the WRLOCK bit
(RTCCON1L[11]) is kept clear at any
other time. For the WRLOCK bit to be set,
there is only one instruction cycle time
window allowed between the 55h/AA
sequence and the setting of WRLOCK;
therefore, it is recommended that code
follow the procedure in Example 19-1.
SELECTING RTCC CLOCK SOURCE
The clock source for the RTCC module can be selected
using the CLKSEL[1:0] bits in the RTCCON2L register.
When the bits are set to ‘00’, the Secondary Oscillator
(SOSC) is used as the reference clock and when the
bits are ‘01’, LPRC is used as the reference clock.
When CLKSEL[1:0] = 10, the external powerline (50 Hz
and 60 Hz) is used as the clock source. When
CLKSEL[1:0] = 11, the system clock is used as the
clock source.
SETTING THE WRLOCK BIT
#6
#NVKEY, W1
#0x55, W2
W2, [W1]
#0xAA, W3
W3, [W1]
RTCCON1L, #WRLOCK
2019-2020 Microchip Technology Inc.
;disable interrupts for 6 instructions
;
;
;
;
;
first unlock code
write first unlock code
second unlock sequence
write second unlock sequence
clear the WRLOCK bit
DS30010198B-page 237
PIC24FJ128GL306 FAMILY
19.3
RTCC Registers
19.3.1
RTCC CONTROL REGISTERS
REGISTER 19-1:
RTCCON1L: RTCC CONTROL REGISTER 1 LOW
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
RTCEN
—
—
—
WRLOCK
PWCEN
PWCPOL
PWCPOE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
RTCOE
OUTSEL2
OUTSEL1
OUTSEL0
—
—
—
TSAEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
RTCEN: RTCC Enable bit
1 = RTCC is enabled and counts from selected clock source
0 = RTCC is not enabled
bit 14-12
Unimplemented: Read as ‘0’
bit 11
WRLOCK: RTCC Register Write Lock bit
1 = RTCC registers are locked
0 = RTCC registers may be written to by user
bit 10
PWCEN: Power Control Enable bit
1 = Power control is enabled
0 = Power control is disabled
bit 9
PWCPOL: Power Control Polarity bit
1 = Power control output is active-high
0 = Power control output is active-low
bit 8
PWCPOE: Power Control Output Enable bit
1 = Power control output pin is enabled
0 = Power control output pin is disabled
bit 7
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 6-4
OUTSEL[2:0]: RTCC Output Signal Selection bits
111 = Unused
110 = Unused
101 = Unused
100 = Timestamp A event
011 = Power control
010 = RTCC input clock
001 = Second clock
000 = Alarm event
bit 3-1
Unimplemented: Read as ‘0’
bit 0
TSAEN: Timestamp A Enable bit
1 = Timestamp event will occur when a low pulse is detected on the TMPRN pin
0 = Timestamp is disabled
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REGISTER 19-2:
RTCCON1H: RTCC CONTROL REGISTER 1 HIGH
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
—
—
AMASK3
AMASK2
AMASK1
AMASK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALMRPT7
ALMRPT6
ALMRPT5
ALMRPT4
ALMRPT3
ALMRPT2
ALMRPT1
ALMRPT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ALMRPT[7:0] = 00h and
CHIME = 0)
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit
1 = Chime is enabled; ALMRPT[7:0] bits roll over from 00h to FFh
0 = Chime is disabled; ALMRPT[7:0] bits stop once they reach 00h
bit 13-12
Unimplemented: Read as ‘0’
bit 11-8
AMASK[3:0]: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every ten seconds
0011 = Every minute
0100 = Every ten minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every four years)
101x = Reserved – do not use
11xx = Reserved – do not use
bit 7-0
ALMRPT[7:0]: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
•
•
•
00000000 = Alarm will repeat 0 more times
The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’
unless CHIME = 1.
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REGISTER 19-3:
RTCCON2L: RTCC CONTROL REGISTER 2 LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
PWCPS1
PWCPS0
PS1
PS0
—
—
CLKSEL1
CLKSEL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
FDIV[4:0]: Fractional Clock Divide bits
00000 = No fractional clock division
00001 = Increase period by 1 RTCC input clock cycle every 16 seconds
00010 = Increase period by 2 RTCC input clock cycles every 16 seconds
•
•
•
11101 = Increase period by 30 RTCC input clock cycles every 16 seconds
11111 = Increase period by 31 RTCC input clock cycles every 16 seconds
bit 10-8
Unimplemented: Read as ‘0’
bit 7-6
PWCPS[1:0]: Power Control Prescale Select bits
00 = 1:1
01 = 1:16
10 = 1:64
11 = 1:256
bit 5-4
PS[1:0]: Prescale Select bits
00 = 1:1
01 = 1:16
10 = 1:64
11 = 1:256
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CLKSEL[1:0]: Clock Select bits
00 = SOSC
01 = LPRC
10 = PWRLCLK pin
11 = System clock
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19.3.2
RTCVAL REGISTER MAPPINGS
REGISTER 19-4:
R/W-0
RTCCON2H: RTCC CONTROL REGISTER 2 HIGH(1)
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
DIV[15:8]
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
DIV[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
DIV[15:0]: Clock Divide bits
Sets the period of the clock divider counter; value should cause a nominal 1/2 second underflow.
A write to this register is only allowed when WRLOCK = 1.
2019-2020 Microchip Technology Inc.
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REGISTER 19-5:
R/W-0
RTCCON3L: RTCC CONTROL REGISTER 3 LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWCSAMP[7:0]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
PWCSTAB[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
PWCSAMP[7:0]: Power Control Sample Window Timer bits
11111111 = Sample window is always enabled, even when PWCEN = 0
11111110 = Sample window is 254 TPWCCLK clock periods
•
•
•
00000001 = Sample window is 1 TPWCCLK clock period
00000000 = No sample window
bit 7-0
PWCSTAB[7:0]: Power Control Stability Window Timer bits(1)
11111111 = Stability window is 255 TPWCCLK clock periods
11111110 = Stability window is 254 TPWCCLK clock periods
•
•
•
00000001 = Stability window is 1 TPWCCLK clock period
00000000 = No stability window; sample window starts when the alarm event triggers
Note 1:
The sample window always starts when the stability window timer expires, except when its initial value is 00h.
DS30010198B-page 242
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REGISTER 19-6:
RTCSTATL: RTCC STATUS REGISTER LOW
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/C-0
ALMEVT
U-0
—
R/C-0
TSAEVT
(1)
R-0
R-0
R-0
SYNC
ALMSYNC
HALFSEC(2)
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5
ALMEVT: Alarm Event bit
1 = An alarm event has occurred
0 = An alarm event has not occurred
bit 4
Unimplemented: Read as ‘0’
bit 3
TSAEVT: Timestamp A Event bit(1)
1 = A timestamp event has occurred
0 = A timestamp event has not occurred
bit 2
SYNC: Synchronization Status bit
1 = TIMEL/H registers may change during software read
0 = TIMEL/H registers may be read safely
bit 1
ALMSYNC: Alarm Synchronization Status bit
1 = Alarm registers (ALMTIMEL/H and ALMDATEL/H) and Alarm Mask Configuration bits
(AMASK[3:0]) should not be modified, and Alarm control bits (ALRMEN, ALMRPT[7:0]) may
change during software read
0 = Alarm registers and Alarm control bits may be written/modified safely
bit 0
HALFSEC: Half Second Status bit(2)
1 = Second half period of a second
0 = First half period of a second
Note 1:
2:
User software may write a ‘1’ to this location to initiate a Timestamp A event; timestamp capture is not
valid until TSAEVT reads as ‘1’.
This bit is read-only; it is cleared to ‘0’ on a write to the SECONE[3:0] bits.
2019-2020 Microchip Technology Inc.
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19.3.3
RTCC VALUE REGISTERS
REGISTER 19-7:
TIMEL: RTCC TIME REGISTER LOW
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
bit 11-8
SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-0
Unimplemented: Read as ‘0’
REGISTER 19-8:
TIMEH: RTCC TIME REGISTER HIGH
U-0
U-0
R/W-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-12
HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
bit 11-8
HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
DS30010198B-page 244
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REGISTER 19-9:
DATEL: RTCC DATE REGISTER LOW
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-12
DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
bit 11-8
DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
REGISTER 19-10: DATEH: RTCC DATE REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 15
bit 8
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
MTHTEN
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits
bit 11-8
YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4
MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit
Contains a value either 0 or 1.
bit 3-0
MTHONE[3:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 245
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19.3.4
ALARM VALUE REGISTERS
REGISTER 19-11: ALMTIMEL: RTCC ALARM TIME REGISTER LOW
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
bit 11-8
SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-0
Unimplemented: Read as ‘0’
REGISTER 19-12: ALMTIMEH: RTCC ALARM TIME REGISTER HIGH
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-12
HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
bit 11-8
HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
DS30010198B-page 246
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REGISTER 19-13: ALMDATEL: RTCC ALARM DATE REGISTER LOW
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-12
DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
bit 11-8
DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
REGISTER 19-14: ALMDATEH: RTCC ALARM DATE REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
MTHTEN
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits
bit 11-8
YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4
MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit
Contains a value either 0 or 1.
bit 3-0
MTHONE[3:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 247
PIC24FJ128GL306 FAMILY
19.3.5
TIMESTAMP REGISTERS
REGISTER 19-15: TSATIMEL: RTCC TIMESTAMP A TIME REGISTER LOW(1)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
bit 11-8
SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
If TSAEN = 0, bits[15:0] can be used for persistent storage throughout a non-Power-on Reset (MCLR,
WDT, etc.).
DS30010198B-page 248
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REGISTER 19-16: TSATIMEH: RTCC TIMESTAMP A TIME REGISTER HIGH(1)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13-12
HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
bit 11-8
HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
Note 1:
x = Bit is unknown
If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR,
WDT, etc.).
2019-2020 Microchip Technology Inc.
DS30010198B-page 249
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REGISTER 19-17: TSADATEL: RTCC TIMESTAMP A DATE REGISTER LOW(1)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-12
DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
bit 11-8
DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
Note 1:
If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR,
WDT, etc.).
DS30010198B-page 250
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REGISTER 19-18: TSADATEH: RTCC TIMESTAMP A DATE REGISTER HIGH(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
MTHTEN
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits
bit 11-8
YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits
bit 7-5
Unimplemented: Read as ‘0’
bit 4
MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit
Contains a value either 0 or 1.
bit 3-0
MTHONE[2:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
Note 1:
x = Bit is unknown
If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR,
WDT, etc.).
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DS30010198B-page 251
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19.4
19.4.1
Calibration
CLOCK SOURCE CALIBRATION
A crystal oscillator that is connected to the RTCC may
be calibrated to provide an accurate 1-second clock in
two ways. First, coarse frequency adjustment is performed by adjusting the value written to the DIV[15:0]
bits. Secondly, a 5-bit value can be written to the
FDIV[4:0] control bits to perform a fine clock division.
The DIVx and FDIVx values can be concatenated and
considered as a 21-bit prescaler value. If the oscillator
source is slightly faster than ideal, the FDIV[4:0] value
can be increased to make a small decrease in the RTC
frequency. The value of DIV[15:0] should be increased
to make larger decreases in the RTC frequency. If the
oscillator source is slower than ideal, FDIV[4:0] may be
decreased for small calibration changes and DIV[15:0]
may need to be decreased to make larger calibration
changes.
Before calibration, the user must determine the error of
the crystal. This should be done using another timer
resource on the device or an external timing reference.
It is up to the user to include in the error value, the initial
error of the crystal, drift due to temperature and drift
due to crystal aging.
19.5
Alarm
• Configurable from half second to one year
• Enabled using the ALRMEN bit (RTCCON1H[15])
• One-time alarm and repeat alarm options are
available
19.5.1
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
the Alarm Value registers should only take place when
ALRMEN = 0.
As shown in Figure 19-2, the interval selection of the
alarm is configured through the AMASK[3:0] bits
(RTCCON1H[11:8]). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur.
The alarm can also be configured to repeat based on a
preconfigured interval. The amount of times this
occurs, once the alarm is enabled, is stored in the
ALMRPT[7:0] bits (RTCCON1H[7:0]). When the value
of the ALMRPTx bits equals 00h and the CHIME bit
(RTCCON1H[14]) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can
be repeated, up to 255 times, by loading ALMRPT[7:0]
with FFh.
After each alarm is issued, the value of the ALMRPTx
bits is decremented by one. Once the value has reached
00h, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off.
Indefinite repetition of the alarm can occur if the
CHIME bit = 1. Instead of the alarm being disabled
when the value of the ALMRPTx bits reaches 00h, it
rolls over to FFh and continues counting indefinitely
while CHIME is set.
19.5.2
ALARM INTERRUPT
At every alarm event, an interrupt is generated. This
output is completely synchronous to the RTCC clock
and can be used as a trigger clock to the other
peripherals.
Note:
DS30010198B-page 252
CONFIGURING THE ALARM
Changing any of the register bits, other
than the RTCOE bit (RTCCON1L[7]), the
ALMRPT[7:0] bits (RTCCON1H[7:0] and
the CHIME bit, while the alarm is enabled
(ALRMEN = 1), can result in a false alarm
event leading to a false alarm interrupt. To
avoid a false alarm event, the timer and
alarm values should only be changed
while the alarm is disabled (ALRMEN = 0).
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 19-2:
ALARM MASK SETTINGS
Alarm Mask Setting
(AMASK[3:0])
Day of
the
Week
Month
Day
Hours
Minutes
Seconds
0000 - Every half second
0001 - Every second
0010 - Every 10 seconds
s
0011 - Every minute
s
s
m
s
s
m
m
s
s
0100 - Every 10 minutes
0101 - Every hour
0110 - Every day
0111 - Every week
d
1000 - Every month
1001 - Every year(1)
m
m
h
h
m
m
s
s
h
h
m
m
s
s
d
d
h
h
m
m
s
s
d
d
h
h
m
m
s
s
Note 1: Annually, except when configured for February 29.
19.6
Power Control
The RTCC includes a power control feature that allows
the device to periodically wake-up an external device,
wait for the device to be stable before sampling wake-up
events from that device and then shut down the external
device. This can be done completely autonomously by
the RTCC, without the need to wake-up from the current
lower power mode.
To use this feature:
1.
2.
3.
Enable the RTCC (RTCEN = 1).
Set the PWCEN bit (RTCCON1L[10]).
Configure the RTCC pin to drive the PWC control
signal (RTCOE = 1 and OUTSEL[2:0] = 011).
The polarity of the PWC control signal may be chosen
using the PWCPOL bit (RTCCON1L[9]). An active-low
or active-high signal may be used with the appropriate
external switch to turn on or off the power to one or
more external devices. The active-low setting may also
be used in conjunction with an open-drain setting on
the RTCC pin, in order to drive the ground pin(s) of the
external device directly (with the appropriate external
VDD pull-up device), without the need for external
switches. Finally, the CHIME bit should be set to enable
the PWC periodicity.
2019-2020 Microchip Technology Inc.
Once the RTCC and PWC are enabled and running, the
PWC logic will generate a control output and a sample
gate output. The control output is driven out on the
RTCC pin (when RTCOE = 1 and OUTSEL[2:0] = 011)
and is used to power up or down the device, as
described above.
Once the control output is asserted, the stability window
begins, in which the external device is given enough
time to power up and provide a stable output.
Once the output is stable, the RTCC provides a sample
gate during the sample window. The use of this sample
gate depends on the external device being used, but
typically, it is used to mask out one or more wake-up
signals from the external device.
Finally, both the stability and the sample windows close
after the expiration of the sample window and the
external device is powered down.
DS30010198B-page 253
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19.6.1
POWER CONTROL CLOCK SOURCE
19.7.1
TIMESTAMP OPERATION
The stability and sample windows are controlled by the
PWCSAMPx and PWCSTABx bit fields in the
RTCCON3L register (RTCCON3L[15:8] and [7:0],
respectively). As both the stability and sample windows
are defined in terms of the RTCC clock, their
absolute values vary by the value of the PWC clock
base period (TPWCCLK). For example, using a
32.768 kHz SOSC input clock would produce a
TPWCCLK of 1/32768 = 30.518 µs. The 8-bit magnitude
of PWCSTABx and PWCSAMPx allows for a window
size of 0 to 255 TPWCCLK. The period of the PWC clock
can also be adjusted with a 1:1, 1:16, 1:64 or
1:256 prescaler, determined by the PWCPS[1:0] bits
(RTCCON2L[7:6]).
The event input is enabled for timestamping using the
TSAEN bit (RTCCON1L[0]). When the timestamp event
occurs, the present time and date values will be stored in
the TSATIMEL/H and TSADATEL/H registers, the
TSAEVT status bit (RTCSTATL[3]) will be set and an
RTCC interrupt will occur. A new timestamp capture event
cannot occur until the user clears the TSAEVT status bit.
In addition, certain values for the PWCSTABx and
PWCSAMPx fields have specific control meanings in
determining power control operations. If either bit field is
00h, the corresponding window is inactive. In addition, if
the PWCSTABx field is FFh, the stability window
remains active continuously, even if power control is
disabled.
19.7.2
19.7
Event Timestamping
The RTCC includes a set of Timestamp registers that
may be used for the capture of Time and Date register
values when an external input signal is received. The
RTCC will trigger a timestamp event when a low pulse
occurs on the TMPRN pin.
DS30010198B-page 254
Note 1: The TSATIMEL/H and TSADATEL/H register pairs can be used for data storage when
TSAEN = 0. The values of TSATIMEL/H
and TSADATEL/H will be maintained
throughout all types of non-Power-on
Resets (MCLR, WDT, etc).
MANUAL TIMESTAMP OPERATION
The current time and date may be captured in the
TSATIMEL/H and TSADATEL/H registers by writing a
‘1’ to the TSAEVT bit location while the timestamp functionality is enabled (TSAEN = 1). This write will not set
the TSAEVT bit, but it will initiate a timestamp capture.
The TSAEVT bit will be set when the capture operation
is complete. The user must poll the TSAEVT bit to
determine when the capture operation is complete.
After the Timestamp registers have been read, the
TSAEVT bit should be cleared to allow further
hardware or software timestamp capture events.
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
20.0
32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
Note:
The 32-bit programmable CRC generator provides a
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-Programmable CRC Polynomial Equation,
Up to 32 Bits
• Programmable Shift Direction (little or big-endian)
• Independent Data and Polynomial Lengths
• Configurable Interrupt Output
• Data FIFO
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “32-Bit Programmable Cyclic
Redundancy
Check
(CRC)”
(www.microchip.com/DS30009729) in the
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data
sheet supersedes the information in the
FRM.
FIGURE 20-1:
Figure 20-1 displays a simplified block diagram of the
CRC generator. A simple version of the CRC shift
engine is displayed in Figure 20-2.
CRC BLOCK DIAGRAM
CRCDATH
CRCDATL
FIFO Empty
Event
Variable FIFO
(4x32, 8x16 or 16x8)
CRCWDATH
CRCISEL
1
CRCWDATL
LENDIAN
Shift Buffer
0
1
CRC Shift Engine
0
CRC
Interrupt
Shift
Complete
Event
Shifter Clock
2 * FCY
FIGURE 20-2:
CRC SHIFT ENGINE DETAIL
CRC Shift Engine
CRCWDATH
CRCWDATL
Read/Write Bus
X0
Shift Buffer
Data
Note 1:
Xn(1)
X1
Bit 0
Bit 1
Bit n(1)
n = PLEN[4:1] + 1.
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DS30010198B-page 255
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20.1
20.1.1
User Interface
20.1.2
POLYNOMIAL INTERFACE
The CRC module can be programmed for CRC
polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN[4:0] bits
(CRCCON2[4:0]).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the equation. Functionally, this includes an XOR operation on
the corresponding bit in the CRC engine. Clearing the
bit disables the XOR.
For example, consider two CRC polynomials, one a
16-bit and the other a 32-bit equation.
EQUATION 20-1:
DATA INTERFACE
The module incorporates a FIFO that works with a
variable datum width. Input datum width can be configured to any value, between 1 and 32 bits, using the
DWIDTH[4:0] bits (CRCCON2[12:8]). When the datum
width is greater than 15, the FIFO is 4 words deep.
When the DWIDTHx bits are between 15 and 8, the
FIFO is 8 words deep. When the DWIDTHx bits are
less than 8, the FIFO is 16 words deep.
The data for which the CRC is to be calculated must
first be written into the FIFO. Even if the datum width is
less than 8, the smallest data element that can be
written into the FIFO is 1 byte. For example, if the
DWIDTHx bits are 5, then the size of the data is
DWIDTH[4:0] + 1 or 6. The data are written as a whole
byte; the two unused upper bits are ignored by the
module.
Once datum is written into the MSb of the CRCDAT registers (that is, the MSb as defined by the datum width),
the value of the VWORD[4:0] bits (CRCCON1[12:8])
increments by one. For example, if the DWIDTHx bits
are 24, the VWORDx bits will increment when bit 7 of
CRCDATH is written. Therefore, CRCDATL must always
be written to before CRCDATH.
16-BIT, 32-BIT CRC
POLYNOMIALS
X16 + X12 + X5 + 1
and
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X + 1
To program these polynomials into the CRC generator,
set the register bits, as shown in Table 20-1.
Note that the appropriate positions are set to ‘1’ to indicate that they are used in the equation (for example,
X26 and X23). The ‘0’ bit required by the equation is
always XORed; thus, X0 is a don’t care. For a polynomial of length 32, it is assumed that the 32nd bit will
be used. Therefore, the X[31:1] bits do not have the
32nd bit.
The CRC engine starts shifting data when the CRCGO
bit (CRCCON1[4]) is set and the value of the VWORDx
bits is greater than zero.
Each word is copied out of the FIFO into a buffer
register, which decrements the VWORDx bits. The data
are then shifted out of the buffer. The CRC engine
continues shifting at a rate of two bits per instruction
cycle, until the VWORDx bits reach zero. This means
that for a given data width, it takes half that number of
instructions for each word to complete the calculation.
For example, it takes 16 cycles to calculate the CRC for
a single word of 32-bit data.
When the VWORDx bits reach the maximum value for
the configured value of the DWIDTHx bits (4, 8 or 16),
the CRCFUL bit (CRCCON1[7]) becomes set. When
the VWORDx bits reach zero, the CRCMPT bit
(CRCCON1[6]) becomes set. The FIFO is emptied and
the VWORD[4:0] bits are set to ‘00000’ whenever
CRCEN is ‘0’.
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORDx bits is done.
TABLE 20-1:
CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS
CRC Control Bits
Bit Values
16-Bit Polynomial
32-Bit Polynomial
PLEN[4:0]
01111
11111
X[31:16]
0000 0000 0000 0001
0000 0100 1100 0001
X[15:1]
0001 0000 0010 000
0001 1101 1011 011
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20.1.3
DATA SHIFT DIRECTION
The LENDIAN bit (CRCCON1[3]) is used to control the
shift direction. By default, the CRC will shift data
through the engine, MSb first. Setting LENDIAN (= 1)
causes the CRC to shift data, LSb first. This setting
allows better integration with various communication
schemes and removes the overhead of reversing the
bit order in software. Note that this only changes the
direction that the data are shifted into the engine. The
result of the CRC calculation will still be a normal CRC
result, not a reverse CRC result.
20.1.4
Or, if the data width (DWIDTH[4:0] bits) is less than the
polynomial length (PLEN[4:0] bits):
1.
2.
3.
INTERRUPT OPERATION
The module generates an interrupt that is configurable
by the user for either of two conditions.
If CRCISEL is ‘0’, an interrupt is generated when the
VWORD[4:0] bits make a transition from a value of ‘1’
to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated
after the CRC operation finishes and the module sets
the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’
will not generate an interrupt. Note that when an
interrupt occurs, the CRC calculation would not yet be
complete. The module will still need (PLENx + 1)/2
clock cycles after the interrupt is generated until the
CRC calculation is finished.
20.1.5
TYPICAL OPERATION
To use the module for a typical CRC calculation:
1.
2.
3.
4.
5.
6.
7.
Set the CRCEN bit to enable the module.
Configure the module for desired operation:
a) Program the desired polynomial using the
CRCXOR registers and PLEN[4:0] bits.
b) Configure the data width and shift direction
using the DWIDTH[4:0] and LENDIAN bits.
Set the CRCGO bit to start the calculations.
Set the desired CRC non-direct initial value by
writing to the CRCWDAT registers.
Load all data into the FIFO by writing to the
CRCDAT registers as space becomes available
(the CRCFUL bit must be zero before the next
data loading).
Wait until the data FIFO is empty (CRCMPT bit
is set).
Read the result:
If the data width (DWIDTH[4:0] bits) is more than
the polynomial length (PLEN[4:0] bits):
a) Wait (DWIDTH[4:0] + 1)/2 instruction cycles
to make sure that shifts from the shift buffer
are finished.
b) Change the data width to the polynomial
length (DWIDTH[4:0] = PLEN[4:0]).
c) Write one dummy data word to the CRCDAT
registers.
d) Wait two instruction cycles to move the data
from the FIFO to the shift buffer and
(PLEN[4:0] + 1)/2 instruction cycles to shift
out the result.
2019-2020 Microchip Technology Inc.
Clear the CRC Interrupt Selection bit
(CRCISEL = 0) to get the interrupt when all
shifts are done. Clear the CRC interrupt flag.
Write dummy data in the CRCDAT registers and
wait until the CRC interrupt flag is set.
Read the final CRC result from the CRCWDAT
registers.
Restore the data width (DWIDTH[4:0] bits) for
further calculations (optional). If the data width
(DWIDTH[4:0] bits) is equal to, or less than, the
polynomial length (PLEN[4:0] bits):
a) Clear the CRC Interrupt Selection bit
(CRCISEL = 0) to get the interrupt when all
shifts are done.
b) Suspend the calculation by setting
CRCGO = 0.
c) Clear the CRC interrupt flag.
d) Write the dummy data with the total data
length equal to the polynomial length in the
CRCDAT registers.
e) Resume the calculation by setting
CRCGO = 1.
f) Wait until the CRC interrupt flag is set.
g) Read the final CRC result from the
CRCWDAT registers.
There are eight registers used to control programmable
CRC operation:
•
•
•
•
•
•
•
•
CRCCON1
CRCCON2
CRCXORL
CRCXORH
CRCDATL
CRCDATH
CRCWDATL
CRCWDATH
The CRCCON1 and CRCCON2 registers (Register 20-1
and Register 20-2) control the operation of the module
and configure the various settings.
The CRCXOR registers (Register 20-3 and
Register 20-4) select the polynomial terms to be used
in the CRC equation. The CRCDAT and CRCWDAT
registers are each register pairs that serve as buffers
for the double-word input data, and CRC processed
output, respectively.
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REGISTER 20-1:
CRCCON1: CRC CONTROL 1 REGISTER
R/W-0
U-0
R/W-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
CRCEN
—
CSIDL
VWORD4
VWORD3
VWORD2
VWORD1
VWORD0
bit 15
bit 8
HSC/R-0
HSC/R-1
R/W-0
HC/R/W-0
R/W-0
U-0
U-0
U-0
CRCFUL
CRCMPT
CRCISEL
CRCGO
LENDIAN
—
—
—
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CRCEN: CRC Enable bit
1 = Enables module
0 = Disables module; all state machines, pointers and CRCWDAT/CRCDAT registers reset; other SFRs
are NOT reset
bit 14
Unimplemented: Read as ‘0’
bit 13
CSIDL: CRC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-8
VWORD[4:0]: CRC Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN[4:0] 7 or 16
when PLEN[4:0] 7.
bit 7
CRCFUL: CRC FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6
CRCMPT: CRC FIFO Empty bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5
CRCISEL: CRC Interrupt Selection bit
1 = Interrupt on FIFO is empty; the final word of datum is still shifting through the CRC
0 = Interrupt on shift is complete and results are ready
bit 4
CRCGO: Start CRC bit
1 = Starts CRC serial shifter
0 = CRC serial shifter is turned off
bit 3
LENDIAN: Data Shift Direction Select bit
1 = Data word is shifted into the CRC, starting with the LSb (little endian)
0 = Data word is shifted into the CRC, starting with the MSb (big endian)
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 20-2:
CRCCON2: CRC CONTROL 2 REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DWIDTH4
DWIDTH3
DWIDTH2
DWIDTH1
DWIDTH0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
PLEN4
PLEN3
PLEN2
PLEN1
PLEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
DWIDTH[4:0]: CRC Data Word Width Configuration bits
Configures the width of the data word (Data Word Width – 1).
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
PLEN[4:0]: Polynomial Length Configuration bits
Configures the length of the polynomial (Polynomial Length – 1).
2019-2020 Microchip Technology Inc.
x = Bit is unknown
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REGISTER 20-3:
R/W-0
CRCXORL: CRC XOR POLYNOMIAL REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
X[7:1]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-1
X[15:1]: XOR of Polynomial Term Xn Enable bits
bit 0
Unimplemented: Read as ‘0’
REGISTER 20-4:
R/W-0
x = Bit is unknown
CRCXORH: CRC XOR POLYNOMIAL REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X[31:24]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X[23:16]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
X[31:16]: XOR of Polynomial Term Xn Enable bits
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21.0
Note:
CONFIGURABLE LOGIC CELL
(CLC)
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive reference source. For more information, refer
to “Configurable Logic Cell (CLC)”
(www.microchip.com/DS70005298) in the
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
FIGURE 21-1:
There are four input gates to the selected logic function. These four input gates select from a pool of up to
32 signals that are selected using four data source
selection multiplexers. Figure 21-1 shows an overview
of the module. Figure 21-3 shows the details of the data
source multiplexers and logic input gate connections.
CLCx MODULE
See Figure 21-2
Input Data Selection Gates
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[3]
CLCIN[4]
CLCIN[5]
CLCIN[6]
CLCIN[7]
CLCIN[8]
CLCIN[9]
CLCIN[10]
CLCIN[11]
CLCIN[12]
CLCIN[13]
CLCIN[14]
CLCIN[15]
CLCIN[16]
CLCIN[17]
CLCIN[18]
CLCIN[19]
CLCIN[20]
CLCIN[21]
CLCIN[22]
CLCIN[23]
CLCIN[24]
CLCIN[25]
CLCIN[26]
CLCIN[27]
CLCIN[28]
CLCIN[29]
CLCIN[30]
CLCIN[31]
The Configurable Logic Cell (CLC) module allows the
user to specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins. This provides greater
flexibility and potential in embedded designs, since the
CLC module can operate outside the limitations of
software execution and supports a vast amount of
output designs.
LCOE
LCEN
Gate 1
Gate 2
Logic
Gate 3
Function
Gate 4
TRISx Control
CLCx
Output
CLCx
Logic
Output
LCPOL
Interrupt
MODE[2:0]
det
INTP
INTN
Sets
CLCxIF
Flag
Interrupt
det
See Figure 21-3
Note: All register bits shown in this figure can be found in the CLCxCONL register.
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FIGURE 21-2:
CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS
AND – OR
OR – XOR
Gate 1
Gate 1
Gate 2
Logic Output
Gate 3
Gate 2
Logic Output
Gate 3
Gate 4
Gate 4
MODE[2:0] = 000
MODE[2:0] = 001
4-Input AND
S-R Latch
Gate 1
Gate 1
Gate 2
Gate 2
Logic Output
Gate 3
Gate 4
S
Gate 3
Q
R
Gate 4
MODE[2:0] = 010
MODE[2:0] = 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
Gate 4
D
Gate 2
S
Gate 4
Q
Logic Output
D
Gate 2
Gate 1
Gate 1
Logic Output
Q
Logic Output
R
R
Gate 3
Gate 3
MODE[2:0] = 100
MODE[2:0] = 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
Gate 4
Gate 2
J
Q
Logic Output
Gate 1
K
Gate 4
R
Gate 2
D
Gate 1
LE
Gate 3
S
Q
Logic Output
R
Gate 3
MODE[2:0] = 110
DS30010198B-page 262
MODE[2:0] = 111
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FIGURE 21-3:
CLCx INPUT SOURCE SELECTION DIAGRAM
Data Selection
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[3]
CLCIN[4]
CLCIN[5]
CLCIN[6]
CLCIN[7]
000
Data Gate 1
Data 1 Noninverted
Data 1
Inverted
111
DS1x (CLCxSEL[2:0])
G1D1T
G1D1N
G1D2T
G1D2N
CLCIN[8]
CLCIN[9]
CLCIN[10]
CLCIN[11]
CLCIN[12]
CLCIN[13]
CLCIN[14]
CLCIN[15]
G1D3T
Data 2 Noninverted
Data 2
Inverted
G1D4T
000
G1D4N
Data Gate 2
Data 3 Noninverted
Data 3
Inverted
Gate 2
(Same as Data Gate 1)
Data Gate 3
111
Gate 3
DS3x (CLCxSEL[10:8])
CLCIN[24]
CLCIN[25]
CLCIN[26]
CLCIN[27]
CLCIN[28]
CLCIN[29]
CLCIN[30]
CLCIN[31]
G1D3N
G1POL
(CLCxCONH[0])
111
DS2x (CLCxSEL[6:4])
CLCIN[16]
CLCIN[17]
CLCIN[18]
CLCIN[19]
CLCIN[20]
CLCIN[21]
CLCIN[22]
CLCIN[23]
Gate 1
000
(Same as Data Gate 1)
Data Gate 4
000
Gate 4
Data 4 Noninverted
(Same as Data Gate 1)
Data 4
Inverted
111
DS4x (CLCxSEL[14:12])
Note:
All controls are undefined at power-up.
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21.1
Control Registers
The CLCx Input MUX Select register (CLCxSEL)
allows the user to select up to four data input sources
using the four data input selection multiplexers. Each
multiplexer has a list of eight data sources available.
The CLCx module is controlled by the following registers:
•
•
•
•
•
CLCxCONL
CLCxCONH
CLCxSEL
CLCxGLSL
CLCxGLSH
The CLCx Gate Logic Input Select registers (CLCxGLSL
and CLCxGLSH) allow the user to select which outputs
from each of the selection MUXes are used as inputs to
the input gates of the logic cell. Each data source MUX
outputs both a true and a negated version of its output.
All of these eight signals are enabled, ORed together by
the logic cell input gates. If no gate inputs are selected,
the output will be zero or one, depending on the GxPOL
bits.
The CLCx Control registers (CLCxCONL and
CLCxCONH) are used to enable the module and interrupts, control the output enable bit, select output polarity
and select the logic function. The CLCx Control registers
also allow the user to control the logic polarity of not only
the cell output, but also some intermediate variables.
REGISTER 21-1:
CLCxCONL: CLCx CONTROL REGISTER LOW
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
LCEN
—
—
—
INTP
INTN
—
—
bit 15
bit 8
R/W-0
R-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
LCOE
LCOUT
LCPOL
—
—
MODE2
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
LCEN: CLCx Enable bit
1 = CLCx is enabled and mixing input signals
0 = CLCx is disabled and has logic zero outputs
bit 14-12
Unimplemented: Read as ‘0’
bit 11
INTP: CLCx Positive Edge Interrupt Enable bit
1 = Interrupt will be generated when a rising edge occurs on LCOUT
0 = Interrupt will not be generated
bit 10
INTN: CLCx Negative Edge Interrupt Enable bit
1 = Interrupt will be generated when a falling edge occurs on LCOUT
0 = Interrupt will not be generated
bit 9-8
Unimplemented: Read as ‘0’
bit 7
LCOE: CLCx Port Enable bit
1 = CLCx port pin output is enabled
0 = CLCx port pin output is disabled
bit 6
LCOUT: CLCx Data Output Status bit
1 = CLCx output high
0 = CLCx output low
bit 5
LCPOL: CLCx Output Polarity Control bit
1 = The output of the module is inverted
0 = The output of the module is not inverted
bit 4-3
Unimplemented: Read as ‘0’
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REGISTER 21-1:
bit 2-0
CLCxCONL: CLCx CONTROL REGISTER LOW (CONTINUED)
MODE[2:0]: CLCx Mode bits
111 = Cell is a 1-input transparent latch with S and R
110 = Cell is a JK flip-flop with R
101 = Cell is a 2-input D flip-flop with R
100 = Cell is a 1-input D flip-flop with S and R
011 = Cell is an SR latch
010 = Cell is a 4-input AND
001 = Cell is an OR-XOR
000 = Cell is an AND-OR
REGISTER 21-2:
CLCxCONH: CLCx CONTROL REGISTER (HIGH)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
G4POL
G3POL
G2POL
G1POL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
Unimplemented: Read as ‘0’
bit 3
G4POL: Gate 4 Polarity Control bit
1 = The output of Channel 4 logic is inverted when applied to the logic cell
0 = The output of Channel 4 logic is not inverted
bit 2
G3POL: Gate 3 Polarity Control bit
1 = The output of Channel 3 logic is inverted when applied to the logic cell
0 = The output of Channel 3 logic is not inverted
bit 1
G2POL: Gate 2 Polarity Control bit
1 = The output of Channel 2 logic is inverted when applied to the logic cell
0 = The output of Channel 2 logic is not inverted
bit 0
G1POL: Gate 1 Polarity Control bit
1 = The output of Channel 1 logic is inverted when applied to the logic cell
0 = The output of Channel 1 logic is not inverted
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REGISTER 21-3:
U-0
CLCxSEL: CLCx INPUT MUX SELECT REGISTER
R/W-0
—
bit 15
U-0
—
R/W-0
R/W-0
DS4[2:0]
U-0
R/W-0
—
R/W-0
R/W-0
DS3[2:0]
bit 8
R/W-0
R/W-0
DS2[2:0]
R/W-0
U-0
—
R/W-0
R/W-0
DS1[2:0]
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
Unimplemented: Read as ‘0’
DS4[2:0]: Data Selection MUX 4 Signal Selection bits
111 = MCCP3 OC out
110 = MCCP1 OC out
101 = Unimplemented
100 = LCD automation timer interrupt
011 = SPIx Input (SDIx) corresponding to the CLCx module(1)
010 = Comparator 3 output
001 = Module-specific CLCx output(1)
000 = CLCIND I/O pin
bit 11
bit 10-8
Unimplemented: Read as ‘0’
DS3[2:0]: Data Selection MUX 3 Signal Selection bits
111 = MCCP3 OC out
110 = MCCP2 OC out
101 = DMA Channel 1 interrupt
100 = UARTx RX output corresponding to the CLCx module(1)
011 = SPIx Output (SDOx) corresponding to the CLCx module(1)
010 = Comparator 2 output
001 = CLCx output(1)
000 = CLCINC I/O pin
Unimplemented: Read as ‘0’
bit 7
bit 6-4
DS2[2:0]: Data Selection MUX 2 Signal Selection bits
111 = MCCP2 OC out
110 = MCCP1 OC out
101 = DMA Channel 0 interrupt
100 = A/D conversion done interrupt
011 = UARTx TX input corresponding to the CLCx module(1)
010 = Comparator 1 output
001 = CLCx output(1)
000 = CLCINB I/O pin
bit 3
bit 2-0
Unimplemented: Read as ‘0’
DS1[2:0]: Data Selection MUX 1 Signal Selection bits
111 = Timer3 match event
110 = Timer2 match event
101 = Unimplemented
100 = REFO output
011 = INTRC/LPRC clock source
010 = SOSC clock source
001 = System clock (TCY)
000 = CLCINA I/O pin
Note 1:
For more information, see Table 21-1.
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TABLE 21-1:
MODULE-SPECIFIC INPUT DATA SOURCES
Input Source
Bit Field Value
DS4[2:0]
DS3[2:0]
DS2[2:0]
CLC1
CLC2
CLC3
CLC4
011
SDI1
SDI2
SDI1
SDI2
001
CLC2 Output
CLC1 Output
CLC4 Output
CLC3 Output
100
U1RX
U2RX
U3RX
U4RX
011
SDO1
SDO2
SDO1
SDO2
001
CLC1 Output
CLC2 Output
CLC1 Output
CLC2 Output
011
U1TX
U2TX
U3TX
U4TX
001
CLC2 Output
CLC1 Output
CLC2 Output
CLC1 Output
REGISTER 21-4:
CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
G2D4T: Gate 2 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 2
0 = The Data Source 4 signal is disabled for Gate 2
bit 14
G2D4N: Gate 2 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 2
0 = The Data Source 4 inverted signal is disabled for Gate 2
bit 13
G2D3T: Gate 2 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 2
0 = The Data Source 3 signal is disabled for Gate 2
bit 12
G2D3N: Gate 2 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 2
0 = The Data Source 3 inverted signal is disabled for Gate 2
bit 11
G2D2T: Gate 2 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 2
0 = The Data Source 2 signal is disabled for Gate 2
bit 10
G2D2N: Gate 2 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 2
0 = The Data Source 2 inverted signal is disabled for Gate 2
bit 9
G2D1T: Gate 2 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 2
0 = The Data Source 1 signal is disabled for Gate 2
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 267
PIC24FJ128GL306 FAMILY
REGISTER 21-4:
CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER (CONTINUED)
bit 8
G2D1N: Gate 2 Data Source 1 Negated Enable bit
1 = The Data Source 1 inverted signal is enabled for Gate 2
0 = The Data Source 1 inverted signal is disabled for Gate 2
bit 7
G1D4T: Gate 1 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 1
0 = The Data Source 4 signal is disabled for Gate 1
bit 6
G1D4N: Gate 1 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 1
0 = The Data Source 4 inverted signal is disabled for Gate 1
bit 5
G1D3T: Gate 1 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 1
0 = The Data Source 3 signal is disabled for Gate 1
bit 4
G1D3N: Gate 1 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 1
0 = The Data Source 3 inverted signal is disabled for Gate 1
bit 3
G1D2T: Gate 1 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 1
0 = The Data Source 2 signal is disabled for Gate 1
bit 2
G1D2N: Gate 1 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 1
0 = The Data Source 2 inverted signal is disabled for Gate 1
bit 1
G1D1T: Gate 1 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 1
0 = The Data Source 1 signal is disabled for Gate 1
bit 0
G1D1N: Gate 1 Data Source 1 Negated Enable bit
1 = The Data Source 1 inverted signal is enabled for Gate 1
0 = The Data Source 1 inverted signal is disabled for Gate 1
DS30010198B-page 268
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PIC24FJ128GL306 FAMILY
REGISTER 21-5:
CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G4D4T
G4D4N
G4D3T
G4D3N
G4D2T
G4D2N
G4D1T
G4D1N
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G3D4T
G3D4N
G3D3T
G3D3N
G3D2T
G3D2N
G3D1T
G3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
G4D4T: Gate 4 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 4
0 = The Data Source 4 signal is disabled for Gate 4
bit 14
G4D4N: Gate 4 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 4
0 = The Data Source 4 inverted signal is disabled for Gate 4
bit 13
G4D3T: Gate 4 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 4
0 = The Data Source 3 signal is disabled for Gate 4
bit 12
G4D3N: Gate 4 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 4
0 = The Data Source 3 inverted signal is disabled for Gate 4
bit 11
G4D2T: Gate 4 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 4
0 = The Data Source 2 signal is disabled for Gate 4
bit 10
G4D2N: Gate 4 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 4
0 = The Data Source 2 inverted signal is disabled for Gate 4
bit 9
G4D1T: Gate 4 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 4
0 = The Data Source 1 signal is disabled for Gate 4
bit 8
G4D1N: Gate 4 Data Source 1 Negated Enable bit
1 = The Data Source 1 inverted signal is enabled for Gate 4
0 = The Data Source 1 inverted signal is disabled for Gate 4
bit 7
G3D4T: Gate 3 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 3
0 = The Data Source 4 signal is disabled for Gate 3
bit 6
G3D4N: Gate 3 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 3
0 = The Data Source 4 inverted signal is disabled for Gate 3
bit 5
G3D3T: Gate 3 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 3
0 = The Data Source 3 signal is disabled for Gate 3
bit 4
G3D3N: Gate 3 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 3
0 = The Data Source 3 inverted signal is disabled for Gate 3
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 269
PIC24FJ128GL306 FAMILY
REGISTER 21-5:
CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER (CONTINUED)
bit 3
G3D2T: Gate 3 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 3
0 = The Data Source 2 signal is disabled for Gate 3
bit 2
G3D2N: Gate 3 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 3
0 = The Data Source 2 inverted signal is disabled for Gate 3
bit 1
G3D1T: Gate 3 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 3
0 = The Data Source 1 signal is disabled for Gate 3
bit 0
G3D1N: Gate 3 Data Source 1 Negated Enable bit
1 = The Data Source 1 inverted signal is enabled for Gate 3
0 = The Data Source 1 inverted signal is disabled for Gate 3
DS30010198B-page 270
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PIC24FJ128GL306 FAMILY
22.0
Note:
12-BIT A/D CONVERTER WITH
THRESHOLD DETECT
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “12-Bit A/D Converter with
Threshold Detect” (www.microchip.com/
DS39739) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in
this data sheet supersedes the
information in the FRM.
22.1
To perform a standard A/D conversion:
1.
The A/D Converter has the following key features:
• Successive Approximation Register (SAR)
Conversion
• Selectable 10-Bit or 12-Bit (default) Conversion
Resolution
• Conversion Speeds of Up to 350 ksps (12-bit) and
400 ksps (10-bit)
• Up to 20 Analog Input Channels (internal and
external)
• Multiple Internal Reference Input Channels
• External Voltage Reference Input Pins
• Unipolar Differential Sample-and-Hold (S/H)
Amplifier
• Automated Threshold Scan and Compare
Operation to Pre-Evaluate Conversion Results
• Selectable Conversion Trigger Source
• Fixed Length (one word per channel),
Configurable Conversion Result Buffer
• Four Options for Results Alignment
• Configurable Interrupt Generation
• Enhanced DMA Operations with Indirect Address
Generation
• Operation During CPU Sleep and Idle modes
Basic Operation
2.
3.
Configure the module:
a) Configure port pins as analog inputs by
setting the appropriate bits in the ANSELx
registers (see Section 11.2 “Configuring
Analog Port Pins (ANSELx)” for more
information).
b) Select the voltage reference source to
match the expected range on analog inputs
(AD1CON2[15:13]).
c) Select the positive and negative multiplexer
inputs for each channel (AD1CHS[15:0]).
d) Select the analog conversion clock to match
the desired data rate with the processor
clock (AD1CON3[7:0]).
e) Select the appropriate sample/conversion
sequence
(AD1CON1[7:4]
and
AD1CON3[12:8]).
f) For Channel A scanning operations, select
the positive channels to be included
(AD1CSSH and AD1CSSL registers).
g) Select how conversion results are
presented in the buffer (AD1CON1[9:8] and
AD1CON5 register).
h) Select the interrupt rate (AD1CON2[5:2]).
i) Turn on A/D module (AD1CON1[15]).
Configure the A/D interrupt (if required):
a) Clear the AD1IF bit (IFS0[13]).
b) Enable the AD1IE interrupt (IEC0[13]).
c) Select the A/D interrupt priority (IPC3[6:4]).
If the module is configured for manual sampling,
set the SAMP bit (AD1CON1[1]) to begin
sampling.
The 12-bit A/D Converter module is an enhanced
version of the 10-bit module offered in earlier PIC24
devices. It is a Successive Approximation Register
(SAR) Converter, enhanced with 12-bit resolution, a
wide range of automatic sampling options, tighter integration with other analog modules and a configurable
results buffer.
It also includes a unique Threshold Detect feature that
allows the module itself to make simple decisions
based on the conversion results, and enhanced operation with the DMA Controller through Peripheral Indirect
Addressing (PIA).
A simplified block diagram for the module is shown in
Figure 22-1.
2019-2020 Microchip Technology Inc.
DS30010198B-page 271
PIC24FJ128GL306 FAMILY
FIGURE 22-1:
12-BIT A/D CONVERTER BLOCK DIAGRAM (PIC24FJ128GL306 FAMILY)
AVDD
AVSS
VREF+
VR Select
Internal Data Bus
VR+
16
VRVR -
VR +
VINH
VINL
SAR
AN0
AN1
VINH
Data Formatting
MUX A
AN2
AN12(1)
Extended DMA Data
VINL
ADC1BUF0:
ADC1BUF15
AN13(1)
AN14(1)
AD1CON1
AD1CON2
AN15(1)
VBG
AVDD
AVSS
MUX B
AN16
AD1CON3
AD1CON4
(1)
VINH
AD1CON5
AD1CHS
AD1CHITL
AD1CSSL
VINL
AD1CSSH
AD1RESDMA
Sample Control
Control Logic
Conversion Control
16
Input MUX Control
DMA Data Bus
Note 1: Available ANx pins are package-dependent.
DS30010198B-page 272
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PIC24FJ128GL306 FAMILY
22.2
Extended DMA Operations
In addition to the standard features available on all 12-bit
A/D Converters, PIC24FJ128GL306 family devices
implement a limited extension of DMA functionality.
This extension adds features that work with the
device’s DMA Controller to expand the A/D module’s
data storage abilities beyond the module’s built-in
buffer.
The Extended DMA functionality is controlled by the
DMAEN bit (AD1CON1[11]); setting this bit enables
the functionality. The DMABM bit (AD1CON1[12])
configures how the DMA feature operates.
22.2.1
EXTENDED BUFFER MODE
Extended Buffer mode (DMABM = 1) maps the A/D
Data Buffer registers and data from all channels above
13 into a user-specified area of data RAM. This allows
users to read the conversion results of channels above
13, which do not have their own memory-mapped A/D
buffer locations, from data memory.
To accomplish this, the DMA destination address must
be configured in Peripheral Indirect Addressing mode,
the DMA destination address must point to the beginning of the buffer, the DMA source address must be
configured in “Remains Unchanged” mode and the
source address should be pointing to the AD1RESDMA
register. The DMA count must be set to generate an
interrupt after the desired number of conversions.
In Extended Buffer mode, the A/D control bits will function
similarly to non-DMA modes. The BUFREGEN bit will still
select between FIFO mode and Channel-Aligned mode,
but the number of words in the destination FIFO will be
determined by the SMPI[4:0] bits in DMA mode. In FIFO
mode, the BUFM bit will still split the output FIFO into two
sets of 13 results (the SMPIx bits should be set accordingly) and the BUFS bit will still indicate which set of
results is being written to and which can be read.
22.2.2
PIA MODE
When DMABM = 0, the A/D module is configured to
function with the DMA Controller for Peripheral Indirect
Addressing (PIA) mode operations. In this mode, the
A/D module generates an 11-bit Indirect Address (IA).
This is ORed with the destination address in the DMA
Controller to define where the A/D conversion data will
be stored.
2019-2020 Microchip Technology Inc.
In PIA mode, the buffer space is created as a series of
contiguous smaller buffers, one per analog channel.
The size of the channel buffer determines how many
analog channels can be accommodated. The size of
the buffer is selected by the DMABL[2:0] bits
(AD1CON4[2:0]). The size options range from a single
word per buffer to 128 words. Each channel is allocated
a buffer of this size, regardless of whether or not the
channel will actually have conversion data.
The IA is created by combining the base address within
a channel buffer with three to five bits (depending on
the buffer size) to identify the channel. The base
address ranges from zero to seven bits wide, depending on the buffer size. The address is right-padded with
a ‘0’ in order to maintain address alignment in the Data
Space. The concatenated channel and base address
bits are then left-padded with zeros, as necessary, to
complete the 11-bit IA.
The IA is configured to auto-increment which channel
is written in each analog input’s sub-buffer during write
operations by using the SMPIx bits (AD1CON2[6:2]).
As with PIA operations for any DMA-enabled module,
the base destination address in the DMADSTn register
must be masked properly to accommodate the IA.
Table 22-1 shows how complete addresses are
formed. Note that the address masking varies for each
buffer size option. Because of masking requirements,
some address ranges may not be available for certain
buffer sizes. Users should verify that the DMA base
address is compatible with the buffer size selected.
Figure 22-2 shows how the parts of the address define
the buffer locations in data memory. In this case, the
module “allocates” 256 bytes of data RAM (1000h to
1100h) for 32 buffers of four words each. However, this
is not a hard allocation and nothing prevents these
locations from being used for other purposes. For
example, in the current case, if Analog Channels 1, 3
and 8 are being sampled and converted, conversion
data will only be written to the channel buffers, starting
at 1008h, 1018h and 1040h. The holes in the PIA buffer
space can be used for any other purpose. It is the
user’s responsibility to keep track of buffer locations
and prevent data overwrites.
DS30010198B-page 273
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TABLE 22-1:
INDIRECT ADDRESS GENERATION IN PIA MODE
DMABL[2:0]
Buffer Size per
Channel (words)
Generated Offset
Address (lower 11 bits)
Available
Input
Channels
Allowable DMADSTn
Addresses
000
1
000 00cc ccc0
32
xxxx xxxx xx00 0000
001
2
000 0ccc ccn0
32
xxxx xxxx x000 0000
010
4
000 cccc cnn0
32
xxxx xxxx 0000 0000
011
8
00c cccc nnn0
32
xxxx xxx0 0000 0000
100
16
0cc cccn nnn0
32
xxxx xx00 0000 0000
101
32
ccc ccnn nnn0
32
xxxx x000 0000 0000
110
64
ccc cnnn nnn0
16
xxxx x000 0000 0000
111
128
ccc nnnn nnn0
8
xxxx x000 0000 0000
Legend: ccc = Channel number (three to five bits), n = Base buffer address (zero to seven bits),
x = User-definable range of DMADSTn for base address, 0 = Masked bits of DMADSTn for IA
FIGURE 22-2:
EXAMPLE OF BUFFER ADDRESS GENERATION IN PIA MODE
(4-WORD BUFFERS PER CHANNEL)
A/D Module
(PIA Mode)
BBA
DMABL[2:0] = 010
(4 Words Per Input)
Data RAM
Channel
ccccc (0-31)
000 cccc cnn0 (IA)
nn (0-3)
(Buffer Base Address)
Ch 0 Buffer (4 Words)
Ch 1 Buffer (4 Words)
Ch 2 Buffer (4 Words)
Ch 3 Buffer (4 Words)
1000h
1008h
1010h
1018h
Ch 7 Buffer (4 Words)
Ch 8 Buffer (4 Words)
1038h
1040h
Destination
Range
1000h (DMA Base Address)
Ch 27 Buffer (4 Words) 10F0h
Ch 29 Buffer (4 Words) 10F8h
Ch 31 Buffer (4 Words) 1100h
DMADSTn
DMA Channel
Buffer Address
Channel Address
Address Mask
DMA Base Address
Ch 0, Word 0
Ch 0, Word 1
Ch 0, Word 2
Ch 0, Word 3
Ch 1, Word 0
Ch 1, Word 1
Ch 1, Word 2
Ch 1, Word 3
DS30010198B-page 274
1000h
1002h
1004h
1006h
1008h
100Ah
100Ch
100Eh
0001
0001
0001
0001
0001
0001
0001
0001
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
0100
0110
1000
1010
1100
1110
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
22.3
Registers
• ANCFG (Register 22-7)
• AD1CHITH and AD1CHITL (Register 22-8 and
Register 22-9)
• AD1CSSH and AD1CSSL (Register 22-10 and
Register 22-11)
• AD1RESDMA (not shown) – The 16-bit conversion
buffer for Extended Buffer mode
The 12-bit A/D Converter is controlled through a total of
12 registers:
• AD1CON1 through AD1CON5 (Register 22-1
through Register 22-5)
• AD1CHS (Register 22-6)
REGISTER 22-1:
R/W-0
AD1CON1: A/D CONTROL REGISTER 1
U-0
ADON
—
R/W-0
ADSIDL
R/W-0
DMABM
(1)
R/W-0
R/W-0
R/W-0
R/W-0
DMAEN
MODE12
FORM1
FORM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
HSC/R/W-0
HSC/R/C-0
SSRC3
SSRC2
SSRC1
SSRC0
—
ASAM
SAMP
DONE
bit 7
bit 0
Legend:
C = Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: A/D Operating Mode bit
1 = A/D Converter is operating
0 = A/D Converter is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: A/D Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
DMABM: Extended DMA Buffer Mode Select bit(1)
1 = Extended Buffer mode: Buffer address is defined by the DMADSTn register
0 = PIA mode: Buffer addresses are defined by the DMA Controller and AD1CON4[2:0]
bit 11
DMAEN: Extended DMA/Buffer Enable bit
1 = Extended DMA and buffer features are enabled
0 = Extended features are disabled
bit 10
MODE12: A/D 12-Bit Operation Mode bit
1 = 12-bit A/D operation
0 = 10-bit A/D operation
bit 9-8
FORM[1:0]: Data Output Format bits (see formats following)
11 = Fractional result, signed, left justified
10 = Absolute fractional result, unsigned, left justified
01 = Decimal result, signed, right justified
00 = Absolute decimal result, unsigned, right justified
bit 7-4
SSRC[3:0]: Sample Clock Source Select bits
0000 = SAMP is cleared by software
0001 = INT0
0010 = Timer3
0011 = Timer5
0101 = Timer1 (will not trigger during Sleep mode)
0110 = Timer1 (may trigger during Sleep mode)
0111 = Auto-Convert mode
Note 1:
This bit is only available when Extended DMA and buffer features are available (DMAEN = 1).
2019-2020 Microchip Technology Inc.
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REGISTER 22-1:
AD1CON1: A/D CONTROL REGISTER 1 (CONTINUED)
bit 3
Unimplemented: Read as ‘0’
bit 2
ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after last conversion; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is manually set
bit 1
SAMP: A/D Sample Enable bit
1 = A/D Sample-and-Hold amplifiers are sampling
0 = A/D Sample-and-Hold amplifiers are holding
bit 0
DONE: A/D Conversion Status bit
1 = A/D conversion cycle has completed
0 = A/D conversion cycle has not started or is in progress
Note 1:
This bit is only available when Extended DMA and buffer features are available (DMAEN = 1).
DS30010198B-page 276
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REGISTER 22-2:
AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
r-0
R/W-0
R/W-0
U-0
U-0
PVCFG1
PVCFG0
NVCFG0
—
BUFREGEN
CSCNA
—
—
bit 15
bit 8
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFS
SMPI4
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
PVCFG[1:0]: A/D Converter Positive Voltage Reference Configuration bits
1x = Unimplemented, do not use
01 = External VREF+
00 = AVDD
bit 13
NVCFG0: A/D Converter Negative Voltage Reference Configuration bit
1 = AVSS
0 = AVSS
bit 12
Reserved: Maintain as ‘0’
bit 11
BUFREGEN: A/D Buffer Register Enable bit
1 = Conversion result is loaded into the buffer location determined by the converted channel
0 = A/D result buffer is treated as a FIFO
bit 10
CSCNA: Scan Input Selections for CH0+ During Sample A bit
1 = Scans inputs
0 = Does not scan inputs
bit 9-8
Unimplemented: Read as ‘0’
bit 7
BUFS: Buffer Fill Status bit
When DMAEN = 1 and DMABM = 1:
1 = A/D is currently filling the destination buffer from [buffer start + (buffer size/2)] to
[buffer start + (buffer size – 1)]. User should access data located from [buffer start] to
[buffer start + (buffer size/2) – 1].
0 = A/D is currently filling the destination buffer from [buffer start] to [buffer start + (buffer size/2) – 1].
User should access data located from [buffer start + (buffer size/2)] to [buffer start + (buffer size – 1)].
When DMAEN = 0:
1 = A/D is currently filling ADC1BUF13-ADC1BUF25, user should access data in
ADC1BUF0-ADC1BUF12
0 = A/D is currently filling ADC1BUF0-ADC1BUF12, user should access data in
ADC1BUF13-ADC1BUF25
2019-2020 Microchip Technology Inc.
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REGISTER 22-2:
AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED)
bit 6-2
SMPI[4:0]: Interrupt Sample/DMA Increment Rate Select bits
When DMAEN = 1 and DMABM = 0:
11111 = Increments the DMA address after completion of the 32nd sample/conversion operation
11110 = Increments the DMA address after completion of the 31st sample/conversion operation
•
•
•
00001 = Increments the DMA address after completion of the 2nd sample/conversion operation
00000 = Increments the DMA address after completion of each sample/conversion operation
When DMAEN = 1 and DMABM = 1:
11111 = Resets the DMA offset after completion of the 32nd sample/conversion operation
11110 = Resets the DMA offset after completion of the 31nd sample/conversion operation
•
•
•
00001 = Resets the DMA offset after completion of the 2nd sample/conversion operation
00000 = Resets the DMA offset after completion of every sample/conversion operation
When DMAEN = 0:
11111 = Interrupts at the completion of the conversion for each 32nd sample
11110 = Interrupts at the completion of the conversion for each 31st sample
•
•
•
00001 = Interrupts at the completion of the conversion for every other sample
00000 = Interrupts at the completion of the conversion for each sample
bit 1
BUFM: Buffer Fill Mode Select bit
1 = Starts buffer filling at ADC1BUF0 on first interrupt and ADC1BUF13 on next interrupt
0 = Always starts filling buffer at ADC1BUF0
bit 0
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
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REGISTER 22-3:
R/W-0
R-0
(1)
ADRC
AD1CON3: A/D CONTROL REGISTER 3
EXTSAM
R/W-0
(2)
PUMPEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ADRC: A/D Conversion Clock Source bit(1)
1 = Dedicated ADC RC clock generator (4 MHz nominal)
0 = Clock derived from system clock
bit 14
EXTSAM: Extended Sampling Time bit
1 = A/D is still sampling after SAMP = 0
0 = A/D is finished sampling
bit 13
PUMPEN: Charge Pump Enable bit(2)
1 = Charge pump for switches is enabled
0 = Charge pump for switches is disabled
bit 12-8
SAMC[4:0]: Auto-Sample Time Select bits
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD
bit 7-0
ADCS[7:0]: A/D Conversion Clock Select bits
11111111 = 256 • TCY = TAD
•
•
•
00000001 = 2 • TCY = TAD
00000000 = TCY = TAD
Note 1:
2:
x = Bit is unknown
Selecting the internal ADC RC clock requires that ADCSx be one or greater. Setting ADCSx = 0 when
ADRC = 1 will violate the TAD (minimum) specification.
The user should enable the charge pump if AVDD is < 2.7V. Longer sample times are required due to the
increase of the internal resistance of the MUX if the charge pump is disabled.
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REGISTER 22-4:
AD1CON4: A/D CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
DMABL[2:0](1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
DMABL[2:0]: DMA Buffer Size Select bits(1)
111 = Allocates 128 words of buffer to each analog input
110 = Allocates 64 words of buffer to each analog input
101 = Allocates 32 words of buffer to each analog input
100 = Allocates 16 words of buffer to each analog input
011 = Allocates 8 words of buffer to each analog input
010 = Allocates 4 words of buffer to each analog input
001 = Allocates 2 words of buffer to each analog input
000 = Allocates 1 word of buffer to each analog input
Note 1:
x = Bit is unknown
The DMABL[2:0] bits are only used when AD1CON1[11] = 1 and AD1CON1[12] = 0; otherwise, their value
is ignored.
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REGISTER 22-5:
AD1CON5: A/D CONTROL REGISTER 5
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
ASEN
LPEN
—
BGREQ
—
—
ASINT1
ASINT0
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
WM1
WM0
CM1
CM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ASEN: Auto-Scan Enable bit
1 = Auto-scan is enabled
0 = Auto-scan is disabled
bit 14
LPEN: Low-Power Enable bit
1 = Low power is enabled after scan
0 = Full power is enabled after scan
bit 13
Unimplemented: Read as ‘0’
bit 12
BGREQ: Band Gap Request bit
1 = Band gap is enabled when the A/D is enabled and active
0 = Band gap is not enabled by the A/D
bit 11-10
Unimplemented: Read as ‘0’
bit 9-8
ASINT[1:0]: Auto-Scan (Threshold Detect) Interrupt Mode bits
11 = Interrupt after Threshold Detect sequence has completed and a valid compare has occurred
10 = Interrupt after a valid compare has occurred
01 = Interrupt after Threshold Detect sequence has completed
00 = No interrupt
bit 7-4
Unimplemented: Read as ‘0’
bit 3-2
WM[1:0]: Write Mode bits
11 = Reserved
10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid
match occurs, as defined by the CMx and ASINTx bits)
01 = Convert and save (conversion results are saved to locations as determined by the register bits
when a match occurs, as defined by the CMx bits)
00 = Legacy operation (conversion data are saved to a location determined by the buffer register bits)
bit 1-0
CM[1:0]: Compare Mode bits
11 = Outside Window mode: Valid match occurs if the conversion result is outside of the window
defined by the corresponding buffer pair
10 = Inside Window mode: Valid match occurs if the conversion result is inside the window defined by
the corresponding buffer pair
01 = Greater Than mode: Valid match occurs if the result is greater than the value in the corresponding
buffer register
00 = Less Than mode: Valid match occurs if the result is less than the value in the corresponding buffer
register
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REGISTER 22-6:
AD1CHS: A/D SAMPLE SELECT REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NB2
CH0NB1
CH0NB0
CH0SB4
CH0SB3
CH0SB2
CH0SB1
CH0SB0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NA2
CH0NA1
CH0NA0
CH0SA4
CH0SA3
CH0SA2
CH0SA1
CH0SA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
CH0NB[2:0]: Sample B Channel 0 Negative Input Select bits
1xx = Unimplemented
011 = Unimplemented
010 = AN1001 = Unimplemented
000 = AVSS
bit 12-8
CH0SB[4:0]: Sample B Channel 0 Positive Input Select bits
11111 = Reserved
11110 = AVDD(1)
11101 = AVSS(1)
11100 = Band Gap Reference (VBG)(1)
10001-11011 = Reserved
10000 = AN16
01111 = AN15
01110 = AN14
01101 = AN13
01100 = AN12
01011 = AN11
01010 = AN10
01001 = AN9
01000 = AN8
00111 = AN7
00110 = AN6
00101 = AN5
00100 = AN4
00011 = AN3
00010 = AN2
00001 = AN1
00000 = AN0
bit 7-5
CH0NA[2:0]: Sample A Channel 0 Negative Input Select bits
Same definitions as for CHONB[2:0].
bit 4-0
CH0SA[4:0]: Sample A Channel 0 Positive Input Select bits
Same definitions as for CHOSB[4:0].
Note 1:
x = Bit is unknown
These input channels do not have corresponding memory-mapped result buffers.
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REGISTER 22-7:
ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
U-0
—
U-0
U-0
—
—
R/W-0
VBGEN3
R/W-0
(1)
VBGEN2
R/W-0
(1)
VBGEN1(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
Unimplemented: Read as ‘0’
bit 2
VBGEN3: A/D Band Gap Reference Enable bit(1)
1 = Band gap reference is enabled
0 = Band gap reference is disabled
bit 1
VBGEN2: Comparator Band Gap Reference Enable bit(1)
1 = Band gap reference is enabled
0 = Band gap reference is disabled
bit 0
VBGEN1: VREG, BOR, HLVD, FRC, NVM and A/D Boost Band Gap Reference Enable bit(1)
1 = Band gap reference is enabled
0 = Band gap reference is disabled
Note 1:
When a module requests a band gap reference voltage, that reference will be enabled automatically after
a brief start-up time. The user can manually enable the band gap references using the ANCFG register,
before enabling the module requesting the band gap reference, to avoid this start-up time (~1 ms).
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REGISTER 22-8:
AD1CHITH: A/D SCAN COMPARE HIT REGISTER HIGH
U/0
U/0
U/0
U/0
U/0
U/0
U/0
U/0
—
—
—
—
—
—
—
—
bit 15
bit 8
U/0
U/0
U/0
U/0
U/0
U/0
U/0
R/W-0
—
—
—
—
—
—
—
CHH16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-1
Unimplemented: Read as ‘0’
bit 0
CHH16: A/D Compare Hit bit
If CM[1:0] = 11:
1 = A/D Result Buffer n has been written with data or a match has occurred
0 = A/D Result Buffer n has not been written with data
For All Other Values of CM[1:0]:
1 = A match has occurred on A/D Result Channel n
0 = No match has occurred on A/D Result Channel n
REGISTER 22-9:
R/W-0
AD1CHITL: A/D SCAN COMPARE HIT REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHH[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHH[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
CHH[15:0]: A/D Compare Hit bits
If CM[1:0] = 11:
1 = A/D Result Buffer n has been written with data or a match has occurred
0 = A/D Result Buffer n has not been written with data
For All Other Values of CM[1:0]:
1 = A match has occurred on A/D Result Channel n
0 = No match has occurred on A/D Result Channel n
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REGISTER 22-10: AD1CSSH: A/D INPUT SCAN SELECT REGISTER HIGH
U-0
R/W-0
—
R/W-0
R/W-0
CSS[30:28]
U-0
U-0
U-0
U-0
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CSS16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CSS[30:28]: A/D Input Scan Selection bits
1 = Includes corresponding channel for input scan
0 = Skips channel for input scan
bit 11-1
Unimplemented: Read as ‘0’
bit 0
CSS16: A/D Input Scan Selection bit
1 = Includes corresponding channel for input scan
0 = Skips channel for input scan
x = Bit is unknown
REGISTER 22-11: AD1CSSL: A/D INPUT SCAN SELECT REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS[15:8]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
CSS[15:0]: A/D Input Scan Selection bits
1 = Includes corresponding channel for input scan
0 = Skips channel for input scan
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FIGURE 22-3:
12-BIT A/D CONVERTER ANALOG INPUT MODEL
AVDD
Sampling
Switch
VT = 0.6V
Rs
VA
ANx
CPIN
SS RSS
RIC 250
VT = 0.6V
CHOLD
= S/H Input Capacitance
= 40 pF
ILEAKAGE
500 nA
AVSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
ILEAKAGE = Leakage Current at the Pin due to
Various Junctions
RIC
= Interconnect Resistance
RSS
= Sampling Switch Resistance
CHOLD
= Sample/Hold Capacitance
Sampling
RMAX
Switch
(RSS 3 k)
RMIN
AVDD (V)
AVDDMIN
AVDDMAX
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs 2.5 k.
EQUATION 22-1:
A/D CONVERSION CLOCK PERIOD
TAD = TCY (ADCS + 1)
ADCS =
TAD
–1
TCY
Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled.
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FIGURE 22-4:
12-BIT A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
1111 1111 1111 (4095)
1111 1111 1110 (4094)
0010 0000 0011 (2051)
0010 0000 0010 (2050)
0010 0000 0001 (2049)
0010 0000 0000 (2048)
0001 1111 1111 (2047)
0001 1111 1110 (2046)
0001 1111 1101 (2045)
0000 0000 0001 (1)
2019-2020 Microchip Technology Inc.
(VINH – VINL)
VR+
4096
4095 * (VR+ – VR-)
VR- +
4096
2048 * (VR+ – VR-)
VR-+
VR- +
4096
0
Voltage Level
VRVR+ – VR-
0000 0000 0000 (0)
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FIGURE 22-5:
10-BIT A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
11 1111 1111 (1023)
11 1111 1110 (1022)
10 0000 0011 (515)
10 0000 0010 (514)
10 0000 0001 (513)
10 0000 0000 (512)
01 1111 1111 (511)
01 1111 1110 (510)
01 1111 1101 (509)
00 0000 0001 (1)
DS30010198B-page 288
(VINH – VINL)
VR+
1024
1023 * (VR+ – VR-)
VR- +
1024
VR-+
512 * (VR+ – VR-)
1024
VR- +
VR+ – VR-
0
Voltage Level
VR-
00 0000 0000 (0)
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
23.0
Note:
TRIPLE COMPARATOR
MODULE
voltage reference input from one of the internal band
gap references or the comparator voltage reference
generator (VBG and CVREF).
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive reference source. For more information, refer
to “Scalable Comparator Module”
(www.microchip.com/DS39734) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be
configured to use any one of five external analog inputs
(CxINA, CxINB, CxINC, CxIND and CVREF+) and a
FIGURE 23-1:
Each comparator has its own control register,
CMxCON (Register 23-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 23-2).
EVPOL[1:0]
Input
Select
Logic
CxINB
CPOL
VINVIN+
00
01
CxINC
Trigger/Interrupt
Logic
CEVT
COE
C1
C1OUT
Pin
COUT
–
10
CxIND
CVREF+
A simplified block diagram of the module in shown in
Figure 23-1. Diagrams of the possible individual
comparator configurations are shown in Figure 23-2
through Figure 23-4.
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
CCH[1:0]
VBG
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE bit equals
‘1’, the I/O pad logic makes the unsynchronized output
of the comparator available on the pin.
00
11
EVPOL[1:0]
11
CPOL
VINCVREFM[1:0](1)
VIN+
0
CVREF+
1
CVREFP(1)
COE
C2OUT
Pin
COUT
EVPOL[1:0]
+
Comparator Voltage
Reference
CEVT
C2
0
CxINA
Trigger/Interrupt
Logic
1
CPOL
VINVIN+
Trigger/Interrupt
Logic
CEVT
COE
C3
C3OUT
Pin
COUT
CREF
Note 1: Refer to the CVRCON register (Register 24-1) for bit details.
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FIGURE 23-2:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0
Comparator Off
CEN = 0, CREF = x, CCH[1:0] = xx
COE
VINVIN+
Cx
Off (Read as ‘0’)
CxOUT
Pin
Comparator CxINB > CxINA Compare
Comparator CxINC > CxINA Compare
CEN = 1, CCH[1:0] = 00, CVREFM[1:0] = xx
CEN = 1, CCH[1:0] = 01, CVREFM[1:0] = xx
CxINB
CxINA
COE
VINVIN+
Cx
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 00
CEN = 1, CCH[1:0] = 10, CVREFM[1:0] = xx
CxINA
COE
VINVIN+
CxOUT
Pin
Comparator VBG > CxINA Compare
Comparator CxIND > CxINA Compare
CxIND
Cx
VIN+
CxINA
CxOUT
Pin
COE
VIN-
CxINC
Cx
Cx
VIN+
CxINA
CxOUT
Pin
COE
VIN-
VBG
CxOUT
Pin
Comparator CVREF+ > CxINA Compare
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 11
VIN+
CxINA
FIGURE 23-3:
COE
VIN-
CVREF+
Cx
CxOUT
Pin
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0
Comparator CxINB > CVREF Compare
Comparator CxINC > CVREF Compare
CEN = 1, CCH[1:0] = 00, CVREFM[1:0] = xx
CEN = 1, CCH[1:0] = 01, CVREFM[1:0] = xx
CxINB
CVREF
COE
VINVIN+
CxINC
Cx
CVREF
CxOUT
Pin
CVREF
VIN+
Cx
CxOUT
Pin
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 00
CEN = 1, CCH[1:0] = 10, CVREFM[1:0] = xx
COE
VIN-
VIN+
Comparator VBG > CVREF Compare
Comparator CxIND > CVREF Compare
CxIND
COE
VIN-
VBG
Cx
CVREF
CxOUT
Pin
COE
VINVIN+
Cx
CxOUT
Pin
Comparator CVREF+ > CVREF Compare
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 11
CVREF+
CVREF
DS30010198B-page 290
COE
VINVIN+
Cx
CxOUT
Pin
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FIGURE 23-4:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 1
Comparator CxINB > CVREF Compare
Comparator CxINC > CVREF Compare
CEN = 1, CCH[1:0] = 00, CVREFM[1:0] = xx
CEN = 1, CCH[1:0] = 01, CVREFM[1:0] = xx
CxINB
CVREF+
COE
VINVIN+
CxINC
Cx
CxOUT
Pin
CVREF+
VIN+
COE
VBG
Cx
2019-2020 Microchip Technology Inc.
Cx
CxOUT
Pin
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 00
CEN = 1, CCH[1:] = 10, CVREFM[1:0] = xx
VIN-
VIN+
Comparator VBG > CVREF Compare
Comparator CxIND > CVREF Compare
CxIND
CVREF+
COE
VIN-
CxOUT
Pin
CVREF+
COE
VINVIN+
Cx
CxOUT
Pin
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REGISTER 23-1:
CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3)
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
HS/R/W-0
HSC/R-0
CEN
COE
CPOL
—
—
—
CEVT
COUT
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
bit 7
bit 0
Legend:
HS = Hardware Settable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CEN: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14
COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-10
Unimplemented: Read as ‘0’
bit 9
CEVT: Comparator Event bit
1 = Comparator event that is defined by EVPOL[1:0] has occurred; subsequent triggers and interrupts
are disabled until the bit is cleared
0 = Comparator event has not occurred
bit 8
COUT: Comparator Output bit
When CPOL = 0:
1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1:
1 = VIN+ < VIN0 = VIN+ > VIN-
bit 7-6
EVPOL[1:0]: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (noninverted polarity):
High-to-low transition only.
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
01 = Trigger/event/interrupt is generated on transition of comparator output:
If CPOL = 0 (noninverted polarity):
Low-to-high transition only.
If CPOL = 1 (inverted polarity):
High-to-low transition only.
00 = Trigger/event/interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
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REGISTER 23-1:
CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3) (CONTINUED)
bit 4
CREF: Comparator Reference Select bits (noninverting input)
1 = Noninverting input connects to the internal CVREF voltage
0 = Noninverting input connects to the CxINA pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH[1:0]: Comparator Channel Select bits
11 = Inverting input of the comparator connects to the internal selectable reference voltage specified
by the CVREFM[1:0] bits in the CVRCON register
10 = Inverting input of the comparator connects to the CxIND pin
01 = Inverting input of the comparator connects to the CxINC pin
00 = Inverting input of the comparator connects to the CxINB pin
REGISTER 23-2:
CMSTAT: COMPARATOR MODULE STATUS REGISTER
R/W-0
U-0
U-0
U-0
U-0
HSC/R-0
HSC/R-0
HSC/R-0
CMIDL
—
—
—
—
C3EVT
C2EVT
C1EVT
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
HSC/R-0
HSC/R-0
HSC/R-0
—
—
—
—
—
C3OUT
C2OUT
C1OUT
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CMIDL: Comparator Stop in Idle Mode bit
1 = Discontinues operation of all comparators when device enters Idle mode
0 = Continues operation of all enabled comparators in Idle mode
bit 14-11
Unimplemented: Read as ‘0’
bit 10
C3EVT: Comparator 3 Event Status bit (read-only)
Shows the current event status of Comparator 3 (CM3CON[9]).
bit 9
C2EVT: Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON[9]).
bit 8
C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON[9]).
bit 7-3
Unimplemented: Read as ‘0’
bit 2
C3OUT: Comparator 3 Output Status bit (read-only)
Shows the current output of Comparator 3 (CM3CON[8]).
bit 1
C2OUT: Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON[8]).
bit 0
C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON[8]).
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NOTES:
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24.0
Note:
COMPARATOR VOLTAGE
REFERENCE
24.1
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “Dual Comparator Module”
(www.microchip.com/DS39710) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
Configuring the Comparator
Voltage Reference
The voltage reference module is controlled through the
CVRCON register (Register 24-1). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The primary difference between the ranges is the size of the steps
selected by the CVREF Value Selection bits (CVR[4:0]),
with one range offering finer resolution.
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF-. The voltage source is selected by the CVRSS
bit (CVRCON[5]).
The settling time of the comparator voltage reference
must be considered when changing the CVREF output.
FIGURE 24-1:
CVREF+
AVDD
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
CVR[4:0]
R
CVREN
R
R
32 Steps
32-to-1 MUX
R
CVREF
CVROE
R
R
R
CVREF-
CVREF
Pin
CVRSS = 1
CVRSS = 0
AVSS
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REGISTER 24-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
CVREFP
CVREFM1
CVREFM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRSS
CVR4
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10
CVREFP: Comparator Voltage Reference Select bit (valid only when CREF is ‘1’)
1 = CVREF+ is used as a reference voltage to the comparators
0 = The CVR[4:0] bits (5-bit DAC) within this module provide the reference voltage to the comparators
bit 9-8
CVREFM[1:0]: Comparator Band Gap Reference Source Select bits (valid only when CCH[1:0] = 11)
00 = Band gap voltage is provided as an input to the comparators
01 = Reserved
10 = Reserved
11 = CVREF+ is provided as an input to the comparators
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on the CVREF pin
0 = CVREF voltage level is disconnected from the CVREF pin
bit 5
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = CVREF+ – CVREF0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 4-0
CVR[4:0]: Comparator VREF Value Selection bits (0 CVR[4:0] 31)
When CVRSS = 1:
CVREF = (CVREF-) + (CVR[4:0]/32) (CVREF+ – CVREF-)
When CVRSS = 0:
CVREF = (AVSS) + (CVR[4:0]/32) (AVDD – AVSS)
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25.0
HIGH/LOW-VOLTAGE DETECT
(HLVD)
Note:
An interrupt flag is set if the device experiences an
excursion past the trip point in the direction of change.
If the interrupt is enabled, the program execution will
branch to the interrupt vector address and the software
can then respond to the interrupt. The HLVDIF flag may
be set during a POR or BOR event. The firmware
should clear the flag before the application uses it for
the first time, even if the interrupt was disabled.
This data sheet summarizes the features
of the PIC24FJ128GL306 family of
devices. It is not intended to be a
comprehensive reference source. For
more information, refer to “High-Level
Integration
with
Programmable
High/Low-Voltage Detect (HLVD)”
(www.microchip.com/DS39725) in the
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data
sheet supersedes the information in the
FRM.
The HLVD Control register (see Register 25-1)
completely controls the operation of the HLVD module.
This allows the circuitry to be “turned off” by the user
under software control, which minimizes the current
consumption for the device.
The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
FIGURE 25-1:
HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDD
VDD
HLVDIN
HLVDL[3:0]
16-to-1 MUX
CMPEN
VDIR
Set
HLVDIF
Band Gap
1.2V Typical
HLVDEN
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REGISTER 25-1:
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
HLVDEN
bit 15
U-0
—
R/W-0
LSIDL
U-0
—
R/W-0
VDIR
HS/HC/R-0
BGVST
HS/HC/R-0
IRVST
R/S-0
CMPEN(3)
bit 7
U-0
—
U-0
—
U-0
—
R/W-0
HLVDL3
R/W-0
HLVDL2
R/W-0
HLVDL1
Legend:
R = Readable bit
-n = Value at POR
bit 15
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
HS/HC/R-0
HLVDEVT(2)
bit 8
R/W-0
HLVDL0
bit 0
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
S = Settable bit
HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD is enabled
0 = HLVD is disabled
Unimplemented: Read as ‘0’
LSIDL: HLVD Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
Unimplemented: Read as ‘0’
VDIR: Voltage Change Direction Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL[3:0])
0 = Event occurs when voltage equals or falls below trip point (HLVDL[3:0])
BGVST: Band Gap Voltage Stable Flag bit
1 = Indicates that the band gap voltage is stable
0 = Indicates that the band gap voltage is unstable
IRVST: Internal Reference Voltage Stable Flag bit
1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the
specified voltage range
0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt
flag at the specified voltage range and the HLVD interrupt should not be enabled
HLVDEVT: High/Low-Voltage Detect Event Status bit(2)
1 = HLVD event is true during current instruction cycle
0 = HLVD event is not true during current instruction cycle
CMPEN: High/Low-Voltage Detect Comparator Enable bit(3)
1 = HLVD comparator is enabled
0 = HLVD comparator is disabled
Unimplemented: Read as ‘0’
HLVDL[3:0]: High/Low-Voltage Detection Limit bits
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = Trip Point 1(1)
1101 = Trip Point 2(1)
1100 = Trip Point 3(1)
•
•
•
0100 = Trip Point 11(1)
00xx = Unused
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-4
bit 3-0
Note 1:
2:
3:
For the actual trip point, see Section 30.0 “Electrical Characteristics”.
The HLVDIF flag cannot be cleared by software unless HLVDEVT = 0. The voltage must be monitored so
that the HLVD condition (as set by VDIR and HLVDL[3:0]) is not asserted.
CMPEN can only be written when the HLVDEN bit = 1.
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26.0
Note:
DEADMAN TIMER (DMT)
This data sheet summarizes the features
of the PIC24FJ128GL306 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Deadman Timer (DMT)”
(www.microchip.com/DS70005155) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The primary function of the Deadman Timer (DMT) is to
interrupt the processor in the event of a software malfunction. The DMT, which works on the system clock, is
a free-running instruction fetch timer. The DMT is
FIGURE 26-1:
clocked whenever an instruction fetch occurs until a
count match occurs. Instructions are not fetched when
the processor is in Sleep mode.
The DMT can be enabled in the Configuration fuse or
by software in the DMTCON register by setting the ON
bit. The DMT consists of a 32-bit counter with a
time-out count match value, as specified by the two
16-bit Configuration Fuse registers: FDMTCNTL and
FDMTCNTH.
A DMT is typically used in mission-critical and safetycritical applications, where any single failure of
software functionality and sequencing must be
detected.
Figure 26-1 shows a block diagram of the Deadman
Timer module.
DEADMAN TIMER BLOCK DIAGRAM
BAD1
BAD2
Improper Sequence
Flag
DMT Enable
Instruction Fetched Strobe(2)
32-Bit Counter
(Counter) = DMT Max. Count(1)
DMT Event
System Clock
Note 1: DMT Max. Count is controlled by the initial value of the FDMTCNTL and FDMTCNTH Configuration registers.
2: DMT window interval is controlled by the value of the FDMTIVTL and FDMTIVTH Configuration registers.
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26.1
Deadman Timer Control Registers
REGISTER 26-1:
DMTCON: DEADMAN TIMER CONTROL REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
ON(1)
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ON: DMT Module Enable bit(1)
1 = Deadman Timer module is enabled
0 = Deadman Timer module is not enabled
bit 14-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
This bit has control only when DMTDIS = 0 in the FDMT register.
REGISTER 26-2:
R/W-0
DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP1[7:0]
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
STEP1[7:0]: DMT Preclear Enable bits
01000000 =
Enables the Deadman Timer preclear (STEP1)
All Other
Write Patterns = Sets the BAD1 flag; these bits are cleared when a DMT Reset event occurs.
STEP1[7:0] bits are also cleared if the STEP2[7:0] bits are loaded with the correct
value in the correct sequence.
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 26-3:
DMTCLR: DEADMAN TIMER CLEAR REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP2[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
STEP2[7:0]: DMT Clear Timer bits
00001000 =
Clears STEP1[7:0], STEP2[7:0] and the Deadman Timer if preceded by the correct loading of the STEP1[7:0] bits in the correct sequence. The write to these bits may be verified
by reading the DMTCNTL/H register pair and observing the counter being reset.
All Other
Write Patterns = Sets the BAD2 bit; the value of STEP1[7:0] will remain unchanged and the new value
being written to STEP2[7:0] will be captured. These bits are cleared when a DMT
Reset event occurs.
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REGISTER 26-4:
DMTSTAT: DEADMAN TIMER STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
HC/R-0
HC/R-0
HC/R-0
U-0
U-0
U-0
U-0
R-0
BAD1
BAD2
DMTEVENT
—
—
—
—
WINOPN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7
BAD1: Deadman Timer Bad STEP1[7:0] Value Detect bit
1 = Incorrect STEP1[7:0] value was detected
0 = Incorrect STEP1[7:0] value was not detected
bit 6
BAD2: Deadman Timer Bad STEP2[7:0] Value Detect bit
1 = Incorrect STEP2[7:0] value was detected
0 = Incorrect STEP2[7:0] value was not detected
bit 5
DMTEVENT: Deadman Timer Event bit
1 = Deadman Timer event was detected (counter expired, or bad STEP1[7:0] or STEP2[7:0] value was
entered prior to counter increment)
0 = Deadman Timer event was not detected
bit 4-1
Unimplemented: Read as ‘0’
bit 0
WINOPN: Deadman Timer Clear Window bit
1 = Deadman Timer clear window is open
0 = Deadman Timer clear window is not open
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REGISTER 26-5:
R-0
DMTCNTL: DEADMAN TIMER COUNT REGISTER LOW
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER[15:8]
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
COUNTER[15:0]: Read Current Contents of Lower DMT Counter bits
REGISTER 26-6:
R-0
DMTCNTH: DEADMAN TIMER COUNT REGISTER HIGH
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER[31:24]
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER[23:16]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
COUNTER[31:16]: Read Current Contents of Higher DMT Counter bits
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REGISTER 26-7:
R-y
DMTPSCNTL: DMT POST-CONFIGURE COUNT STATUS REGISTER LOW
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSCNT[15:8]
bit 15
bit 8
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSCNT[7:0]
bit 7
bit 0
Legend:
y = Value from Configuration bit on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PSCNT[15:0]: Lower DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTL Configuration register.
REGISTER 26-8:
R-y
DMTPSCNTH: DMT POST-CONFIGURE COUNT STATUS REGISTER HIGH
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSCNT[31:24]
bit 15
bit 8
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSCNT[23:16]
bit 7
bit 0
Legend:
y = Value from Configuration bit on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PSCNT[31:16]: Higher DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTH Configuration register.
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REGISTER 26-9:
R-y
DMTPSINTVL: DMT POST-CONFIGURE INTERVAL STATUS REGISTER LOW
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSINTV[15:8]
bit 15
bit 8
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSINTV[7:0]
bit 7
bit 0
Legend:
y = Value from Configuration bit on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PSINTV[15:0]: Lower DMT Window Interval Configuration Status bits
This is always the value of the FDMTIVTL Configuration register.
REGISTER 26-10: DMTPSINTVH: DMT POST-CONFIGURE INTERVAL STATUS REGISTER HIGH
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSINTV[31:24]
bit 15
bit 8
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSINTV[23:16]
bit 7
bit 0
Legend:
y = Value from Configuration bit on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PSINTV[15:0]: Higher DMT Window Interval Configuration Status bits
This is always the value of the FDMTIVTH Configuration register.
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REGISTER 26-11: DMTHOLDREG: DMT HOLD REGISTER(1)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
UPRCNT[15:8]
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
UPRCNT[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
UPRCNT[15:0]: DMTCNTH Register Value When DMTCNTL/DMTCNTH were Last Read bits
Note 1:
The DMTHOLDREG register is initialized to ‘0’ on Reset, and is only loaded when the DMTCNTL and
DMTCNTH registers are read.
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27.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to the following sections of the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
• “Watchdog Timer (WDT)”
(www.microchip.com/DS39697)
• “High-Level Device Integration”
(www.microchip.com/DS39719)
• “Programming and Diagnostics”
(www.microchip.com/DS39716)
PIC24FJ128GL306 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
•
•
•
•
•
•
Flexible Configuration
Watchdog Timer (WDT)
Code Protection
JTAG Boundary Scan Interface
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Emulation
27.1
Configuration Bits
The Configuration bits are stored in the last page location of implemented program memory. These bits can be
set or cleared to select various device configurations.
There are two types of Configuration bits: system operation bits and code-protect bits. The system operation
bits determine the power-on settings for system-level
components, such as the oscillator and the Watchdog
Timer. The code-protect bits prevent program memory
from being read and written.
27.1.1
CONSIDERATIONS FOR
CONFIGURING PIC24FJ128GL306
FAMILY DEVICES
In PIC24FJ128GL306 family devices, the Configuration
bytes are implemented as volatile memory. This means
that configuration data must be programmed each time
the device is powered up. Configuration data are stored
in the three words at the top of the on-chip program
memory space, known as the Flash Configuration
Words. Their specific locations are shown in Table 27-1.
The configuration data are automatically loaded from the
Flash Configuration Words to the proper Configuration
registers during device Resets.
Note:
Configuration data are reloaded on all
types of device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper byte of all Flash Configuration Words in
program memory should always be ‘0000 0000’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘0’s to these
locations has no effect on device operation.
2019-2020 Microchip Technology Inc.
DS30010198B-page 307
PIC24FJ128GL306 FAMILY
TABLE 27-1:
CONFIGURATION WORD ADDRESSES
Configuration Register
FSEC
PIC24FJ128GL30X
PIC24FJ64GL30X
0x015F00
0x00AF00
FBSLIM
0x015F10
0x00AF10
FSIGN
0x015F14
0x00AF14
FOSCSEL
0x015F18
0x00AF18
FOSC
0x015F1C
0x00AF1C
FWDT
0x015F20
0x00AF20
FPOR
0x015F24
0x00AF24
FICD
0x015F28
0x00AF28
FDMTIVTL
0x015F2C
0x00AF2C
FDMTIVTH
0x015F30
0x00AF30
FDMTCNTL
0x015F34
0x00AF34
FDMTCNTH
0x015F38
0x00AF38
FDMT
0x015F3C
0x00AF3C
FDEVOPT1
0x015F40
0x00AF40
DS30010198B-page 308
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2019-2020 Microchip Technology Inc.
TABLE 27-2:
Register
Name
CONFIGURATION REGISTER MAP
Bits
23-16
Bit 15
Bit 14
Bit 13
Bit 12
—
FSEC
—
AIVTDIS
—
—
FBSLIM
—
—
—
—
FSIGN
—
r(2)
—
—
Bit 11
Bit 10
Bit 9
CSS[2:0]
CWRP
—
—
—
—
—
(2)
r
(2)
IESO
—
—
—
—
—
—
—
—
r
—
—
—
—
—
—
—
—
FWDT
—
—
—
WDTCMX
—
FPOR
—
—
—
—
—
—
—
—
—
Bit 6
GSS[1:0]
—
FOSC
—
Bit 7
Bit 5
Bit 4
Bit 3
GWRP
—
BSEN
—
—
Bit 2
Bit 1
BSS[1:0]
Bit 0
BWRP
BSLIM[12:0]
FOSCSEL
WDTCLK[1:0]
Bit 8
—
—
—
—
—
—
PLLMODE[3:0]
FCKSM[1:0]
WDTWIN[1:0] WINDIS
—
—
IOL1WAY
FWDTEN[1:0]
PLLSS
—
—
FNOSC[2:0]
SOSCSEL OSCIOFNC
FWPSA
POSCMD[1:0]
WDTPS[3:0]
—
—
—
—
—
DNVPEN
LPCFG
BOREN[1:0]
—
r(1)
—
JTAGEN
—
—
—
ICS[1:0]
FICD
—
FDMTIVTL
—
DMTIVT[15:0]
FDMTIVTH
—
DMTIVT[31:16]
FDMTCNTL
—
DMTCNT[15:0]
FDMTCNTH
—
FDMT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMTDIS
FDEVOPT1
—
—
—
—
—
—
SMB3EN
—
—
—
—
—
ALTI2C1
SOSCHP
TMPRPIN
ALTCMPI
—
DMTCNT[31:16]
Legend: — = unimplemented, read as ‘1’.
2: Bit is reserved, maintain as ‘0’.
DS30010198B-page 309
PIC24FJ128GL306 FAMILY
Note 1: Bit is reserved, maintain as ‘1’.
PIC24FJ128GL306 FAMILY
REGISTER 27-1:
FSEC CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
U-1
U-1
U-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
AIVTDIS
—
—
—
CSS2
CSS1
CSS0
CWRP
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
U-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
GSS1
GSS0
GWRP
—
BSEN
BSS1
BSS0
BWRP
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘1’
bit 15
AIVTDIS: Alternate Interrupt Vector Table Disable bit
1 = Disables AIVT; AIVTEN bit (INTCON2[8]) is not available
0 = Enables AIVT; AIVTEN bit (INTCON2[8]) is available
bit 14-12
Unimplemented: Read as ‘1’
bit 11-9
CSS[2:0]: Configuration Segment (CS) Code Protection Level bits
111 = No protection (other than CWRP)
110 = Standard security
10x = Enhanced security
0xx = High security
bit 8
CWRP: Configuration Segment Program Write Protection bit
1 = Configuration Segment is not write-protected
0 = Configuration Segment is write-protected
bit 7-6
GSS[1:0]: General Segment (GS) Code Protection Level bits
11 = No protection (other than GWRP)
10 = Standard security
0x = High security
bit 5
GWRP: General Segment Program Write Protection bit
1 = General Segment is not write-protected
0 = General Segment is write-protected
bit 4
Unimplemented: Read as ‘1’
bit 3
BSEN: Boot Segment (BS) Control bit
1 = No Boot Segment is enabled
0 = Boot Segment size is determined by BSLIM[12:0]
bit 2-1
BSS[1:0]: Boot Segment Code Protection Level bits
11 = No protection (other than BWRP)
10 = Standard security
0x = High security
bit 0
BWRP: Boot Segment Program Write Protection bit
1 = Boot Segment can be written
0 = Boot Segment is write-protected
DS30010198B-page 310
x = Bit is unknown
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 27-2:
FBSLIM CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
U-1
U-1
—
—
—
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
BSLIM[12:8]
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
BSLIM[7:0]
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-13
Unimplemented: Read as ‘1’
bit 12-0
BSLIM[12:0]: Active Boot Segment Code Flash Page Address Limit (inverted) bits
This bit field contains the last active Boot Segment Page + 1 (i.e., first page address of GS). The value
is stored as an inverted page address, such that programming additional ‘0’s can only increase the size
of BS. If the BSLIM[12:0] bits are set to all ‘1’s (unprogrammed default), the active Boot Segment size
is zero.
2019-2020 Microchip Technology Inc.
DS30010198B-page 311
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REGISTER 27-3:
FSIGN CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
r-0
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 15
bit 8
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
PO = Program Once bit
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘1’
bit 15
Reserved: Maintain as ‘0’
bit 14-0
Unimplemented: Read as ‘1’
x = Bit is unknown
\
DS30010198B-page 312
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PIC24FJ128GL306 FAMILY
REGISTER 27-4:
FOSCSEL CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
r-0
r-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
IESO
PLLMODE3
PLLMODE2
PLLMODE1
PLLMODE0
FNOSC2
FNOSC1
FNOSC0
bit 7
bit 0
Legend:
PO = Program Once bit
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-10
Unimplemented: Read as ‘1’
bit 9-8
Reserved: Maintain as ‘0’
bit 7
IESO: Two-Speed Oscillator Start-up Enable bit
1 = Starts up the device with FRC, then automatically switches to the user-selected oscillator when ready
0 = Starts up the device with the user-selected oscillator source
bit 6-3
PLLMODE[3:0]: Frequency Multiplier Select bits
1111 = No PLL is used (PLLEN bit is unavailable)
1110 = 8x PLL is selected
1101 = 6x PLL is selected
1100 = 4x PLL is selected
0111 = 96 MHz PLL is selected (Input Frequency = 48 MHz)
0110 = 96 MHz PLL is selected (Input Frequency = 32 MHz)
0101 = 96 MHz PLL is selected (Input Frequency = 24 MHz)
0100 = 96 MHz PLL is selected (Input Frequency = 20 MHz)
0011 = 96 MHz PLL is selected (Input Frequency = 16 MHz)
0010 = 96 MHz PLL is selected (Input Frequency = 12 MHz)
0001 = 96 MHz PLL is selected (Input Frequency = 8 MHz)
0000 = 96 MHz PLL is selected (Input Frequency = 4 MHz)
bit 2-0
FNOSC[2:0]: Oscillator Selection bits
111 = Oscillator with Frequency Divider (OSCFDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
2019-2020 Microchip Technology Inc.
DS30010198B-page 313
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REGISTER 27-5:
FOSC CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
FCKSM1
FCKSM0
IOL1WAY
PLLSS
SOSCSEL
OSCIOFNC
POSCMD1
POSCMD0
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-8
Unimplemented: Read as ‘1’
bit 7-6
FCKSM[1:0]: Clock Switching and Monitor Selection bits
1x = Clock switching and the Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching and the Fail-Safe Clock Monitor are enabled
bit 5
IOL1WAY: Peripheral Pin Select Configuration bit
1 = The IOLOCK bit can be set only once (with unlock sequence).
0 = The IOLOCK bit can be set and cleared as needed (with unlock sequence)
bit 4
PLLSS: PLL Secondary Selection Configuration bit
This Configuration bit only takes effect when the PLL is NOT being used by the system (i.e., not
selected as part of the system clock source). Used to generate an independent clock out of REFO.
1 = PLL is fed by the Primary Oscillator
0 = PLL is fed by the on-chip Fast RC (FRC) Oscillator
bit 3
SOSCSEL: SOSC Selection Configuration bit
1 = Crystal (SOSCI/SOSCO) mode
0 = Digital (SCLKI) Externally Supplied Clock mode
bit 2
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output signal is active on the OSCO pin (when the Primary Oscillator is disabled or configured
for EC mode)
0 = CLKO output is disabled
bit 1-0
POSCMD[1:0]: Primary Oscillator Configuration bits
11 = Primary Oscillator mode is disabled
10 = HS Oscillator mode is selected (10 MHz-32 MHz)
01 = XT Oscillator mode is selected (1.5 MHz-10 MHz)
00 = External Clock mode is selected
DS30010198B-page 314
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PIC24FJ128GL306 FAMILY
REGISTER 27-6:
FWDT CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
R/PO-1
R/PO-1
U-1
R/PO-1
U-1
R/PO-1
R/PO-1
—
WDTCLK1
WDTCLK0
—
WDTCMX
—
WDTWIN1
WDTWIN0
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
WINDIS
FWDTEN1
FWDTEN0
FWPSA
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-15
Unimplemented: Read as ‘1’
bit 14-13
WDTCLK[1:0]: Watchdog Timer Clock Select bits (when WDTCMX = 1)
11 = Always uses LPRC
10 = Uses FRC when WINDIS = 0, system clock is not LPRC and device is not in Sleep; otherwise,
uses LPRC
01 = Always uses SOSC
00 = Uses peripheral clock when system clock is not LPRC and device is not in Sleep; otherwise, uses
LPRC
bit 12
Unimplemented: Read as ‘1’
bit 11
WDTCMX: WDT Clock MUX Control bit
1 = Enables WDT clock MUX, WDT clock is selected by WDTCLK[1:0]
0 = WDT clock is LPRC
bit 10
Unimplemented: Read as ‘1’
bit 9-8
WDTWIN[1:0]: Watchdog Timer Window Width bits
11 = WDT window is 25% of the WDT period
10 = WDT window is 37.5% of the WDT period
01 = WDT window is 50% of the WDT period
00 = WDT window is 75% of the WDT period
bit 7
WINDIS: Windowed Watchdog Timer Disable bit
1 = Windowed WDT is disabled
0 = Windowed WDT is enabled
bit 6-5
FWDTEN[1:0]: Watchdog Timer Enable bits
11 = WDT is enabled
10 = WDT is disabled (control is placed on the SWDTEN bit)
01 = WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled
00 = WDT and SWDTEN are disabled
bit 4
FWPSA: Watchdog Timer Prescaler bit
1 = WDT prescaler ratio of 1:128
0 = WDT prescaler ratio of 1:32
2019-2020 Microchip Technology Inc.
DS30010198B-page 315
PIC24FJ128GL306 FAMILY
REGISTER 27-6:
bit 3-0
FWDT CONFIGURATION REGISTER (CONTINUED)
WDTPS[3:0]: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
DS30010198B-page 316
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 27-7:
FPOR CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 15
bit 8
U-1
U-1
U-1
U-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
—
—
—
—
DNVPEN
LPCFG
BOREN1
BOREN0
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-4
Unimplemented: Read as ‘1’
bit 3
DNVPEN: Downside Voltage Protection Enable bit
1 = Downside protection is enabled when BOR is inactive
0 = Downside protection is disabled when BOR is inactive
bit 2
LPCFG: Low-Power Regulator Control bit
1 = Retention feature is not available
0 = Retention feature is available and controlled by RETEN during Sleep
bit 1-0
BOREN[1:0]: Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10 = Brown-out Reset is enabled only while device is active and is disabled in Sleep; SBOREN bit is
disabled
01 = Brown-out Reset is controlled with the SBOREN bit setting
00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled
2019-2020 Microchip Technology Inc.
DS30010198B-page 317
PIC24FJ128GL306 FAMILY
REGISTER 27-8:
FICD CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 15
bit 8
r-1
U-1
R/PO-0
U-1
U-1
U-1
R/PO-1
R/PO-1
—
—
JTAGEN
—
—
—
ICS1
ICS0
bit 7
bit 0
Legend:
PO = Program Once bit
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-8
Unimplemented: Read as ‘1’
bit 7
Reserved: Maintain as ‘1’
bit 6
Unimplemented: Read as ‘1’
bit 5
JTAGEN: JTAG Port Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
bit 4-2
Unimplemented: Read as ‘1’
bit 1-0
ICS[1:0]: ICD Communication Channel Select bits
11 = Communicates on PGC1/PGD1
10 = Communicates on PGC2/PGD2
01 = Communicates on PGC3/PGD3
00 = Reserved; do not use
DS30010198B-page 318
x = Bit is unknown
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 27-9:
FDMTIVTL CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTIVT[15:8]
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTIVT[7:0]
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘1’
bit 15-0
DMTIVT[15:0]: DMT Window Interval Lower 16 bits
x = Bit is unknown
REGISTER 27-10: FDMTIVTH CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTIVT[31:24]
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTIVT[23:16]
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-16
Unimplemented: Read as ‘1’
bit 15-0
DMTIVT[31:16]: DMT Window Interval Higher 16 bits
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 319
PIC24FJ128GL306 FAMILY
REGISTER 27-11: FDMTCNTL CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTCNT[15:8]
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTCNT[7:0]
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
Unimplemented: Read as ‘1’
bit 15-0
DMTCNT[15:0]: DMT Instruction Count Time-out Value Lower 16 bits
REGISTER 27-12: FDMTCNTH CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTCNT[31:24]
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTCNT[23:16]
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
Unimplemented: Read as ‘1’
bit 15-0
DMTIVT[31:16]: DMT Instruction Count Time-out Value Higher 16 bits
DS30010198B-page 320
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 27-13: FDMT CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 15
bit 8
U-1
U-1
U-1
U-1
U-1
U-1
U-1
R/PO-1
—
—
—
—
—
—
—
DMTDIS
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-1
Unimplemented: Read as ‘1’
bit 0
DMTDIS: DMT Disable bit
1 = DMT is disabled
0 = DMT is enabled
2019-2020 Microchip Technology Inc.
x = Bit is unknown
DS30010198B-page 321
PIC24FJ128GL306 FAMILY
REGISTER 27-14: FDEVOPT1 CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
R/PO-1
U-1
U-1
—
—
—
—
—
SMB3EN(2)
—
—
bit 15
bit 8
U-1
U-1
U-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
U-1
—
—
—
ALTI2C1
SOSCHP
TMPRPIN
ALTCMPI
—
bit 7
bit 0
Legend:
PO = Program Once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-11
Unimplemented: Read as ‘1’
bit 10
SMB3EN: SMBus 3.0 Levels Enable bit(2)
1 = SMBus 3.0 input levels
0 = Normal I2C input levels
bit 9-5
Unimplemented: Read as ‘1’
bit 4
ALTI2C1: Alternate I2C1 bit
1 = SDA1 and SCL1 on RG2 and RG3
0 = ASDA1 and ASCL1 on RB5 and RB4
bit 3
SOSCHP: SOSC High-Power Enable bit (valid only when SOSCSEL = 1)
1 = SOSC High-Power mode is enabled
0 = SOSC Low-Power mode is enabled (see Section 9.10.3 “Low-Power SOSC Operation” for more
information)
bit 2
TMPRPIN: Tamper Pin Enable bit
1 = TMPRN pin function is disabled
0 = TMPRN pin function is enabled
bit 1
ALTCMPI: Alternate Comparator Input Enable bit
1 = C2INC and C3INC are on their standard pin locations
0 = C2INC and C3INC are on RG7(1)
bit 0
Unimplemented: Read as ‘1’
Note 1:
2:
RG7 is used for multiple functions, but only one use case is allowable.
SMBus mode is enabled by the SMEN bit (I2CxCONL[8]).
DS30010198B-page 322
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 27-3:
PIC24FJ CORE DEVICE ID REGISTERS
Address
Name
FF0000h
DEVID
FF0002h
DEVREV
TABLE 27-4:
Bit Field
Bit
15
14
13
12
9
8
7
6
5
4
Description
DEVID
Encodes the family ID of
the device; FAMID = 0x22.
DEV[7:0]
DEVID
Encodes the individual ID
of the device.
REV[3:0]
DEVREV Encodes the sequential
(numerical) revision
identifier of the device.
PIC24FJ128GL306 FAMILY
DEVICE IDs
Device
DEVID
PIC24FJ128GL306
0x220E
PIC24FJ64GL306
0x2206
PIC24FJ128GL305
0x220C
3
2
1
0
DEV[7:0]
—
FAMID[7:0]
TABLE 27-5:
10
FAMID[7:0]
DEVICE ID BIT FIELD
DESCRIPTIONS
Register
11
REV[3:0]
27.2
Unique Device Identifier (UDID)
All PIC24FJ128GL306 family devices are individually
encoded during final manufacturing with a Unique
Device Identifier, or UDID. The UDID cannot be erased
by a bulk erase command or any other user-accessible
means. This feature allows for manufacturing
traceability of Microchip Technology devices in applications where this is a requirement. It may also be used
by the application manufacturer for any number of
things that may require unique identification, such as:
• Tracking the device
• Unique serial number
• Unique security key
The UDID comprises five 24-bit program words. When
taken together, these fields form a unique 120-bit
identifier.
PIC24FJ64GL305
0x2204
The UDID is stored in five read-only locations, located
between 0x801600 and 0x801608 in the device configuration space. Table 27-6 lists the addresses of the
Identifier Words and shows their contents.
PIC24FJ128GL303
0x220A
TABLE 27-6:
PIC24FJ64GL303
0x2202
PIC24FJ128GL302
0x2208
PIC24FJ64GL302
0x2200
2019-2020 Microchip Technology Inc.
UDID ADDRESSES
UDID
Address
Description
UDID1
0x801600
UDID Word 1
UDID2
0x801602
UDID Word 2
UDID3
0x801604
UDID Word 3
UDID4
0x801606
UDID Word 4
UDID5
0x801608
UDID Word 5
DS30010198B-page 323
PIC24FJ128GL306 FAMILY
27.3
On-Chip Voltage Regulator
All PIC24FJ128GL306 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ128GL306 family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
This regulator is always enabled. It provides a constant
voltage (1.8V nominal) to the digital core logic, from a
VDD of about 2.1V, all the way up to the device’s
VDDMAX. It does not have the capability to boost VDD
levels. In order to prevent brown-out conditions when
the voltage drops too low for the regulator, the Brownout Reset occurs. Then, the regulator output follows
VDD with a typical voltage drop of 300 mV.
A low-ESR capacitor (such as ceramic) must be
connected to the VCAP pin (Figure 27-1). This helps to
maintain the stability of the regulator. The recommended
value for the filter capacitor (CEFC) is provided in
Section 30.1 “DC Characteristics”.
FIGURE 27-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
3.3V(1)
PIC24FJXXXGL30X
VDD
VCAP
CEFC
(10 F typ.)
VSS
Note 1: This is a typical operating voltage. Refer to
Section 30.0 “Electrical Characteristics”
for the full operating ranges of VDD.
DS30010198B-page 324
27.3.1
ON-CHIP REGULATOR AND POR
The voltage regulator takes approximately 10 µs for it
to generate output. During this time, designated as
TVREG, code execution is disabled. TVREG is applied
every time the device resumes operation after any
power-down, including Sleep mode. TVREG is determined by the status of the VREGS bit (RCON[8]) and
the WDTWIN[1:0] Configuration bits (FWDT[9:8]).
Refer to Section 30.0 “Electrical Characteristics” for
more information on TVREG.
Note:
27.3.2
For more information, see Section 30.0
“Electrical Characteristics”. The information in this data sheet supersedes the
information in the FRM.
VOLTAGE REGULATOR STANDBY
MODE
The on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when
the device is in Sleep mode, even though the core
digital logic does not require power. To provide additional savings in applications where power resources
are critical, the regulator can be made to enter Standby
mode, on its own, whenever the device goes into Sleep
mode. This feature is controlled by the VREGS bit
(RCON[8]). Clearing the VREGS bit enables the
Standby mode. When waking up from Standby mode,
the regulator needs to wait for TVREG to expire before
wake-up.
27.3.3
LOW-VOLTAGE RETENTION
REGULATOR
When in Sleep mode, PIC24FJ128GL306 family
devices may use a separate low-power, low-voltage
retention regulator to power critical circuits. This regulator, which operates at 1.2V nominal, maintains power
to data RAM and the RTCC, while all other core digital
logic is powered down. The low-voltage retention regulator is described in more detail in Section 10.2.4
“Low-Voltage Retention Regulator”.
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
27.4
Watchdog Timer (WDT)
For PIC24FJ128GL306 family devices, the WDT is driven
by the LPRC Oscillator, the Secondary Oscillator (SOSC)
or the system timer. When the device is in Sleep mode,
the LPRC Oscillator will be used. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT Time-out (TWDT) period of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS[3:0] Configuration bits (FWDT[3:0]), which allow the selection of a
total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranges from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
The WDT Time-out Flag bit, WDTO (RCON[4]), is not
automatically cleared following a WDT time-out. To
detect subsequent WDT events, the flag must be
cleared in software.
Note:
27.4.1
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (FWDT[7]) to ‘0’.
27.4.2
CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN[1:0]
Configuration bits (FWDT[6:5]). When the Configuration
bits, FWDTEN[1:0] = 11, the WDT is always enabled.
The WDT can be optionally controlled in software when
the Configuration bits, FWDTEN[1:0] = 10. When
FWDTEN[1:0] = 00, the Watchdog Timer is always disabled. The WDT is enabled in software by setting the
SWDTEN control bit (RCON[5]). The SWDTEN control
bit is cleared on any device Reset. The software WDT
option allows the user to enable the WDT for critical
code segments and disable the WDT during non-critical
code segments for maximum power savings.
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE
(RCON[3:2]) bits will need to be cleared in software
after the device wakes up.
2019-2020 Microchip Technology Inc.
DS30010198B-page 325
PIC24FJ128GL306 FAMILY
FIGURE 27-2:
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN[1:0]
Wake from
Sleep
LPRC Control
WDTPS[3:0]
FWPSA
WDTCLK[1:0]
32 kHz
SOSC
Prescaler
(5-bit/7-bit)
WDT
Counter
Postscaler
1:1 to 1:32.768
WDT Overflow
Reset
1 ms/4 ms
FRC
Peripheral Clock
All Device Resets
Transition to New
Clock Source
LPRC
Exit Sleep or
Idle Mode
WINDIS
System Clock (LRPC)
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
DS30010198B-page 326
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
27.5
Program Verification and
Code Protection
PIC24FJ128GL306 family devices offer basic
implementation of CodeGuard™ Security that supports
General Segment (GS) security and Boot Segment
(BS) security. This feature helps protect individual
intellectual property.
Note:
27.6
For more information on usage, configuration and operation, refer to
“CodeGuard™ Intermediate Security”
(www.microchip.com/DS70005182) in the
“dsPIC33/PIC24
Family
Reference
Manual”.
JTAG Interface
PIC24FJ128GL306 family devices implement a JTAG
interface, which supports boundary scan device
testing.
27.7
27.8
PIC24FJ128GL306 family devices provide 256 bytes of
One-Time-Programmable (OTP) memory, located at
addresses, 801700h through 8017FEh. This memory
can be used for persistent storage of application-specific
information that will not be erased by reprogramming the
device. This includes many types of information, such as
(but not limited to):
•
•
•
•
•
•
Application checksums
Code revision information
Product information
Serial numbers
System manufacturing dates
Manufacturing lot numbers
Customer OTP memory may be programmed in any
mode, including user RTSP mode, but it cannot be
erased. Data are not cleared by a chip erase.
Note:
In-Circuit Serial Programming™
PIC24FJ128GL306 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGCx) and
data (PGDx), and three other lines for power (VDD),
ground (VSS) and MCLR. This allows customers to manufacture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
2019-2020 Microchip Technology Inc.
Customer OTP Memory
27.9
Do not write the OTP memory more than
once. Writing to the OTP memory more
than once may result in an ECC Double-Bit
Error (ECCDBE).
In-Circuit Debugger
This function allows simple debugging functions when
used with MPLAB® X IDE. Debugging functionality is
controlled through the PGCx (Emulation/Debug Clock)
and PGDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device,
the design must implement ICSP™ connections to
MCLR, VDD, VSS and the PGCx/PGDx pin pair, designated by the ICS[1:0] Configuration bits. In addition,
when the feature is enabled, some of the resources are
not available for general use. These resources include
the first 80 bytes of data RAM and two I/O pins.
DS30010198B-page 327
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 328
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
28.0
Note:
INSTRUCTION SET SUMMARY
This chapter is a brief summary of the
PIC24F Instruction Set Architecture (ISA)
and is not intended to be a comprehensive
reference source.
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
Table 28-1 shows the general symbols used in
describing the instructions. The PIC24F instruction set
summary in Table 28-2 lists all the instructions, along
with the status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register, ‘Wb’, without any address modifier
• The second source operand, which is typically a
register, ‘Ws’, with or without an address modifier
• The destination of the result, which is typically a
register, ‘Wd’, with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register, ‘Wb’,
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register, ‘Wd’, with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the Table Read and Table Write
instructions
All instructions are a single word, except for certain
double-word instructions, which were made doubleword instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all
Table Reads and Table Writes, and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles.
Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register, ‘Wb’)
2019-2020 Microchip Technology Inc.
DS30010198B-page 329
PIC24FJ128GL306 FAMILY
TABLE 28-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{ }
Optional field or operation
[n:m]
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit Bit Selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0000h...1FFFh}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0...1023} for Word mode
lit14
14-bit unsigned literal {0...16383}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388607}; LSb must be ‘0’
None
Field does not require an entry, may be blank
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (direct addressing)
Wn
One of 16 Working registers {W0..W15}
Wnd
One of 16 destination Working registers {W0..W15}
Wns
One of 16 source Working registers {W0..W15}
WREG
W0 (Working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
DS30010198B-page 330
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 28-2:
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
BTG
BTSC
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
ADD
f
f = f + WREG
1
1
C, DC, N, OV, Z
ADD
f,WREG
WREG = f + WREG
1
1
C, DC, N, OV, Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C, DC, N, OV, Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C, DC, N, OV, Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C, DC, N, OV, Z
ADDC
f
f = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C, DC, N, OV, Z
AND
f
f = f .AND. WREG
1
1
N, Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N, Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N, Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N, Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N, Z
ASR
f
f = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C, N, OV, Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N, Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N, Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if Greater Than or Equal
1
1 (2)
None
BRA
GEU,Expr
Branch if Unsigned Greater Than or Equal
1
1 (2)
None
BRA
GT,Expr
Branch if Greater Than
1
1 (2)
None
BRA
GTU,Expr
Branch if Unsigned Greater Than
1
1 (2)
None
BRA
LE,Expr
Branch if Less Than or Equal
1
1 (2)
None
BRA
LEU,Expr
Branch if Unsigned Less Than or Equal
1
1 (2)
None
BRA
LT,Expr
Branch if Less Than
1
1 (2)
None
BRA
LTU,Expr
Branch if Unsigned Less Than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws[Wb]
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws[Wb]
1
1
None
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
None
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
2019-2020 Microchip Technology Inc.
DS30010198B-page 331
PIC24FJ128GL306 FAMILY
TABLE 28-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTSS
BTST
BTSTS
Assembly Syntax
# of
Words
Description
# of
Cycles
Status Flags
Affected
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
None
(2 or 3)
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
None
(2 or 3)
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws[Wb] to C
1
1
C
BTST.Z
Ws,Wb
Bit Test Ws[Wb] to Z
1
1
Z
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
CALL
lit23
Call Subroutine
2
2
None
CALL
Wn
Call Indirect Subroutine
1
2
None
CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
Clear Watchdog Timer
1
1
WDTO, Sleep
CLRWDT
CLRWDT
COM
COM
f
f=f
1
1
N, Z
COM
f,WREG
WREG = f
1
1
N, Z
COM
Ws,Wd
Wd = Ws
1
1
N, Z
CP
f
Compare f with WREG
1
1
C, DC, N, OV, Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C, DC, N, OV, Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C, DC, N, OV, Z
CP0
CP0
f
Compare f with 0x0000
1
1
C, DC, N, OV, Z
CP0
Ws
Compare Ws with 0x0000
1
1
C, DC, N, OV, Z
CPB
CPB
f
Compare f with WREG, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C, DC, N, OV, Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, Skip if =
1
None
1
(2 or 3)
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, Skip if >
1
1
None
(2 or 3)
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, Skip if <
1
1
None
(2 or 3)
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, Skip if
1
1
None
(2 or 3)
DAW
DAW.B
Wn
Wn = Decimal Adjust Wn
1
1
C
DEC
DEC
f
f = f –1
1
1
C, DC, N, OV, Z
DEC
f,WREG
WREG = f –1
1
1
C, DC, N, OV, Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C, DC, N, OV, Z
DEC2
f
f=f–2
1
1
C, DC, N, OV, Z
DEC2
f,WREG
WREG = f – 2
1
1
C, DC, N, OV, Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C, DC, N, OV, Z
DISI
DISI
#lit14
Disable Interrupts for k Instruction Cycles
1
1
None
DIV
DIV.SW
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UW
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N, Z, C, OV
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
CP
DEC2
DS30010198B-page 332
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 28-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
GOTO
INC
INC2
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
GOTO
Expr
Go to Address
2
2
GOTO
Wn
Go to Indirect
1
2
None
None
INC
f
f=f+1
1
1
C, DC, N, OV, Z
INC
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C, DC, N, OV, Z
INC2
f
f=f+2
1
1
C, DC, N, OV, Z
INC2
f,WREG
WREG = f + 2
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N, Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N, Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N, Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N, Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N, Z
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
LSR
LSR
f
f = Logical Right Shift f
1
1
C, N, OV, Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C, N, OV, Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C, N, OV, Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N, Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N, Z
MOV
f,Wn
Move f to Wn
1
1
None
MOV
[Wns+Slit10],Wnd
Move [Wns+Slit10] to Wnd
1
1
None
MOV
f
Move f to f
1
1
N, Z
MOV
f,WREG
Move f to WREG
1
1
N, Z
MOV
#lit16,Wn
Move 16-bit Literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wns,[Wns+Slit10]
Move Wns to [Wns+Slit10]
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
N, Z
MOV.D
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
1
2
None
None
IOR
MOV
MUL
NEG
NOP
POP
MOV.D
Ws,Wnd
Move Double from Ws to W(nd+1):W(nd)
1
2
MUL.SS
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
f
f=f+1
1
1
C, DC, N, OV, Z
NEG
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C, DC, N, OV, Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)
1
2
None
Pop Shadow Registers
1
1
All
POP.S
PUSH
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
1
2
None
Push Shadow Registers
1
1
None
PUSH.S
2019-2020 Microchip Technology Inc.
DS30010198B-page 333
PIC24FJ128GL306 FAMILY
TABLE 28-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO, Sleep
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 Times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 Times
1
1
None
REPEAT
RESET
RESET
Software Device Reset
1
1
None
RETFIE
RETFIE
Return from Interrupt
1
3 (2)
None
RETLW
RETLW
Return with Literal in Wn
1
3 (2)
None
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C, N, Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C, N, Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C, N, Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N, Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N, Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N, Z
RRC
f
f = Rotate Right through Carry f
1
1
C, N, Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C, N, Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C, N, Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N, Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N, Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N, Z
SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C, N, Z
SETM
SETM
f
f = FFFFh
1
1
None
SETM
WREG
WREG = FFFFh
1
1
None
RLNC
RRC
RRNC
SL
SUB
SUBB
SUBR
SUBBR
SWAP
#lit10,Wn
SETM
Ws
Ws = FFFFh
1
1
None
SL
f
f = Left Shift f
1
1
C, N, OV, Z
SL
f,WREG
WREG = Left Shift f
1
1
C, N, OV, Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C, N, OV, Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N, Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N, Z
SUB
f
f = f – WREG
1
1
C, DC, N, OV, Z
SUB
f,WREG
WREG = f – WREG
1
1
C, DC, N, OV, Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C, DC, N, OV, Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C, DC, N, OV, Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C, DC, N, OV, Z
SUBB
f
f = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C, DC, N, OV, Z
SUBR
f
f = WREG – f
1
1
C, DC, N, OV, Z
SUBR
f,WREG
WREG = WREG – f
1
1
C, DC, N, OV, Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C, DC, N, OV, Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C, DC, N, OV, Z
SUBBR
f
f = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C, DC, N, OV, Z
SWAP.b
Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
DS30010198B-page 334
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 28-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
TBLRDH
TBLRDH
Ws,Wd
Read Prog[23:16] to Wd[7:0]
1
2
None
TBLRDL
TBLRDL
Ws,Wd
Read Prog[15:0] to Wd
1
2
None
TBLWTH
TBLWTH
Ws,Wd
Write Ws[7:0] to Prog[23:16]
1
2
None
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog[15:0]
1
2
None
ULNK
ULNK
Unlink Frame Pointer
1
1
None
XOR
XOR
f
f = f .XOR. WREG
1
1
N, Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N, Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N, Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N, Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N, Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C, Z, N
ZE
2019-2020 Microchip Technology Inc.
DS30010198B-page 335
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 336
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
29.0
DEVELOPMENT SUPPORT
Move a design from concept to production in record time with Microchip’s award-winning development tools. Microchip
tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs)
in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools.
Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers and emulators work
seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application,
while our line of third party tools round out our comprehensive development tool solutions.
Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which support multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible
with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows.
Go to the following website for more information and details:
https://www.microchip.com/development-tools/
2019-2020 Microchip Technology Inc.
DS30010198B-page 337
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 338
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
30.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ128GL306 family electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ128GL306 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to VSS ....... -0.3V to (VDD + 0.3V)
Voltage on any general purpose digital or analog pin (5.5V tolerant, including MCLR) with respect to VSS:
When VDD = 0V: .......................................................................................................................... -0.3V to +4.0V
When VDD 2.0V: ....................................................................................................................... -0.3V to +6.0V
Voltage on AVDD with respect to VSS ................................................... (VDD – 0.3V) to (lesser of: 4.0V or (VDD + 0.3V))
Voltage on AVSS with respect to VSS ........................................................................................................ -0.3V to +0.3V
Maximum current out of VSS pin:
+85°C......................................................................................................................................................300 mA
+125°C....................................................................................................................................................100 mA
Maximum current into VDD pin (Note 1):
+85°C......................................................................................................................................................300 mA
+125°C....................................................................................................................................................100 mA
Maximum output current sunk by any I/O pin:
RB15, RC15 .............................................................................................................................................50 mA
All other I/Os .............................................................................................................................................25 mA
Maximum output current sourced by any I/O pin:
RB15, RC15 .............................................................................................................................................50 mA
All other I/Os .............................................................................................................................................25 mA
Maximum current sunk by group of I/Os between two VSS Pins (Note 2):
+85°C......................................................................................................................................................300 mA
+125°C......................................................................................................................................................75 mA
Maximum current sourced by group of I/Os between two VDD pins (Note 2):
+85°C......................................................................................................................................................300 mA
+125°C......................................................................................................................................................75 mA
Note 1:
2:
†
Maximum allowable current is a function of device maximum power dissipation (see Table 30-1).
Only on the 28-lead and 36-lead packages can AVDD/AVSS be considered for grouping of I/Os.
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2019-2020 Microchip Technology Inc.
DS30010198B-page 339
PIC24FJ128GL306 FAMILY
30.1
DC Characteristics
FIGURE 30-1:
PIC24FJ128GL306 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Voltage (VDD)
3.6V
3.6V
PIC24FJ128GL306
(Note 1)
(Note 1)
32 MHz
Frequency
Note 1:
TABLE 30-1:
Lower operating boundary is 2.0V or VBOR (when BOR is enabled), whichever is lower. For best
analog performance, operate above 2.2V.
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+135
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
PIC24FJ128GL306:
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 30-2:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 6x6 mm 28-Pin QFN
JA
38.4
—
°C/W
(Note 1)
Package Thermal Resistance, 4x4x0.6 mm 28-Pin UQFN
JA
38.7
—
°C/W
(Note 1)
Package Thermal Resistance, 7.50 mm 28-Pin SOIC
JA
79.0
—
°C/W
(Note 1)
Package Thermal Resistance, 5.30 mm 28-Pin SSOP
JA
67.1
—
°C/W
(Note 1)
Package Thermal Resistance, 5x5 mm 36-Pin UQFN
JA
35.4
—
°C/W
(Note 1)
Package Thermal Resistance, 6x6x0.5 mm 48-Pin UQFN
JA
28.3
—
°C/W
(Note 1)
Package Thermal Resistance, 7x7x1 mm 48-Pin TQFP
JA
71.0
—
°C/W
(Note 1)
Package Thermal Resistance, 9x9x0.9 mm 64-Pin QFN
JA
23.0
—
°C/W
(Note 1)
Package Thermal Resistance, 10x10x1 mm 64-Pin TQFP
JA
68.9
—
°C/W
(Note 1)
Note 1:
Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.
DS30010198B-page 340
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PIC24FJ128GL306 FAMILY
TABLE 30-3:
TEMPERATURE AND VOLTAGE SPECIFICATIONS
Operating Conditions:
Operating temperature
Param
Symbol
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ
Max
Units
2.0
—
3.6
V
Conditions
Operating Voltage
DC10
VDD
Supply Voltage
VBOR
—
3.6
V
BOR is enabled
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
VSS
—
—
V
(Note 1)
DC17A SVDD
Recommended
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
1V/20 ms
—
1V/10 µS
sec
DC17B VBOR
Brown-out Reset
Voltage on VDD
Transition, High-to-Low
1.95
2.1
2.2
V
Note 1:
2:
3:
BOR is disabled
(Notes 1 and 3)
(Note 2)
If the VPOR or SVDD parameters are not met, or the application experiences slow power-down VDD ramp
rates, it is recommended to enable and use BOR.
On a rising VDD power-up sequence, application firmware execution begins at the higher of the VPORREL or
VBOR level (when BOREN = 1).
VDD rise times outside this window may not internally reset the processor and are not parametrically
tested.
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TABLE 30-4:
OPERATING CURRENT (IDD)
Operating Conditions:
Operating temperature
Parameter
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Typical(1)
Max(2)
Units
208.8
350
µA
215.4
350
µA
362.3
550
µA
366.4
550
µA
1.3
1.6
mA
1.35
1.6
mA
5
6.2
mA
5.1
6.2
mA
41.5
130
µA
47.4
130
µA
55.5
310
µA
61.9
310
µA
1.34
1.7
mA
1.35
1.7
mA
Operating
Temperature
VDD
Conditions
Operating Current (IDD)(3)
DC19
DC20
DC23
DC24
DC31
DC32
Note 1:
2:
3:
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +125°C
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
0.5 MIPS,
FOSC = 1 MHz
1 MIPS,
FOSC = 2 MHz
4 MIPS,
FOSC = 8 MHz
16 MIPS,
FOSC = 32 MHz
2.0V
3.3V
2.0V
LPRC (16 KIPS),
FOSC = 32 kHz
3.3V
2.0V
3.3V
FRC (4 MIPS),
FOSC = 8 MHz
Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Typical parameters are for design
guidance only and are not tested.
Data in “Max” column are production tested.
Base IDD current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 010,
PLLMODE[3:0] (FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 00)
• OSCI pin is driven with external square wave, with levels from 0.3V to VDD – 0.3V
• OSCO is configured as an I/O in the Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and
LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins (except OSCI) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• NOP instructions are executed
DS30010198B-page 342
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TABLE 30-5:
IDLE CURRENT (IIDLE)
Operating Conditions:
Operating temperature
Parameter
No.
Typical(1)
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Max(2)
Units
Operating
Temperature
VDD
Conditions
Idle Current (IIDLE)(3)
DC40
DC43
DC47
DC50
DC51
Note 1:
2:
3:
110
250
µA
121.3
250
µA
130.2
325
µA
130.2
325
µA
329.7
500
µA
357.5
500
µA
350
600
µA
370.9
600
µA
1.2
1.8
mA
1.3
1.8
mA
1.22
1.9
mA
1.31
1.9
mA
369.6
550
µA
375.1
550
µA
382.9
650
µA
388.9
650
µA
37.5
110
µA
43.3
110
µA
50.8
300
µA
57.1
300
µA
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
2.0V
3.3V
2.0V
1 MIPS,
FOSC = 2 MHz
3.3V
2.0V
3.3V
2.0V
4 MIPS,
FOSC = 8 MHz
3.3V
2.0V
3.3V
2.0V
16 MIPS,
FOSC = 32 MHz
3.3V
2.0V
3.3V
2.0V
FRC (4 MIPS),
FOSC = 8 MHz
3.3V
2.0V
3.3V
2.0V
LPRC (16 KIPS),
FOSC = 32 kHz
3.3V
Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
Data in “Max” column are production tested.
Base IIDLE current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 010,
PLLMODE[3:0] (FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 00)
• OSCI pin is driven with external square wave, with levels from 0.3V to VDD – 0.3V
• OSCO is configured as an I/O in Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and
LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins (except OSCI) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• pwrsav #1 (IDLE) instruction is executed
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DS30010198B-page 343
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TABLE 30-6:
POWER-DOWN CURRENT (IPD)
Operating Conditions:
Operating temperature
Parameter
Typical(1)
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Max(2)
Units
Operating
Temperature
Conditions
VDD
Power-Down Current(5,6)
DC60
DC61
Note 1:
2:
3:
4:
5:
6:
7:
3.47
10
µA
-40°C
4.31
10
µA
+25°C
9.93
20
µA
+85°C
38.79
150
µA
+125°C
3.72
10
µA
-40°C
4.6
10
µA
+25°C
10.27
20
µA
+85°C
39.45
150
µA
+125°C
272.7
Note 7
nA
-40°C
450
Note 7
nA
+25°C
4.5
Note 7
µA
+85°C
28.7
Note 7
µA
+125°C
336
Note 7
nA
-40°C
460
Note 7
nA
+25°C
4.5
Note 7
µA
+85°C
29
Note 7
µA
+125°C
2.0V
Sleep(3)
3.3V
2.0V
Low-Voltage Retention Sleep(4)
3.3V
Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
Data in “Max” column are production tested.
The retention low-voltage regulator is disabled; RETEN (RCON[12]) = 0, LPCFG (FPOR[2]) = 1.
The retention low-voltage regulator is enabled; RETEN (RCON[12]) = 1, LPCFG (FPOR[2]) = 0.
Base IPD current is measured with:
• Oscillator is configured in FRC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 000,
PLLMODE[3:0] (FOSCSEL[6:3]) = 1111 and POSCMOD[1:0] (FOSC[1:0]) = 11)
• OSCO is configured as an I/O in Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00 and
LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• pwrsav #0 (SLEEP) instruction is executed
These currents are measured on the device containing the most memory in this family.
For design guidance, please refer to Figure 30-2 and Figure 30-3.
DS30010198B-page 344
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FIGURE 30-2:
IPD VS. TEMPERATURE GRAPHS (PAGE 1 OF 2)(1,2)
Base IPD (Extended, V=3.3V)
150
140
130
120
110
100
IPD (uA)
90
80
70
Typical
60
Max
50
40
30
20
10
0
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100105110115120125
Temperature (ºC)
IPD Retention (Extended, V=3.3V)
120
110
100
90
IPD (uA)
80
70
60
Typical
50
Max
40
30
20
10
0
-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100105110115120125
Temperature (ºC)
Note 1:
2:
For base IPD, temperature points of -40°C, +25°C and +125°C are production tested only.
For IPD retention, data provided are characterized but not production tested.
2019-2020 Microchip Technology Inc.
DS30010198B-page 345
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FIGURE 30-3:
IPD VS. TEMPERATURE GRAPHS (PAGE 2 OF 2)(1,2)
IPD (uA)
Base IPD (Industrial, V=3.3V)
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Typical
Max
-40 -35 -30 -25 -20 -15 -10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Temperature (ºC)
IPD Retention (Industrial, V=3.3V)
15
14
13
12
11
10
IPD (uA)
9
8
7
Typical
6
Max
5
4
3
2
1
0
-40 -35 -30 -25 -20 -15 -10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
Temperature (ºC)
Note 1:
2:
For base IPD, temperature points of -40°C, +25°C and +125°C are production tested only.
For IPD retention, data provided are characterized but not production tested.
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TABLE 30-7:
CURRENT (BOR, WDT, HLVD, ADC, LCD, DMT, RTCC)(3)
Operating Conditions:
Operating temperature
Parameter
No.
Typical(1)
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Max
Units
Operating
Temperature
Conditions
VDD
Incremental Current Brown-out Reset (BOR)(2)
DC70
1.3
5
µA
2
5
µA
1.5
10
µA
2.1
10
µA
Incremental Current Watchdog Timer (WDT)
DC71
0.27
1
µA
0.35
1
µA
0.55
5
µA
0.6
5
µA
-40°C to +85°C
-40°C to +125°C
2.0V
3.3V
2.0V
BOR(2)
3.3V
(2)
-40°C to +85°C
-40°C to +125°C
2.0V
3.3V
2.0V
WDT(2)
3.3V
Incremental Current High/Low-Voltage Detect (HLVD)(2)
DC72
1.9
5
µA
2.6
5
µA
2.6
10
µA
3.3
10
µA
Incremental Current ADC (ADC)
DC73
379.6
-40°C to +85°C
-40°C to +125°C
2.0V
3.3V
2.0V
HLVD(2)
3.3V
(2)
700
µA
522.7
700
µA
398.6
750
µA
522
750
µA
-40°C to +85°C
-40°C to +125°C
2.0V
3.3V
2.0V
ADC(2) with internal RC clock
3.3V
Incremental Current LCD (LCD)(2)
DC74
DC75
DC76
DC77
DC78
DC79
Note 1:
2:
3:
4:
1.3
12
µA
1.7
12
µA
7.8
25
µA
12.2
25
µA
64.3
140
µA
105.1
140
µA
10.2
25(4)
µA
10.2
25(4)
µA
11.5
45(4)
µA
13.8
45(4)
µA
40.1
70(4)
µA
39.2
70(4)
µA
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
LCD (low-power resistor ladder)
LCD (medium power resistor
ladder)
LCD (high-power resistor ladder)
LCD + Charge Pump (low-power
resistor ladder)
LCD + Charge Pump (low-power
resistor ladder)
LCD + Charge Pump (medium
power resistor ladder)
Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
Incremental current while the module is enabled and running.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current. The current includes the selected clock source enabled for WDT
and RTCC.
These parameters are characterized but not tested in manufacturing.
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TABLE 30-7:
CURRENT (BOR, WDT, HLVD, ADC, LCD, DMT, RTCC)(3) (CONTINUED)
Operating Conditions:
Operating temperature
Parameter
No.
DC80
DC81
DC82
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Typical(1)
Max
Units
43.1
85(4)
µA
42
85(4)
µA
299.2
420(4)
µA
252.8
420
(4)
µA
295.5
420(4)
µA
237.6
(4)
µA
420
Operating
Temperature
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
Conditions
VDD
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
LCD + Charge Pump (medium
power resistor ladder)
LCD + Charge Pump
(high-power resistor ladder)
LCD + Charge Pump
(high-power resistor ladder)
Incremental Current DMT (DMT)(2)
DC83
177.2
1000
nA
234.1
1000
nA
575
1500
nA
750
1500
nA
-40°C to +85°C
-40°C to +125°C
2.0V
3.3V
DMT(2)
2.0V
3.3V
Incremental Current Real-Time Clock and Calendar (RTCC)(2)
DC84
786.4
DC85
Note 1:
2:
3:
4:
—
nA
894.6
—
nA
500
1000
nA
550
1000
nA
570
1300
nA
600
1300
nA
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
2.0V
3.3V
2.0V
3.3V
RTCC (with SOSC enabled in
Low-Power mode)(2)
RTCC (with LPRC enabled)(2)
2.0V
3.3V
Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
Incremental current while the module is enabled and running.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current. The current includes the selected clock source enabled for WDT
and RTCC.
These parameters are characterized but not tested in manufacturing.
DS30010198B-page 348
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PIC24FJ128GL306 FAMILY
TABLE 30-8:
I/O PIN INPUT SPECIFICATIONS
Operating Conditions:
Operating temperature
Param
Symbol
No.
VIL
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ(1)
Max
Units
Input Low Voltage(3)
DI10
I/O Pins with ST Buffer
VSS
—
0.2 VDD
V
DI11
I/O Pins with TTL Buffer
VSS
—
0.15 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSCI (EC mode)
VSS
—
0.2 VDD
V
DI18
I/O Pins with I2C Buffer
VSS
—
0.3 VDD
V
I/O Pins with SMBus Buffer
VSS
—
0.8
V
I/O Pins with ST Buffer:
with Analog Functions,
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
I/O Pins with TTL Buffer:
with Analog Functions,
Digital Only
0.25 VDD + 0.8
0.25 VDD + 0.8
—
—
VDD
5.5
V
V
DI19
VIH
DI20
DI21
Conditions
SMBus is enabled
Input High Voltage(3)
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSCI (EC mode)
0.7 VDD
—
VDD
V
DI28
I2 C
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
I/O Pins with SMBus Buffer:
with Analog Functions,
Digital Only
1.35
1.35
—
—
VDD
5.5
V
V
CNx Pull-up Current
100
—
450
µA
VDD = 3.3V, VPIN = VSS
CNx Pull-Down Current
150
—
550
µA
VDD = 3.3V, VPIN = VDD
I/O Pins with
Buffer:
with Analog Functions,
Digital Only
DI29
DI30
ICNPU
DI30A ICNPD
IIL
Input Leakage
Current(2)
DI50
I/O Ports
—
—
±1
µA
VSS VPIN VDD,
pin at high-impedance
DI51
Analog Input Pins
—
—
±1
µA
VSS VPIN VDD,
pin at high-impedance
DI55
MCLR
—
—
±1
µA
VSS VPIN VDD
DI56
OSCI/CLKI
—
—
±1
µA
VSS VPIN VDD,
EC, XT and HS modes
Note 1:
2:
3:
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Negative current is defined as current sourced by the pin.
Refer to Table 1-1 for I/O pin buffer types.
2019-2020 Microchip Technology Inc.
DS30010198B-page 349
PIC24FJ128GL306 FAMILY
TABLE 30-9:
I/O PIN OUTPUT SPECIFICATIONS
Operating Conditions:
Operating temperature
Param
Symbol
No.
VOL
DO10
Note 1:
Min
Typ(1)
Max
Units
Conditions
Output Low Voltage
RB15, RC15
VOH
DO26
Characteristic
I/O Ports
DO16
DO20
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
—
—
0.35
V
IOL = 6 mA, VDD = 3.6V
—
—
0.7
V
IOL = 18 mA, VDD = 3.6V
—
—
0.4
V
IOL = 5.0 mA, VDD = 2V
—
—
0.35
V
IOL = 9 mA, VDD = 3.6V
—
—
0.35
V
IOL = 6 mA, VDD = 2V
Output High Voltage
I/O Ports
RB15, RC15
3.2
—
—
V
IOH = -6.0 mA, VDD = 3.6V
2.7
—
—
V
IOH = -18 mA, VDD = 3.6V
1.75
—
—
V
IOH = -1.0 mA, VDD = 2V
0.9
—
—
V
IOH = -10 mA, VDD = 2V
3.25
—
—
V
IOH = -6.0 mA, VDD = 3.6V
1.75
—
—
V
IOH = -1.0 mA, VDD = 2V
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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I/O VOL VS. IOL CHARACTER GRAPHS(1)
FIGURE 30-4:
I/O VOL Versus IOL (VDD = 3.6V)
0.9
0.8
0.7
VOL (V)
0.6
-40C Typical
0.5
25C Typical
0.4
85C Typical
125C Typical
0.3
Max
0.2
0.1
0
6
8
10
12
IOL (mA)
14
16
18
I/O VOL Versus IOL (VDD = 2.0V)
0.9
0.8
0.7
VOL (V)
0.6
-40C Typical
0.5
25C Typical
0.4
85C Typical
0.3
125C Typical
Max
0.2
0.1
0
5
Note 1:
6
7
8
IOL (mA)
9
10
11
Production test conditions are given in Table 30-9.
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I/O VOH VS. IOL CHARACTER GRAPHS(1)
FIGURE 30-5:
I/O VOH Versus IOL (VDD = 3.6V)
3.6
3.5
3.4
3.3
-40C Typical
VOH (V)
3.2
25C Typical
3.1
85C Typical
125C Typical
3
Min
2.9
2.8
2.7
-18
-16
-14
-12
IOL (mA)
-10
-8
-6
I/O VOH Versus IOL (VDD = 2.0V)
1.9
1.8
1.7
VOH (V)
1.6
1.5
-40C Typical
1.4
25C Typical
1.3
85C Typical
125C Typical
1.2
Min
1.1
1
0.9
-9
-8
-7
-6
-5
-4
IOL (mA)
Note 1:
Production test conditions are given in Table 30-9.
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FIGURE 30-6:
RC15, RB15 VOL VS. IOL CHARACTER GRAPHS(1)
RC15 & RB15 VOL Versus IOL (VDD = 3.6V)
0.9
0.8
0.7
VOL (V)
0.6
-40C Typical
0.5
25C Typical
0.4
85C Typical
125C Typical
0.3
Max
0.2
0.1
0
9
14
19
24
29
34
IOL (mA)
RC15 & RB15 VOL Versus IOL (VDD = 2.0V)
0.9
0.8
0.7
VOL (V)
0.6
-40C Typical
0.5
25C Typical
0.4
85C Typical
0.3
125C Typical
Max
0.2
0.1
0
6
8
10
12
14
16
18
20
IOL (mA)
Note 1:
Production test conditions are given in Table 30-9.
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RC15, RB15 VOH VS. IOL CHARACTER GRAPHS(1)
FIGURE 30-7:
RC15 & RB15 VOH Versus IOL (VDD = 3.6V)
3.6
3.5
3.4
3.3
-40C Typical
VOH (V)
3.2
25C Typical
3.1
85C Typical
125C Typical
3
Min
2.9
2.8
2.7
-26
-22
-18
-14
-10
-6
IOL (mA)
RC15 & RB15 VOH Versus IOL (VDD = 2.0V)
1.9
1.8
1.7
VOH (V)
1.6
1.5
-40C Typical
1.4
25C Typical
1.3
85C Typical
125C Typical
1.2
Min
1.1
1
0.9
-14
Note 1:
-13
-12
-11
-10
-9
IOL (mA)
-8
-7
-6
-5
Production test conditions are given in Table 30-9.
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TABLE 30-10: PROGRAM MEMORY
Operating Conditions:
Operating temperature
Param
Symbol
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ(1)
Max
Units
10000
—
—
E/W
—
3.6
V
Characteristic
Conditions
Program Flash Memory
D130
EP
Cell Endurance
D131
VPR
VDD for Read
2.0
D132B
VDD for Self-Timed Write
2.0
—
3.6
V
D133A TIW
Self-Timed Word Write
Cycle Time
—
20
—
µs
Self-Timed Row Write
Cycle Time
—
1.5
—
ms
D133B TIE
Self-Timed Page Erase
Time
20
—
40
ms
D134
Characteristic Retention
20
—
—
Year
Note 1:
TRETD
-40C to +125C
If no other specifications are violated
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.
TABLE 30-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions:
Param
No.
Symbol
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics
Min
Typ
Max Units
—
10
—
µs
1.14
1.2
1.26
V
ms
DVR
TVREG
Voltage Regulator Start-up Time
DVR10
VBG
Internal Band Gap Reference
DVR11
TBG
Band Gap Reference
Start-up Time
—
1
—
Comments
VREGS = 0 with any POR or
BOR
DVR20
VRGOUT
Regulator Output Voltage
1.6
1.8
2.0
V
VDD > 1.9V
DVR21
CEFC
External Filter Capacitor Value
10
—
—
µF
Series resistance < 3
recommended; < 5 required
DVR30
VLVR
Low-Voltage Regulator
Output Voltage
0.9
—
1.2
V
RETEN = 1, LPCFG = 0
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TABLE 30-12: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Operating Conditions:
Param
Symbol
No.
DC18
VHLVD
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ
Max
Units
HLVD Voltage on VDD HLVDL[3:0] = 0100(1)
Transition
HLVDL[3:0] = 0101
3.39
—
—
V
3.24
—
—
V
HLVDL[3:0] = 0110
2.93
—
3.39
V
HLVDL[3:0] = 0111
2.73
—
3.17
V
HLVDL[3:0] = 1000
2.62
—
3.06
V
HLVDL[3:0] = 1001
2.39
—
2.8
V
HLVDL[3:0] = 1010
2.29
—
2.68
V
HLVDL[3:0] = 1011
2.18
—
2.56
V
HLVDL[3:0] = 1100
2.08
—
2.45
V
HLVDL[3:0] = 1101
1.98
—
2.34
V
HLVDL[3:0] = 1110
1.88
—
2.23
V
DC101 VTHL
HLVD Voltage on
HLVDL[3:0] = 1111
HLVDIN Pin Transition
—
1.20
—
V
DC105 TONLVD
HLVD Module Enable Time
—
5
—
µs
Note 1:
Conditions
From POR or
HLVDEN = 1
Trip points for values of HLVD[3:0], from ‘0000’ to ‘0011’, are not implemented.
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TABLE 30-13: COMPARATOR DC SPECIFICATIONS
Operating Conditions:
Param
Symbol
No.
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ
Max
Units
Comments
D300
VIOFF
Input Offset Voltage
—
12
50
mV
(Note 1)
D301
VICM
Input Common-Mode Voltage
0
—
VDD
V
(Note 1)
D302
CMRR
Common-Mode Rejection Ratio
55
—
—
dB
(Note 1)
D306
IQCMP
AVDD Quiescent Current per Comparator
—
27
—
µA
Comparator is enabled
D307
TRESP
Response Time
—
300
—
ns
(Note 2)
D308
TMC2OV Comparator Mode Change to Valid Output
—
—
10
µs
D309
IDD
—
30
—
µA
Note 1:
2:
Operating Supply Current
AVDD = 3.3V
Parameters are characterized but not tested.
Measured with one input at VDD/2 and the other transitioning from VSS to VDD, 40 mV step, 15 mV overdrive.
TABLE 30-14: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS
Operating Conditions:
Param
No.
Min
Typ
Max
Units
Settling Time
—
—
10
µs
VRD311 CVRAA
Absolute Accuracy
-20
—
+80
mV
VRD312 CVRUR
Unit Resistor Value (R)
—
4.5
—
k
VR310
Note 1:
Symbol
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
TSET
Characteristic
Comments
(Note 1)
Measures the interval while CVR[4:0] transitions from ‘11111’ to ‘00000’.
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30.2
AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ128GL306 family AC characteristics and timing
parameters.
TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 30.1 “DC Characteristics”.
AC CHARACTERISTICS
FIGURE 30-8:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSCO
Load Condition 2 – for OSCO
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSCO
15 pF for OSCO output
VSS
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
15
pF
In XT and HS modes when the
External Clock is used to drive
OSCI
DO50
COSCO
OSCO/CLKO Pin
—
—
DO56
CIO
All I/O Pins and OSCO
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C mode
Note 1:
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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FIGURE 30-9:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
OSCI
OS20
OS30
OS30
OS31
OS31
OS25
CLKO
OS40
OS41
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
Param
Symbol
No.
OS10
FOSC
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ(1)
Max
Units
External CLKI Frequency
(External clocks allowed
only in EC mode)
DC
4
—
—
32
48
MHz
MHz
EC
ECPLL (Note 2)
Oscillator Frequency
3.5
4
10
12
31
—
—
—
—
—
10
8
32
24
33
MHz
MHz
MHz
MHz
kHz
XT
XTPLL
HS
HSPLL
SOSC
—
—
—
—
Conditions
OS20
TOSC
TOSC = 1/FOSC
OS25
TCY
Instruction Cycle Time(3)
62.5
—
DC
ns
OS30
TosL,
TosH
External Clock in (OSCI)
High or Low Time
0.45 x TOSC
—
—
ns
EC
OS31
TosR,
TosF
External Clock in (OSCI)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(4)
—
15
30
ns
OS41
TckF
CLKO Fall Time(4)
—
15
30
ns
Note 1:
2:
3:
4:
See Parameter OS10 for
FOSC value
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Represents input to the system clock prescaler. PLL dividers and postscalers must still be configured so
that the system clock frequency does not exceed the maximum frequency shown in Figure 30-1.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
External Clock applied to the OSCI/CLKI pin. When an External Clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
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TABLE 30-18: AC SPECIFICATIONS FOR PHASE-LOCKED LOOP (PLL) MODE
Operating Conditions:
Operating temperature
Sym
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ
Max
Units
Conditions
FIN
Input Frequency Range
2
—
24
MHz
FMIN
Minimum Output Frequency from
the Frequency Multiplier
—
—
16
MHz 4 MHz FIN with 4x feedback ratio,
2 MHz FIN with 8x feedback ratio
FMAX
Maximum Output Frequency from
the Frequency Multiplier
96
—
—
MHz 4 MHz FIN with 24x net multiplication ratio,
24 MHz FIN with 4x net multiplication ratio
FSLEW Maximum Step Function of FIN at
which the PLL will be Ensured to
Maintain Lock
-4
—
+4
%
Full input range of FIN
TLOCK Lock Time for VCO
—
—
24
µs
With the specified minimum, TREF, and a
lock timer count of one cycle, this is the
maximum VCO lock time supported
JFM8
—
—
±0.12
%
4 MHz FIN with 4x feedback ratio
Cumulative Jitter of Frequency
Multiplier Over Voltage and
Temperature during Any Eight
Consecutive Cycles of the PLL Output
TABLE 30-19: INTERNAL RC ACCURACY
Operating Conditions:
Operating temperature
Param
No.
F20
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
FRC Accuracy @ 8 MHz
F20A
FRC Accuracy @ 8 MHz with
Enabled Self-Tune
Feature
Min
Typ(1)
Max
Units
-1.5
+0.15
1.5
%
2.0V VDD 3.6V, -20°C TA +85°C
(Note 2)
-2
—
2
%
2.0V VDD 3.6V, -40°C TA -20°C
-2
—
2
%
2.0V VDD 3.6V, +85°C TA +125°C
(Note 2)
-0.20
+0.05
-0.20
%
-20°C TA +85°C
VCAP Output Voltage = 1.8V
F21
LPRC @ 32 kHz
-20
—
20
%
F22
OSCTUN Step-Size
—
0.1
—
%/bit
F23
TLOCK FRC Self-Tune Lock
Time(3)
—
5
8
ms
Note 1:
2:
3:
Conditions
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB)
must be kept to a minimum.
Time from reference clock stable, and in range, to FRC tuned within range specified by F20
(with self-tune).
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PIC24FJ128GL306 FAMILY
FIGURE 30-10:
FRC ACCURACY OVER TEMPERATURE AND VDD(1)
VDD (V)
Note 1:
Temperature points of -40°C, +25°C and +85°C are production tested only.
TABLE 30-20: RC OSCILLATOR START-UP TIME
Operating Conditions:
Operating temperature
Param
Symbol
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ(1)
Max
Units
FR0
TFRC
FRC Oscillator Start-up
Time
—
2
—
µs
FR1
TLPRC
Low-Power RC Oscillator
Start-up Time
—
50
—
µs
Note 1:
Conditions
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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FIGURE 30-11:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Old Value
New Value
DO31
DO32
Note:
Refer to Figure 30-8 for Load conditions.
TABLE 30-21: CLKO AND I/O TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
Param
Symbol
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ(1)
Max
Units
DO31
TIOR
Port Output Rise Time
—
10
25
ns
DO32
TIOF
Port Output Fall Time
—
10
25
ns
DI35
TINP
INTx Pin High or Low
Time (input)
1
—
—
TCY
DI40
TRBP
CNx High or Low Time
(input)
1
—
—
TCY
Note 1:
Conditions
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.
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TABLE 30-22: RESET AND BROWN-OUT RESET REQUIREMENTS
Operating Conditions:
Operating temperature
Param
Symbol
No.
SY10
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min
Typ(1)
Max
Units
TMCL
MCLR Pulse Width (Low)
2
—
—
µs
Conditions
SY12
TPOR
Power-on Reset Delay
—
2
—
µs
SY13
TIOZ
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
Lesser of:
(3 TCY + 2)
or 700
—
(3 TCY + 2)
µs
SY25
TBOR
Brown-out Reset Pulse
Width
1
—
—
µs
SY45
TRST
Internal State Reset Time
—
50
—
µs
SY71
TWAKEUP Wake-up Time from Sleep
Mode
—
7
—
µs
VREGS (RCON[8]) = 1,
RETEN (RCON[12]) = 0,
LPCFG (FPOR[2]) = 1
—
35
—
µs
VREGS (RCON[8]) = 0,
RETEN (RCON[12]) = 0,
LPCFG (FPOR[2]) = 1
—
210
—
µs
VREGS (RCON[8]) = 1,
RETEN (RCON[12]) = 1,
LPCFG (FPOR[2]) = 0
—
325
—
µs
VREGS (RCON[8]) = 0,
RETEN (RCON[12]) = 1,
LPCFG (FPOR[2]) = 0
Note 1:
VDD VBOR
Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.
2019-2020 Microchip Technology Inc.
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FIGURE 30-12:
TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS
T1CK
TA11
TA10
TA15
TA20
TMR1
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS
Operating Conditions:
Operating temperature
Param.
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Symbol
TA10
TCKH
T1CK High Time Synchronous
TA11
TCKL
T1CK Low Time
TA15
TCKP
T1CK Input
Period
TA20
Note 1:
Min
Max
Units
Conditions
1
—
TCY
Must also meet Parameter TA15
Asynchronous
10
—
ns
Synchronous
1
—
TCY
Asynchronous
10
—
ns
Synchronous
2
—
TCY
Asynchronous
20
—
ns
TCKEXTMRL Delay from External T1CK Clock
Edge to Timer Increment
—
3
TCY
Must also meet Parameter TA15
Synchronous mode
These parameters are characterized but not tested in manufacturing.
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FIGURE 30-13:
MCCP TIMER MODE EXTERNAL CLOCK TIMING CHARACTERISTICS
TCKIx
TMR10
TMR11
TMR15
TMR20
CCPxTMR
TABLE 30-24: MCCP TIMER MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
Param.
No.
Symbol
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Min
Max
Units
—
TCY
TMR10
TCKH
TCKIx High Time
Synchronous
1
Asynchronous
10
—
ns
TMR11
TCKL
TCKIx Low Time
Synchronous
1
—
TCY
Asynchronous
10
—
ns
TMR15
TCKP
TCKIx Input Period Synchronous
2
—
TCY
20
—
ns
TMR20
TCKEXTMRL Delay from External TCKIx Clock Edge
to Timer Increment
—
1
TCY
Note 1:
These parameters are characterized but not tested in manufacturing.
Asynchronous
2019-2020 Microchip Technology Inc.
Conditions
Must also meet
Parameter TMR15
Must also meet
Parameter TMR15
DS30010198B-page 365
PIC24FJ128GL306 FAMILY
FIGURE 30-14:
MCCP INPUT CAPTURE x MODE TIMING CHARACTERISTICS
ICMx
IC10
IC11
IC15
TABLE 30-25: MCCP INPUT CAPTURE x MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
Param.
Symbol
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Min
Max
Units
Conditions
IC10
TICL
ICMx Input Low Time
25
—
ns
Must also meet Parameter IC15
IC11
TICH
ICMx Input High Time
25
—
ns
Must also meet Parameter IC15
IC15
TICP
ICMx Input Period
50
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
FIGURE 30-15:
MCCP PWM MODE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCMnx is Tri-Stated
OCMnx
TABLE 30-26: MCCP PWM MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
Param
No.
OC15
OC20
Note 1:
Symbol
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Min
Max
Units
TFD
Fault Input to PWM I/O Change
—
30
ns
TFLT
Fault Input Pulse Width
10
—
ns
These parameters are characterized but not tested in manufacturing.
DS30010198B-page 366
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 30-27: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Mode
Master Transmit Only (Half-Duplex)
Master Transmit/Receive (Full-Duplex)
Slave Transmit/Receive (Full-Duplex)
Note 1:
CKE
CKP
SMP
Maximum Data
Rate Typ.(1)
0,1
0,1
0,1
25 MHz
0,1
0,1
0,1
0,1
0
11 MHz
1
21 MHz
0,1
11 MHz
These parameters are characterized but not tested in manufacturing.
FIGURE 30-16:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP10
SCKx
(CKP = 1)
SP35
SDOx
SDIx
MSb
MSb In
LSb
LSb In
SP40 SP41
2019-2020 Microchip Technology Inc.
DS30010198B-page 367
PIC24FJ128GL306 FAMILY
FIGURE 30-17:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SCKx
(CKP = 1)
SP10
SP35
SDOx
MSb
SDIx
MSb In
SP40
DS30010198B-page 368
LSb
LSb In
SP41
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 30-28: SPIx MODULE MASTER MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
Param.
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Symbol
Min
Max
Units
SP10
TSCL, TSCH
SCKx Output Low or High Time
20
—
ns
SP35
TSCH2DOV,
TSCL2DOV
SDOx Data Output Valid After SCKx Edge
—
7
ns
SP36
TDOV2SC,
TDOV2SCL
SDOx Data Output Setup to First SCKx Edge
7
—
ns
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input to SCKx Edge
7
—
ns
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input to SCKx Edge
7
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
FIGURE 30-18:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP70
SCKx
(CKP = 1)
SP35
SDOx
MSb
LSb
SP51
SDIx
MSb In
SP40
2019-2020 Microchip Technology Inc.
LSb In
SP41
DS30010198B-page 369
PIC24FJ128GL306 FAMILY
FIGURE 30-19:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP70
SCKx
(CKP = 1)
SP35
MSb
SDOx
LSb
SP51
SDIx
MSb In
SP40
LSb In
SP41
TABLE 30-29: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
Param.No.
Symbol
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Min
Max
Units
SP70
TSCL, TSCH
SCKx Input Low Time or High Time
45
—
ns
SP35
TSCH2DOV,
TSCL2DOV
SDOx Data Output Valid After SCKx Edge
—
10
ns
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input to SCKx Edge
0
—
ns
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input to SCKx Edge
7
—
ns
SP50
TSSL2SCH,
TSSL2SCL
SSx to SCKx or SCKx Input
40
—
ns
SP51
TSSH2DOZ
SSx to SDOx Output High-Impedance
2.5
12
ns
SP52
TSCH2SSH,
TSCL2SSH
SSx After SCKx Edge
10
—
ns
SP60
TSSL2DOV
SDOx Data Output Valid After SSx Edge
—
12.5
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
DS30010198B-page 370
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 30-20:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
Start Condition
Stop Condition
SDAx
Note: Refer to Figure 30-8 for load conditions.
FIGURE 30-21:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 30-8 for load conditions.
2019-2020 Microchip Technology Inc.
DS30010198B-page 371
PIC24FJ128GL306 FAMILY
TABLE 30-30: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Operating Conditions:
Operating temperature
Param
Symbol
No.
IM10
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.(1)
Max.
Units
TLO:SCL Clock Low Time 100 kHz mode
TCY * (BRG + 2)
—
µs
400 kHz mode
TCY * (BRG + 2)
—
µs
Characteristics
1 MHz mode
IM11
IM20
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
µs
400 kHz mode
TCY * (BRG + 2)
—
µs
1 MHz mode
TCY * (BRG + 2)
—
µs
THI:SCL Clock High Time 100 kHz mode
TF:SCL
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode
IM21
TR:SCL
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
IM26
IM30
TSU:DAT Data Input
Setup Time
THD:DAT Data Input
Hold Time
IM45
IM50
ns
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
100
—
ns
0
—
µs
100 kHz mode
400 kHz mode
0
0.9
µs
1 MHz mode
0
0.3
µs
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
µs
TSU:STA Start Condition 100 kHz mode
Setup Time
400 kHz mode
THD:STA Start Condition 100 kHz mode
Hold Time
400 kHz mode
TSU:STO Stop Condition 100 kHz mode
Setup Time
400 kHz mode
THD:STO Stop Condition 100 kHz mode
Hold Time
400 kHz mode
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
µs
TCY * (BRG + 2)
—
ns
TCY * (BRG + 2)
—
ns
TCY * (BRG + 2)
—
ns
—
3500
ns
400 kHz mode
—
1000
ns
1 MHz mode
—
350
ns
TBF:SDA Bus Free Time 100 kHz mode
4.7
—
µs
400 kHz mode
1.3
—
µs
1 MHz mode
0.5
—
µs
—
400
pF
TAA:SCL Output Valid
from Clock
100 kHz mode
Bus Capacitive 100 kHz mode
Loading
400 kHz mode
CB
1 MHz mode
IM51
ns
1000
ns
1 MHz mode
IM40
100
—
300
1 MHz mode
IM34
—
300
1 MHz mode
IM33
ns
ns
—
1 MHz mode
IM31
300
300
20 + 0.1 CB
1 MHz mode
IM25
—
20 + 0.1 CB
TPGD
Note 1:
Pulse Gobbler Delay
2C
BRG is the value of the I
DS30010198B-page 372
—
400
pF
—
10
pF
52
312
ns
Conditions
Only relevant for Repeated
Start condition
After this period, the first clock
pulse is generated
The amount of time the bus
must be free before a new
transmission can start
Baud Rate Generator.
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 30-22:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Start
Condition
Stop
Condition
Note: Refer to Figure 30-8 for load conditions.
FIGURE 30-23:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
Note: Refer to Figure 30-8 for load conditions.
2019-2020 Microchip Technology Inc.
DS30010198B-page 373
PIC24FJ128GL306 FAMILY
TABLE 30-31: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Operating Conditions:
Operating temperature
Param
Symbol
No.
IS10
IS11
IS20
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics
TLO:SCL Clock Low Time 100 kHz mode
THI:SCL
TF:SCL
TR:SCL
IS26
IS31
IS33
IS34
IS40
IS45
IS50
CPU clock must be minimum 800 kHz
CPU clock must be minimum 3.2 MHz
µs
µs
Clock High Time 100 kHz mode
4.0
—
µs
CPU clock must be minimum 800 kHz
400 kHz mode
0.6
—
µs
CPU clock must be minimum 3.2 MHz
1 MHz mode
0.5
—
µs
300
ns
SDAx and SCLx 100 kHz mode
—
Fall Time
400 kHz mode 20 + 0.1 CB
—
SDAx and SCLx 100 kHz mode
—
Rise Time
400 kHz mode 20 + 0.1 CB
Data Input
Hold Time
Start Condition
Hold Time
Stop Condition
Hold Time
TAA:SCL Output Valid
from Clock
TBF:SDA Bus Free Time
CB
µs
—
TSU:STO Stop Condition
Setup Time
THD:STO
—
—
TSU:STA Start Condition
Setup Time
THD:STA
4.7
1.3
Bus Capacitive
Loading
DS30010198B-page 374
300
ns
100
ns
1000
ns
300
ns
—
300
ns
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
µs
100 kHz mode
1 MHz mode
IS30
Conditions
0.5
TSU:DAT Data Input
Setup Time
THD:DAT
Units
1 MHz mode
1 MHz mode
IS25
Max.
400 kHz mode
1 MHz mode
IS21
Min.
0
0.3
µs
4700
—
ns
400 kHz mode
600
—
ns
1 MHz mode
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
100 kHz mode
1 MHz mode
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
600
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
250
—
ns
0
3500
ns
400 kHz mode
0
1000
ns
1 MHz mode
0
350
ns
100 kHz mode
4.7
—
µs
400 kHz mode
1.3
—
µs
1 MHz mode
0.5
—
µs
100 kHz mode
—
400
pF
400 kHz mode
—
400
pF
1 MHz mode
—
10
pF
100 kHz mode
Only relevant for Repeated Start
condition
After this period, the first clock pulse is
generated
The amount of time the bus must be
free before a new transmission can
start
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 30-32: A/D MODULE SPECIFICATIONS
Operating Conditions:
Operating temperature
Param
Symbol
No.
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 2.2
—
Lesser of:
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS – 0.3
—
VSS + 0.3
V
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 1.7
—
AVDD
V
AD06
VREFL
Reference Voltage Low
AVSS
—
AVDD – 1.7
V
AD07
VREF
Absolute Reference
Voltage
AVSS – 0.3
—
AVDD + 0.3
V
AD10
VINH-VINL Full-Scale Input Span
Analog Inputs
VREFL
—
VREFH
V
(Note 2)
AD11
VIN
Absolute Input Voltage
AVSS – 0.3
—
AVDD + 0.3
V
AD12
VINL
Absolute VINL Input
Voltage
AVSS – 0.3
—
AVDD/3
V
Leakage Current
—
±1.0
±610
nA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V,
Source Impedance = 2.5 k
Recommended
Impedance of Analog
Voltage Source
—
—
2.5k
10-bit
AD20B Nr
Resolution
—
12
—
bits
AD21B INL
Integral Nonlinearity
—
±1
< ±2
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V,
Conversion Rate = 125 ksps
AD22B DNL
Differential Nonlinearity
—
±0.5
< ±1(3)
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V,
Conversion Rate = 125 ksps
AD23B GERR
Gain Error
—
±0.6
-2 to +5
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V,
Conversion Rate = 125 ksps
AD24B EOFF
Offset Error
—
±0.5
-2 to +4
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V,
Conversion Rate = 125 ksps
AD25B
Monotonicity(1)
—
—
—
—
AD13
AD17
RIN
A/D Accuracy
Note 1:
2:
3:
Guaranteed
The A/D conversion result never decreases with an increase in the input voltage.
Measurements are taken with the external VREF+ and VREF- used as the A/D voltage reference.
Code 2047 can have a DNL error of 1 LSb to 2.7V, 12-bit mode
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
DS30010198B-page 376
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 30-24:
10-BIT AND 12-BIT ENOB
10-it Mode (ENOB)
9.94
9.93
9.92
9.91
ENOB
9.9
-40C
9.89
25C
9.88
85C
9.87
125C
9.86
9.85
9.84
100
150
200
250
300
Conversion Rate (ŬƐƉƐ)
350
400
12-it Mode (ENOB)
11.8
11.75
11.7
ENOB
11.65
-40C
11.6
25C
85C
11.55
125C
11.5
11.45
11.4
100
2019-2020 Microchip Technology Inc.
150
200
250
Conversion Rate (ŬƐƉƐ)
300
350
DS30010198B-page 377
PIC24FJ128GL306 FAMILY
FIGURE 30-25:
12-BIT INL DNL PLOTS
DNL, 12-bit Mode, 100KSPS, Vdd=3.3V
INL, 12-bit Mode, 100KSPS, Vdd=3.3V
0.4
0.8
0.3
0.6
0.2
0.1
0.4
0
0.2
-0.1
-0.2
0
-0.3
-0.2
-0.4
-0.5
-0.4
-0.6
-0.6
-0.7
0
500
1000
1500
2000
2500
3000
3500
0
4000
500
1000
1500
2000
2500
3000
3500
4000
3500
4000
3500
4000
INL, 12-bit Mode, 250KSPS, Vdd=3.3V
DNL, 12-bit Mode, 250KSPS, Vdd=3.3V
1
0.4
0.3
0.8
0.2
0.6
0.1
0
0.4
-0.1
0.2
-0.2
-0.3
0
-0.4
-0.2
-0.5
-0.4
-0.6
-0.6
-0.7
0
500
1000
1500
2000
2500
3000
3500
0
4000
500
DNL, 12-bit Mode, 350KSPS, Vdd=3.3V
1000
1500
2000
2500
3000
INL, 12-bit Mode, 350KSPS, Vdd=3.3V
1
2
0.8
1.5
0.6
0.4
1
0.2
0
0.5
-0.2
0
-0.4
-0.6
-0.5
-0.8
-1
0
500
1000
1500
-1.2
DS30010198B-page 378
2000
2500
3000
3500
4000
-1
0
500
1000
1500
2000
2500
3000
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 30-26:
10-BIT INL DNL PLOTS
DNL, 10-bit Mode, 100KSPS, Vdd=3.3V
INL, 10-bit Mode, 100KSPS, Vdd=3.3V
0.1
0.2
0.15
0.05
0.1
0
0.05
-0.05
0
-0.1
-0.05
-0.15
-0.1
-0.15
-0.2
0
200
400
600
800
0
1000
200
DNL, 10-bit Mode, 250KSPS, Vdd=3.3V
0.2
0.1
0.15
0.05
0.1
0
0.05
-0.05
0
-0.1
-0.05
-0.15
-0.1
-0.2
-0.15
200
400
600
600
800
1000
800
1000
800
1000
INL, 10-bit Mode, 250KSPS, Vdd=3.3V
0.15
0
400
800
0
1000
200
DNL, 10-bit Mode, 400KSPS, Vdd=3.3V
400
600
INL, 10-bit Mode, 400KSPS, Vdd=3.3V
0.25
0.3
0.2
0.2
0.15
0.1
0.1
0.05
0
0
-0.05
-0.1
-0.1
-0.15
-0.2
-0.2
-0.3
-0.25
0
200
400
600
2019-2020 Microchip Technology Inc.
800
1000
0
200
400
600
DS30010198B-page 379
GAIN AND OFFSET VOLTAGES
10-Bit Mode (Oīset)
12-Bit Mode (Oīset)
0.4
0.7
Charge
Charrge Pump
Pu
ump Enabled
Enab
bled
ї
і
0.6
0.3
0.5
-40C
0.25
25C
85C
0.2
Oīset (LSB)
Oīset (LSB)
і
0.35
Charge
Char
rge Pump
Pu
ump Enabled
Enablled
-40C
0.4
25C
85C
0.3
125C
0.15
125C
0.2
0.1
0.1
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VDD (V)
3
3.1 3.2 3.3 3.4 3.5 3.6
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VDD (V)
10-Bit Mode (Gain)
і
Charge
Pump
Charrge Pu
ump Enabled
Enab
bled
ї
1.4
і
Charge
Char
rge Pump
Pu
ump Enabled
ї
1.2
1
-40C
0.6
25C
2019-2020 Microchip Technology Inc.
0.4
85C
0.2
125C
Gain (LSB)
0.8
Gain (LSB)
3.1 3.2 3.3 3.4 3.5 3.6
12-Bit Mode (Gain)
1
0.8
-40C
0.6
25C
85C
0.4
125C
0.2
0
2
2.1
2.2
2..1 2.
.2 2.3
2..3 2.4
2..4 2.5
2..5 2.6
2..6 2.7
2.. 2.8 2.9
-0.2
-0.4
3
1.6
1.4
1.2
ї
3
3.1 3.2 3.3 3.4 3.5 3.6
0
-0.2
VDD (V)
-0.4
2
2.1
2.2
2
.1 2.
.2 2.3
2..3 2.4
2..4 2.5
2..5 2.6
2..6 2.7
2. 2.8 2.9
VDD (V)
3
3.1 3.2 3.3 3.4 3.5 3.6
PIC24FJ128GL306 FAMILY
DS30010198B-page 380
FIGURE 30-27:
PIC24FJ128GL306 FAMILY
31.0
PACKAGING INFORMATION
31.1
Package Marking Information
28-Lead QFN (6x6 mm)
XXXXXXXX
XXXXXXXX
YYWWNNN
24FJ128
GL302
1910017
28-Lead UQFN (4x4x0.6 mm)
XXXXX
XXXXXX
XXXXXX
YYWWNNN
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SSOP (5.30 mm)
Legend: XX...X
Y
YY
WW
NNN
Note:
Example
PIC24
FJ128
GL302
1910017
28-Lead SOIC (7.50 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
Example
PIC24FJ128GL302
1910017
Example
PIC24FJ128
GL302
1910017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019-2020 Microchip Technology Inc.
DS30010198B-page 381
PIC24FJ128GL306 FAMILY
31.1
Package Marking Information (Continued)
36-Lead UQFN (5x5 mm)
XXXXXXXX
XXXXXXXX
YYWWNNN
48-Lead UQFN (6x6 mm)
XXXXXXXX
XXXXXXXX
YYWWNNN
48-Lead TQFP (7x7x1.0 mm)
XXXXXXX
XXXYYWW
NNN
64-Lead QFN (9x9x0.9 mm)
XXXXXXXX
XXXXXXXX
YYWWNNN
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS30010198B-page 382
Example
24FJ128
GL303
1910017
Example
24FJ128
GL305
1910017
Example
FJ128GL
3051910
017
Example
24FJ128
GL306
1910017
Example
PIC24FJ128
GL306
1920017
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
31.2
Package Details
The following sections give the technical details of the packages.
2019-2020 Microchip Technology Inc.
DS30010198B-page 383
PIC24FJ128GL306 FAMILY
DS30010198B-page 384
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
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2019-2020 Microchip Technology Inc.
DS30010198B-page 385
PIC24FJ128GL306 FAMILY
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS30010198B-page 386
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019-2020 Microchip Technology Inc.
DS30010198B-page 387
PIC24FJ128GL306 FAMILY
DS30010198B-page 388
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019-2020 Microchip Technology Inc.
DS30010198B-page 389
PIC24FJ128GL306 FAMILY
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS30010198B-page 390
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019-2020 Microchip Technology Inc.
DS30010198B-page 391
PIC24FJ128GL306 FAMILY
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