AN8150FB

DATA SHEET Part No. Package Code No. AN8150FB QFP044-P-1010F Publication date: February 2008 SDJ00021AEB 1 AN8150FB Contents Overview Features Package Type ……..……………………………………………………………………………………………………. 3 ……..……………………………………………………………………………………………………. 3 ………………………………………………………………………………………………………. 3 …………………………………...………………………………………………………………………. 3 ………………………………………….…………………………………………………………. 4 …………………..………………………………………………………………………………. 5 ……………………..……………..…………………………......………………… 7 ………………….………………….…………………………………………………. 8 Applications …………….………………………………………………………………………………………………… 3 Block Diagram Pin Descriptions Absolute Maximum Ratings Electrical Characteristics Technical Data Usage Notes Operating Supply Voltage Range …………………………………………..……………………………………. 7 …………………………………….………….…………………………………………………. 9 ……….……………………….………………….…………………………………………………. 17 SDJ00021AEB 2 AN8150FB AN8150FB Octal, high precision 13-bit voltage output DAC Overview AN8150FB is IC which has octal 13 bit DACs constituted by Bi-CMOS process. Features Resolution: 13-bit Built-in DAC: 8 DACs. Integral linearity error: ±2 LSB typ. Differential linearity error: ±0.5 LSB typ. Supply voltage: +10.5 V (AVCC), –7.5 V (AVEE), +5 V (VDD) Output range: –3.3 V to +7.7 V DAC input data: 13-bit parallel DAC selection address data: 3-bit parallel Input interface: TTL compatible Applications Industrial instrumentation Package 44 pin plastic quad flat package (QFP type) Type Silicon monolithic bipolar IC SDJ00021AEB 3 AN8150FB Block Diagram 3 VRBAB 4 VRMAB 5 AVCC D0(LSB) 15 D1 16 D2 17 D3 18 D4 19 D5 20 D6 21 D7 22 D8 23 D9 24 D10 25 D11 26 D12(MSB) 27 INPUT LATCH A INPUT LATCH B INPUT LATCH C INPUT LATCH D INPUT LATCH E INPUT LATCH F INPUT LATCH G INPUT LATCH H CONTROL LOGIC DAC LATCH A DAC LATCH B DAC LATCH C DAC LATCH D DAC LATCH E DAC LATCH F DAC LATCH G DAC LATCH H 38 AVCC 2 VOUTA 44 VOUTB 1 AMPREFAB 43 VOUTC 41 VOUTD 42 AMPREFCD 37 VOUTE 35 VOUTF 36 AMPREFEF 34 VOUTG 32 VOUTH 33 AMPREFGH DAC A (DAC+BUF) DAC B (DAC+BUF) DAC C (DAC+BUF) DAC D (DAC+BUF) DAC E (DAC+BUF) DAC F (DAC+BUF) DAC G (DAC+BUF) DAC H (DAC+BUF) A2 A1 8 9 CS 11 A0 10 VRMCDEF 39 VRBGH 31 VRMGH 30 VRBCDEF 40 CLR 28 WR 12 LD 7 Note) This block diagram is for explaining functions. The part of the block diagram may be omitted, or it may be simplified. SDJ00021AEB 29 AVEE 13 VDD 14 VSS 6 AVEE 4 AN8150FB Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin name AMPREFAB VOUTA VRBAB VRMAB AVCC AVEE LD A2 A1 A0 CS WR VDD VSS D0(LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12(MSB) CLR AVEE VRMGH VRBGH VOUTH AMPREFGH VOUTG Type Input Output Input Input Power supply Power supply Input Input Input Input Input Input Power supply GND Input Input Input Input Input Input Input Input Input Input Input Input Input Input Power supply Input Input Output Input Output Offset adjustment for DAC A, B Output voltage of DAC A Reference voltage (Bottom) for DAC A, B Reference voltage (Midpoint) for DAC A, B Analogue positive supply voltage Analogue negative supply voltage Load input Address 2 digital input (MSB) Address 1 digital input Address 0 digital input (LSB) Chip selection digital input Write digital input Digital positive supply voltage Ground for digital Digital input (LSB) Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input (MSB) Asynchronous clear input Analogue negative supply voltage Reference voltage (Midpoint) for DAC G, H Reference voltage (Bottom) for DAC G, H Output voltage of DAC H Offset adjustment for DAC G, H Output voltage of DAC G Description SDJ00021AEB 5 AN8150FB Pin Descriptions (continued) Pin No. 35 36 37 38 39 40 41 42 43 44 Pin name VOUTF AMPREFEF VOUTE AVCC VRMCDEF VRBCDEF VOUTD AMPREFCD VOUTC VOUTB Type Output Input Output Power supply Input Input Output Input Output Output Output voltage of DAC F Offset adjustment for DAC E, F Output voltage of DAC E Analog positive supply voltage Reference voltage (Midpoint) for DAC C, D, E, F Reference voltage (Bottom) for DAC C, D, E, F Output voltage of DAC D Offset adjustment for DAC C, D Output voltage of DAC C Output voltage of DAC B Description SDJ00021AEB 6 AN8150FB Absolute Maximum Ratings A No. 1 Parameter Supply voltage Symbol AVCC – AVEE VDD ICC 2 Supply current IEE IDD 3 4 5 Power dissipation Operating ambient temperature Storage temperature PD Topr Tstg Rating 19.7 7 50 –50 10 359 0 to +70 –55 to +125 Unit V V mA mA mA mW °C °C Note *1 ⎯ ⎯ ⎯ *2 *3 *3 Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at Ta = 70°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the • PD – Ta diagram in the Technical Data and use under the condition not exceeding the allowable value. *3: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C. Operating Supply Voltage Range Parameter Symbol AVCC Supply voltage range AVEE VDD Range +10.0 V to +11.0 V –7.7 V to –6.8 V 4.75 V to 5.25 V V Unit Note ⎯ ⎯ ⎯ Note) The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. SDJ00021AEB 7 AN8150FB Electrical Characteristics at AVCC = 10.5 V, AVEE = –7.5 V, VDD = 5 V Note) Ta = 25°C±2° unless otherwise specified. B No. 1 2 3 4 5 6 7 8 9 Parameter Supply current Supply current Supply current High digital input current Low digital input current High reference resistor current (1) Low reference resistor current (1) High reference resistor current (2) Low reference resistor current (2) Symbol ICC IEE IDD IIH IIL IVRM IVRB IVRM IVRB DIH DIL VOMAX VOMIN VRM VRB Res EL ED EFS EZS EG EOFF SR TST Conditions — — — — — VRMAB, VRMGH VRM = 2.2 V, VRB = 0 V VRBAB, VRBGH VRM = 2.2 V, VRB = 0 V VRMCDEF VRM = 2.2 V, VRB = 0 V VRBCDEF VRM = 2.2 V, VRB = 0 V — — — — — — — — — — — — — — — Technical Data. Limits Min 28 –33 — –1 –1 –3 Typ 33 –28 0.01 — — –1.5 Max 38 –23 1 1 1 — Unit mA mA mA μA μA μA μA μA μA V V V V V V Bits LSB LSB LSB LSB LSB LSB V/μs μs No te — — — — — — — — — — — *1 *1 *1 *1 — — — — –1 870 –1 600 –1 330 –6 –3 — –3 740 –3 200 – 2 660 0.7 × VDD VSS AVCC –2 — VRB — — — — — — — — 3 — — — — — 2.2 0 13 ±2 ±0.5 ±4 ±4 ±4 ±4 — — VDD 0.3 × VDD — AVEE +3 — VRM — ±4 ±1 ±8 ±8 ±10 ±8 — 30 10 High-level digital input voltage 11 Low-level digital input voltage 12 Max. output voltage 13 Min. output voltage 14 Reference voltage (midpoint) 15 Reference voltage (bottom) 16 Resolution 17 Linearity error 18 Differential linearity error 19 Full-scale error 20 Zero-scale error 21 Gain error 22 Offset error 23 Output voltage slew rate 24 Settling time Note) *1: Sets so that the following conditions are satisfied. For details, refer to VOMAX = 5 × VRM – 2.5 × VRB – 1.5 × AMPREF < AVCC – 2 V VOMIN = 2.5 × VRB – 1.5 × AMPREF > AVEE + 3 V SDJ00021AEB 8 AN8150FB Technical Data 1. I/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit AVCC (Pin5, Pin38) Impedance Description Offset adjustment pin of DAC A, B. Apply the same voltage as VRMAB normally. 1 DC = 2.2 V 1 10 MΩ or more AVEE (Pin6, Pin29) 2, 32, 34, 35, 37, 41, 43, 44 7.7 V Pin 2, 32, 34, 35, 37, 41, 43, 44 AVCC (Pin 5, Pin 38) DAC A to H output voltage 80 Ω –3.3 V AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) Reference voltage of DAC A, B (bottom). Apply 0 V normally. 1.38 kΩ or more 3 DC = 0 V 3 AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) 4 DC = 2.2 V 4 10 MΩ or more Reference voltage of DAC A, B (midpoint) VRTAB. i.e., 2 × (VRMAB–VRBAB) is generated inside the IC. DAC A, B output amplitude = 2.5 × (VRTAB – VRBAB) AVEE (Pin 6, Pin 29) 5, 38 6, 29 +10.0 V to +11.0 V –7.7 V to –6.8 V — — — — Analog positive supply voltage Apply 10.5 V normally Analog negative supply voltage Apply –7.5 V normally. SDJ00021AEB 9 AN8150FB Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit VDD (Pin 13) Impedance Description Load input Transfer the data of input latch to DAC latch at LD. Start DAC settling. 5V 7 0V VSS (Pin 14) VDD (Pin13) 7 10 MΩ or more 5V 8, 9, 10 0V Address input A2: MSB, A0: LSB Pin 8, 9, 10 10 MΩ or more VSS (Pin14) VDD (Pin 13) 5V 11 0V VSS (Pin 14) Chip select digital input Level trigger. DAC determined by A1, A2, and A0 is selected when this pin is low. 10 MΩ or more 11 VDD (Pin 13) 5V 12 0V VSS (Pin 14) 12 10 MΩ or more Write digital input Level trigger. The data is written to the input latch of DAC selected at A2, A1, A0 when this pin is low. 13 14 +4.75 V to +5.25 V 0V — — — — Digital positive supply voltage Apply 5 V normally. Digital ground SDJ00021AEB 10 AN8150FB Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit VDD (Pin 13) Impedance Description Digital input DB0: LSB, DB12: MSB 5V 15 to 27 0V VSS (Pin 14) Pin 15 to 27 10 MΩ or more VDD (Pin 13) 5V 28 0V VSS (Pin 14) Asynchronous clear input 0 V is output during low. The previous value is hold as for latch. 10 MΩ or more 28 AVCC (Pin 5, Pin 38) 30 DC = 2.2 V 30 10 MΩ or more Reference voltage of DAC G, H (midpoint) VRTGH. i.e., 2 × (VRMGH – VRBGH) is generated inside the IC. DAC G, H output amplitude = 2.5 × (VRTGH – VRBGH) AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) Reference voltage of DAC G, H (bottom). Apply 0 V normally. 1.38 kΩ 31 DC = 0 V 31 AVEE (Pin 6, Pin 29) SDJ00021AEB 11 AN8150FB Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit AVCC (Pin 5, Pin 38) Impedance Description Offset adjustment pin of DAC G, H. Apply the same voltage as VRMGH normally. 33 DC = 2.2 V 33 9 kΩ AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) Offset adjustment pin of DAC E, F. Apply the same voltage as VRMEF normally. 9 kΩ 36 DC = 2.2 V 36 AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) 39 DC = 2.2 V 39 10 MΩ or more Reference voltage of DAC C, D, E, F (midpoint) VRTAB. i.e., 2 × (VRMCDEF – VRBCDEF) is generated inside the IC. DAC C, D, E, F output amplitude = 2.5 × (VRTCDEF – VRBCDEF) AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) Reference voltage of DAC C, D, E, F (bottom). Apply 0 V normally. 0.69 kΩ 40 DC = 0 V 40 AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) Offset adjustment pin of DAC C, D. Apply the same voltage as VRMCD normally. 9 kΩ 42 DC = 2.2 V 42 AVEE (Pin 6, Pin 29) SDJ00021AEB 12 AN8150FB Technical Data (continued) 2. Timing chart At operation of D/A converter t1 A0, A1, A2 t5 CS t3 t6 t2 WR t7 DATA t4 t8 t10 LDAC t9 t11 VOUT At CLR operation t12 CLR t13 VOUT Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Rating 25 25 75 75 0 0 15 15 75 100 30 75 30 30 0V Unit ns ns ns ns ns ns ns ns ns ns μs ns μs μs Description Setup time of A0, A1, A2 compared to WR Hold time of A0, A1, A2 compared to WR Pulse width of CS Min. pulse width of WR Setup time of CS compared to WR Hold time of CS compared to WR Setup time of DATA compared to WR Hold time of DATA compared to WR Min. pulse width of LDAC Setup time of WR compared to LDAC Settling time of VOUT compared to LDAC Min. pulse width of CLR Settling time of VOUT compared to CLR Settling time of VOUT compared to CLR cancel t14 SDJ00021AEB 13 AN8150FB Technical Data (continued) 3. Truth table DAC address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 DAC A input latch DAC B input latch DAC C input latch DAC D input latch DAC E input latch DAC F input latch DAC G input latch DAC H input latch 機能 DAC operation CLR 1 1 1 1 1 1 1 0 Note) T: through L: latch LD 0 1 1 x x x 0 x WR 0 1 x 0 1 x x x CS 0 x 1 0 x 1 x x INPUT LATCH T L L T L L x T (0 V) DAC LATCH T L L x x x T (0 V) T (0 V) SDJ00021AEB 14 AN8150FB Technical Data (continued) 4. DAC code table Bipolar VRM VRB Output amplitude Midpoint electric potential DACOUT (Max) DACOUT (Min) 1 1111 1111 1111 : 1 0000 0000 0001 1 0000 0000 0000 0 1111 1111 1111 : 0 0000 0000 0001 0 0000 0000 0000 2.2 V (VRT = 4.4 V) *1 0V 11 V[p-p] 2.2 V 7.69866 V –3.3 V 7.69866 V : 2.20134 V 2.2 V 2.19866 V : –3.29866 V –3.3 V Unipolar 2 V (VRT = 4 V) 0V 10 V[p-p] 2V 6.99878 V –3 V 6.99878 V : 2.00122 V 2V 1.99878 V : –2.99878 V –3 V Note) *1: VRT = 2 × VRM – VRB (generated inside) VDAC = (VRM–VRB) × 2 × D/8192+VRB (internal DAC output voltage) DACOUT = 2.5 × VDAC – 1.5 × AMPREF AMPREF = VRM VRT VRB VDAC DAC + amp. – 1.5R DACOUT R AMPREF Equivalent circuit of DAC output block SDJ00021AEB 15 AN8150FB Technical Data (continued) 5. PD ⎯ Ta diagram SDJ00021AEB 16 AN8150FB Usage Notes 1. This IC is intended to be used for Industrial instrumentation. Consult our sales staff in advance for information on the following applications: • Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. 1) Space appliance (such as artificial satellite, and rocket) 2) Traffic control equipment (such as for automobile, airplane, train, and ship) 3) Medical equipment for life support 4) Submarine transponder 5) Control equipment for power plant 7) Weapon 8) Others: Applications of which reliability equivalent to 1) to 7) is required. 2. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might smoke or ignite. 3. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description for the pin configuration. 4. Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as a solderbridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin – VCC short (Power supply fault), output pin – GND short (Ground fault), or output-to-output-pin short (load short). And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 6. When using the LSI for new models, verify the safety including the long-term reliability for each product. 7. When the application system is designed by using this LSI, be sure to confirm notes in this book. Be sure to read the notes to descriptions and the usage notes in the book. 8. Power-on sequence Note that this IC may be latched up depending on the power-on sequence because it has positive/negative multi-power supplies. The recommended power-on sequence is described below. 1) DVDD ↓ 2) AVCC , VRT, VRB, AMPREF (No sequence limit) Note) The sequence of AVEE does not matter; that is, AVEE does not malfunction either before or after DVDD . 9. DVDD voltage supply range The conversion accuracy of this IC may deteriorates depending on the voltage of DVDD and VRM. Use the IC within the following range. 2 × VRM – VRB – DVDD ≤ 0.3 V 10.The conversion accuracy of this IC deteriorates depending on the voltage of VRM. Use the IC within the following range. VRB ≥ – 0.3 V SDJ00021AEB 17 AN8150FB Usage Notes (continued) 11. Output voltage and load resistance This IC has been designed to drive an output load resistance of 50 Ω. When this IC is used with a resistance under 50 kΩ, the integral linearity error might be worse. In this case, raise the power supply voltage to prevent it. Determine the power supply voltage referring to the diagrams below. VCC – VOUTmax output load resistance characteristics VCC – VOUTmax (V) Output load resistance (kΩ) VEE – VOUTmin output load resistance characteristics VOUTmin – VEE (V) Output load resistance (kΩ) SDJ00021AEB 18 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: – Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. – Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.