94302-01

Advance Information PE94302 Product Description The PE94302 is a high linearity, 6-bit UltraCMOS™ RF Digital Step Attenuator (DSA) specifically optimized for rad-hard space applications. This 50-ohm RF DSA covers a 31.5 dB attenuation range in 0.5 dB steps. It provides both parallel and serial CMOS control interface. The PE 94302 maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and power consumption. The PE94302 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. 50 Ω RF Digital Step Attenuator For Rad-Hard Space Applications 6-bit, 31.5 dB, DC – 4.0 GHz Features • Attenuation: 0.5 dB steps to 31.5 dB • Flexible parallel and serial programming interfaces • 100 Krads (Si) Total Dose • Positive CMOS control logic • High attenuation accuracy and linearity over temperature and frequency • Very low power consumption • 50 Ω impedance Figure 1. Functional Schematic Diagram Switched Attenuator Array RF Input RF Output Figure 2. Package Type 28-lead CQFP Parallel Control Serial Control 6 3 Control Logic Interface Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V Parameter Operation Frequency Insertion Loss Any Bit or Bit Combination 0.5 dB - 23.5 dB Attenuation 24 dB - 31.5 dB Attenuation 3 Test Conditions Frequency DC-4000 DC - 2.2 GHz DC ≤ 1.0 GHz 1.0 GHz ≤ 2.2 GHz 1.0 GHz ≤ 2.2 GHz 1 MHz - 2.2 GHz Typical Max Units MHz 1.5 +/-(0.25 + 3% of attenuation setting) +/-(0.25 + 5% of attenuation setting) +/-(11% of attenuation setting) 34 52 20 12 dB Attenuation Accuracy dB 1 dB Compression1,2 Input IP3 1 dBm dBm dB dBm µs Two-tone inputs 1 MHz - 2.2 GHz DC - 2.2 GHz Return Loss RF Input Power (50 Ω) Switching Speed 50% of control voltage to 90% of final attenuation level 1 Notes: 1. Device Linearity will begin to degrade below 1 MHz 2. Maximum Operating Power = +12 dBm 3. Specs are guaranteed to 2.2 GHz, Characterized to 4.0 GHz Document No. 70/0186-02 │ www.psemi.com ©2005-2007 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 6 PE94302 Advance Information Figure 3. Pin Configuration (Top View) 26 GND 25 GND 24 GND 28 C0.5 27 C1 23 C2 22 C4 Table 3. Absolute Maximum Ratings Symbol VDD Parameter/Conditions Power supply voltage Negative Power supply voltage (-VDD) Voltage on any DC input Storage temperature range Input power (50Ω) ESD voltage (Human Body Model) Min -0.3 -4.0 -0.3 -65 Max 4.0 0.3 VDD+ 0.3 150 24 500 Units V V V °C dBm V C16 GND RF1 GND Data GND CLK 1 2 3 4 5 6 7 21 20 C8 GND Vss VI TST PIN VESD 19 RF2 PE94302 18 17 16 GND P/S GND 15 Reset Table 2. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Paddle Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute maximum ratings for extended periods may affect device reliability. GND 10 11 GND 12 13 RS2 RS1 VDD Pin Name C16 GND RF1 GND Data GND CLK LE VDD GND RS1 GND RS2 VSS Reset GND P/S GND RF2 GND C8 C4 C2 GND GND GND C1 C0.5 GND Description Attenuation control bit, 16dB Ground connection RF port (Note 1). Ground connection Serial interface data input Ground connection Serial interface clock input. Latch Enable input (Note 2). Power supply pin. Ground connection Reset Selection (note 3) Ground connection Reset Selection (Note 3) Negative supply voltage Reset (Note 4) Ground connection Parallel/Serial mode select. Ground connection RF port (Note 1). Ground connection Attenuation control bit, 8 dB. Attenuation control bit, 4 dB. Attenuation control bit, 2 dB. Ground connection Ground connection Ground connection Attenuation control bit, 1 dB. Attenuation control bit, 0.5 dB. Ground connection VSS LE 14 8 9 Table 4. DC Electrical Specifications Parameter VDD Power Supply Voltage Vss Power Supply Voltage IDD Power Supply Current Iss Power Supply Current TOP Operating temperature range Digital Input High Digital Input Low Digital Input Leakage -100 -40 0.7xV DD 0.3xVDD 1 85 Min 2.7 -3.3 Typ 3.0 -3.0 Max 3.3 -2.7 100 Units V V µA µA °C V V µA Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Note 1: Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor. 2: Latch Enable (LE) has an internal 100 kΩresistor to VDD. 3: Must be tied to Vdd or GND under normal operation. 4: Must be tied to GND under normal operation ©2005-2007 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 6 Switching Frequency The PE94302 has a maximum 25 kHz switching rate. Document No. 70/0186-02 │ U ltraCMOS™ RFIC Solutions PE94302 Advance Information Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE94302. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of six CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 5 (Parallel Interface Timing Diagram), Table 8 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 5) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) should be either pulled high or floated (see Table 2, note 2). Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 4 (Serial Interface Timing Diagram) and Table 7 (Serial Interface AC Characteristics). Table 5. Truth Table P/S 0 0 0 0 0 0 0 0 C16 0 0 0 0 0 0 1 1 C8 0 0 0 0 0 1 0 1 C4 0 0 0 0 1 0 0 1 C2 0 0 0 1 0 0 0 1 C1 0 0 1 0 0 0 0 1 C0.5 0 1 0 0 0 0 0 1 Attenuation State Reference Loss 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB Note: Not all 64 possible combinations of C0.5-C16 are shown in table Document No. 70/0186-02 │ www.psemi.com ©2005-2007 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 6 PE94302 Advance Information Figure 4. Serial Interface Timing Diagram LE Table 6. 6-Bit Attenuator Serial Programming Register Map Clock B5 C16 Data MSB LSB B4 C8 B3 C4 B2 C2 B1 C1 B0 C0.5 ↑ MSB (first in) tLESUP tLEPW ↑ LSB (last in) tSDSUP tSDHLD Figure 5. Parallel Interface Timing Diagram LE Parallel Data C16:C0.5 tPDSUP tLEPW tPDHLD Table 7. Serial Interface AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol fClk tClkH tClkL tLESUP tLEPW tSDSUP tSDHLD Note: Table 8. Parallel Interface AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol tLEPW tPDSUP tPDHLD Parameter Serial data clock frequency (Note 1) Serial clock HIGH time Serial clock LOW time LE set-up time after last clock falling edge LE minimum pulse width Serial data set-up time before clock rising edge Serial data hold time after clock falling edge Min Max 10 Unit MHz ns ns ns ns ns ns Parameter LE minimum pulse width Data set-up time before rising edge of LE Data hold time after falling edge of LE Min 10 10 10 Max Unit ns ns ns 30 30 10 30 10 10 fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. ©2005-2007 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 6 Document No. 70/0186-02 │ U ltraCMOS™ RFIC Solutions PE94302 Advance Information Figure 6. Package Drawing (dimensions in inches) 28-lead CQFP Table 9. Ordering Information Order Code 94302-01 94302-11 94302-00 Part Marking 94302 94302 PE94302-EK Description PE94302-28CQFP-50B Engineering Samples PE94302-28CQFP-50B Production Units PE94302 Evaluation Kit Package 28-lead CQFP 28-lead CQFP Evaluation Board Shipping Method 25 Count Trays 25 Count Trays 1 / Box Document No. 70/0186-02 │ www.psemi.com ©2005-2007 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 6 PE94302 Advance Information Sales Offices The Americas Peregrine Semiconductor Corporation 9450 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Space and Defense Products Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). ©2005-2007 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 6 Document No. 70/0186-02 │ U ltraCMOS™ RFIC Solutions