HEF4008BD

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4008B MSI 4-bit binary full adder Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-bit binary full adder DESCRIPTION The HEF4008B is a 4-bit binary full adder with two 4-bit data inputs (A0 to A3, B0 to B3), a carry input (CIN), four sum outputs (S0 to S3), and a carry output (COUT). The IC uses full look-ahead across 4-bits to generate COUT. This minimizes the necessity for extensive look-ahead and carry-cascading circuits. HEF4008B MSI Fig.2 Pinning diagram. PINNING A0 to A3 B0 to B3 S0 to S3 CIN COUT data inputs data inputs sum outputs carry input carry output TRUTH TABLE (one adder) CIN L L L L H Fig.1 Functional diagram. H H H HEF4008BP(N): HEF4008BD(F): HEF4008BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI See Family Specifications A L L H H L L H H B L H L H L H L H COUT L L L H L H H H S L H H L H L L H January 1995 2 Philips Semiconductors Product specification 4-bit binary full adder HEF4008B MSI Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification 4-bit binary full adder AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays sum in → sum out HIGH to LOW 5 10 15 5 LOW to HIGH sum in → COUT HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CIN → sum out HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CIN → COUT HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 150 55 40 135 55 40 125 50 35 100 45 30 130 50 35 115 50 35 90 35 25 75 35 25 60 30 20 60 30 20 300 ns 110 ns 80 ns 270 ns 110 ns 80 ns 250 ns 100 ns 70 ns 200 ns 90 ns 60 ns 260 ns 100 ns 70 ns 230 ns 100 ns 70 ns 180 ns 70 ns 50 ns 150 ns 70 ns 50 ns 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns SYMBOL MIN. TYP. MAX. HEF4008B MSI TYPICAL EXTRAPOLATION FORMULA 123 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 108 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 98 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 103 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 88 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 63 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 48 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL January 1995 4 Philips Semiconductors Product specification 4-bit binary full adder HEF4008B MSI VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 1 500 fi + ∑ (foCL) × VDD2 6 000 fi + ∑ (foCL) × 13 500 fi + ∑ (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) APPLICATION INFORMATION Fig.4 Example of a 16-bit full adder using 4 HEF4008B ICs. January 1995 5