HN58V65AT-10

HN58V65A Series HN58V66A Series 64 k EEPROM (8-kword × 8-bit) Ready/Busy Function, RES Function (HN58V66A) REJ03C0149-0300Z (Previous ADE-203-539B (Z) Rev. 2.0) Rev. 3.00 Dec. 04. 2003 Description Renesas Technology's HN58V65A series and HN58V66A series are a electrically erasable and programmable EEPROM’s organized as 8192-word × 8-bit. They have realized high speed, low power consumption and high relisbility by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster. Features • Single supply: 2.7 to 5.5 V • Access time:   100 ns (max) at 2.7 V ≤ VCC < 4.5 V 70 ns (max) at 4.5 V ≤ VCC ≤ 5.5 V • Power dissipation: • Active: 20 mW/MHz (typ) • Standby: 110 µW (max) • On-chip latches: address, data, CE, OE, WE • Automatic byte write: 10 ms (max) • Automatic page write (64 bytes): 10 ms (max) • Ready/Busy • Data polling and Toggle bit • Data protection circuit on power on/off • Conforms to JEDEC byte-wide standard • Reliable CMOS with MNOS cell technology Rev.3.00, Dec. 04.2003, page 1 of 26 HN58V65A Series, HN58V66A Series Features (cont) • 10 erase/write cycles (in page mode) 5 • 10 years data retention • Software data protection • Write protection by RES pin (only the HN58V66A series) • Industrial versions (Temperatur range: −20 to 85°C and −40 to 85°C) are also available. • There are also lead free products. Ordering Information Access time Type No. HN58V65AP-10 HN58V66AP-10 HN58V65AFP-10 HN58V66AFP-10 HN58V65AT-10 HN58V66AT-10 HN58V65AP-10E HN58V66AP-10E HN58V65AFP-10E HN58V66AFP-10E HN58V65AT-10E HN58V66AT-10E 2.7 V ≤ VCC < 4.5 V 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 4.5 V ≤ VCC ≤ 5.5 V 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 600 mil 28-pin plastic DIP (DP-28V) Lead free 400 mil 28-pin plastic SOP (FP-28DV) Lead free 28-pin plastic TSOP(TFP-28DBV) Lead free 28-pin plastic TSOP(TFP-28DB) 400 mil 28-pin plastic SOP (FP-28D) Package 600 mil 28-pin plastic DIP (DP-28) Rev.3.00, Dec. 04.2003, page 2 of 26 HN58V65A Series, HN58V66A Series Pin Arrangement HN58V65AP Series HN58V65AFP Series RDY/Busy A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC RDY/Busy A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS HN58V66AP Series HN58V66AFP Series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 WE RES A8 A9 A11 OE A10 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 CE I/O7 I/O6 I/O5 I/O4 I/O3 (Top view) (Top view) Rev.3.00, Dec. 04.2003, page 3 of 26 HN58V65A Series, HN58V66A Series Pin Arrangement (cont) HN58V65AT Series A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 RDY/Busy VCC WE OE CE NC A8 A9 A11 (Top view) HN58V66AT Series A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 RDY/Busy VCC WE RES A8 A9 A11 CE OE (Top view) Rev.3.00, Dec. 04.2003, page 4 of 26 HN58V65A Series, HN58V66A Series Pin Description Pin name A0 to A12 I/O0 to I/O7 OE CE WE VCC VSS RDY/Busy RES* NC Note: 1 Function Address input Data input/output Output enable Chip enable Write enable Power supply Ground Ready busy Reset No connection 1. This function is supported by only the HN58V66A series. Block Diagram Note: 1. This function is supported by only the HN58V66A series. VCC VSS I/O0to High voltage generator I/O7 RDY/Busy RES *1 OE CE WE RES *1 A0 to I/O buffer and input latch Control logic and timing Y decoder Y gating A5 Address buffer and latch A6 to X decoder Memory array A12 Data latch Rev.3.00, Dec. 04.2003, page 5 of 26 HN58V65A Series, HN58V66A Series Operation Table Operation Read Standby Write Deselect Write Inhibit Data Polling Program reset CE CE VIL VIH VIL VIL × × VIL × OE OE VIL ×* 2 WE WE VIH × VIL VIH VIH × VIH × RES RES* VH* × VH VH × × VH VIL 1 3 RDY/Busy High-Z High-Z High-Z to VOL High-Z   VOL High-Z I/O Dout High-Z Din High-Z   Dout (I/O7) High-Z VIH VIH × VIL VIL × Notes: 1. Refer to the recommended DC operating conditions. 2. × : Don’t care 3. This function supported by only the HN58V66A series. Absolute Maximum Ratings Parameter Power supply voltage relative to VSS Input voltage relative to VSS Operating temperature range * Storage temperature range 2 Symbol VCC Vin Topr Tstg Value −0.6 to +7.0 −0.5* to +7.0* 1 3 Unit V V °C °C 0 to +70 −55 to +125 Notes: 1. Vin min : −3.0 V for pulse width ≤ 50 ns. 2. Including electrical characteristics and data retention. 3. Should not exceed VCC + 1 V. Recommended DC Operating Conditions Parameter Supply voltage Input voltage Symbol VCC VSS VIL VIH VH* Operating temperature Notes: 1. 2. 3. 4. 5. 4 Min 2.7 0 −0.3* 1.9* 0 2 1 Typ  0     Max 5.5 0 0.6* 5 3 Unit V V V V V °C VCC + 0.3* VCC + 1.0 +70 VCC −0.5 Topr VIL min: −1.0 V for pulse width ≤ 50 ns. VIH = 2.2 V for VCC = 3.6 to 5.5 V. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns. This function is supported by only the HN58V66A series. VIL = 0.8 V for VCC = 3.6 V to 5.5 V Rev.3.00, Dec. 04.2003, page 6 of 26 HN58V65A Series, HN58V66A Series DC Characteristics (Ta = 0 to + 70°C, VCC = 2.7 to 5.5 V) Parameter Input leakage current Output leakage current Standby VCC curren Operating VCC current Symbol ILI ILO ICC1 ICC2 ICC3 Min         Output low voltage Output high voltage Note: VOL VOH  Typ   1 to 2       Max 2* 2 5 1 6 8 12 25 0.4  1 Unit µA µA µA mA mA mA mA mA V V Test conditions Vin = 0 V to VCC Vout = 0 V to VCC CE = VCC – 0.3 V to VCC + 1.0 V CE = VIH Iout = 0 mA, Duty = 100%, Cycle = 1 µs, VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 1 µs, VCC = 5.5 V Iout = 0 mA, Duty = 100%, Cycle = 100 ns, VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 70 ns, VCC = 5.5 V IOL = 2.1 mA IOH = –400 µA VCC × 0.8  1. ILI on RES : 100 µA max (only the HN58V66A series) Capacitance (Ta = +25°C, f = 1 MHz) Parameter Input capacitance Output capacitance Note: Symbol Cin* 1 1 Min   Typ   Max 6 12 Unit pF pF Test conditions Vin = 0 V Vout = 0 V Cout* 1. This parameter is sampled and not 100% tested. Rev.3.00, Dec. 04.2003, page 7 of 26 HN58V65A Series, HN58V66A Series AC Characteristics (Ta = 0 to + 70°C, VCC = 2.7 to 5.5 V) Test Conditions • Input pulse levels : 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V) 2 0 V to VCC (RES pin* ) • Input rise and fall time : ≤ 5 ns • Input timing reference levels : 0.8, 1.8 V • Output load : 1TTL Gate +100 pF • Output reference levels : 1.5 V, 1.5 V Read Cycle 1 (2.7 V ≤ VCC < 4.5 V) HN58V65A/HN58V66A -10 Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float* RES low to output float* RES to output delay* 2 1, 2 1 Symbol tACC tCE tOE tOH tDF tDFR tRR Min   10 0 0 0 0 Max 100 100 50  40 350 450 Unit ns ns ns ns ns ns ns Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE= VIL, WE = VIH Rev.3.00, Dec. 04.2003, page 8 of 26 HN58V65A Series, HN58V66A Series Write Cycle 1 (2.7 V ≤ VCC < 4.5 V) Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time* Reset high time* 2, 6 2 Symbol tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW tRP tRES Min* 0 50 0 0 0 0 0 0 50 0 200 200 100 0.3 100 — 120 0* 1 5 3 Typ                     Max              30  10*     4 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs ms ns ns µs µs Test conditions 100 Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58V66A series. 3. Use this device in longer cycle than this value. 4. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used. 6. This parameter is sampled and not 100% tested. 7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of WE. 8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of CE. 9. See AC read characteristics. Rev.3.00, Dec. 04.2003, page 9 of 26 HN58V65A Series, HN58V66A Series Read Cycle 2 (4.5 V ≤ VCC ≤ 5.5 V) HN58V65A/HN58V66A -10 Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float* RES low to output float* RES to output delay* 2 1, 2 1 Symbol tACC tCE tOE tOH tDF tDFR tRR Min   10 0 0 0 0 Max 70 70 40  30 350 450 Unit ns ns ns ns ns ns ns Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE= VIL, WE = VIH Rev.3.00, Dec. 04.2003, page 10 of 26 HN58V65A Series, HN58V66A Series Write Cycle 2 (4.5 V ≤ VCC ≤ 5.5 V) Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time* Reset high time* 2, 6 2 Symbol tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW tRP tRES Min* 0 50 0 0 0 0 0 0 50 0 100 100 50 0.2 100 — 120 0* 1 5 3 Typ                     Max              30  10*     4 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs ms ns ns µs µs Test conditions 100 Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58V66A series. 3. Use this device in longer cycle than this value. 4. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used. 6. This parameter is sampled and not 100% tested. 7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of WE. 8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of CE. 9. See AC read characteristics. Rev.3.00, Dec. 04.2003, page 11 of 26 HN58V65A Series, HN58V66A Series Timing Waveforms Read Timing Waveform Address tACC CE tCE tOH OE tOE tDF WE Data Out High Data out valid tRR tDFR RES *2 Rev.3.00, Dec. 04.2003, page 12 of 26 HN58V65A Series, HN58V66A Series Byte Write Timing Waveform(1) (WE Controlled) tWC Address tCS tAH tCH CE tAS tWP tOES tBL WE tOEH OE tDS Din tDW RDY/Busy High-Z tRP tDB High-Z tDH tRES RES *2 VCC Rev.3.00, Dec. 04.2003, page 13 of 26 HN58V65A Series, HN58V66A Series Byte Write Timing Waveform(2) (CE Controlled) Address tWS tAH tCW tAS tWH tBL tWC CE WE tOES tOEH OE tDS Din tDW RDY/Busy High-Z tRP tRES tDB High-Z tDH RES *2 VCC Rev.3.00, Dec. 04.2003, page 14 of 26 HN58V65A Series, HN58V66A Series Page Write Timing Waveform(1) (WE Controlled) *7 Address A0 to A12 tAS tAH tWP tDL tBLC tBL WE tCS tCH tWC CE tOES tOEH tDH tDS OE Din RDY/Busy High-Z tDB tDW High-Z tRP RES *2 VCC tRES Rev.3.00, Dec. 04.2003, page 15 of 26 HN58V65A Series, HN58V66A Series Page Write Timing Waveform(2) (CE Controlled) *8 Address A0 to A12 tAS tAH tCW tDL tBLC CE tWS tBL tWH tWC WE tOEH tOES OE Din tDH tDS RDY/Busy High-Z tDB tDW High-Z tRP RES *2 VCC tRES Rev.3.00, Dec. 04.2003, page 16 of 26 HN58V65A Series, HN58V66A Series Data Data Polling Timing Waveform Address An An An CE WE OE tOE*9 I/O7 Din X Dout X Dout X tWC tDW tCE *9 tOEH tOES Rev.3.00, Dec. 04.2003, page 17 of 26 HN58V65A Series, HN58V66A Series Toggle Bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Toggle Bit Waveform Notes: 1. I/O6 begining state is “1”. 2. I/O6 ending state will vary. 3. See AC read characteristics. 4. Any address location can be used, but the address must be fixed. Next mode *4 Address CE WE OE tOEH tCE *3 tOE *3 tOES *1 *2 *2 I/O6 Din Dout Dout tWC Dout Dout tDW Rev.3.00, Dec. 04.2003, page 18 of 26 HN58V65A Series, HN58V66A Series Software Data Protection Timing Waveform(1) (in protection mode) VCC +9tBLC Address Data 1555 AA 0AAA 55 1555 A0 Write address Write data tWC Software Data Protection Timing Waveform(2) (in non-protection mode) VCC tWC Normal active mode +9Address Data 1555 0AAA 1555 1555 0AAA 1555 AA 55 80 AA 55 20 Rev.3.00, Dec. 04.2003, page 19 of 26 HN58V65A Series, HN58V66A Series Functional Description Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Data Polling Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Signal RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance. RES RES Signal (only the HN58V66A series) When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn’t provide a latch function. VCC Read inhibit Read inhibit 4-5 Program inhibit Program inhibit Rev.3.00, Dec. 04.2003, page 20 of 26 HN58V65A Series, HN58V66A Series WE CE WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 10 cycles in case of the page programming and 10 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is 4 page-programmed less than 10 cycles. Data Protection To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 15 ns or less. 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. Be careful not to allow noise of a width of more than 15 ns on the control pins. 5 4 WE CE VIH 0V OE VIH 0V 15 ns max Rev.3.00, Dec. 04.2003, page 21 of 26 HN58V65A Series, HN58V66A Series 2. Data protection at VCC on/off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET signal. VCC CPU RESET * Unprogrammable * Unprogrammable 2.1 Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below. CE OE WE ×: Don’t care. VCC: Pull-up to VCC level. VSS: Pull-down to VSS level. VCC × × × VSS × × × VCC 2.2 Protection by RES (only the HN58V66A series) The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s RES pin. RES should be kept VSS level during VCC on/off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn’t finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input. VCC 4-5 Program inhibit Program inhibit 9or +- 1 µs min 100 µs min 10 ms min Rev.3.00, Dec. 04.2003, page 22 of 26 HN58V65A Series, HN58V66A Series 3. Software data protection To prevent unintentional programming caused by noise generated by external circuits, this device has the software data protection function. In software data protection mode, 3 bytes of data must be input before write data as follows. And these bytes can switch the non-protection mode to the protection mode. SDP is enabled if only the 3 bytes code is input. Address Data 1555 AA ↓ ↓ 0AAA 55 ↓ ↓ 1555 A0 ↓ ↓ Write address Write data } Normal data input Software data protection mode can be cancelled by inputting the following 6 bytes. After that, this device turns to the non-protection mode and can write data normally. But when the data is input in the cancelling cycle, the data cannot be written. Address 1555 ↓ 0AAA ↓ 1555 ↓ 1555 ↓ 0AAA ↓ 1555 Data AA ↓ 55 ↓ 80 ↓ AA ↓ 55 ↓ 20 The software data protection is not enabled at the shipment. Note: There are some differences between Renesas Technology’s and other company’s for enable/disable sequence of software data protection. If there are any questions , please contact with Renesas Technology’s sales offices. Rev.3.00, Dec. 04.2003, page 23 of 26 HN58V65A Series, HN58V66A Series Package Dimensions HN58V65AP Series HN58V66AP Series (DP-28, DP-28V) Unit: mm 15 28 35.6 36.5 Max 1 1.2 1.9 Max 14 13.4 14.6 Max 0.51 Min 2.54 Min 5.70 Max 15.24 0.25 – 0.05 0˚ – 15˚ + 0.11 2.54 ± 0.25 0.48 ± 0.10 Package Code JEDEC JEITA Mass (reference value) DP-28, DP-28V — Conforms 4.6 g Rev.3.00, Dec. 04.2003, page 24 of 26 HN58V65A Series, HN58V66A Series Package Dimensions (cont) HN58V65AFP Series HN58V66AFP Series (FP-28D, FP-28DV) Unit: mm 18.3 18.8 Max 28 15 8.4 1.12 Max *0.17 ± 0.05 0.15 ± 0.04 1 14 2.50 Max 11.8 ± 0.3 1.7 0˚ – 8˚ 1.27 0.15 *0.40 ± 0.08 0.38 ± 0.06 0.20 ± 0.10 1.0 ± 0.2 0.20 M *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-28D, FP-28DV Conforms — 0.7 g Rev.3.00, Dec. 04.2003, page 25 of 26 HN58V65A Series, HN58V66A Series Package Dimensions (cont) HN58V65AT Series HN58V66AT Series (TFP-28DB, TFP-28DBV) Unit: mm 8.00 8.20 Max 28 15 1 14 0.55 *0.22 ± 0.08 0.10 M 0.20 ± 0.06 0.45 Max 11.80 13.40 ± 0.30 0˚ – 5˚ 0.80 *0.17 ± 0.05 0.15 ± 0.04 1.20 Max 0.10 0.13 –0.08 +0.07 0.50 ± 0.10 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) TFP-28DB, TFP-28DBV — — 0.23 g Rev.3.00, Dec. 04.2003, page 26 of 26 Revision History Rev. Date HN58V65A/HN58V66A Series Data Sheet Contents of Modification Page Description Initial issue Change of FP-28DA to DP-28 Addition of 5 V specification Change of page size: 32 byte to 64 byte Recommended DC Operating Conditions VCC (typ) : 0.3 V to  Addition of note 5 Change of note 2 (VIH = 2.4 V to VIH = 2.2 V) DC Characteristics ICC1 (min/typ/max): //20 µA to /1 to 2/5 µA Change of Test conditions ILI: VCC = 5.5 V, Vin = 5.5 V to Vin = 0 V to VCC ILO: VCC = 5.5 V, Vout = 5.5/0.4 V to Vout = 0 V to VCC ICC1: CE = VCC to CE = VCC –0.3 V to VCC + 1 V DC Characteristics ICC3: //10 µA to //8 µA AC Characteristic Input pules level: 0.4 V to VSS to 0 V to VSS Timing Waveform Read Timing Waveform: Correct error Functional Description Data Protection: Addition of description Change of Subtitle     6 0.0 0.1 0.2 Mar. 18. 1996 Nov. 12. 1996 Mar. 7. 1997 7 1.0 Aug. 28. 1997 7 8 12 20 2.0 3.00 Jan. 22.1998 Dec. 04. 2003   2 Change format issued by Renesas Technology Corp. Ordering Information Addition of HN58V65AP-10E, HN58V66AP-10E, HN58V65AFP-10E, HN58V66AFP-10E, HN58V65AT-10E, HN58V66AT-10E 24-26 Package Dimensions DP-28 to DP-28, DP-28V FP-28D to FP-28D, FP-28DV TFP-28DB to TFP-28DB, TFP-28DBV Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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