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ISL8487EIPZ

ISL8487EIPZ

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    DIP8

  • 描述:

    IC TRANSCEIVER HALF 1/1 8DIP

  • 数据手册
  • 价格&库存
ISL8487EIPZ 数据手册
DATASHEET ISL8487E, ISL81487L, ISL81487E FN6051 Rev.8.00 Sep 20, 2018 ±15kV ESD Protected, 1/8 Unit Load, 5V, Low Power, High Speed or Slew Rate Limited RS-485/RS-422 Transceivers The ISL8487E, ISL81487L, and ISL81487E RS-485/RS-422 devices are ESD protected, fractional unit load (UL), BiCMOS, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output/receiver input is protected against ±15kV ESD strikes without latch-up. Unlike competitive devices, this device family is specified for 10% tolerance supplies (4.5V to 5.5V). Features All devices present a 1/8 unit load to the RS-485 bus, which allows up to 256 transceivers on the network for large node count systems (for example, process automation and remote meter reading systems). In a remote utility meter reading system, individual utility meter readings (in apartments, for example) are routed to a concentrator with an RS-485 network, so the high allowed node count minimizes the number of repeaters required to network all the meters. Data for all meters is then read out from the concentrator from a single access port or a wireless link. • Slew rate limited versions for error free data transmission (ISL8487E, ISL81487L) . . . . .up to 250kbps • RS-485 I/O pin ESD protection . . . . . . . . . . . ±15kV HBM - Class 3 ESD level on all other pins . . . . . . . >7kV HBM • Fractional unit load allows up to 256 devices on the bus • Specified for 10% tolerance supplies • High data rate version (ISL81487E) . . . . . . . up to 5Mbps • Low current shutdown mode (except ISL81487E) . . . 0.5µA • Low quiescent supply current: - ISL8487E, ISL81487L . . . . . . . . . . . 145µA (maximum) - ISL81487E . . . . . . . . . . . . . . . . . . . . 420µA (maximum) • -7V to +12V common mode input voltage range • Three state Rx and Tx outputs • 30ns propagation delays, 5ns skew (ISL81487E) Slew rate limited drivers on the ISL8487E and ISL81487L reduce EMI and minimize reflections from improperly terminated transmission lines or unterminated stubs in multidrop and multipoint applications. Data rates up to 250kbps are achievable with these devices. • Half duplex pinouts • Operate from a single +5V supply (10% tolerance) • Current limiting and thermal shutdown for driver overload protection Data rates up to 5Mbps are achievable by using the ISL81487E, which features higher slew rates. • Pin compatible replacements for: MAX487E, (ISL8487E); LTC1487, ADM1487 (ISL81487L); MAX1487E, ST485ER (ISL81487E) The receiver (Rx) inputs feature a “fail-safe if open” design, which ensures a logic high Rx output if Rx inputs are floating. • Pb-free plus anneal available (RoHS compliant) The driver (Tx) outputs are short-circuit protected, even for voltages exceeding the power supply voltage. Additionally, on-chip thermal shutdown circuitry disables the Tx outputs to prevent damage if power dissipation becomes excessive. Applications • High node count networks • Automated utility meter reading systems The half duplex devices multiplex the Rx inputs and Tx outputs to allow transceivers with Rx and Tx disable functions in 8 lead packages. • Factory automation • Security networks • Building environmental control systems Related Literature • Industrial/process control networks For a full list of related documents, visit our website: • ISL8487E, ISL81487L, and ISL81487E product pages TABLE 1. SUMMARY OF FEATURES PART NUMBER HALF/FULL DUPLEX ISL8487E Half 256 0.25 Yes Yes 120 Yes 8 ISL81487L Half 256 0.25 Yes Yes 120 Yes 8 ISL81487E Half 256 5 No Yes 350 No 8 FN6051 Rev.8.00 Sep 20, 2018 NO. OF DEVICES DATA RATE ALLOWED ON BUS (Mbps) SLEW RATE LIMITED? RECEIVER/ QUIESCENT LOW POWER PIN DRIVER ENABLE? ICC (A) SHUTDOWN? COUNT Page 1 of 16 ISL8487E, ISL81487L, ISL81487E Typical Operating Circuits 9  9&& 538  52 9 Q) Q) 5% $<   5(  '(  9&&  $< 57 %=  9)6 57 538 52  5(  '(   %=  ', ',  5% *1'  *1'  To calculate the resistor values, refer to TB509. Ordering Information PART NUMBER () PART MARKING TEMP. RANGE (°C) TAPE AND REEL (UNITS) (Note 1) PACKAGE PKG. DWG. # ISL8487EIBZ 8487EIBZ -40 to +85 - 8 Ld SOIC (Pb-free) M8.15 ISL8487EIBZ-T 8487EIBZ -40 to +85 2.5k 8 Ld SOIC (Pb-free) M8.15 8487EIPZ ISL8487EIPZ (not recommended for new designs, recommended replacement ISL81487LIPZ) -40 to +85 - 8 Ld PDIP E8.3 (Pb-free, Note 4) ISL81487LIBZ 81487LIBZ -40 to +85 - 8 Ld SOIC (Pb-free) M8.15 ISL81487LIBZ-T 81487LIBZ -40 to +85 2.5k 8 Ld SOIC (Pb-free) M8.15 ISL81487LIPZ 81487LIPZ -40 to +85 - E8.3 8 Ld PDIP (Pb-free, Note 4) ISL81487EIBZ 81487EIBZ -40 to +85 - 8 Ld SOIC (Pb-free) M8.15 ISL81487EIBZ-T 81487EIBZ -40 to +85 2.5k 8 Ld SOIC (Pb-free) M8.15 ISL81487EIPZ ISL81487EIPZ -40 to +85 - 8 Ld PDIP E8.3 (Pb-free, Note 4) NOTES: 1. Refer to TB347 for details about reel specifications. 2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 3. For Moisture Sensitivity Level (MSL), see the ISL8487E, ISL81487L, and ISL81487E product information pages. For more information about MSL, see TB363. 4. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN6051 Rev.8.00 Sep 20, 2018 Page 2 of 16 ISL8487E, ISL81487L, ISL81487E Pinout PDIP, SOIC TOP VIEW RO 1 8 VCC RE 2 7 B/Z DE 3 6 A/Y 5 GND DI 4 R D Pin Descriptions PIN FUNCTION RO Receiver output. RO is high if A > B by at least 0.2V; RO is low if A < B by 0.2V or more; RO is high if A and B are unconnected (floating). RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs Y and Z are enabled by bringing DE high. They are high impedance when DE is low. DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y 15kV HBM ESD protected, RS-485/422 level, noninverting receiver input and noninverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1. B/Z 15kV HBM ESD protected, RS-485/422 level, inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1. VCC System power supply input (4.5V to 5.5V). Truth Tables TRANSMITTING RECEIVING INPUTS OUTPUTS INPUTS OUTPUT RE DE DI Z Y RE DE A-B RO X 1 1 0 1 0 X ≥ +0.2V 1 X 1 0 1 0 0 X ≤ -0.2V 0 0 0 X High-Z High-Z 0 X Inputs Open 1 1 0 X High-Z (Note 12) High-Z (Note 12) 1 X X High-Z (Note 12) 1 0 X High-Z FN6051 Rev.8.00 Sep 20, 2018 Page 3 of 16 ISL8487E, ISL81487L, ISL81487E Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltages DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) Input/Output Voltages A/Y, B/Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) Short-Circuit Duration Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . See “Electrical Specifications” Thermal Resistance (Typical, Note 5) JA (°C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170 140 8 Ld PDIP Package (Note 6) . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Temperature Range ISL8XXXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can permanently damage the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 5. JA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379 for details. 6. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. ( Electrical Specifications PARAMETER Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C, Note 7 SYMBOL TEST CONDITIONS TEMP (°C) MIN TYP MAX UNIT Full - - VCC V DC CHARACTERISTICS Driver Differential VOUT (No Load) VOD1 Driver Differential VOUT (with Load) VOD2 R = 50Ω (RS-422), (Figure 1) Full 2 3 - V R = 27Ω (RS-485), (Figure 1) Full 1.5 2.3 5 V VOD R = 27Ω or 50Ω, (Figure 1) Full - 0.01 0.2 V VOC R = 27Ω or 50Ω, (Figure 1) Full - - 3 V VOC R = 27Ω or 50Ω, (Figure 1) Full - 0.01 0.2 V VIH DE, DI, RE Full 2 - - V Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V Logic Input Current IIN1 DE, DI, RE Input Current (A/Y, B/Z), (Note 15) IIN2 DE = 0V, VCC = 4.5 to 5.5V Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Common-Mode VOUT Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States Logic Input High Voltage IIN2 Receiver Differential Threshold Voltage VTH Full -2 - 2 µA VIN = 12V Full - - 140 µA VIN = -7V Full - - -120 µA VIN = 12V Full - - 180 µA VIN = -7V Full - - -100 µA -7V  VCM  12V Full -0.2 - 0.2 V - mV DE = 0V, VCC = 0V Receiver Input Hysteresis VTH VCM = 0V 25 - 70 Receiver Output High Voltage VOH IO = -4mA, VID = 200mV Full 3.5 - - V Receiver Output Low Voltage VOL IO = -4mA, VID = 200mV Full - - 0.4 V Three-State (High Impedance) Receiver Output Current IOZR 0.4V  VO  2.4V Full - - 1 µA Receiver Input Resistance RIN -7V  VCM  12V Full 96 - - kΩ FN6051 Rev.8.00 Sep 20, 2018 Page 4 of 16 ISL8487E, ISL81487L, ISL81487E Electrical Specifications PARAMETER No-Load Supply Current, (Note 8) Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C, Note 7 (Continued) SYMBOL ICC TEST CONDITIONS ISL81487E, DI, RE = 0V DE = VCC or VCC DE = 0V ISL8487E, ISL81487L, DI, RE = 0V or VCC TEMP (°C) MIN TYP MAX UNIT Full - 400 500 µA Full - 350 420 µA DE = VCC Full - 160 200 µA DE = 0V Full - 120 145 µA Shutdown Supply Current ISHDN (Note 12), DE = 0V, RE = VCC, DI = 0V or VCC Full - 0.5 8 µA Driver Short-Circuit Current, VO = High or Low IOSD1 DE = VCC, -7V  VY or VZ  12V, (Note 9) Full 35 - 250 mA Receiver Short-Circuit Current IOSR 0V  VO  VCC Full 7 - 85 mA tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 15 24 50 ns tSKEW RDIFF = 54Ω, CL = 100pF, (Figure 2) Full - 3 10 ns tR, tF RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 3 12 25 ns tZH CL = 100pF, SW = GND, (Figure 2) Full - 14 70 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC, (Figure 2) Full - 14 70 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure 2) Full - 44 70 ns Driver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure 2) Full - 21 70 ns Receiver Input to Output Delay tPLH, tPHL (Figure 4) Full 30 90 150 ns tSKD SWITCHING CHARACTERISTICS (ISL81487E) Driver Input to Output Delay Driver Output Skew Driver Differential Rise or Fall Time Driver Enable to Output High Receiver Skew | tPLH - tPHL | (Figure 4) 25 - 5 - ns Receiver Enable to Output High tZH CL = 15pF, SW = GND, (Figure 5) Full - 9 50 ns Receiver Enable to Output Low tZL CL = 15pF, SW = VCC, (Figure 5) Full - 9 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure 5) Full - 9 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure 5) Full - 9 50 ns Full 5 - - Mbps Maximum Data Rate fMAX SWITCHING CHARACTERISTICS (ISL8487E) Driver Input to Output Delay Driver Output Skew Driver Differential Rise or Fall Time tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 250 650 2000 ns tSKEW RDIFF = 54Ω, CL = 100pF, (Figure 2) Full - 160 800 ns tR, tF RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 250 900 2000 ns Driver Enable to Output High tZH CL = 100pF, SW = GND, (Figure 3, Note 10) Full 250 1000 2000 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC, (Figure 3, Note 10) Full 250 860 2000 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure 3) Full 300 660 3000 ns Driver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure 3) Full 300 640 3000 ns Receiver Input to Output Delay tPLH, tPHL (Figure 4) Full 250 500 2000 ns tSKD (Figure 4) 25 - 60 - ns Receiver Skew | tPLH - tPHL | Receiver Enable to Output High tZH CL = 15pF, SW = GND, (Figure 5, Note 11) Full - 10 50 ns Receiver Enable to Output Low tZL CL = 15pF, SW = VCC, (Figure 5, Note 11) Full - 10 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure 5) Full - 10 50 ns tLZ CL = 15pF, SW = VCC, (Figure 5) Full - 10 50 ns Full 250 - - kbps (Note 12) Full 50 120 600 ns Receiver Disable from Output Low Maximum Data Rate Time to Shutdown fMAX tSHDN Driver Enable from Shutdown to Output High tZH(SHDN) CL = 100pF, SW = GND, (Figure 3, Notes 12 and 13) Full - 1000 2000 ns Driver Enable from Shutdown to Output Low tZL(SHDN) CL = 100pF, SW = VCC, (Figure 3, Notes 12 and 13) Full - 1000 2000 ns FN6051 Rev.8.00 Sep 20, 2018 Page 5 of 16 ISL8487E, ISL81487L, ISL81487E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C, Note 7 (Continued) TEMP (°C) MIN TYP MAX UNIT CL = 15pF, SW = GND, (Figure 5, Notes 12 and 14) Full - 800 2500 ns CL = 15pF, SW = VCC, (Figure 5, Notes 12 and 14) Full - 800 2500 ns tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 150 650 1200 ns tSKEW RDIFF = 54Ω, CL = 100pF, (Figure 2) Full - 160 600 ns tR, tF RDIFF = 54Ω, CL = 100pF, (Figure 2) Full 250 900 1200 ns PARAMETER SYMBOL TEST CONDITIONS Receiver Enable from Shutdown to Output High tZH(SHDN) Receiver Enable from Shutdown to Output Low tZL(SHDN) SWITCHING CHARACTERISTICS (ISL81487L) Driver Input to Output Delay Driver Output Skew Driver Differential Rise or Fall Time Driver Enable to Output High tZH CL = 100pF, SW = GND, (Figure 3, Note 10) Full 100 1000 1500 ns Driver Enable to Output Low tZL CL = 100pF, SW = VCC, (Figure 3, Note 10) Full 100 1000 1500 ns Driver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure 3) Full 150 750 1500 ns Driver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure 3) Full 150 750 1500 ns Receiver Input to Output Delay tPLH, tPHL (Figure 4) Full 30 175 250 ns tSKD Receiver Skew | tPLH - tPHL | (Figure 4) 25 - 13 - ns Receiver Enable to Output High tZH CL = 15pF, SW = GND, (Figure 5, Note 11) Full - 10 50 ns Receiver Enable to Output Low tZL CL = 15pF, SW = VCC, (Figure 5, Note 11) Full - 10 50 ns Receiver Disable from Output High tHZ CL = 15pF, SW = GND, (Figure 5) Full - 10 50 ns Receiver Disable from Output Low tLZ CL = 15pF, SW = VCC, (Figure 5) Full - 10 50 ns Full 250 - - kbps Maximum Data Rate Time to Shutdown fMAX tSHDN (Note 12) Full 50 140 600 ns Driver Enable from Shutdown to Output High tZH(SHDN) CL = 100pF, SW = GND, (Figure 3, Notes 12 and 13) Full - 1100 2000 ns Driver Enable from Shutdown to Output Low tZL(SHDN) CL = 100pF, SW = VCC, (Figure 3, Notes 12 and 13) Full - 1000 2000 ns Receiver Enable from Shutdown to Output High tZH(SHDN) CL = 15pF, SW = GND, (Figure 3, Notes 12 and 14) Full - 900 2000 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) CL = 15pF, SW = VCC, (Figure 3, Notes 12 and 14) Full - 900 2000 ns Human Body Model 25 - 15 - kV 25 - >7 - kV ESD PERFORMANCE RS-485 Pins (A/Y, B/Z) All Other Pins NOTES: 7. Currents into device pins are positive; currents out of device pins are negative. Voltages are referenced to ground unless otherwise specified. 8. Supply current specification is valid for loaded drivers when DE = 0V. 9. Applies to peak current. See “Typical Performance Curves” for more information. 10. When testing the ISL8487E and ISL81487L, keep RE = 0 to prevent the device from entering shutdown (SHDN). 11. When testing the ISL8487E and ISL81487L, the RE signal high time must be short enough (typically 600ns to ensure that the device enters SHDN. 14. Set the RE signal high time >600ns to ensure that the device enters SHDN. 15. Devices meeting these limits are denoted as 1/8 unit load (1/8 UL) transceivers. The RS-485 standard allows up to 32 UL on the bus, so there can be 256 1/8 UL devices on a bus. FN6051 Rev.8.00 Sep 20, 2018 Page 6 of 16 ISL8487E, ISL81487L, ISL81487E Test Circuits and Waveforms VCC R DE DI Z VOD D Y R VOC FIGURE 1. DRIVER VOD AND VOC 3V DI 1.5V 1.5V 0V tPHL tPLH VOH 50% OUT (Y) 50% VOL tPHL tPLH VOH VCC CL = 100pF DE OUT (Z) 50% 50% VOL Z DI RDIFF D Y SIGNAL GENERATOR CL = 100pF 90% DIFF OUT (Y - Z) 10% tR +VOD 90% 10% -VOD tF SKEW = |tPLH (Y or Z) - tPHL (Z or Y)| FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES FN6051 Rev.8.00 Sep 20, 2018 Page 7 of 16 ISL8487E, ISL81487L, ISL81487E Test Circuits and Waveforms (Continued) DE Z DI 500 VCC D SIGNAL GENERATOR GND SW Y CL 3V (SHDN) for ISL8487E and ISL81487L only. PARAMETER OUTPUT tHZ RE DI SW CL (pF) X 1/0 GND 15 Y/Z tLZ Y/Z tZH Y/Z 0 (Note 10) tZL Y/Z tZH(SHDN) Y/Z tZLSHDN) X Y/Z 0/1 VCC 15 1/0 GND 100 0 (Note 10) 0/1 VCC 100 1 (Note 12) 1/0 GND 100 1 (Note 12) 0/1 DE 1.5V NOTE 7 1.5V 0V tZH, tZH(SHDN) VOH - 0.5V OUT (Y, Z) 100 VCC tHZ OUTPUT HIGH NOTE 7 VOH 2.3V 0V tZL, tZL(SHDN) tLZ NOTE 7 VCC OUT (Y, Z) 2.3V VOL + 0.5V V OL OUTPUT LOW FIGURE 3B. MEASUREMENT POINTS FIGURE 3A. TEST CIRCUIT FIGURE 3. DRIVER ENABLE AND DISABLE TIMES RE +1.5V 3V 15pF B R A A RO 1.5V 1.5V 0V tPLH tPHL VCC SIGNAL GENERATOR 50% RO 50% 0V FIGURE 4A. TEST CIRCUIT FIGURE 4B. MEASUREMENT POINTS FIGURE 4. RECEIVER PROPAGATION DELAY RE B R SIGNAL GENERATOR 1k RO VCC SW A NOTE 7 3V GND 15pF RE 1.5V 1.5V 0V tZH, tZH(SHDN) (SHDN) for ISL8487E and ISL81487L only. PARAMETER DE A SW tHZ 0 +1.5V GND tLZ 0 -1.5V VCC tZH (Note 11) 0 +1.5V GND tZL (Note 11) 0 -1.5V VCC tZH(SHDN) (Note 12) 0 +1.5V GND tZL(SHDN) (Note 12) 0 -1.5V VCC FIGURE 5A. TEST CIRCUIT OUTPUT HIGH NOTE 7 tHZ VOH - 0.5V RO VOH 1.5V 0V tZL, tZL(SHDN) tLZ NOTE 7 VCC RO 1.5V OUTPUT LOW VOL + 0.5V V OL FIGURE 5B. MEASUREMENT POINTS FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES FN6051 Rev.8.00 Sep 20, 2018 Page 8 of 16 ISL8487E, ISL81487L, ISL81487E Application Information RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard that allows only one driver and up to 10 receivers on each bus (assuming one unit load devices). RS-485 is a true multipoint standard that allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 specification requires that drivers handle bus contention without sustaining any damage. An important advantage of RS-485 is the extended Common-Mode Range (CMR), which specifies that the driver outputs and receiver inputs withstand signals ranging from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000ft, so the wide CMR is necessary to handle ground potential differences and voltages induced in the cable by external fields. Receiver Features These devices use a differential input receiver for maximum noise immunity and common-mode rejection. Input sensitivity is 200mV, as required by the RS-422 and RS-485 specifications. The receiver input resistance of 96kΩ surpasses the RS-422 specification of 4kΩ and is eight times the RS-485 Unit Load (UL) requirement of 12kΩ minimum. Thus, these products are known as one-eighth UL transceivers. A network can host up to 256 of these devices still complying with the RS-485 loading specification. maximum data rate on these slew rate limited versions is 250kbps. The ISL81487E drivers are not limited, so faster output transition times allow data rates of at least 5Mbps. Data Rate, Cables, and Terminations RS-485/422 are intended for network lengths up to 4000ft, but the maximum system data rate decreases as the transmission length increases. Devices operating at 5Mbps are limited to lengths less than a few hundred feet, while the 250kbps versions can operate at full data rates with lengths in excess of 1000ft. Twisted pair cable is the cable of choice for RS-485/422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common-mode signals that are effectively rejected by the differential receivers in these ICs. Proper termination is imperative to minimize reflections when using the 5Mbps device. Short networks using the 250kbps versions do not need to be terminated, but terminations are recommended unless power dissipation is an overriding concern. In point-to-point or point-to-multipoint (single driver on bus) networks, terminate the main cable in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, keep stubs connecting receivers to the main cable as short as possible. In multipoint (multi-driver) systems, terminate the main cable in its characteristic impedance at both ends. Keep stubs connecting a transceiver to the main cable as short as possible. Built-In Driver Overload Protection The receiver inputs function with common-mode voltages as great as 7V outside the power supplies (that is, +12V and -7V), making them ideal for long networks in which induced voltages are a realistic concern. The RS-485 specification requires that drivers survive worst case bus contentions undamaged. These devices meet this requirement with driver output short-circuit current limits and on-chip thermal shutdown circuitry. All the receivers include a “fail-safe if open” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating). The driver output stages incorporate short-circuit current limiting circuitry that ensures the output current never exceeds the RS-485 specification, even at the common-mode voltage range extremes. These devices also use a foldback circuit that reduces the short-circuit current and as a result, the power dissipation when the contending voltage exceeds either supply. Receivers easily meet the data rates supported by the corresponding driver. The receiver outputs are three-statable using the active low RE input. Driver Features The RS-485/422 driver is a differential output device that delivers at least 1.5V across a 54Ω load (RS-485) and at least 2V across a 100Ω load (RS-422). The drivers feature low propagation delay skew to maximize bit width and to minimize EMI. Driver outputs are three-statable using the active high DE input. In the event of a major short-circuit condition, the thermal shutdown feature disables the drivers when the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about 15°C. If the condition persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. The ISL8487E and ISL81487L driver outputs are slew rate limited to minimize EMI and to minimize reflections in unterminated or improperly terminated networks. The FN6051 Rev.8.00 Sep 20, 2018 Page 9 of 16 ISL8487E, ISL81487L, ISL81487E Low Power Shutdown Mode (Excluding ISL81487E) These CMOS transceivers all use a fraction of the power required by their bipolar counterparts, but the ISL8487E and ISL81487L include a shutdown feature that reduces the already low quiescent ICC to a 500nA trickle. They enter shutdown whenever the receiver and driver are simultaneously disabled (RE = VCC and DE = GND) for a period of at least 600ns. Disabling both the driver and the receiver for less than 50ns guarantees that shutdown is not entered. Note that receiver and driver enable times increase when enabling from shutdown. Refer to Note 10 through 14 at the end of the “Electrical Specifications” table for more information. ESD Protection All pins on the interface devices include Class 3 Human Body Model (HBM) ESD protection structures, but the RS-485 pins (driver outputs and receiver inputs) incorporate advanced structures allowing them to survive ESD events in excess of 15kV HBM. The RS-485 pins are particularly vulnerable to Human Body Model Testing This test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge stored on a 100pF capacitor through a 1.5k current limiting resistor into the pin under test. The HBM method determines an IC’s ability to withstand the ESD events typically present during handling and manufacturing. The RS-485 pin survivability on this high ESD family has been characterized to be in excess of 15kV for discharges to GND. VCC = 5V, TA = +25°C, ISL8487E, ISL81487L, and ISL81487E; unless otherwise specified 90 3.6 80 3.4 DIFFERENTIAL OUTPUT VOLTAGE (V) DRIVER OUTPUT CURRENT (mA) Typical Performance Curves ESD damage because they typically connect to an exposed port on the exterior of the finished product. Touching the port pins or connecting a cable can cause an ESD event that destroys unprotected ICs. The ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and without degrading the RS-485 common-mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection structures (for example, transient suppression diodes), and the associated undesirable capacitive load they present. 70 60 50 40 30 20 10 0 0 1 2 3 4 DIFFERENTIAL OUTPUT VOLTAGE (V) FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE FN6051 Rev.8.00 Sep 20, 2018 5 3.2 RDIFF = 100Ω 3 2.8 2.6 2.4 RDIFF = 54Ω 2.2 2 -40 -25 0 50 25 75 TEMPERATURE (°C) FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE Page 10 of 16 85 ISL8487E, ISL81487L, ISL81487E Typical Performance Curves VCC = 5V, TA = +25°C, ISL8487E, ISL81487L, and ISL81487E; unless otherwise specified 400 160 ISL81487E, DE = VCC, RE = X 140 ISL81487E 120 ISL81487E, DE = GND, RE = X 80 ISL8487E, ISL81487L 300 60 40 ICC (µA) OUTPUT CURRENT (mA) 350 Y OR Z = LOW 100 20 0 -20 200 Y OR Z = HIGH -40 250 ISL8487E, ISL81487L, DE = VCC, RE = X -60 ISL81487E -80 ISL8487E, ISL81487L -100 150 -120 100 -40 -7 -6 -4 -2 ISL8487E, ISL81487L, DE = GND, RE = GND 0 2 4 6 OUTPUT VOLTAGE (V) 8 10 12 FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT-CIRCUIT VOLTAGE 0 25 TEMPERATURE (°C) 50 75 FIGURE 9. SUPPLY CURRENT vs TEMPERATURE 250 750 700 200 tPLHY tPLHZ 650 |tPLHY - tPHLZ| 150 600 SKEW (ns) PROPAGATION DELAY (ns) -25 tPHLY 550 tPHLZ 50 500 450 -40 |tPHLY - tPLHZ| 100 |CROSS PT. OF Y & Z - CROSS PT. OF Y & Z| -25 0 25 TEMPERATURE (°C) 50 75 0 -40 85 -25 0 25 TEMPERATURE (°C) 50 75 85 FIGURE 11. DRIVER SKEW vs TEMPERATURE (ISL8487E and ISL81487L) FIGURE 10. DRIVER PROPAGATION DELAY vs TEMPERATURE (ISL8487E and ISL81487L) 30 5 4 |tPHLY - tPLHZ| 26 3 24 22 20 SKEW (ns) PROPAGATION DELAY (ns) 28 tPLHY tPHLZ tPLHZ |tPLHY - tPHLZ| 2 1 18 |CROSSING PT. OF Y & Z - CROSSING PT. OF Y & Z| tPHLY 16 -40 -25 0 25 50 TEMPERATURE (°C) FIGURE 12. DRIVER PROPAGATION DELAY vs TEMPERATURE (ISL81487E) FN6051 Rev.8.00 Sep 20, 2018 75 85 0 -40 -25 0 50 25 75 TEMPERATURE (°C) FIGURE 13. DRIVER SKEW vs TEMPERATURE (ISL81487E) Page 11 of 16 85 ISL8487E, ISL81487L, ISL81487E RO 0 ISL81487L 5 RO 0 ISL8487E 4 3 2 B/Z A/Y 1 0 5 RO 0 5 RO 0 3 2 DRIVER OUTPUT (V) 4 RECEIVER OUTPUT (V) 5 DRIVER INPUT (V) RECEIVER OUTPUT (V) DRIVER OUTPUT (V) RO 0 B/Z A/Y 1 0 TIME (20ns/DIV) FIGURE 16. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL81487E) ISL8487E 3 2 A/Y B/Z 1 0 TIME (400ns/DIV) 0 5 ISL81487L FIGURE 15. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL8487E and ISL81487L) FIGURE 14. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL8487E and ISL81487L) DI RDIFF = 54Ω, CL = 100pF DI 5 0 5 RO 0 4 3 2 A/Y B/Z 1 0 TIME (20ns/DIV) FIGURE 17. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL81487E) Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 518 PROCESS: Si Gate CMOS FN6051 Rev.8.00 Sep 20, 2018 0 4 TIME (400ns/DIV) RDIFF = 54Ω, CL = 100pF 5 DRIVER INPUT (V) 5 0 RDIFF = 54Ω, CL = 100pF DI Page 12 of 16 DRIVER INPUT (V) RDIFF = 54Ω, CL = 100pF DRIVER INPUT (V) 5 DI RECEIVER OUTPUT (V) VCC = 5V, TA = +25°C, ISL8487E, ISL81487L, and ISL81487E; unless otherwise specified DRIVER OUTPUT (V) DRIVER OUTPUT (V) RECEIVER OUTPUT (V) Typical Performance Curves ISL8487E, ISL81487L, ISL81487E Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Sep 20, 2018 FN6051.8 Applied Renesas Header/Footer. Added Related Literature section. Updated Ordering Information table by removing retired parts ISL8487EIB, ISL81487LIB, ISL81487LIP, and ISL81487EIP, adding Notes 1 and 3, and adding tape and reel parts and column. Updated the Typical Operating Circuit diagram on page 2. Added Revision History section. Updated POD M8.15 to the latest revision. Changes are as follows: -Revision 1: Initial revision -Revision 1 to revision 2: Updated to new package outline drawing format by removing table, moving dimensions onto drawing, and adding land pattern -Revision 2 to revision 3: Changed the following values in Typical Recommended Landing Pattern: 2.41(0.095) to 2.20 (0.087) 0.76(0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -Revision 3 to revision 4: Changed text in Note 1 from “1982” to “1994” FN6051 Rev.8.00 Sep 20, 2018 Page 13 of 16 ISL8487E, ISL81487L, ISL81487E Package Outline Drawings E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE N INCHES E1 INDEX AREA 1 2 3 N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 e B1 D1 B 0.010 (0.25) M A1 eC C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C L C 0.008 0.014 0.204 eA D 0.355 0.400 9.01 A L D1 MILLIMETERS C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.355 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eB - 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. L 0.115 N 8 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 6 10.92 7 3.81 4 9 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . For the most recent package outline drawing, see E8.3. 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN6051 Rev.8.00 Sep 20, 2018 Page 14 of 16 ISL8487E, ISL81487L, ISL81487E M8.15 For the most recent package outline drawing, see M8.15. 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6051 Rev.8.00 Sep 20, 2018 Page 15 of 16 Notice 1. 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