M32182F8TFP

REJ09B0014-0100Z 32 32182 Group User's Manual RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES Before using this material, please visit the our website to confirm that this is the most current document available. Rev. 1.00 Revision date: Jun 4, 2003 www.renesas.com Keep safety first in your circuit designs! • Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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Date Page 1.00 Jun 4, 2003 – First edition issued 32182 Group User’s Manual Description Summary (1/1) Table of contents CHAPTER 1 OVERVIEW 1.1 Outline of the 32182 Group --------------------------------------------------------------------------------------------- 1-2 1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) --------------------------------------------- 1-2 1.1.2 Built-in Multiplier/Accumulator ------------------------------------------------------------------------------- 1-3 1.1.3 Built-in Single-precision FPU -------------------------------------------------------------------------------- 1-3 1.1.4 Built-in Flash Memory and RAM ---------------------------------------------------------------------------- 1-3 1.1.5 Built-in Clock Frequency Multiplier ------------------------------------------------------------------------- 1-4 1.1.6 Powerful Peripheral Functions Built-in -------------------------------------------------------------------- 1-4 1.2 Block Diagram -------------------------------------------------------------------------------------------------------------- 1-5 1.3 Pin Functions --------------------------------------------------------------------------------------------------------------- 1-8 1.4 Pin Assignments ----------------------------------------------------------------------------------------------------------- 1-14 CHAPTER 2 CPU 2.1 CPU Registers ------------------------------------------------------------------------------------------------------------- 2-2 2.2 General-purpose Registers --------------------------------------------------------------------------------------------- 2-2 2.3 Control Registers ---------------------------------------------------------------------------------------------------------- 2-2 2.3.1 Processor Status Word Register: PSW (CR0) ---------------------------------------------------------- 2-3 2.3.2 Condition Bit Register: CBR (CR1) ------------------------------------------------------------------------ 2-4 2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3) ------------------------- 2-4 2.3.4 Backup PC: BPC (CR6) -------------------------------------------------------------------------------------- 2-4 2.3.5 Floating-point Status Register: FPSR (CR7) ------------------------------------------------------------ 2-5 2.4 Accumulator ----------------------------------------------------------------------------------------------------------------- 2-7 2.5 Program Counter ---------------------------------------------------------------------------------------------------------- 2-7 2.6 Data Formats --------------------------------------------------------------------------------------------------------------- 2-8 2.6.1 Data Types ------------------------------------------------------------------------------------------------------- 2-8 2.6.2 Data Formats ---------------------------------------------------------------------------------------------------- 2-9 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution ----------------- 2-14 CHAPTER 3 ADDRESS SPACE 3.1 Outline of the Address Space ------------------------------------------------------------------------------------------ 3-2 3.2 Operation Modes ---------------------------------------------------------------------------------------------------------- 3-5 3.3 Internal ROM and Extended External Areas ------------------------------------------------------------------------ 3-9 3.3.1 Internal ROM Area --------------------------------------------------------------------------------------------- 3-9 3.3.2 Extended External Area -------------------------------------------------------------------------------------- 3-9 3.4 Internal RAM and SFR Areas ------------------------------------------------------------------------------------------ 3-10 3.4.1 Internal RAM Area --------------------------------------------------------------------------------------------- 3-10 3.4.2 SFR (Special Function Register) Area -------------------------------------------------------------------- 3-10 3.5 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 3-33 3.6 ICU Vector Table ---------------------------------------------------------------------------------------------------------- 3-34 3.7 Notes about Address Space -------------------------------------------------------------------------------------------- 3-36 (1) CHAPTER 4 EIT 4.1 Outline of EIT --------------------------------------------------------------------------------------------------------------- 4-2 4.2 EIT Events ------------------------------------------------------------------------------------------------------------------ 4-3 4.2.1 Exception --------------------------------------------------------------------------------------------------------- 4-3 4.2.2 Interrupt ----------------------------------------------------------------------------------------------------------- 4-5 4.2.3 Trap ---------------------------------------------------------------------------------------------------------------- 4-6 4.3 EIT Processing Procedure ---------------------------------------------------------------------------------------------- 4-6 4.4 EIT Processing Mechanism --------------------------------------------------------------------------------------------- 4-7 4.5 Acceptance of EIT Events ----------------------------------------------------------------------------------------------- 4-8 4.6 Saving and Restoring the PC and PSW ----------------------------------------------------------------------------- 4-8 4.7 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 4-10 4.8 Exception Processing ---------------------------------------------------------------------------------------------------- 4-11 4.8.1 Reserved Instruction Exception (RIE) --------------------------------------------------------------------- 4-11 4.8.2 Address Exception (AE) -------------------------------------------------------------------------------------- 4-12 4.8.3 Floating-Point Exception (FPE) ----------------------------------------------------------------------------- 4-13 4.9 Interrupt Processing ------------------------------------------------------------------------------------------------------ 4-15 4.9.1 Reset Interrupt (RI) -------------------------------------------------------------------------------------------- 4-15 4.9.2 System Break Interrupt (SBI) -------------------------------------------------------------------------------- 4-15 4.9.3 External Interrupt (EI) ----------------------------------------------------------------------------------------- 4-17 4.10 Trap Processing ---------------------------------------------------------------------------------------------------------- 4-18 4.10.1 Trap ---------------------------------------------------------------------------------------------------------------- 4-18 4.11 EIT Priority Levels ------------------------------------------------------------------------------------------------------- 4-19 4.12 Example of EIT Processing ------------------------------------------------------------------------------------------- 4-20 4.13 Precautions on EIT ------------------------------------------------------------------------------------------------------ 4-22 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller -------------------------------------------------------------------------------------- 5-2 5.2 ICU Related Registers --------------------------------------------------------------------------------------------------- 5-4 5.2.1 Interrupt Vector Register ------------------------------------------------------------------------------------- 5-5 5.2.2 Interrupt Request Mask Register --------------------------------------------------------------------------- 5-6 5.2.3 SBI (System Break Interrupt) Control Register --------------------------------------------------------- 5-7 5.2.4 Interrupt Control Registers ----------------------------------------------------------------------------------- 5-8 5.3 Interrupt Request Sources in Internal Peripheral I/O ------------------------------------------------------------- 5-11 5.4 ICU Vector Table ---------------------------------------------------------------------------------------------------------- 5-12 5.5 Description of Interrupt Operation ------------------------------------------------------------------------------------- 5-13 5.5.1 Acceptance of Internal Peripheral I/O Interrupts ------------------------------------------------------- 5-13 5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers -------------------------------------------- 5-15 5.6 Description of System Break Interrupt (SBI) Operation ---------------------------------------------------------- 5-18 5.6.1 Acceptance of SBI --------------------------------------------------------------------------------------------- 5-18 5.6.2 SBI Processing by Handler ---------------------------------------------------------------------------------- 5-18 CHAPTER 6 INTERNAL MEMORY 6.1 Outline of the Internal Memory ----------------------------------------------------------------------------------------- 6-2 6.2 Internal RAM ---------------------------------------------------------------------------------------------------------------- 6-2 6.3 Internal Flash Memory --------------------------------------------------------------------------------------------------- 6-2 (2) 6.4 Registers Associated with the Internal Flash Memory ----------------------------------------------------------- 6-5 6.4.1 Flash Mode Register ------------------------------------------------------------------------------------------ 6-5 6.4.2 Flash Status Registers ---------------------------------------------------------------------------------------- 6-6 6.4.3 Flash Status Register 2 (FSTAT2) ------------------------------------------------------------------------- 6-6 6.4.4 Flash Control Registers --------------------------------------------------------------------------------------- 6-8 6.4.5 Virtual Flash S Bank Registers ----------------------------------------------------------------------------- 6-12 6.5 Programming the Internal Flash Memory ---------------------------------------------------------------------------- 6-13 6.5.1 Outline of Internal Flash Memory Programming -------------------------------------------------------- 6-13 6.5.2 Controlling Operation Modes during Flash Programming -------------------------------------------- 6-18 6.5.3 Procedure for Programming/Erasing the Internal Flash Memory ---------------------------------- 6-21 6.5.4 Flash Programming Time (Reference) -------------------------------------------------------------------- 6-30 6.6 Virtual Flash Emulation Function -------------------------------------------------------------------------------------- 6-31 6.6.1 Virtual Flash Emulation Area -------------------------------------------------------------------------------- 6-32 6.6.2 Entering Virtual Flash Emulation Mode ------------------------------------------------------------------- 6-35 6.6.3 Application Example of Virtual Flash Emulation Mode ------------------------------------------------ 6-36 6.7 Connecting to A Serial Programmer ---------------------------------------------------------------------------------- 6-38 6.8 Internal Flash Memory Protect Function ----------------------------------------------------------------------------- 6-40 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory -------------------------------------- 6-41 CHAPTER 7 RESET 7.1 Outline of Reset ------------------------------------------------------------------------------------------------------------ 7-2 7.2 Reset Operation ----------------------------------------------------------------------------------------------------------- 7-2 7.2.1 Reset at Power-on --------------------------------------------------------------------------------------------- 7-3 7.2.2 Reset during Operation --------------------------------------------------------------------------------------- 7-3 7.2.3 Reset at Entering RAM Backup Mode -------------------------------------------------------------------- 7-3 7.2.4 Reset Vector Relocation during Flash Programming -------------------------------------------------- 7-3 7.3 Internal State Immediately after Reset ------------------------------------------------------------------------------- 7-4 7.4 Things to Be Considered after Reset --------------------------------------------------------------------------------- 7-4 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports ------------------------------------------------------------------------------------------- 8-2 8.2 Selecting Pin Functions -------------------------------------------------------------------------------------------------- 8-3 8.3 Input/Output Port Related Registers ---------------------------------------------------------------------------------- 8-5 8.3.1 Port Data Registers -------------------------------------------------------------------------------------------- 8-7 8.3.2 Port Direction Registers -------------------------------------------------------------------------------------- 8-8 8.3.3 Port Operation Mode Registers ----------------------------------------------------------------------------- 8-9 8.3.4 Port Peripheral Output Select Registers ------------------------------------------------------------------ 8-20 8.3.5 Port Input Special Function Control Register ------------------------------------------------------------ 8-21 8.4 Port Input Level Switching Function ---------------------------------------------------------------------------------- 8-24 8.5 Port Peripheral Circuits -------------------------------------------------------------------------------------------------- 8-27 8.6 Precautions on Input/Output Ports ------------------------------------------------------------------------------------ 8-31 (3) CHAPTER 9 DMAC 9.1 Outline of the DMAC ------------------------------------------------------------------------------------------------------ 9-2 9.2 DMAC Related Registers ------------------------------------------------------------------------------------------------ 9-4 9.2.1 DMA Channel Control Registers --------------------------------------------------------------------------- 9-6 9.2.2 DMA Software Request Generation Registers ---------------------------------------------------------- 9-18 9.2.3 DMA Source Address Registers ---------------------------------------------------------------------------- 9-19 9.2.4 DMA Destination Address Registers ---------------------------------------------------------------------- 9-20 9.2.5 DMA Transfer Count Registers ----------------------------------------------------------------------------- 9-21 9.2.6 DMA Interrupt Related Registers --------------------------------------------------------------------------- 9-22 9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-27 9.3.1 DMA Transfer Request Sources ---------------------------------------------------------------------------- 9-27 9.3.2 DMA Transfer Processing Procedure --------------------------------------------------------------------- 9-33 9.3.3 Starting DMA ---------------------------------------------------------------------------------------------------- 9-34 9.3.4 DMA Channel Priority ----------------------------------------------------------------------------------------- 9-34 9.3.5 Gaining and Releasing Control of the Internal Bus ---------------------------------------------------- 9-34 9.3.6 Transfer Units --------------------------------------------------------------------------------------------------- 9-35 9.3.7 Transfer Counts ------------------------------------------------------------------------------------------------- 9-35 9.3.8 Address Space -------------------------------------------------------------------------------------------------- 9-35 9.3.9 Transfer Operation --------------------------------------------------------------------------------------------- 9-35 9.3.10 End of DMA and Interrupt ------------------------------------------------------------------------------------ 9-37 9.3.11 Each Register Status after Completion of DMA Transfer -------------------------------------------- 9-37 9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------ 9-38 CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers --------------------------------------------------------------------------------------- 10-2 10.2 Common Units of Multijunction Timers ----------------------------------------------------------------------------- 10-8 10.2.1 MJT Common Unit Register Map -------------------------------------------------------------------------- 10-9 10.2.2 Prescaler Unit -------------------------------------------------------------------------------------------------- 10-10 10.2.3 Clock Bus and Input/Output Event Bus Control Unit ------------------------------------------------- 10-11 10.2.4 Input Processing Control Unit ------------------------------------------------------------------------------ 10-15 10.2.5 Output Flip-flop Control Unit -------------------------------------------------------------------------------- 10-21 10.2.6 Interrupt Control Unit ----------------------------------------------------------------------------------------- 10-26 10.3 TOP (Output-Related 16-Bit Timer) --------------------------------------------------------------------------------- 10-43 10.3.1 Outline of TOP -------------------------------------------------------------------------------------------------- 10-43 10.3.2 Outline of Each Mode of TOP ------------------------------------------------------------------------------- 10-45 10.3.3 TOP Related Register Map ---------------------------------------------------------------------------------- 10-47 10.3.4 TOP Control Registers ---------------------------------------------------------------------------------------- 10-49 10.3.5 TOP Counters (TOP0CT–TOP10CT) --------------------------------------------------------------------- 10-54 10.3.6 TOP Reload Registers (TOP0RL–TOP10RL) ----------------------------------------------------------- 10-55 10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) ----------------------------------------------------- 10-56 10.3.8 TOP Enable Control Registers ------------------------------------------------------------------------------ 10-57 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) -------------------------- 10-59 10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) -------------- 10-65 10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) --------------------- 10-70 (4) 10.4 TIO (Input/Output-Related 16-Bit Timer) --------------------------------------------------------------------------- 10-73 10.4.1 Outline of TIO --------------------------------------------------------------------------------------------------- 10-73 10.4.2 Outline of Each Mode of TIO -------------------------------------------------------------------------------- 10-75 10.4.3 TIO Related Register Map ----------------------------------------------------------------------------------- 10-78 10.4.4 TIO Control Registers ----------------------------------------------------------------------------------------- 10-80 10.4.5 TIO Counters (TIO0CT–TIO9CT) -------------------------------------------------------------------------- 10-88 10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0) --------------------------------------------- 10-89 10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ---------------------------------------------------------- 10-90 10.4.8 TIO Enable Control Registers ------------------------------------------------------------------------------- 10-91 10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes -------------------------------------------- 10-93 10.4.10 Operation in TIO Noise Processing Input Mode -------------------------------------------------------- 10-95 10.4.11 Operation in TIO PWM Output Mode ---------------------------------------------------------------------- 10-96 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) ----------------------- 10-99 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) ----------- 10-101 10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) ----------------------- 10-103 10.5 TMS (Input-Related 16-Bit Timer) ----------------------------------------------------------------------------------- 10-105 10.5.1 Outline of TMS -------------------------------------------------------------------------------------------------- 10-105 10.5.2 Outline of TMS Operation ------------------------------------------------------------------------------------ 10-105 10.5.3 TMS Related Register Map ---------------------------------------------------------------------------------- 10-107 10.5.4 TMS Control Registers ---------------------------------------------------------------------------------------- 10-108 10.5.5 TMS Counters (TMS0CT, TMS1CT) ---------------------------------------------------------------------- 10-109 10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0) ---------------------------------------------- 10-109 10.5.7 Operation of TMS Measure Input -------------------------------------------------------------------------- 10-110 10.6 TML (Input-Related 32-Bit Timer) ------------------------------------------------------------------------------------ 10-111 10.6.1 Outline of TML -------------------------------------------------------------------------------------------------- 10-111 10.6.2 Outline of TML Operation ------------------------------------------------------------------------------------ 10-112 10.6.3 TML Related Register Map ---------------------------------------------------------------------------------- 10-112 10.6.4 TML Control Registers ---------------------------------------------------------------------------------------- 10-113 10.6.5 TML Counters --------------------------------------------------------------------------------------------------- 10-114 10.6.6 TML Measure Registers -------------------------------------------------------------------------------------- 10-114 10.6.7 Operation of TML Measure Input --------------------------------------------------------------------------- 10-115 CHAPTER 11 A-D CONVERTER 11.1 Outline of A-D Converter ----------------------------------------------------------------------------------------------- 11-2 11.1.1 Conversion Modes --------------------------------------------------------------------------------------------- 11-5 11.1.2 Operation Modes ----------------------------------------------------------------------------------------------- 11-5 11.1.3 Special Operation Modes ------------------------------------------------------------------------------------ 11-8 11.1.4 A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------ 11-11 11.1.5 Sample-and-Hold Function ----------------------------------------------------------------------------------- 11-11 11.2 A-D Converter Related Registers ------------------------------------------------------------------------------------ 11-12 11.2.1 A-D Single Mode Register 0 --------------------------------------------------------------------------------- 11-14 11.2.2 A-D Single Mode Register 1 --------------------------------------------------------------------------------- 11-16 11.2.3 A-D Scan Mode Register 0 ---------------------------------------------------------------------------------- 11-18 11.2.4 A-D Scan Mode Register 1 ---------------------------------------------------------------------------------- 11-20 11.2.5 A-D Conversion Speed Control Register ----------------------------------------------------------------- 11-22 (5) 11.2.6 A-D Disconnection Detection Assist Function Control Register ------------------------------------ 11-23 11.2.7 A-D Disconnection Detection Assist Method Select Register --------------------------------------- 11-24 11.2.8 A-D Successive Approximation Register ----------------------------------------------------------------- 11-27 11.2.9 A-D Comparate Data Register ------------------------------------------------------------------------------ 11-28 11.2.10 10-bit A-D Data Registers ------------------------------------------------------------------------------------ 11-29 11.2.11 8-bit A-D Data Registers -------------------------------------------------------------------------------------- 11-30 11.3 Functional Description of A-D Converter --------------------------------------------------------------------------- 11-31 11.3.1 How to Find Analog Input Voltages ------------------------------------------------------------------------ 11-31 11.3.2 A-D Conversion by Successive Approximation Method ---------------------------------------------- 11-32 11.3.3 Comparator Operation ---------------------------------------------------------------------------------------- 11-33 11.3.4 Calculating the A-D Conversion Time --------------------------------------------------------------------- 11-34 11.3.5 Accuracy of A-D Conversion -------------------------------------------------------------------------------- 11-37 11.4 Inflow Current Bypass Circuit ----------------------------------------------------------------------------------------- 11-39 11.5 Precautions on Using A-D Converter ------------------------------------------------------------------------------- 11-41 CHAPTER 12 SERIAL I/O 12.1 Outline of Serial I/O ----------------------------------------------------------------------------------------------------- 12-2 12.2 Serial I/O Related Registers ------------------------------------------------------------------------------------------ 12-5 12.2.1 SIO Interrupt Related Registers ---------------------------------------------------------------------------- 12-6 12.2.2 SIO Transmit Control Registers ---------------------------------------------------------------------------- 12-13 12.2.3 SIO Transmit/Receive Mode Registers ------------------------------------------------------------------- 12-14 12.2.4 SIO Transmit Buffer Registers ------------------------------------------------------------------------------ 12-17 12.2.5 SIO Receive Buffer Registers ------------------------------------------------------------------------------- 12-18 12.2.6 SIO Receive Control Registers ----------------------------------------------------------------------------- 12-19 12.2.7 SIO Baud Rate Registers ------------------------------------------------------------------------------------ 12-22 12.3 Transmit Operation in CSIO Mode ---------------------------------------------------------------------------------- 12-23 12.3.1 Setting the CSIO Baud Rate --------------------------------------------------------------------------------- 12-23 12.3.2 Initializing CSIO Transmission ------------------------------------------------------------------------------ 12-24 12.3.3 Starting CSIO Transmission --------------------------------------------------------------------------------- 12-26 12.3.4 Successive CSIO Transmission ---------------------------------------------------------------------------- 12-26 12.3.5 Processing at End of CSIO Transmission ---------------------------------------------------------------- 12-27 12.3.6 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-27 12.3.7 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-27 12.3.8 Example of CSIO Transmit Operation -------------------------------------------------------------------- 12-29 12.4 Receive Operation in CSIO Mode ----------------------------------------------------------------------------------- 12-31 12.4.1 Initialization for CSIO Reception ---------------------------------------------------------------------------- 12-31 12.4.2 Starting CSIO Reception ------------------------------------------------------------------------------------- 12-33 12.4.3 Processing at End of CSIO Reception -------------------------------------------------------------------- 12-33 12.4.4 About Successive Reception -------------------------------------------------------------------------------- 12-34 12.4.5 Flags Showing the Status of CSIO Receive Operation ----------------------------------------------- 12-35 12.4.6 Example of CSIO Receive Operation --------------------------------------------------------------------- 12-36 12.5 Precautions on Using CSIO Mode ----------------------------------------------------------------------------------- 12-38 12.6 Transmit Operation in UART Mode --------------------------------------------------------------------------------- 12-39 12.6.1 Setting the UART Baud Rate -------------------------------------------------------------------------------- 12-39 12.6.2 UART Transmit/Receive Data Formats ------------------------------------------------------------------- 12-39 12.6.3 Initializing UART Transmission ----------------------------------------------------------------------------- 12-41 12.6.4 Starting UART Transmission -------------------------------------------------------------------------------- 12-43 (6) 12.6.5 Successive UART Transmission --------------------------------------------------------------------------- 12-43 12.6.6 Processing at End of UART Transmission --------------------------------------------------------------- 12-43 12.6.7 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-43 12.6.8 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-44 12.6.9 Example of UART Transmit Operation -------------------------------------------------------------------- 12-45 12.7 Receive Operation in UART Mode ---------------------------------------------------------------------------------- 12-47 12.7.1 Initialization for UART Reception --------------------------------------------------------------------------- 12-47 12.7.2 Starting UART Reception ------------------------------------------------------------------------------------ 12-49 12.7.3 Processing at End of UART Reception ------------------------------------------------------------------- 12-49 12.7.4 Example of UART Receive Operation -------------------------------------------------------------------- 12-51 12.7.5 Start Bit Detection during UART Reception -------------------------------------------------------------- 12-53 12.8 Fixed Period Clock Output Function -------------------------------------------------------------------------------- 12-54 12.9 Precautions on Using UART Mode ---------------------------------------------------------------------------------- 12-55 CHAPTER 13 CAN MODULE 13.1 Outline of the CAN Module -------------------------------------------------------------------------------------------- 13-2 13.2 CAN Module Related Registers -------------------------------------------------------------------------------------- 13-4 13.2.1 CAN Control Registers ---------------------------------------------------------------------------------------- 13-15 13.2.2 CAN Status Registers ----------------------------------------------------------------------------------------- 13-18 13.2.3 CAN Frame Format Select Registers --------------------------------------------------------------------- 13-21 13.2.4 CAN Configuration Registers -------------------------------------------------------------------------------- 13-22 13.2.5 CAN Timestamp Count Registers -------------------------------------------------------------------------- 13-24 13.2.6 CAN Error Count Registers ---------------------------------------------------------------------------------- 13-25 13.2.7 CAN Baud Rate Prescalers ---------------------------------------------------------------------------------- 13-26 13.2.8 CAN Interrupt Related Registers --------------------------------------------------------------------------- 13-27 13.2.9 CAN Cause of Error Registers ------------------------------------------------------------------------------ 13-45 13.2.10 CAN Mode Registers ------------------------------------------------------------------------------------------ 13-46 13.2.11 CAN DMA Transfer Request Select Register ----------------------------------------------------------- 13-47 13.2.12 CAN Mask Registers ------------------------------------------------------------------------------------------ 13-48 13.2.13 CAN Single-Shot Mode Control Registers --------------------------------------------------------------- 13-52 13.2.14 CAN Message Slot Control Registers --------------------------------------------------------------------- 13-53 13.2.15 CAN Message Slots ------------------------------------------------------------------------------------------- 13-57 13.3 CAN Protocol ------------------------------------------------------------------------------------------------------------- 13-72 13.3.1 CAN Protocol Frames ----------------------------------------------------------------------------------------- 13-72 13.3.2 Data Formats during CAN Transmission/Reception --------------------------------------------------- 13-73 13.3.3 CAN Controller Error States --------------------------------------------------------------------------------- 13-74 13.4 Initializing the CAN Module -------------------------------------------------------------------------------------------- 13-75 13.4.1 Initializing the CAN Module ---------------------------------------------------------------------------------- 13-75 13.5 Transmitting Data Frames --------------------------------------------------------------------------------------------- 13-78 13.5.1 Data Frame Transmit Procedure --------------------------------------------------------------------------- 13-78 13.5.2 Data Frame Transmit Operation ---------------------------------------------------------------------------- 13-79 13.5.3 Transmit Abort Function -------------------------------------------------------------------------------------- 13-80 13.6 Receiving Data Frames ------------------------------------------------------------------------------------------------ 13-81 13.6.1 Data Frame Receive Procedure ---------------------------------------------------------------------------- 13-81 13.6.2 Data Frame Receive Operation ----------------------------------------------------------------------------- 13-82 13.6.3 Reading Out Received Data Frames ---------------------------------------------------------------------- 13-84 (7) 13.7 Transmitting Remote Frames ---------------------------------------------------------------------------------------- 13-86 13.7.1 Remote Frame Transmit Procedure ----------------------------------------------------------------------- 13-86 13.7.2 Remote Frame Transmit Operation ------------------------------------------------------------------------ 13-87 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission ------------- 13-89 13.8 Receiving Remote Frames -------------------------------------------------------------------------------------------- 13-91 13.8.1 Remote Frame Receive Procedure ------------------------------------------------------------------------ 13-91 13.8.2 Remote Frame Receive Operation ------------------------------------------------------------------------ 13-92 13.9 Precautions about CAN Module -------------------------------------------------------------------------------------- 13-95 CHAPTER 14 REAL TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) ------------------------------------------------------------------------ 14-2 14.2 Pin Functions of the RTD ---------------------------------------------------------------------------------------------- 14-3 14.3 Functional Description of the RTD ----------------------------------------------------------------------------------- 14-4 14.3.1 Outline of the RTD Operation ------------------------------------------------------------------------------ 14-4 14.3.2 Operation of RDR (Real-time RAM Content Output) ------------------------------------------------- 14-4 14.3.3 Operation of the WRR (RAM Content Forcible Rewrite) --------------------------------------------- 14-6 14.3.4 Operation of VER (Continuous Monitor) ----------------------------------------------------------------- 14-7 14.3.5 Operation of VEI (Interrupt Request) --------------------------------------------------------------------- 14-7 14.3.6 Operation of RCV (Recover from Runaway) ----------------------------------------------------------- 14-8 14.3.7 Method for Setting a Specified Address when Using the RTD ------------------------------------- 14-9 14.3.8 Resetting the RTD --------------------------------------------------------------------------------------------- 14-10 14.4 Typical Connection with the Host ------------------------------------------------------------------------------------ 14-11 CHAPTER 15 EXTERNAL BUS INTERFACE 15.1 Outline of the External Bus Interface ------------------------------------------------------------------------------- 15-2 15.1.1 External Bus Interface Related Signals ------------------------------------------------------------------ 15-2 15.2 External Bus Interface Related Registers ------------------------------------------------------------------------- 15-4 15.2.1 Port Operation Mode Registers ---------------------------------------------------------------------------- 15-4 15.2.2 Port Peripheral Output Select Register ------------------------------------------------------------------ 15-8 15.2.3 Bus Mode Control Register --------------------------------------------------------------------------------- 15-9 15.3 Read/Write Operations ------------------------------------------------------------------------------------------------- 15-10 15.4 Bus Arbitration ------------------------------------------------------------------------------------------------------------ 15-16 15.5 Typical Connection of External Extension Memory ------------------------------------------------------------- 15-18 15.6 Example of Bus Voltage Settings Using VCC-BUS ------------------------------------------------------------- 15-21 CHAPTER 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller ----------------------------------------------------------------------------------------- 16-2 16.2 Wait Controller Related Registers ----------------------------------------------------------------------------------- 16-4 16.2.1 CS Area Wait Control Registers ---------------------------------------------------------------------------- 16-4 16.3 Typical Operation of the Wait Controller --------------------------------------------------------------------------- 16-6 CHAPTER 17 RAM BACKUP MODE 17.1 Outline of RAM Backup Mode ---------------------------------------------------------------------------------------- 17-2 17.2 Example of RAM Backup when Power is Off -------------------------------------------------------------------------- 17-3 17.2.1 Normal Operating State --------------------------------------------------------------------------------------- 17-3 17.2.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-4 (8) 17.3 Example of RAM Backup for Saving Power Consumption ---------------------------------------------------- 17-5 17.3.1 Normal Operating State --------------------------------------------------------------------------------------- 17-5 17.3.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-6 17.3.3 Precautions to Be Observed at Power-On --------------------------------------------------------------- 17-7 17.4 Exiting RAM Backup Mode (Wakeup) ------------------------------------------------------------------------------ 17-8 CHAPTER 18 OSCILLATOR CIRCUIT 18.1 Oscillator Circuit ---------------------------------------------------------------------------------------------------------- 18-2 18.1.1 Example of an Oscillator Circuit ---------------------------------------------------------------------------- 18-2 18.1.2 XIN Oscillation Stoppage Detection Circuit -------------------------------------------------------------- 18-3 18.1.3 Oscillation Drive Capability Select Function ------------------------------------------------------------- 18-5 18.1.4 System Clock Output Function ------------------------------------------------------------------------------ 18-7 18.1.5 Oscillation Stabilization Time at Power-On -------------------------------------------------------------- 18-7 18.2 Clock Generator Circuit ------------------------------------------------------------------------------------------------ 18-8 CHAPTER 19 JTAG 19.1 Outline of JTAG ---------------------------------------------------------------------------------------------------------- 19-2 19.2 Configuration of the JTAG Circuit ------------------------------------------------------------------------------------ 19-3 19.3 JTAG Registers ---------------------------------------------------------------------------------------------------------- 19-4 19.3.1 Instruction Register (JTAGIR) ------------------------------------------------------------------------------- 19-4 19.3.2 Data Register ---------------------------------------------------------------------------------------------------- 19-5 19.4 Basic Operation of JTAG ---------------------------------------------------------------------------------------------- 19-6 19.4.1 Outline of JTAG Operation ----------------------------------------------------------------------------------- 19-6 19.4.2 IR Path Sequence ---------------------------------------------------------------------------------------------- 19-8 19.4.3 DR Path Sequence -------------------------------------------------------------------------------------------- 19-9 19.4.4 Inspecting and Setting Data Registers -------------------------------------------------------------------- 19-10 19.5 Boundary Scan Description Language ----------------------------------------------------------------------------- 19-11 19.6 Notes on Board Design when Connecting JTAG ---------------------------------------------------------------------- 19-12 19.7 Processing Pins when Not Using JTAG ---------------------------------------------------------------------------- 19-13 CHAPTER 20 POWER SUPPLY CIRCUIT 20.1 Configuration of the Power Supply Circuit ------------------------------------------------------------------------- 20-2 20.2 Power-On Sequence ---------------------------------------------------------------------------------------------------- 20-3 20.2.1 Power-On Sequence when Not Using RAM Backup -------------------------------------------------- 20-3 20.2.2 Power-On Sequence when Using RAM Backup -------------------------------------------------------- 20-4 20.3 Power-Off Sequence ---------------------------------------------------------------------------------------------------- 20-5 20.3.1 Power-Off Sequence when Not Using RAM Backup -------------------------------------------------- 20-5 20.3.2 Power-Off Sequence when Using RAM Backup ------------------------------------------------------- 20-6 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings ------------------------------------------------------------------------------------------- 21-2 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ---------------------------------------------- 21-3 21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz) ------------------- 21-3 21.2.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) ----------------------------------------- 21-5 21.2.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) -------------------------- 21-6 (9) 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz ------------------------------------------------ 21-7 21.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) -------------------- 21-7 21.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ------------------------------------------- 21-9 21.3.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ---------------------------- 21-10 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz -------------------------------------------- 21-11 21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ------ 21-11 21.4.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ---------------------------- 21-13 21.4.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ------------- 21-14 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz ---------------------------------------------- 21-15 21.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V f(XIN) = 8 MHz) -------- 21-15 21.5.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) ------------------------------ 21-17 21.5.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) --------------- 21-18 21.6 Flash Memory Related Characteristics ----------------------------------------------------------------------------- 21-19 21.7 A.C. Characteristics (when VCCE = 5 V) -------------------------------------------------------------------------- 21-20 21.7.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-20 21.7.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-24 21.7.3 A.C. Characteristics -------------------------------------------------------------------------------------------- 21-27 21.8 A.C. Characteristics (when VCCE = 3.3 V) ----------------------------------------------------------------------- 21-36 21.8.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-36 21.8.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-40 21.8.3 A.C. Characteristics -------------------------------------------------------------------------------------------- 21-43 CHAPTER 22 TYPICAL CHARACTERISTICS To be written at a later time --------------------------------------------------------------------------------------------------- 22-2 APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1.1 Dimensional Outline Drawing ------------------------------------------------------------------- Appendix 1-2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32182 Instruction Processing Time ------------------------------------------------------------ Appendix 2-2 APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example Processing of Unused Pins --------------------------------------------------------- Appendix 3-2 APPENDIX 4 SUMMARY OF PRECAUTIONS Appendix 4.1 Precautions about the CPU --------------------------------------------------------------------Appendix 4.1.1 Precautions Regarding Data Transfer -----------------------------------------------Appendix 4.2 Precautions about the Address Space ------------------------------------------------------Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------Appendix 4.3 Precautions about EIT --------------------------------------------------------------------------Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory --------Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------Appendix 4.5.1 Input/output Ports -------------------------------------------------------------------------Appendix 4-2 Appendix 4-2 Appendix 4-3 Appendix 4-3 Appendix 4-3 Appendix 4-3 Appendix 4-4 Appendix 4-4 (10) Appendix 4.6 Precautions about Input/Output Ports --------------------------------------------------Appendix 4.6.1 When Using Input/Output Ports in Output Mode ------------------------------Appendix 4.6.2 About the Port Input Disable Function -------------------------------------------Appendix 4.7 Precautions about the DMAC -------------------------------------------------------------Appendix 4.7.1 About Writing to the DMAC Related Registers ---------------------------------Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer -------------Appendix 4.7.3 About the DMA Interrupt Request Status Register ----------------------------Appendix 4.7.4 About the Stable Operation of DMA Transfer ----------------------------------Appendix 4.8 Precautions about the Multijunction Timers -------------------------------------------Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode -----------------------Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode -----------Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode ------------------------Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes --------Appendix 4.8.5 Precautions on Using TIO PWM Output Mode ---------------------------------Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode ------------------------Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode -------------Appendix 4.8.8 Precautions on Using TIO Continuous Output Mode -------------------------Appendix 4.8.9 Precautions on Using TMS Measure Input --------------------------------------Appendix 4.8.10 Precautions on Using TML Measure Input -------------------------------------Appendix 4.9 Precautions about the A-D Converters -------------------------------------------------Appendix 4.10 Precautions about Serial I/O --------------------------------------------------------------Appendix 4.10.1 Precautions on Using CSIO Mode ------------------------------------------------Appendix 4.10.2 Precautions on Using UART Mode -----------------------------------------------Appendix 4.11 Precautions about RAM Backup Mode ------------------------------------------------Appendix 4.11.1 Precautions to Be Observed at Power-On -------------------------------------Appendix 4.12 Precautions about JTAG ------------------------------------------------------------------Appendix 4.12.1 Notes on Board Design when Connecting JTAG ------------------------------Appendix 4.12.2 Processing Pins when Not Using JTAG -----------------------------------------Appendix 4.13 Precautions about Noise ------------------------------------------------------------------Appendix 4.13.1 Reduction of Wiring Length --------------------------------------------------------Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines --------------Appendix 4.13.3 Processing Analog Input Pin Wiring ---------------------------------------------Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin ---------------------------Appendix 4.13.5 Processing Input/Output Ports ----------------------------------------------------- Appendix 4-4 Appendix 4-4 Appendix 4-4 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-6 Appendix 4-6 Appendix 4-8 Appendix 4-9 Appendix 4-9 Appendix 4-9 Appendix 4-9 Appendix 4-10 Appendix 4-10 Appendix 4-10 Appendix 4-11 Appendix 4-12 Appendix 4-15 Appendix 4-15 Appendix 4-16 Appendix 4-17 Appendix 4-17 Appendix 4-18 Appendix 4-18 Appendix 4-19 Appendix 4-20 Appendix 4-20 Appendix 4-23 Appendix 4-23 Appendix 4-24 Appendix 4-28 (11) This page is blank for reasons of layout. (12) CHAPTER 4 EIT 4.1 Outline of EIT --------------------------------------------------------------------------------------------------------------- 4-2 4.2 EIT Events ------------------------------------------------------------------------------------------------------------------ 4-3 4.2.1 Exception --------------------------------------------------------------------------------------------------------- 4-3 4.2.2 Interrupt ----------------------------------------------------------------------------------------------------------- 4-5 4.2.3 Trap ---------------------------------------------------------------------------------------------------------------- 4-6 4.3 EIT Processing Procedure ---------------------------------------------------------------------------------------------- 4-6 4.4 EIT Processing Mechanism --------------------------------------------------------------------------------------------- 4-7 4.5 Acceptance of EIT Events ----------------------------------------------------------------------------------------------- 4-8 4.6 Saving and Restoring the PC and PSW ----------------------------------------------------------------------------- 4-8 4.7 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 4-10 4.8 Exception Processing ---------------------------------------------------------------------------------------------------- 4-11 4.8.1 Reserved Instruction Exception (RIE) --------------------------------------------------------------------- 4-11 4.8.2 Address Exception (AE) -------------------------------------------------------------------------------------- 4-12 4.8.3 Floating-Point Exception (FPE) ----------------------------------------------------------------------------- 4-13 4.9 Interrupt Processing ------------------------------------------------------------------------------------------------------ 4-15 4.9.1 Reset Interrupt (RI) -------------------------------------------------------------------------------------------- 4-15 4.9.2 System Break Interrupt (SBI) -------------------------------------------------------------------------------- 4-15 4.9.3 External Interrupt (EI) ----------------------------------------------------------------------------------------- 4-17 4.10 Trap Processing ---------------------------------------------------------------------------------------------------------- 4-18 4.10.1 Trap ---------------------------------------------------------------------------------------------------------------- 4-18 4.11 EIT Priority Levels ------------------------------------------------------------------------------------------------------- 4-19 4.12 Example of EIT Processing ------------------------------------------------------------------------------------------- 4-20 4.13 Precautions on EIT ------------------------------------------------------------------------------------------------------ 4-22 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller -------------------------------------------------------------------------------------- 5-2 5.2 ICU Related Registers --------------------------------------------------------------------------------------------------- 5-4 5.2.1 Interrupt Vector Register ------------------------------------------------------------------------------------- 5-5 5.2.2 Interrupt Request Mask Register --------------------------------------------------------------------------- 5-6 5.2.3 SBI (System Break Interrupt) Control Register --------------------------------------------------------- 5-7 5.2.4 Interrupt Control Registers ----------------------------------------------------------------------------------- 5-8 5.3 Interrupt Request Sources in Internal Peripheral I/O ------------------------------------------------------------- 5-11 5.4 ICU Vector Table ---------------------------------------------------------------------------------------------------------- 5-12 5.5 Description of Interrupt Operation ------------------------------------------------------------------------------------- 5-13 5.5.1 Acceptance of Internal Peripheral I/O Interrupts ------------------------------------------------------- 5-13 5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers -------------------------------------------- 5-15 5.6 Description of System Break Interrupt (SBI) Operation ---------------------------------------------------------- 5-18 5.6.1 Acceptance of SBI --------------------------------------------------------------------------------------------- 5-18 5.6.2 SBI Processing by Handler ---------------------------------------------------------------------------------- 5-18 CHAPTER 6 INTERNAL MEMORY 6.1 Outline of the Internal Memory ----------------------------------------------------------------------------------------- 6-2 6.2 Internal RAM ---------------------------------------------------------------------------------------------------------------- 6-2 6.3 Internal Flash Memory --------------------------------------------------------------------------------------------------- 6-2 (2) 6.4 Registers Associated with the Internal Flash Memory ----------------------------------------------------------- 6-5 6.4.1 Flash Mode Register ------------------------------------------------------------------------------------------ 6-5 6.4.2 Flash Status Registers ---------------------------------------------------------------------------------------- 6-6 6.4.3 Flash Status Register 2 (FSTAT2) ------------------------------------------------------------------------- 6-6 6.4.4 Flash Control Registers --------------------------------------------------------------------------------------- 6-8 6.4.5 Virtual Flash S Bank Registers ----------------------------------------------------------------------------- 6-12 6.5 Programming the Internal Flash Memory ---------------------------------------------------------------------------- 6-13 6.5.1 Outline of Internal Flash Memory Programming -------------------------------------------------------- 6-13 6.5.2 Controlling Operation Modes during Flash Programming -------------------------------------------- 6-18 6.5.3 Procedure for Programming/Erasing the Internal Flash Memory ---------------------------------- 6-21 6.5.4 Flash Programming Time (Reference) -------------------------------------------------------------------- 6-30 6.6 Virtual Flash Emulation Function -------------------------------------------------------------------------------------- 6-31 6.6.1 Virtual Flash Emulation Area -------------------------------------------------------------------------------- 6-32 6.6.2 Entering Virtual Flash Emulation Mode ------------------------------------------------------------------- 6-35 6.6.3 Application Example of Virtual Flash Emulation Mode ------------------------------------------------ 6-36 6.7 Connecting to A Serial Programmer ---------------------------------------------------------------------------------- 6-38 6.8 Internal Flash Memory Protect Function ----------------------------------------------------------------------------- 6-40 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory -------------------------------------- 6-41 CHAPTER 7 RESET 7.1 Outline of Reset ------------------------------------------------------------------------------------------------------------ 7-2 7.2 Reset Operation ----------------------------------------------------------------------------------------------------------- 7-2 7.2.1 Reset at Power-on --------------------------------------------------------------------------------------------- 7-3 7.2.2 Reset during Operation --------------------------------------------------------------------------------------- 7-3 7.2.3 Reset at Entering RAM Backup Mode -------------------------------------------------------------------- 7-3 7.2.4 Reset Vector Relocation during Flash Programming -------------------------------------------------- 7-3 7.3 Internal State Immediately after Reset ------------------------------------------------------------------------------- 7-4 7.4 Things to Be Considered after Reset --------------------------------------------------------------------------------- 7-4 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports ------------------------------------------------------------------------------------------- 8-2 8.2 Selecting Pin Functions -------------------------------------------------------------------------------------------------- 8-3 8.3 Input/Output Port Related Registers ---------------------------------------------------------------------------------- 8-5 8.3.1 Port Data Registers -------------------------------------------------------------------------------------------- 8-7 8.3.2 Port Direction Registers -------------------------------------------------------------------------------------- 8-8 8.3.3 Port Operation Mode Registers ----------------------------------------------------------------------------- 8-9 8.3.4 Port Peripheral Output Select Registers ------------------------------------------------------------------ 8-20 8.3.5 Port Input Special Function Control Register ------------------------------------------------------------ 8-21 8.4 Port Input Level Switching Function ---------------------------------------------------------------------------------- 8-24 8.5 Port Peripheral Circuits -------------------------------------------------------------------------------------------------- 8-27 8.6 Precautions on Input/Output Ports ------------------------------------------------------------------------------------ 8-31 (3) CHAPTER 9 DMAC 9.1 Outline of the DMAC ------------------------------------------------------------------------------------------------------ 9-2 9.2 DMAC Related Registers ------------------------------------------------------------------------------------------------ 9-4 9.2.1 DMA Channel Control Registers --------------------------------------------------------------------------- 9-6 9.2.2 DMA Software Request Generation Registers ---------------------------------------------------------- 9-18 9.2.3 DMA Source Address Registers ---------------------------------------------------------------------------- 9-19 9.2.4 DMA Destination Address Registers ---------------------------------------------------------------------- 9-20 9.2.5 DMA Transfer Count Registers ----------------------------------------------------------------------------- 9-21 9.2.6 DMA Interrupt Related Registers --------------------------------------------------------------------------- 9-22 9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-27 9.3.1 DMA Transfer Request Sources ---------------------------------------------------------------------------- 9-27 9.3.2 DMA Transfer Processing Procedure --------------------------------------------------------------------- 9-33 9.3.3 Starting DMA ---------------------------------------------------------------------------------------------------- 9-34 9.3.4 DMA Channel Priority ----------------------------------------------------------------------------------------- 9-34 9.3.5 Gaining and Releasing Control of the Internal Bus ---------------------------------------------------- 9-34 9.3.6 Transfer Units --------------------------------------------------------------------------------------------------- 9-35 9.3.7 Transfer Counts ------------------------------------------------------------------------------------------------- 9-35 9.3.8 Address Space -------------------------------------------------------------------------------------------------- 9-35 9.3.9 Transfer Operation --------------------------------------------------------------------------------------------- 9-35 9.3.10 End of DMA and Interrupt ------------------------------------------------------------------------------------ 9-37 9.3.11 Each Register Status after Completion of DMA Transfer -------------------------------------------- 9-37 9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------ 9-38 CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers --------------------------------------------------------------------------------------- 10-2 10.2 Common Units of Multijunction Timers ----------------------------------------------------------------------------- 10-8 10.2.1 MJT Common Unit Register Map -------------------------------------------------------------------------- 10-9 10.2.2 Prescaler Unit -------------------------------------------------------------------------------------------------- 10-10 10.2.3 Clock Bus and Input/Output Event Bus Control Unit ------------------------------------------------- 10-11 10.2.4 Input Processing Control Unit ------------------------------------------------------------------------------ 10-15 10.2.5 Output Flip-flop Control Unit -------------------------------------------------------------------------------- 10-21 10.2.6 Interrupt Control Unit ----------------------------------------------------------------------------------------- 10-26 10.3 TOP (Output-Related 16-Bit Timer) --------------------------------------------------------------------------------- 10-43 10.3.1 Outline of TOP -------------------------------------------------------------------------------------------------- 10-43 10.3.2 Outline of Each Mode of TOP ------------------------------------------------------------------------------- 10-45 10.3.3 TOP Related Register Map ---------------------------------------------------------------------------------- 10-47 10.3.4 TOP Control Registers ---------------------------------------------------------------------------------------- 10-49 10.3.5 TOP Counters (TOP0CT–TOP10CT) --------------------------------------------------------------------- 10-54 10.3.6 TOP Reload Registers (TOP0RL–TOP10RL) ----------------------------------------------------------- 10-55 10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) ----------------------------------------------------- 10-56 10.3.8 TOP Enable Control Registers ------------------------------------------------------------------------------ 10-57 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) -------------------------- 10-59 10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) -------------- 10-65 10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) --------------------- 10-70 (4) 10.4 TIO (Input/Output-Related 16-Bit Timer) --------------------------------------------------------------------------- 10-73 10.4.1 Outline of TIO --------------------------------------------------------------------------------------------------- 10-73 10.4.2 Outline of Each Mode of TIO -------------------------------------------------------------------------------- 10-75 10.4.3 TIO Related Register Map ----------------------------------------------------------------------------------- 10-78 10.4.4 TIO Control Registers ----------------------------------------------------------------------------------------- 10-80 10.4.5 TIO Counters (TIO0CT–TIO9CT) -------------------------------------------------------------------------- 10-88 10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0) --------------------------------------------- 10-89 10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) ---------------------------------------------------------- 10-90 10.4.8 TIO Enable Control Registers ------------------------------------------------------------------------------- 10-91 10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes -------------------------------------------- 10-93 10.4.10 Operation in TIO Noise Processing Input Mode -------------------------------------------------------- 10-95 10.4.11 Operation in TIO PWM Output Mode ---------------------------------------------------------------------- 10-96 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) ----------------------- 10-99 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) ----------- 10-101 10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) ----------------------- 10-103 10.5 TMS (Input-Related 16-Bit Timer) ----------------------------------------------------------------------------------- 10-105 10.5.1 Outline of TMS -------------------------------------------------------------------------------------------------- 10-105 10.5.2 Outline of TMS Operation ------------------------------------------------------------------------------------ 10-105 10.5.3 TMS Related Register Map ---------------------------------------------------------------------------------- 10-107 10.5.4 TMS Control Registers ---------------------------------------------------------------------------------------- 10-108 10.5.5 TMS Counters (TMS0CT, TMS1CT) ---------------------------------------------------------------------- 10-109 10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0) ---------------------------------------------- 10-109 10.5.7 Operation of TMS Measure Input -------------------------------------------------------------------------- 10-110 10.6 TML (Input-Related 32-Bit Timer) ------------------------------------------------------------------------------------ 10-111 10.6.1 Outline of TML -------------------------------------------------------------------------------------------------- 10-111 10.6.2 Outline of TML Operation ------------------------------------------------------------------------------------ 10-112 10.6.3 TML Related Register Map ---------------------------------------------------------------------------------- 10-112 10.6.4 TML Control Registers ---------------------------------------------------------------------------------------- 10-113 10.6.5 TML Counters --------------------------------------------------------------------------------------------------- 10-114 10.6.6 TML Measure Registers -------------------------------------------------------------------------------------- 10-114 10.6.7 Operation of TML Measure Input --------------------------------------------------------------------------- 10-115 CHAPTER 11 A-D CONVERTER 11.1 Outline of A-D Converter ----------------------------------------------------------------------------------------------- 11-2 11.1.1 Conversion Modes --------------------------------------------------------------------------------------------- 11-5 11.1.2 Operation Modes ----------------------------------------------------------------------------------------------- 11-5 11.1.3 Special Operation Modes ------------------------------------------------------------------------------------ 11-8 11.1.4 A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------ 11-11 11.1.5 Sample-and-Hold Function ----------------------------------------------------------------------------------- 11-11 11.2 A-D Converter Related Registers ------------------------------------------------------------------------------------ 11-12 11.2.1 A-D Single Mode Register 0 --------------------------------------------------------------------------------- 11-14 11.2.2 A-D Single Mode Register 1 --------------------------------------------------------------------------------- 11-16 11.2.3 A-D Scan Mode Register 0 ---------------------------------------------------------------------------------- 11-18 11.2.4 A-D Scan Mode Register 1 ---------------------------------------------------------------------------------- 11-20 11.2.5 A-D Conversion Speed Control Register ----------------------------------------------------------------- 11-22 (5) 11.2.6 A-D Disconnection Detection Assist Function Control Register ------------------------------------ 11-23 11.2.7 A-D Disconnection Detection Assist Method Select Register --------------------------------------- 11-24 11.2.8 A-D Successive Approximation Register ----------------------------------------------------------------- 11-27 11.2.9 A-D Comparate Data Register ------------------------------------------------------------------------------ 11-28 11.2.10 10-bit A-D Data Registers ------------------------------------------------------------------------------------ 11-29 11.2.11 8-bit A-D Data Registers -------------------------------------------------------------------------------------- 11-30 11.3 Functional Description of A-D Converter --------------------------------------------------------------------------- 11-31 11.3.1 How to Find Analog Input Voltages ------------------------------------------------------------------------ 11-31 11.3.2 A-D Conversion by Successive Approximation Method ---------------------------------------------- 11-32 11.3.3 Comparator Operation ---------------------------------------------------------------------------------------- 11-33 11.3.4 Calculating the A-D Conversion Time --------------------------------------------------------------------- 11-34 11.3.5 Accuracy of A-D Conversion -------------------------------------------------------------------------------- 11-37 11.4 Inflow Current Bypass Circuit ----------------------------------------------------------------------------------------- 11-39 11.5 Precautions on Using A-D Converter ------------------------------------------------------------------------------- 11-41 CHAPTER 12 SERIAL I/O 12.1 Outline of Serial I/O ----------------------------------------------------------------------------------------------------- 12-2 12.2 Serial I/O Related Registers ------------------------------------------------------------------------------------------ 12-5 12.2.1 SIO Interrupt Related Registers ---------------------------------------------------------------------------- 12-6 12.2.2 SIO Transmit Control Registers ---------------------------------------------------------------------------- 12-13 12.2.3 SIO Transmit/Receive Mode Registers ------------------------------------------------------------------- 12-14 12.2.4 SIO Transmit Buffer Registers ------------------------------------------------------------------------------ 12-17 12.2.5 SIO Receive Buffer Registers ------------------------------------------------------------------------------- 12-18 12.2.6 SIO Receive Control Registers ----------------------------------------------------------------------------- 12-19 12.2.7 SIO Baud Rate Registers ------------------------------------------------------------------------------------ 12-22 12.3 Transmit Operation in CSIO Mode ---------------------------------------------------------------------------------- 12-23 12.3.1 Setting the CSIO Baud Rate --------------------------------------------------------------------------------- 12-23 12.3.2 Initializing CSIO Transmission ------------------------------------------------------------------------------ 12-24 12.3.3 Starting CSIO Transmission --------------------------------------------------------------------------------- 12-26 12.3.4 Successive CSIO Transmission ---------------------------------------------------------------------------- 12-26 12.3.5 Processing at End of CSIO Transmission ---------------------------------------------------------------- 12-27 12.3.6 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-27 12.3.7 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-27 12.3.8 Example of CSIO Transmit Operation -------------------------------------------------------------------- 12-29 12.4 Receive Operation in CSIO Mode ----------------------------------------------------------------------------------- 12-31 12.4.1 Initialization for CSIO Reception ---------------------------------------------------------------------------- 12-31 12.4.2 Starting CSIO Reception ------------------------------------------------------------------------------------- 12-33 12.4.3 Processing at End of CSIO Reception -------------------------------------------------------------------- 12-33 12.4.4 About Successive Reception -------------------------------------------------------------------------------- 12-34 12.4.5 Flags Showing the Status of CSIO Receive Operation ----------------------------------------------- 12-35 12.4.6 Example of CSIO Receive Operation --------------------------------------------------------------------- 12-36 12.5 Precautions on Using CSIO Mode ----------------------------------------------------------------------------------- 12-38 12.6 Transmit Operation in UART Mode --------------------------------------------------------------------------------- 12-39 12.6.1 Setting the UART Baud Rate -------------------------------------------------------------------------------- 12-39 12.6.2 UART Transmit/Receive Data Formats ------------------------------------------------------------------- 12-39 12.6.3 Initializing UART Transmission ----------------------------------------------------------------------------- 12-41 12.6.4 Starting UART Transmission -------------------------------------------------------------------------------- 12-43 (6) 12.6.5 Successive UART Transmission --------------------------------------------------------------------------- 12-43 12.6.6 Processing at End of UART Transmission --------------------------------------------------------------- 12-43 12.6.7 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-43 12.6.8 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-44 12.6.9 Example of UART Transmit Operation -------------------------------------------------------------------- 12-45 12.7 Receive Operation in UART Mode ---------------------------------------------------------------------------------- 12-47 12.7.1 Initialization for UART Reception --------------------------------------------------------------------------- 12-47 12.7.2 Starting UART Reception ------------------------------------------------------------------------------------ 12-49 12.7.3 Processing at End of UART Reception ------------------------------------------------------------------- 12-49 12.7.4 Example of UART Receive Operation -------------------------------------------------------------------- 12-51 12.7.5 Start Bit Detection during UART Reception -------------------------------------------------------------- 12-53 12.8 Fixed Period Clock Output Function -------------------------------------------------------------------------------- 12-54 12.9 Precautions on Using UART Mode ---------------------------------------------------------------------------------- 12-55 CHAPTER 13 CAN MODULE 13.1 Outline of the CAN Module -------------------------------------------------------------------------------------------- 13-2 13.2 CAN Module Related Registers -------------------------------------------------------------------------------------- 13-4 13.2.1 CAN Control Registers ---------------------------------------------------------------------------------------- 13-15 13.2.2 CAN Status Registers ----------------------------------------------------------------------------------------- 13-18 13.2.3 CAN Frame Format Select Registers --------------------------------------------------------------------- 13-21 13.2.4 CAN Configuration Registers -------------------------------------------------------------------------------- 13-22 13.2.5 CAN Timestamp Count Registers -------------------------------------------------------------------------- 13-24 13.2.6 CAN Error Count Registers ---------------------------------------------------------------------------------- 13-25 13.2.7 CAN Baud Rate Prescalers ---------------------------------------------------------------------------------- 13-26 13.2.8 CAN Interrupt Related Registers --------------------------------------------------------------------------- 13-27 13.2.9 CAN Cause of Error Registers ------------------------------------------------------------------------------ 13-45 13.2.10 CAN Mode Registers ------------------------------------------------------------------------------------------ 13-46 13.2.11 CAN DMA Transfer Request Select Register ----------------------------------------------------------- 13-47 13.2.12 CAN Mask Registers ------------------------------------------------------------------------------------------ 13-48 13.2.13 CAN Single-Shot Mode Control Registers --------------------------------------------------------------- 13-52 13.2.14 CAN Message Slot Control Registers --------------------------------------------------------------------- 13-53 13.2.15 CAN Message Slots ------------------------------------------------------------------------------------------- 13-57 13.3 CAN Protocol ------------------------------------------------------------------------------------------------------------- 13-72 13.3.1 CAN Protocol Frames ----------------------------------------------------------------------------------------- 13-72 13.3.2 Data Formats during CAN Transmission/Reception --------------------------------------------------- 13-73 13.3.3 CAN Controller Error States --------------------------------------------------------------------------------- 13-74 13.4 Initializing the CAN Module -------------------------------------------------------------------------------------------- 13-75 13.4.1 Initializing the CAN Module ---------------------------------------------------------------------------------- 13-75 13.5 Transmitting Data Frames --------------------------------------------------------------------------------------------- 13-78 13.5.1 Data Frame Transmit Procedure --------------------------------------------------------------------------- 13-78 13.5.2 Data Frame Transmit Operation ---------------------------------------------------------------------------- 13-79 13.5.3 Transmit Abort Function -------------------------------------------------------------------------------------- 13-80 13.6 Receiving Data Frames ------------------------------------------------------------------------------------------------ 13-81 13.6.1 Data Frame Receive Procedure ---------------------------------------------------------------------------- 13-81 13.6.2 Data Frame Receive Operation ----------------------------------------------------------------------------- 13-82 13.6.3 Reading Out Received Data Frames ---------------------------------------------------------------------- 13-84 (7) 13.7 Transmitting Remote Frames ---------------------------------------------------------------------------------------- 13-86 13.7.1 Remote Frame Transmit Procedure ----------------------------------------------------------------------- 13-86 13.7.2 Remote Frame Transmit Operation ------------------------------------------------------------------------ 13-87 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission ------------- 13-89 13.8 Receiving Remote Frames -------------------------------------------------------------------------------------------- 13-91 13.8.1 Remote Frame Receive Procedure ------------------------------------------------------------------------ 13-91 13.8.2 Remote Frame Receive Operation ------------------------------------------------------------------------ 13-92 13.9 Precautions about CAN Module -------------------------------------------------------------------------------------- 13-95 CHAPTER 14 REAL TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) ------------------------------------------------------------------------ 14-2 14.2 Pin Functions of the RTD ---------------------------------------------------------------------------------------------- 14-3 14.3 Functional Description of the RTD ----------------------------------------------------------------------------------- 14-4 14.3.1 Outline of the RTD Operation ------------------------------------------------------------------------------ 14-4 14.3.2 Operation of RDR (Real-time RAM Content Output) ------------------------------------------------- 14-4 14.3.3 Operation of the WRR (RAM Content Forcible Rewrite) --------------------------------------------- 14-6 14.3.4 Operation of VER (Continuous Monitor) ----------------------------------------------------------------- 14-7 14.3.5 Operation of VEI (Interrupt Request) --------------------------------------------------------------------- 14-7 14.3.6 Operation of RCV (Recover from Runaway) ----------------------------------------------------------- 14-8 14.3.7 Method for Setting a Specified Address when Using the RTD ------------------------------------- 14-9 14.3.8 Resetting the RTD --------------------------------------------------------------------------------------------- 14-10 14.4 Typical Connection with the Host ------------------------------------------------------------------------------------ 14-11 CHAPTER 15 EXTERNAL BUS INTERFACE 15.1 Outline of the External Bus Interface ------------------------------------------------------------------------------- 15-2 15.1.1 External Bus Interface Related Signals ------------------------------------------------------------------ 15-2 15.2 External Bus Interface Related Registers ------------------------------------------------------------------------- 15-4 15.2.1 Port Operation Mode Registers ---------------------------------------------------------------------------- 15-4 15.2.2 Port Peripheral Output Select Register ------------------------------------------------------------------ 15-8 15.2.3 Bus Mode Control Register --------------------------------------------------------------------------------- 15-9 15.3 Read/Write Operations ------------------------------------------------------------------------------------------------- 15-10 15.4 Bus Arbitration ------------------------------------------------------------------------------------------------------------ 15-16 15.5 Typical Connection of External Extension Memory ------------------------------------------------------------- 15-18 15.6 Example of Bus Voltage Settings Using VCC-BUS ------------------------------------------------------------- 15-21 CHAPTER 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller ----------------------------------------------------------------------------------------- 16-2 16.2 Wait Controller Related Registers ----------------------------------------------------------------------------------- 16-4 16.2.1 CS Area Wait Control Registers ---------------------------------------------------------------------------- 16-4 16.3 Typical Operation of the Wait Controller --------------------------------------------------------------------------- 16-6 CHAPTER 17 RAM BACKUP MODE 17.1 Outline of RAM Backup Mode ---------------------------------------------------------------------------------------- 17-2 17.2 Example of RAM Backup when Power is Off -------------------------------------------------------------------------- 17-3 17.2.1 Normal Operating State --------------------------------------------------------------------------------------- 17-3 17.2.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-4 (8) 17.3 Example of RAM Backup for Saving Power Consumption ---------------------------------------------------- 17-5 17.3.1 Normal Operating State --------------------------------------------------------------------------------------- 17-5 17.3.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-6 17.3.3 Precautions to Be Observed at Power-On --------------------------------------------------------------- 17-7 17.4 Exiting RAM Backup Mode (Wakeup) ------------------------------------------------------------------------------ 17-8 CHAPTER 18 OSCILLATOR CIRCUIT 18.1 Oscillator Circuit ---------------------------------------------------------------------------------------------------------- 18-2 18.1.1 Example of an Oscillator Circuit ---------------------------------------------------------------------------- 18-2 18.1.2 XIN Oscillation Stoppage Detection Circuit -------------------------------------------------------------- 18-3 18.1.3 Oscillation Drive Capability Select Function ------------------------------------------------------------- 18-5 18.1.4 System Clock Output Function ------------------------------------------------------------------------------ 18-7 18.1.5 Oscillation Stabilization Time at Power-On -------------------------------------------------------------- 18-7 18.2 Clock Generator Circuit ------------------------------------------------------------------------------------------------ 18-8 CHAPTER 19 JTAG 19.1 Outline of JTAG ---------------------------------------------------------------------------------------------------------- 19-2 19.2 Configuration of the JTAG Circuit ------------------------------------------------------------------------------------ 19-3 19.3 JTAG Registers ---------------------------------------------------------------------------------------------------------- 19-4 19.3.1 Instruction Register (JTAGIR) ------------------------------------------------------------------------------- 19-4 19.3.2 Data Register ---------------------------------------------------------------------------------------------------- 19-5 19.4 Basic Operation of JTAG ---------------------------------------------------------------------------------------------- 19-6 19.4.1 Outline of JTAG Operation ----------------------------------------------------------------------------------- 19-6 19.4.2 IR Path Sequence ---------------------------------------------------------------------------------------------- 19-8 19.4.3 DR Path Sequence -------------------------------------------------------------------------------------------- 19-9 19.4.4 Inspecting and Setting Data Registers -------------------------------------------------------------------- 19-10 19.5 Boundary Scan Description Language ----------------------------------------------------------------------------- 19-11 19.6 Notes on Board Design when Connecting JTAG ---------------------------------------------------------------------- 19-12 19.7 Processing Pins when Not Using JTAG ---------------------------------------------------------------------------- 19-13 CHAPTER 20 POWER SUPPLY CIRCUIT 20.1 Configuration of the Power Supply Circuit ------------------------------------------------------------------------- 20-2 20.2 Power-On Sequence ---------------------------------------------------------------------------------------------------- 20-3 20.2.1 Power-On Sequence when Not Using RAM Backup -------------------------------------------------- 20-3 20.2.2 Power-On Sequence when Using RAM Backup -------------------------------------------------------- 20-4 20.3 Power-Off Sequence ---------------------------------------------------------------------------------------------------- 20-5 20.3.1 Power-Off Sequence when Not Using RAM Backup -------------------------------------------------- 20-5 20.3.2 Power-Off Sequence when Using RAM Backup ------------------------------------------------------- 20-6 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings ------------------------------------------------------------------------------------------- 21-2 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ---------------------------------------------- 21-3 21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz) ------------------- 21-3 21.2.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) ----------------------------------------- 21-5 21.2.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) -------------------------- 21-6 (9) 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz ------------------------------------------------ 21-7 21.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) -------------------- 21-7 21.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ------------------------------------------- 21-9 21.3.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ---------------------------- 21-10 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz -------------------------------------------- 21-11 21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ------ 21-11 21.4.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ---------------------------- 21-13 21.4.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ------------- 21-14 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz ---------------------------------------------- 21-15 21.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V f(XIN) = 8 MHz) -------- 21-15 21.5.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) ------------------------------ 21-17 21.5.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) --------------- 21-18 21.6 Flash Memory Related Characteristics ----------------------------------------------------------------------------- 21-19 21.7 A.C. Characteristics (when VCCE = 5 V) -------------------------------------------------------------------------- 21-20 21.7.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-20 21.7.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-24 21.7.3 A.C. Characteristics -------------------------------------------------------------------------------------------- 21-27 21.8 A.C. Characteristics (when VCCE = 3.3 V) ----------------------------------------------------------------------- 21-36 21.8.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-36 21.8.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-40 21.8.3 A.C. Characteristics -------------------------------------------------------------------------------------------- 21-43 CHAPTER 22 TYPICAL CHARACTERISTICS To be written at a later time --------------------------------------------------------------------------------------------------- 22-2 APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1.1 Dimensional Outline Drawing ------------------------------------------------------------------- Appendix 1-2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32182 Instruction Processing Time ------------------------------------------------------------ Appendix 2-2 APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example Processing of Unused Pins --------------------------------------------------------- Appendix 3-2 APPENDIX 4 SUMMARY OF PRECAUTIONS Appendix 4.1 Precautions about the CPU --------------------------------------------------------------------Appendix 4.1.1 Precautions Regarding Data Transfer -----------------------------------------------Appendix 4.2 Precautions about the Address Space ------------------------------------------------------Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------Appendix 4.3 Precautions about EIT --------------------------------------------------------------------------Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory --------Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------Appendix 4.5.1 Input/output Ports -------------------------------------------------------------------------Appendix 4-2 Appendix 4-2 Appendix 4-3 Appendix 4-3 Appendix 4-3 Appendix 4-3 Appendix 4-4 Appendix 4-4 (10) Appendix 4.6 Precautions about Input/Output Ports --------------------------------------------------Appendix 4.6.1 When Using Input/Output Ports in Output Mode ------------------------------Appendix 4.6.2 About the Port Input Disable Function -------------------------------------------Appendix 4.7 Precautions about the DMAC -------------------------------------------------------------Appendix 4.7.1 About Writing to the DMAC Related Registers ---------------------------------Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer -------------Appendix 4.7.3 About the DMA Interrupt Request Status Register ----------------------------Appendix 4.7.4 About the Stable Operation of DMA Transfer ----------------------------------Appendix 4.8 Precautions about the Multijunction Timers -------------------------------------------Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode -----------------------Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode -----------Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode ------------------------Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes --------Appendix 4.8.5 Precautions on Using TIO PWM Output Mode ---------------------------------Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode ------------------------Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode -------------Appendix 4.8.8 Precautions on Using TIO Continuous Output Mode -------------------------Appendix 4.8.9 Precautions on Using TMS Measure Input --------------------------------------Appendix 4.8.10 Precautions on Using TML Measure Input -------------------------------------Appendix 4.9 Precautions about the A-D Converters -------------------------------------------------Appendix 4.10 Precautions about Serial I/O --------------------------------------------------------------Appendix 4.10.1 Precautions on Using CSIO Mode ------------------------------------------------Appendix 4.10.2 Precautions on Using UART Mode -----------------------------------------------Appendix 4.11 Precautions about RAM Backup Mode ------------------------------------------------Appendix 4.11.1 Precautions to Be Observed at Power-On -------------------------------------Appendix 4.12 Precautions about JTAG ------------------------------------------------------------------Appendix 4.12.1 Notes on Board Design when Connecting JTAG ------------------------------Appendix 4.12.2 Processing Pins when Not Using JTAG -----------------------------------------Appendix 4.13 Precautions about Noise ------------------------------------------------------------------Appendix 4.13.1 Reduction of Wiring Length --------------------------------------------------------Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines --------------Appendix 4.13.3 Processing Analog Input Pin Wiring ---------------------------------------------Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin ---------------------------Appendix 4.13.5 Processing Input/Output Ports ----------------------------------------------------- Appendix 4-4 Appendix 4-4 Appendix 4-4 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-6 Appendix 4-6 Appendix 4-8 Appendix 4-9 Appendix 4-9 Appendix 4-9 Appendix 4-9 Appendix 4-10 Appendix 4-10 Appendix 4-10 Appendix 4-11 Appendix 4-12 Appendix 4-15 Appendix 4-15 Appendix 4-16 Appendix 4-17 Appendix 4-17 Appendix 4-18 Appendix 4-18 Appendix 4-19 Appendix 4-20 Appendix 4-20 Appendix 4-23 Appendix 4-23 Appendix 4-24 Appendix 4-28 (11) This page is blank for reasons of layout. (12) CHAPTER 1 OVERVIEW 1.1 1.2 1.3 1.4 Outline of the 32182 Group Block Diagram Pin Functions Pin Assignments 1 1.1 Outline of the 32182 Group OVERVIEW 1.1 Outline of the 32182 Group The 32182 group (hereafter simply the 32182) belongs to the M32R/ECU series in the M32R family of Renesas microcomputers. For details about the current development status of the 32182, please contact your nearest office of Renesas or its distributor. Table 1.1.1 Product List Type Name M32182F3VFP M32182F3UFP M32182F3TFP M32182F8VFP M32182F8UFP M32182F8TFP ROM Size 384 Kbytes 384 Kbytes 384 Kbytes 1 Mbyte 1 Mbyte 1 Mbyte RAM Size 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Package Type 144-pin LQFP: 144P6Q-A (0.5 mm pitch) 144-pin LQFP: 144P6Q-A (0.5 mm pitch) 144-pin LQFP: 144P6Q-A (0.5 mm pitch) 144-pin LQFP: 144P6Q-A (0.5 mm pitch) 144-pin LQFP: 144P6Q-A (0.5 mm pitch) 144-pin LQFP: 144P6Q-A (0.5 mm pitch) Operating Ambient Temperature –40°C to 125°C (@64 MHz) –40°C to 105°C (@80 MHz) –40°C to 85°C (@80 MHz) –40°C to 125°C (@64 MHz) –40°C to 105°C (@80 MHz) –40°C to 85°C (@80 MHz) 1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) (1) Based on a RISC architecture • The 32182 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in this group of microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to materialize the common instruction set and the high-precision arithmetic operation of the M32R CPU. The 32182 products listed in the above table are built around the M32R-FPU and incorporates flash memory, RAM and various peripheral functions, all integrated into a single chip. • The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store instructions, and various arithmetic/logic operations are executed using register-to-register operation instructions. • The internally has sixteen 32-bit general-purpose registers. The instruction set consists of 100 discrete instructions in total (83 instructions common to the M32R family plus 17 FPU and extended instructions). These instructions are either 16 bits or 32 bits long. • In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions such as Load & Address Update and Store & Address Update. These instructions help to speed up data transfers. (2) Five-stage pipelined processing • The M32R-FPU supports five-stage pipelined instruction processing consisting of Instruction Fetch, Decode, Execute, Memory Access and Write Back (processed in six stages when performing floating-point arithmetic). Not just load/store instructions and register-to-register operation instructions, but also floating-point arithmetic instructions and compound instructions such as Load & Address Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 12.5 ns when f(CPUCLK) = 80 MHz). • Although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation instruction will be executed before that instruction. Using such a facility, which is known as the “out-of-order-completion” mechanism, the M32RFPU is able to control instruction execution without wasting clock cycles. (3) Compact instruction code • The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the 16-bit instruction format especially helps to suppress the code size of a program. • Moreover, the availability of 32-bit instructions makes programming easier and provides higher performance at the same clock speed than in architectures where the address space is segmented. For example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or backward from the currently executed address in one instruction, making programming easy. 1-2 32182 Group User’s Manual (Rev.1.0) 1 1.1.2 Built-in Multiplier/Accumulator (1) Built-in high-speed multiplier OVERVIEW 1.1 Outline of the 32182 Group • The M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU to execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods. (2) DSP-comparable sum-of-products instructions • The M32R-FPU supports the following four types of sum-of-products calculation instructions (or multiplication instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator. (1) (2) (3) (4) 16 high-order bits of register × 16 high-order bits of register 16 low-order bits of register × 16 low-order bits of register Whole 32 bits of register × 16 high-order bits of register Whole 32 bits of register × 16 low-order bits of register • The M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or 32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because these instructions are also executed in one CPUCLK period, when used in combination with highspeed data transfer instructions such as Load & Address Update or Store & Address Update, they enable the M32R-FPU to exhibit data processing capability comparable to that of a DSP. 1.1.3 Built-in Single-precision FPU • The M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754 standards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Division by Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round toward 0, round toward + Infinity and round toward – Infinity) are supported. What’s more, because generalpurpose registers are used to perform floating-point arithmetic, the overhead associated with transferring the operand data can be reduced. 1.1.4 Built-in Flash Memory and RAM • The 32182 contains a RAM that can be accessed with zero wait state, allowing to design a high-speed embedded system. • The internal flash memory can be written to while mounted on a printed circuit board (on-board writing). Use of flash memory facilitates development work, because the chip used at the development stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board. • The internal flash memory can be rewritten as many as 100 times. • The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be superficially mapped into part of the internal flash memory. When combined with the internal RealTime Debugger (RTD) and the M32R family’s common debug interface (Scalable Debug Interface or SDI), this function makes the ROM table data tuning easy. • The internal RAM can be accessed for reading or rewriting data from an external device independently of the M32R-FPU by using the Real-Time Debugger. The external device is communicated using the Real-Time Debugger’s exclusive clock-synchronized serial I/O. 1-3 32182 Group User’s Manual (Rev.1.0) 1 1.1.5 Built-in Clock Frequency Multiplier OVERVIEW 1.1 Outline of the 32182 Group • The 32182 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below. XIN pin (8MHz-10MHz) X8 PLL 1/4 CPUCLK (CPU clock) (64MHz-80MHz) BCLK (peripheral clock) (16MHz-20MHz) Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.2 Clock Functional Block CPUCLK BCLK Clock output (BCLK pin output) Features • CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for the M32R-FPU core, internal flash memory and internal RAM. • Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for the internal peripheral I/O and external data bus. • A clock with the same frequency as f(BCLK) is output from this pin. 1.1.6 Powerful Peripheral Functions Built-in (1) Multijunction timer (MJT) (2) 10-channel DMAC (3) 12-channel A-D converter (ADC) (4) 4-channel high-speed serial I/O (SIO) (5) Real-time debugger (RTD) (6) 8-level interrupt controller (ICU) (7) Three operation modes (8) Wait controller (9) 2-channel Full-CAN (10) M32R family’s common debug function (Scalable Debug Interface or SDI) 1-4 32182 Group User’s Manual (Rev.1.0) 1 1.2 Block Diagram OVERVIEW 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32182. The features of each block are described in Table 1.2.1. M32R-FPU Core (80 MHz) Multiplier/Accumulator (32 bits × 16 bits + 56 bits) Internal Bus Interface DMAC (10 channels) Internal 32-bit bus Single-precision FPU (fully IEEE 754 compliant) Multijunction Timer (37 channels) Internal 32-bit bus Internal Flash Memory (M32182F3: 384 Kbytes) (M32182F8: 1 Mbyte) A-D Converter (A-D0: 10-bit converter, 12 channels) Internal 16-bit bus Serial I/O (4 channels) Internal RAM (64 Kbytes) Interrupt Controller (23 sources, 8 levels) Real-Time Debugger (RTD) Wait Controller PLL Clock Generator External Bus Interface Data Full CAN (2 channels) Internal Power Supply Generator (VDC) Address Input/output ports, 97 lines Figure 1.2.1 Block Diagram of the 32182 1-5 32182 Group User’s Manual (Rev.1.0) 1 Table 1.2.1 Features of the 32182 (1/2) Functional Block M32R-FPU CPU core Features performing floating-point arithmetic) • Internal 32-bit structure of the core • Register configuration General-purpose registers: 32 bits × 16 registers Control registers: 32 bits × 6 registers • Instruction set 16 and 32-bit instruction formats 100 discrete instructions and six addressing modes • Internal multiplier/accumulator (32 bits × 16 bits + 56 bits) • Internal single-precision floating-point arithmetic unit (FPU) RAM • Capacity: 64 Kbytes, accessible with zero wait state OVERVIEW 1.2 Block Diagram • Implementation: Five-stage pipelined instruction processing (processed in six stages when • The internal RAM can be accessed for reading or rewriting data from the outside independently of the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to decrease. Flash memory • Capacity M32182F3: 384 Kbytes, 1M32182F8: 1 Mbyte • One-wait access • Durability: Rewritable 100 times Bus specification • Fundamental bus cycle: 12.5 ns (when f(CPUCLK = 80 MHz) • Logical address space : 4 Gbytes linear • Internal bus specification : Internal 32-bit data bus (for CPU internal flash memory and RAM access) (or accessed in 64 bits when accessing the internal flash memory for instructions) : Internal 16-bit data bus (for internal peripheral I/O access) • Extended external area: Maximum 3 Mbytes (1 Mbytes × 3 blocks during external extension mode) • External data address: 20-bit address • External data bus: 16-bit data bus • Shortest external bus access: 1 BCLK period during read, 1 BCLK period during write Multijunction timer (MJT) • 37-channel multi-functional timer 16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels, 16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels • Flexible timer configuration is possible by interconnecting these timer channels. • Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.) • DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or low level from the TIN pin (These can be used as external DMA transfer request inputs irrespective of timer operation.) DMAC • Number of channels: 10 • Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O and internal RAM are supported. • Capable of advanced DMA transfers when used in combination with internal peripheral I/O • Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN) • DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a transfer on another channel.) • Interrupt request: DMA transfer counter register underflow 1-6 32182 Group User’s Manual (Rev.1.0) 1 Table 1.2.1 Features of the 32182 (2/2) Functional Block A-D converter (ADC) Features • 12 channels: 10-bit resolution A-D converter OVERVIEW 1.2 Block Diagram • Conversion modes: Ordinary conversion modes plus comparator mode • Operation modes: Single conversion mode and n-channel scan mode (n = 1–12) • Sample-and-hold function: Sample-and-hold function can be enabled or disabled as necessary. • A-D disconnection detection assist function: Influences of the analog input voltage leakage from any preceding channel during scan mode operation are suppressed. • An inflow current bypass circuit is built-in. • Can generate an interrupt or start DMA transfer upon completion of A-D conversion. • Either 8 or 10-bit conversion results can be read out. • Interrupt request: Completion of A-D conversion • DMA transfer request: Completion of A-D conversion Serial I/O (SIO) • 4-channel serial I/O • Can be chosen to be clock-synchronized serial I/O or UART. • Data can be transferred at high speed (2 Mbits per second during clock-synchronized mode or 156 Kbits per second during UART mode when f(BCLK) = 20 MHz). • Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed • DMA transfer request: Reception completed or transmit buffer empty CAN • 16 message slots × 2 blocks • Compliant with CAN specification 2.0B active. • Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off or single shot • DMA transfer request: Failed to send, transmission completed or reception completed Real-Time Debugger (RTD) • Internal RAM can be rewritten or monitored independently of the CPU by entering a command from the outside. • Comes with exclusive clock-synchronized serial ports. • Interrupt request: RTD interrupt command input Interrupt Controller (ICU) • Controls interrupt requests from the internal peripheral I/O. • Supports 8-level interrupt priority including an interrupt disabled state. • External interrupt: 11 sources (SBI#, TIN0,TIN3, TIN16-TIN23) • TIN pin input sensing: Rising, falling or both edges or high or low level Wait Controller PLL Clock • Controls wait states for access to the extended external area. • Insertion of 0–7 wait states by setting up in software + wait state extension by entering WAIT# signal • A multiply-by-8 clock generating circuit • Maximum external input clock frequency (XIN) is 10.0 MHz. • CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM The maximum CPU clock is 80 MHz (when f(XIN) = 10 MHz). • BCLK: Operating clock for the internal peripheral I/O and external data bus The maximum peripheral clock is 20 MHz (peripheral module access when f(XIN) = 10 MHz). • Clock output (BCLK pin output): A clock with the same frequency as BCLK is output from this pin. JTAG VDC Ports • Boundary scan function • Internal power supply generating circuit: Generates the internal power supply (2.5 V) from an external single power supply (5 or 3.3 V). • Input/output pins: 97 pins • The port input threshold can be set in a program to one of three levels individually for each port group (with or without Schmitt circuit, selectable). 1-7 32182 Group User’s Manual (Rev.1.0) 1 1.3 Pin Functions OVERVIEW 1.3 Pin Functions Figure 1.3.1 shows the 32182’s pin function diagram. Pin functions are described in Table 1.3.1. OSC-VCC XIN XOUT Clock VCNT OSC-VCC OSC-VSS Reset RESET# MOD0 Mode MOD1 FP Data bus Port 0 Port 1 Port 2 Port 3 Address bus P41/BLW#/BLE# P42/BHW#/BHE# Bus control Port 4 P43/RD# P44/CS0# P45/CS1# P46/A13, P47/A14 Port 6 P61-P63 P70/BCLK/WR# Bus control P71/WAIT# P72/HREQ# P73/HACK# Port 7 P74/RTDTXD P76/RTDACK P77/RTDCLK Interrupt controller SBI# AD0IN0-AD0IN11 AVCC0 A-D converter AVSS0 VREF0 VDDE EXCVDD VCC-BUS 2 12 P75/RTDRXD 2 P00/DB0-P07/DB7 P10/DB8-P17/DB15 P20/A23-P27/A30 P30/A15-P37/A22 8 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 5 P93/TO16-P97/TO20 P100/TO8 P101/TO9/TXD3 Port 10 P102/TO10/CTX1 5 VCCE Port 8 Serial I/O VCCE Port 9 Multijunction timer 8 8 8 VCC-BUS P103/TO11-P107/TO15 P110/TO0-P117/TO7 P124/TCLK0-P127/TCLK3 P130/TIN16-P134/TIN20 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23 CAN Port 13 Port 11 Port 12 Serial I/O 8 4 5 32182 Group 2 P150/TIN0, P153/TIN3 P174/TXD2 P175/RXD2 P220/CTX0 P221/CRX0 Port 15 Port 17 Serial I/O 3 VCCE VCC-BUS CAN Port 22 Address bus Bus control VCC-BUS P224/A11/CS2# P225/A12/CS3# VCCE RTD JTMS VCCE JTCK JTRST JTDO JTDI JTAG 7 4 2 VSS VCCE EXCVCC Note • The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low. • VCCE : Operates with the VCCE power supply VCC-BUS : Operates with the VCC-BUS power supply OSC-VCC : Operates with the OSC-VCC power supply Figure 1.3.1 Pin Function Diagram 1-8 32182 Group User’s Manual (Rev.1.0) 1 Table 1.3.1 Description of Pin Functions (1/5) Type Power supply Pin Name VCCE EXCVCC VCC-BUS VDDE EXCVDD VSS Clock XIN, XOUT Signal Name Main power supply Input/Output Description – Internal power supply – Bus power supply RAM power supply Internal power supply of RAM Ground Clock input Clock output – Input Output – – – OVERVIEW 1.3 Pin Functions Power supply for the device (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). This pin connects an external capacitor. Power supply for the bus control pins (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). Backup power supply for the internal RAM (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). This pin connects an external capacitor for the internal power supply of the internal RAM. Connect all VSS pins to ground (GND). These are clock input/output pins. A PLL-based ×8 frequency multiplier is included, which accepts as input a clock whose frequency is 1/8 of the internal CPU clock frequency. (XIN input is 10 MHz when f(CPUCLK) = 80 MHz.) BCLK System clock Output This pin outputs a clock whose frequency is twice that of the external input clock (XIN). (BCLK output is 20 MHz when f(CPUCLK) = 80 MHz.) Use this clock to synchronize the operation of external devices. OSC-VCC OSC-VSS VCNT Reset Mode RESET# MOD0, MOD1 Clock power supply – Clock ground PLL control Reset Mode – – Input Input Power supply for the oscillator circuit. Connect OSC-VCC to the main power supply. Connect OSC-VSS to ground. Connect a resistor and capacitor for control of the PLL circuit. Reset input pin for the internal circuit. Set the microcomputer’s operation mode. MOD0 0 0 1 1 MOD1 0 1 0 1 Mode Single-chip mode External extension mode Processor mode (Boot mode) (Note 1) (Settings inhibited) Flash protect Address bus FP A11–A30 Flash protect Address bus Input Output This special pin protects the flash memory against rewrites in hardware. Twenty address lines (A11–A30) are included that support up to 2 MB of memory space per chip select. However, A11 and A12 are shared with CS#2 and CS#3, respectively. A31 is not output. Note 1: Boot mode requires that the FP pin should be at the high level. For details about boot mode, see Chapter 6, “Internal Memory.” 1-9 32182 Group User’s Manual (Rev.1.0) 1 Table 1.3.1 Description of Pin Functions (2/5) Type Data bus Pin Name DB0–DB15 Signal Name Data bus Input/Output Description OVERVIEW 1.3 Pin Functions Input/output This 16-bit data bus is used to connect external devices. When writing in byte units during a write cycle, the output data at the invalid byte position is undefined. During a read cycle, data on the entire 16-bit bus is always read in. However, only the data at the valid byte position is transferred into the internal circuit. Bus control CS0#–CS3# Chip select RD# WR# Read Write Output Output Output Output These are chip select signals for external devices. This signal is output when reading an external device. This signal is output when writing to an external device. When writing to an external device, this signal indicates the valid byte position to which data is transferred. BHW# and BLW# correspond to the upper address side (bits 0–7 are valid) and the lower address side (bits 8–15 are valid), respectively. BHW#/BLW# Byte high/low write BHE# BLE# WAIT# HREQ# Byte high enable Byte low enable Wait Hold request Output Output Input Input During an external device access, this signal indicates that the high-order data (bits 0–7) is valid. During an external device access, this signal indicates that the low-order data (bits 8–15) is valid. When accessing an external device, a low-level input on WAIT# pin extends the wait cycle. This input is used by an external device to request control of the external bus. A low-level input on HREQ# pin places the CPU in a hold state. HACK# Multijunction timer TIN0, TIN3, TIN16–TIN23 TO0–TO20 TCLK0 –TCLK3 Hold acknowledge Timer input Timer output Timer clock Output Input Output Input This signal notifies that the CPU has entered a hold state and relinquished control of the external bus. Input pins for the multijunction timer. Output pins for the multijunction timer. Clock input pins for the multijunction timer. 1-10 32182 Group User’s Manual (Rev.1.0) 1 Table 1.3.1 Description of Pin Functions (3/5) Type A-D converter Pin Name AVCC0 AVSS0 AD0IN0 –AD0IN11 VREF0 Interrupt controller Serial I/O SCLKI0/ SCLKO0 SBI# Reference voltage input System break interrupt UART transmit/receive clock output or CSIO transmit/receive clock input/output Input Input Signal Name Analog power supply Analog ground Analog input Input/Output Description – – Input OVERVIEW 1.3 Pin Functions AVCC0 is the power supply for the A-D0 converter. Connect AVCC0 to the power supply rail. AVSS0 is the analog ground for the A-D0 converter. Connect AVSS0 to ground. 12-channel analog input pins for the A-D0 converter. VREF0 is the reference voltage input pin for the A-D0 converter. This is the system break interrupt (SBI) input pin for the interrupt controller. Input/output When channel 0 is in UART mode: This pin outputs a clock derived from BRG output by dividing it by 2. When channel 0 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. SCLKI1/ SCLKO1 UART transmit/receive clock output or CSIO transmit/receive clock input/output Input/output When channel 1 is in UART mode: This pin outputs a clock derived from BRG output by dividing it by 2. When channel 1 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. 1-11 32182 Group User’s Manual (Rev.1.0) 1 Table 1.3.1 Description of Pin Functions (4/5) Type Serial I/O Pin Name TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 Real-time debugger (RTD) RTDTXD RTDRXD RTDCLK RTDACK Signal Name Transmit data Received data Transmit data Received data Transmit data Received data Transmit data Received data RTD transmit data RTD received data RTD clock input RTD acknowledge Input/Output Description Output Input Output Input Output Input Output Input Output Input Input Output OVERVIEW 1.3 Pin Functions Transmit data output pin for serial I/O channel 0. Received data input pin for serial I/O channel 0. Transmit data output pin for serial I/O channel 1. Received data input pin for serial I/O channel 1. Transmit data output pin for serial I/O channel 2. Received data input pin for serial I/O channel 2. Transmit data output pin for serial I/O channel 3. Received data input pin for serial I/O channel 3. Serial data output pin for the real-time debugger. Serial data input pin for the real-time debugger. Serial data transmit/receive clock input pin for the real-time debugger. A low-level pulse is output from this pin synchronously with the start clock for the real-time debugger’s serial data output word. The low-level pulse width indicates the type of command/ data received by the real-time debugger. CAN JTAG CTX0, CTX1 Transmit data CRX0, CRX1 Received data JTMS JTCK JTRST JTDI JTDO Test mode select Test clock Test reset Test data input Test data output Output Input Input Input Input Input Output This pin outputs data from the CAN module. This pin accepts as input the data for the CAN module. Test mode select input to control the state transition of the test circuit. Clock input for the debug module and test circuit. Test reset input to initialize the test circuit asynchronously with device operation. This pin accepts as input the test instruction code or test data that is serially received. This pin outputs the test instruction code or test data serially. 1-12 32182 Group User’s Manual (Rev.1.0) 1 Table 1.3.1 Description of Pin Functions (5/5) Type Input/output ports (Note 1) Pin Name P00–P07 P10–P17 P20–P27 P30–P37 P41–P47 P61–P63 P70–P77 P82–P87 P93–P97 P100–P107 P110–P117 P124–P127 P130–P137 P150–P153 P174, P175 P224, P225 Signal Name Input/output port 0 Input/output port 1 Input/output port 2 Input/output port 3 Input/output port 4 Input/output port 6 Input/output port 7 Input/output port 8 Input/output port 9 Input/output port 10 Input/output port 11 Input/output port 12 Input/output port 13 Input/output port 15 Input/output port 17 Input/Output Description Input/output Programmable input/output port. OVERVIEW 1.3 Pin Functions P220, P221, Input/output port 22 Note 1: • Input/output port 5 is reserved for future use. • P221 is input-only port. • Input/output functions cannot be used for the ports listed below, because no external pins are available for these pins. P65-P67 P140-P147 P151, P152, P154-P157 P160-P167 P172, P173, P176, P177 P180-P187 P190-P197 P200-P203 P210-P217 P222, P223, P226, P227 1-13 32182 Group User’s Manual (Rev.1.0) 1 1.4 Pin Assignments OVERVIEW 1.4 Pin Assignments Figure 1.4.1 shows the 32182’s pin assignment diagram. A pin assignment table is shown in Table 1.4.1. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 VSS VCCE P44/CS0# P45/CS1# P224/A11/CS2# P225/A12/CS3# P46/A13 P47/A14 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 P20/A23 P21/A24 P22/A25 P23/A26 P24/A27 P25/A28 P26/A29 P27/A30 VCC-BUS VSS P93/TO16 P94/TO17 P95/TO18 P96/TO19 P174/TXD2 P175/RXD2 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P12/DB10 P11/DB9 P10/DB8 P07/DB7 P06/DB6 P05/DB5 P04/DB4 P03/DB3 P02/DB2 P01/DB1 P00/DB0 P73/HACK# P72/HREQ# P71/WAIT# P70/BCLK/WR# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# VCC-BUS VSS 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 32182 Group 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 P97/TO20 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 EXCVCC VCCE VSS VSS SBI# P63 P62 P61 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 VREF0 AVCC0 Note: • The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low. Figure 1.4.1 Pin Assignment Diagram (Top View) P150/TIN0 P153/TIN3 P130/TIN16 P131/TIN17 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23 P220/CTX0 P221/CRX0 VCCE VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI JTDO JTRST JTCK JTMS P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Package: 144P6Q-A (0.5 mm pitch) 1-14 32182 Group User’s Manual (Rev.1.0) 1 OVERVIEW 1.4 Pin Assignments The pins directed for input go to a high-impedance state (Hi-z) when reset. The term “when reset” means that input on RESET# pin is held low (the device remains reset), and that the RESET# pin is released back high (the device comes out of reset). Table 1.4.1 Pin Assignments of the 32182 (1/4) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 P150/TIN0 P153/TIN3 P130/TIN16 P131/TIN17 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23 P220/CTX0 P221/CRX0 VCCE VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI (Note 1) JTDO (Note 1) JTRST (Note 1) JTCK (Note 1) JTMS (Note 1) P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 Function Symbol Port P150 P153 P130 P131 P132 P133 P134 P135 P136 P137 P220 P221 P74 P75 P76 P77 P100 P101 P102 P103 P104 Other than port TIN0 TIN3 TIN16 TIN17 TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 CTX0 CRX0 VCCE VCNT OSC-VCC XIN OSC-VSS XOUT RESET# RTDTXD RTDRXD RTDACK RTDCLK JTDI JTDO JTRST JTCK JTMS TO8 TO9 TO10 TO11 TO12 Other than port RXD3 CRX1 TXD3 CTX1 Type Condition Function Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Pin State When Reset Type Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input Input Input Input Input Output Input Input Input Input Input Input Input Input State during State at reset release reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z XOUT Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z XOUT Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P150 P153 P130 P131 P132 P133 P134 P135 P136 P137 P220 P221 VCCE VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P74 P75 P76 P77 JTDI JTDO JTRST JTCK JTMS P100 P101 P102 P103 P104 Input Input Output Input Input/output Input/output Input/output Input/output Input Output Input Input Input Input/output Input/output Input/output Input/output Input/output 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 P105/TO13 P106/TO14 P107/TO15 AVCC0 VREF0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AVSS0 AD0IN8 AD0IN9 AD0IN10 AD01N11 P105 P106 P107 - TO13 TO14 TO15 AVCC0 VREF0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AVSS0 AD0IN8 AD0IN9 AD0IN10 AD01N11 - Input/output Input/output Input/output P105 P106 P107 AVCC0 VREF0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AVSS0 AD0IN8 AD0IN9 AD0IN10 AD01N11 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Input Input Input Input Input Input Input Input Input Input Input Input Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin. 1-15 32182 Group User’s Manual (Rev.1.0) 1 Table 1.4.1 Pin Assignments of the 32182 (2/4) Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 P61 P62 P63 SBI# VSS VSS VCCE EXCVCC P124/TCLK0 P125/TCLK1 P126/TCLK2 P127/TCLK3 P110/TO0 P111/TO1 P112/TO2 P113/TO3 P114/TO4 P115/TO5 P116/TO6 P117/TO7 P97/TO20 P96/TO19 P95/TO18 P94/TO17 P93/TO16 VSS VCC-BUS P27/A30 Function Symbol Port P61 P62 P63 P124 P125 P126 P127 P110 P111 P112 P113 P114 P115 P116 P117 P97 P96 P95 P94 P93 P27 SBI# VSS VSS VCCE EXCVCC TCLK0 TCLK1 TCLK2 TCLK3 TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TO20 TO19 TO18 TO17 TO16 VSS VCC-BUS A30 Other than port Type Condition Function Input/output Input/output Input/output OVERVIEW 1.4 Pin Assignments Pin State When Reset Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output State during State at reset release reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z P61 P62 P63 SBI# VSS VSS VCCE EXCVCC P124 P125 P126 P127 P110 P111 P112 P113 P114 P115 P116 P117 P97 P96 P95 P94 P93 VSS VCC-BUS During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output P27 A30 P26 A29 P25 A28 P24 A27 P23 A26 P22 A25 P21 A24 P20 A23 P37 A22 P36 A21 P35 A20 P34 A19 80 P26/A29 P26 A29 - Input/output 81 P25/A28 P25 A28 - Input/output 82 P24/A27 P24 A27 - Input/output 83 P23/A26 P23 A26 - Input/output 84 P22/A25 P22 A25 - Input/output 85 P21/A24 P21 A24 - Input/output 86 P20/A23 P20 A23 - Input/output 87 P37/A22 P37 A22 - Input/output 88 P36/A21 P36 A21 - Input/output 89 P35/A20 P35 A20 - Input/output 90 P34/A19 P34 A19 - Input/output 1-16 32182 Group User’s Manual (Rev.1.0) 1 Table 1.4.1 Pin Assignments of the 32182 (3/4) Pin No. Function Symbol Port Other than port A18 Other than port Type Condition Function During single-chip and external extension modes During processor mode 92 P32/A17 P32 A17 Input/output OVERVIEW 1.4 Pin Assignments Pin State When Reset Type Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Input Input Input Input State during State at reset release reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z High level Hi-z High level Hi-z Hi-z Hi-z Hi-z Hi-z 91 P33/A18 P33 P33 A18 P32 A17 P31 A16 P30 A15 P47 A14 P46 A13 P225 A12 P224 A11 P45 CS1# P44 CS0# VCCE VSS P87 P86 P85 P84 P83 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 93 P31/A16 P31 A16 - Input/output 94 P30/A15 P30 A15 - Input/output 95 P47/A14 P47 A14 - Input/output 96 P46/A13 P46 A13 - Input/output 97 P225/A12/CS3# P225 A12 CS3# Input/output 98 P224/A11/CS2# P224 A11 CS2# Input/output 99 P45/CS1# P45 CS1# - Input/output 100 P44/CS0# 101 VCCE 102 VSS 103 P87/SCLKI1/SCLKO1 104 P86/RXD1 105 P85/TXD1 106 P84/SCLKI0/SCLKO0 107 P83/RXD0 P44 P87 P86 P85 P84 P83 CS0# VCCE VSS SCLKI1 RXD1 TXD1 SCLKI0 RXD0 SCLKO1 SCLKO0 - Input/output Input/output Input/output Input/output Input/output Input/output 108 P82/TXD0 109 P174/TXD2 110 P175/RXD2 111 FP 112 MOD0 113 MOD1 114 EXCVDD 115 VSS 116 EXCVCC 117 VDDE 118 VSS 119 VCCE 120 P17/DB15 P82 P174 P175 P17 TXD0 TXD2 RXD2 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE DB15 - Input/output Input/output Input/output P82 P174 P175 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode P17 DB15 P16 DB14 P15 DB13 P14 DB12 Input Input Input Input Input Input Input Input/output Input Input/output Input Input/output Input Input/output Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Input Input Input Input/output 121 P16/DB14 P16 DB14 - Input/output 122 P15/DB13 P15 DB13 - Input/output 123 P14/DB12 P14 DB12 - Input/output 1-17 32182 Group User’s Manual (Rev.1.0) 1 Table 1.4.1 Pin Assignments of the 32182 (4/4) Pin No. Function Symbol Port Other than port DB11 Other than port Type Condition Function During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode P13 DB11 P12 DB10 P11 DB9 P10 DB8 P07 DB7 P06 DB6 P05 DB5 P04 DB4 OVERVIEW 1.4 Pin Assignments Pin State When Reset Type Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output State during reset State at reset release 124 P13/DB11 P13 Input/output Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z 125 P12/DB10 P12 DB10 - Input/output 126 P11/DB9 P11 DB9 - Input/output 127 P10/DB8 P10 DB8 - Input/output 128 P07/DB7 P07 DB7 - Input/output 129 P06/DB6 P06 DB6 - Input/output 130 P05/DB5 P05 DB5 - Input/output 131 P04/DB4 P04 DB4 - Input/output 132 P03/DB3 P03 DB3 - Input/output P03 DB3 P02 DB2 P01 DB1 P00 DB0 P73 P72 P71 P70 Input Input/output Input Input/output Input Input/output Input Input/output Input Input Input Input Input Output Input Output Input Output - Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z High level Hi-z High level Hi-z High level - 133 P02/DB2 P02 DB2 - Input/output 134 P01/DB1 P01 DB1 - Input/output 135 P00/DB0 136 P73/HACK# 137 P72/HREQ# 138 P71/WAIT# 139 P70/BCLK/WR# 140 P43/RD# P00 P73 P72 P71 P70 P43 DB0 HACK# HREQ# WAIT# BCLK RD# WR# - Input/output Input/output Input/output Input/output Input/output During processor mode Input/output P43 RD# P42 BHE#/BHE# P41 BLE#/BLE# VCC-BUS - During external extension and processor modes During processor mode During external extension and processor modes During processor mode During external extension and processor modes 141 P42/BHW#/BHE# P42 BHW# BHE# Input/output 142 P41/BLW#/BLE# 143 VCC-BUS 144 VSS P41 - BLW# VCC-BUS VSS BLE# - Input/output - 1-18 32182 Group User’s Manual (Rev.1.0) CHAPTER 2 CPU 2.1 2.2 2.3 2.4 2.5 2.6 2.7 CPU Registers General-purpose Registers Control Registers Accumulator Program Counter Data Formats Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution 2 2.1 CPU Registers CPU 2.1 CPU Registers The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration. 2.2 General-purpose Registers The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data and base address, as well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depending on the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW). After reset, the value of the general-purpose registers is undefined. b0 b31 b0 b31 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note 1) Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW. Figure 2.2.1 General-purpose Registers 2.3 Control Registers There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floatingpoint Status Register (FPSR). The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction. CRn b0 CR0 CR1 CR2 CR3 CR6 CR7 b31 PSW CBR SPI SPU BPC FPSR Processor Status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer Backup PC Floating-point Status Register Notes: • CRn (n = 0-3, 6 and 7) denotes the control register number. • The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. • The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instructions. Figure 2.3.1 Control Registers 2-2 32182 Group User’s Manual (Rev.1.0) 2 2.3.1 Processor Status Word Register: PSW (CR0) b0 0 CPU 2.3 Control Registers 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 b16 BSM ? 17 BIE ? 18 0 19 0 20 0 21 0 22 0 23 BC ? 24 SM 0 25 IE 0 26 0 27 0 28 0 29 0 30 0 b31 C 0 BPSW field PSW field b 0–15 16 17 18–22 23 24 25 26–30 31 Bit Name No function assigned. Fix to "0". BSM Backup SM Bit BIE Backup IE Bit No function assigned. Fix to "0". BC Backup C Bit SM Stack Mode Bit IE Interrupt Enable Bit No function assigned. Fix to "0". C Condition Bit Indicates carry, borrow or overflow resulting from operations (instruction dependent) Saves value of C bit when EIT occurs 0: Uses R15 as the interrupt stack pointer 1: Uses R15 as the user stack pointer 0: Does not accept interrupt 1: Accepts interrupt Saves value of SM bit when EIT occurs Saves value of IE bit when EIT occurs Function R 0 R R 0 R R R 0 R W 0 W W 0 W W W 0 W The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit. The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the Backup Condition (BC) bit. After reset, BSM, BIE and BC are undefined. All other bits are "0". 2-3 32182 Group User’s Manual (Rev.1.0) 2 2.3.2 Condition Bit Register: CBR (CR1) CPU 2.3 Control Registers The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) After reset, the value of CBR is H’0000 0000. b0 b31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C CBR 0 2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3) The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack pointer. These registers can be accessed as the general-purpose register R15. R15 switches between representing the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW. After reset, the values of the SPI and SPU are undefined. b0 b31 SPI SPI b0 b31 SPU SPU 2.3.4 Backup PC: BPC (CR6) The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to "0". When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the next instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always returns to the word-aligned address.) After reset, the value of the BPC is undefined. b0 b31 BPC BPC 0 2-4 32182 Group User’s Manual (Rev.1.0) 2 2.3.5 Floating-point Status Register: FPSR (CR7) b0 FS 0 CPU 2.3 Control Registers 1 FX 0 2 FU 0 3 FZ 0 4 FO 0 5 FV 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 b16 0 17 EX 0 18 EU 0 19 EZ 0 20 EO 0 21 EV 0 22 0 23 DN 1 24 CE 0 25 CX 0 26 CU 0 27 CZ 0 28 CO 0 29 CV 0 30 0 b31 RM 0 b 0 1 Bit Name Function R R R W – W FS Reflects the logical sum of FU, FZ, FO and FV. Floating-point Exception Summary Bit FX Inexact Exception Flag FU Underflow Exception Flag FZ Zero Divide Exception Flag FO Overflow Exception Flag FV Invalid Operation Exception Flag No function assigned. Fix to "0". EX Inexact Exception Enable Bit EU Underflow Exception Enable Bit EZ Zero Divide Exception Enable Bit EO Overflow Exception Enable Bit EV Invalid Operation Exception Enable Bit No function assigned. Fix to "0". DN Denormalized Number Zero Flush Bit (Note 2) CE Unimplemented Operation Exception Cause Bit CX Inexact Exception Cause Bit 0: Handle the denormalized number as a denormalized number. 1: Handle the denormalized number as zero. 0: No unimplemented operation exception occurred. 1: An unimplemented operation exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 0: No inexact exception occurred. 1: An inexact exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 0: Mask EIT processing to be executed when an inexact exception occurs. 1: Execute EIT processing when an inexact exception occurs. 0: Mask EIT processing to be executed when an underflow exception occurs. 1: Execute EIT processing when an underflow exception occurs. 0: Mask EIT processing to be executed when a zero divide exception occurs. 1: Execute EIT processing when a zero divide exception occurs. 0: Mask EIT processing to be executed when an overflow exception occurs. 1: Execute EIT processing when an overflow exception occurs. 0: Mask EIT processing to be executed when an invalid operation exception occurs. 1: Execute EIT processing when an invalid operation exception occurs. Set to "1" when an inexact exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when an underflow exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when a zero divide exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when an overflow exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when an invalid operation exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. 2 R W 3 R W 4 R W 5 R W 6–16 17 18 0 R R 0 W W 19 R W 20 R W 21 R W 22 23 0 R 0 W 24 R (Note 3) 25 R (Note 3) 2-5 32182 Group User’s Manual (Rev.1.0) 2 26 CU Underflow Exception Cause Bit CZ Zero Divide Exception Cause Bit CO Overflow Exception Cause Bit 27 CPU 2.3 Control Registers 0: No underflow exception occurred 1: An underflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 0: No zero divide exception occurred. 1: A zero divide exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 0: No overflow exception occurred. 1: An overflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". R (Note 3) R (Note 3) 28 R (Note 3) 29 CV 0: No invalid operation exception occurred. Invalid Operation Exception Cause Bit 1: An invalid operation exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". RM Rounding Mode Selection Bit 00: Round to nearest 01: Round toward Zero 10: Round toward + Infinity 11: Round toward – Infinity R (Note 3) 30, 31 R W Note 1: The phrase “If EIT processing unexecuted” means whenever one of the exceptions occurs, enable bits 17 to 21 are set to "0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In this case, these two flags do not change state regardless of the enable bits settings. Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented exception occurs. Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had before the write). 2-6 32182 Group User’s Manual (Rev.1.0) 2 2.4 Accumulator CPU 2.4 Accumulator The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction “MUL,” in which case the accumulator value is destroyed by instruction execution. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0–31) and the low-order 32 bits (bits 32–63), respectively. Use the MVFACHI, MVFACLO and MVFACMI instructions for reading data from the accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0–31), the low-order 32 bits (bits 32–63) and the middle 32 bits (bits 16–47), respectively. After reset, the value of accumulator is undefined. (Note 1) b0 78 15 16 Read range of MVFACMI instruction 31 32 47 48 b63 ACC Write and read ranges of MVTACHI and MVFACHI instructions Write and read ranges of MVTACLO and MVFACLO instructions Note 1: When read, bits 0 to 7 always show the sign-extended value of the value of bit 8. Writing to this bit field is ignored. 2.5 Program Counter The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R FPU instruction starts with even-numbered addresses, the LSB (bit 31) is always "0". After reset, the value of PC is H’0000 0000. b0 b31 PC PC 0 2-7 32182 Group User’s Manual (Rev.1.0) 2 2.6 Data Formats 2.6.1 Data Types CPU 2.6 Data Formats The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16 and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2’s complements. b0 b7 Signed byte (8-bit) integer S b0 b7 Unsigned byte (8-bit) integer b0 b15 Signed halfword (16-bit) integer Unsigned halfword (16-bit) integer S b0 b15 b0 b31 Signed word (32-bit) integer S b0 b31 Unsigned word (32-bit) integer b0 b1 b8 b9 b31 Single-precision floating-point number S E F S: Sign bit; E: Exponent field; F: Fraction field Figure 2.6.1 Data Types 2-8 32182 Group User’s Manual (Rev.1.0) 2 2.6.2 Data Formats (1) Data formats in registers CPU 2.6 Data Formats The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded in the register. When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions, respectively. b0 Sign-extended (LDB instruction) or zero-extended (LDUB instruction) From memory (LDB, LDUB instructions) 24 b31 Rn Sign-extended (LDH instruction) or Byte From memory (LDH, LDUH instructions) b31 b0 zero-extended (LDUH instruction) 16 Rn Halfword From memory (LD instruction) b0 b31 Rn Word b0 24 b31 Rn Byte To memory (STB instruction) b0 16 b31 Rn Halfword To memory (STH instruction) b0 b31 Rn Word To memory (ST instruction) Figure 2.6.2 Data Formats in Registers 2-9 32182 Group User’s Manual (Rev.1.0) 2 (2) Data formats in memory CPU 2.6 Data Formats The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word boundary, an address exception occurs. Address +0 address b0 +1 address 78 +2 address +3 address b31 15 16 23 24 Byte Byte Byte Byte Byte b0 15 b31 Halfword Halfword Halfword b0 b31 Word Word Figure 2.6.3 Data Formats in Memory (3) Endian The diagrams below show a general endian system and the endian adopted for the M32R family microcomputers. Bit endian (H'01) Byte endian (H'01234567) Big endian B'0000001 b0 b7 H'01 HH H'23 HL H'45 LH H'67 LL Little endian B'0000001 b7 b0 H'67 LL H'45 LH H'23 HL H'01 HH Note: • Even when bits are arranged in big endian, H'01 is not B'10000000. Figure 2.6.4 General Endian System 2-10 32182 Group User’s Manual (Rev.1.0) 2 Renesas microcomputer family name Endian (bit/byte) Address Data arrangement Bit number Example: 0x01234567 +0 CPU 2.6 Data Formats 7700 and M16C families M32R family Little/little +1 +2 +3 +0 Little/big +1 +2 +3 +0 Big/big +1 +2 +3 LL LH HL HH HH HL LH LL HH HL LH LL 7–0 15–8 23–16 31–24 31–24 23–16 15–8 7–0 0–7 8–15 16–23 24–31 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 Note: • The M32R family uses the big endian for both bits and bytes. Figure 2.6.5 Endian Adopted for the M32R Family (4) Transfer instructions • Constant transfer LD24 LDI LDI Rdest, #imm24 Rdest, #imm16 Rdest, #imm8 LD24 Rdest, #imm24 imm24 b0 b23 Rdest 00 b0 8 b31 SETH Rdest, #imm16 SETH Rdest, #imm16 imm16 b0 b15 Rdest b0 15 00 00 b31 • Register to register transfer MV MV Rdest, Rsrc Rsrc b0 b31 Rdest, Rsrc Rdest b0 b31 • Control register transfer MVTC Rsrc, CRdest MVFC Rdest, CRsrc MVTC Rsrc, CRdest Rsrc b0 b31 CRdest b0 b31 Note: • The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction. Figure 2.6.6 Transfer Instructions 2-11 32182 Group User’s Manual (Rev.1.0) 2 (5) Transfer from memory (signed) to registers CPU 2.6 Data Formats • Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc label Memory Rdest +0 +1 +2 +3 Register b0 b31 • Signed 16 bits label LD24 Rsrc, #label LDH Rdest, @Rsrc Rdest +0 +1 +2 +3 Determined by MSB 0: Positive number 1: Negative number 00 FF b0 00 FF b31 • Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc label Rdest +3 +0 +1 +2 Determined by MSB 0: Positive number 1: Negative number 00 FF b0 00 FF 00 FF b31 Figure 2.6.7 Transfer from Memory (Signed) to Registers (6) Transfer from memory (unsigned) to registers Memory • Unsigned 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc label Rdest Register +0 +1 +2 +3 b0 b31 • Unsigned 16 bits LD24 Rsrc, #label LDUH Rdest, @Rsrc label Rdest 00 +0 +1 +2 +3 b0 00 b31 • Unsigned 8 bits LD24 Rsrc, #label LDUB Rdest, @Rsrc label Rdest 00 +0 +1 +2 +3 b0 00 00 b31 Figure 2.6.8 Transfer from Memory (Unsigned) to Registers 2-12 32182 Group User’s Manual (Rev.1.0) 2 (7) Notes on data transfer CPU 2.6 Data Formats When transferring data, be aware that data arrangements in registers and memory are different. Data in registers Data in memory • Word data (32 bits) (R0–R15) HH HL LH LL +0 HH +1 HL +2 LH +3 LL b0 b31 b0 b31 • Halfword data (16 bits) (R0–R15) H L +0 H +1 L +2 +3 b0 b31 b0 b15 (R0–R15) H L +0 b31 +1 +2 H +3 L b0 b16 b31 • Byte data (8 bits) (R0–R15) b0 b31 b0 +0 b7 +1 +2 +3 (R0–R15) b0 b31 +0 b8 +1 b15 +2 +3 (R0–R15) b0 b31 +0 +1 +2 b16 b23 +3 (R0–R15) b0 b31 +0 +1 +2 +3 b24 b31 Figure 2.6.9 Difference in Data Arrangements 2-13 32182 Group User’s Manual (Rev.1.0) 2 CPU 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR instruction finishes. The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruction is used to clear the LOCK bit. The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit controls granting of bus control requested by devices other than the CPU. • When LOCK bit = "0" Control of the bus requested by devices other than the CPU is granted • When LOCK bit = "1" Control of the bus requested by devices other than the CPU is denied In the 32182 group, control of the bus may be requested by devices other than the CPU in the following two cases: • When DMA transfer is requested by the internal DMAC • When HREQ# input is pulled low to request that the CPU be placed in a hold state 2-14 32182 Group User’s Manual (Rev.1.0) CHAPTER 3 ADDRESS SPACE 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Outline of the Address Space Operation Modes Internal ROM and Extended External Areas Internal RAM and SFR Areas EIT Vector Entry ICU Vector Table Notes about Address Space 3 3.1 Outline of the Address Space ADDRESS SPACE 3.1 Outline of the Address Space The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4 Gbytes. The address space of the M32R/ECU consists of the following: (1) User space • Internal ROM area • Extended external area • Internal RAM area • SFR (Special Function Register) area (2) System space (not open to the user) (1) User space The 2 Gbytes from the address H’0000 0000 to the address H’7FFF FFFF comprise the user space. Located in this space are the internal ROM area, an extended external area, the internal RAM area and the SFR (Special Function Register) area (in which a set of internal peripheral I/O registers exist). Of these, the internal ROM and extended external areas are located differently depending on mode settings as will be described later. (2) System space The 2 Gbytes from the address H’8000 0000 to the address H’FFFF FFFF comprise the system space. This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user. 3-2 32182 Group User’s Manual (Rev.1.0) 3 Logical address H'0000 0000 16 Mbytes ADDRESS SPACE 3.1 Outline of the Address Space EIT vector entry Internal ROM area 384 Mbytes (Note 1) H'0005 FFFF H'0000 0000 H'0006 0000 CS0 area H'001F FFFF H'0020 0000 CS1 area User space 2 Gbytes Ghost area in 16-Mbyte units CS2 area H'005F FFFF H'0060 0000 H'003F FFFF H'0040 0000 CS3 area H'7FFF FFFF H'8000 0000 H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 SFR area 16 Kbytes RAM area 64 Kbytes H'0081 3FFF H'0081 4000 2 Gbytes System space Reserved area 48 Kbytes H'0081 FFFF H'0082 0000 Ghost area in 128-Kbyte units H'FFFF FFFF H'00FF FFFF Note 1: This area is located differently depending on how chip mode is set. Figure 3.1.1 Address Space of the M32182F3 3-3 32182 Group User’s Manual (Rev.1.0) 3 Logical address H'0000 0000 16 Mbytes ADDRESS SPACE 3.1 Outline of the Address Space EIT vector entry Internal ROM area 1 Mbyte (Note 1) H'000F FFFF H'0000 0000 H'0010 0000 CS0 area H'001F FFFF H'0020 0000 CS1 area User space 2 Gbytes Ghost area in 16-Mbyte units CS2 area H'005F FFFF H'0060 0000 H'003F FFFF H'0040 0000 CS3 area H'7FFF FFFF H'8000 0000 H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 SFR area 16 Kbytes RAM area 64 Kbytes H'0081 3FFF H'0081 4000 2 Gbytes System space Reserved area 48 Kbytes H'0081 FFFF H'0082 0000 Ghost area in 128-Kbyte units H'FFFF FFFF H'00FF FFFF Note 1: This area is located differently depending on how chip mode is set. Figure 3.1.2 Address Space of the M32182F8 3-4 32182 Group User’s Manual (Rev.1.0) 3 3.2 Operation Modes ADDRESS SPACE 3.2 Operation Modes The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately in Section 6.5, “Programming the Internal Flash Memory.” Table 3.2.1 Operation Mode Settings MOD0 VSS VSS VCCE VCCE MOD1 (Note 1) VSS VCCE VSS VCCE Operation mode (Note 2) Single-chip mode External extension mode Processor mode (FP = VSS) Reserved (use inhibited) Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively. Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above table, see Section 6.5, “Programming the Internal Flash Memory.” The internal ROM and extended external areas are located differently depending on how operation mode is set. (All other areas in the address space are located the same way.) The diagram below shows how the internal ROM and extended external areas are mapped into the address space in each operation mode. (For flash rewrite mode, see Section 6.5, “Programming the Internal Flash Memory.”) 3-5 32182 Group User’s Manual (Rev.1.0) 3 CS0# Pin function (Note 1) Logical address H'0000 0000 H'0005 FFFF H'0006 0000 CS1# A11 / CS2# A12 / CS3# Internal ROM (384 Kbytes) Reserved area (640 Kbytes) H'000F FFFF H'0010 0000 CS0 area (1 Mbyte) H'001F FFFF H'0020 0000 CS1 area (512 Kbytes) CS1 area (1 Mbyte) CS1 area (2 Mbytes) CS0 area (512 Kbytes) CS0 area (1 Mbyte) CS0# CS1# A11 / CS2# A12 / CS3# Internal ROM (384 Kbytes) Reserved area (640 Kbytes) CS0# CS1# A11 / CS2# A12 / CS3# Internal ROM (384 Kbytes) Reserved area (640 Kbytes) ADDRESS SPACE 3.2 Operation Modes CS0# CS1# A11 / CS2# A12 / CS3# Internal ROM (384 Kbytes) Reserved area (640 Kbytes) CS0 area (512 Kbytes) CS1 area (512 Kbytes) CS1 area (512 Kbytes) H'003F FFFF H'0040 0000 CS2 area (512 Kbytes) CS2 area (1 Mbyte) H'005F FFFF H'0060 0000 CS3 area (512 Kbytes) CS3 area (512 Kbytes) CS3 area (512 Kbytes) H'007F FFFF Note 1: Enclosed in are the valid pin function. Figure 3.2.1 Internal ROM and Extended External Area of the M32182F3 in External Extension Mode 3-6 32182 Group User’s Manual (Rev.1.0) 3 CS0# Pin function (Note 1) Logical address H'0000 0000 Internal ROM (1 Mbyte) H'000F FFFF H'0010 0000 CS0 area (1 Mbyte) H'001F FFFF H'0020 0000 CS1 area (512 Kbytes) CS1 area (1 Mbyte) CS1 area (2 Mbytes) CS0 area (512 Kbytes) CS0 area (1 Mbyte) Internal ROM (1 Mbyte) Internal ROM (1 Mbyte) CS1# A11 / CS2# A12 / CS3# CS0# CS1# A11 / CS2# A12 / CS3# CS0# CS1# A11 / CS2# A12 / CS3# ADDRESS SPACE 3.2 Operation Modes CS0# CS1# A11 / CS2# A12 / CS3# Internal ROM (1 Mbyte) CS0 area (512 Kbytes) CS1 area (512 Kbytes) CS1 area (512 Kbytes) H'003F FFFF H'0040 0000 CS2 area (512 Kbytes) CS2 area (1 Mbyte) H'005F FFFF H'0060 0000 CS3 area (512 Kbytes) CS3 area (512 Kbytes) CS3 area (512 Kbytes) H'007F FFFF Note 1: Enclosed in are the valid pin function. Figure 3.2.2 Internal ROM and Extended External Area of the M32182F8 in External Extension Mode 3-7 32182 Group User’s Manual (Rev.1.0) 3 CS0# Pin function (Note 2) CS1# A11 / CS2# A12 / CS3# H'0000 0000 CS0 area (512 Kbytes) CS0 area (1 Mbyte) CS0 area (2 Mbytes) CS0# CS1# A11 / CS2# A12 / CS3# CS0# CS1# A11 / CS2# A12 / CS3# ADDRESS SPACE 3.2 Operation Modes CS0# CS1# A11 / CS2# A12 / CS3# CS0 area (512 Kbytes) CS0 area (512 Kbytes) H'001F FFFF H'0020 0000 CS1 area (512 Kbytes) CS1 area (1 Mbyte) CS1 area (2 Mbytes) CS1 area (512 Kbytes) CS1 area (512 Kbytes) H'003F FFFF H'0040 0000 CS2 area (512 Kbytes) CS2 area (1 Mbyte) H'005F FFFF H'0060 0000 CS3 area (512 Kbytes) CS3 area (512 Kbytes) CS3 area (512 Kbytes) H'007F FFFF Note 2: Enclosed in are the valid pin function. Figure 3.2.3 Extended External Area in Processor Mode 3-8 32182 Group User’s Manual (Rev.1.0) 3 ADDRESS SPACE 3.3 Internal ROM and Extended External Areas 3.3 Internal ROM and Extended External Areas The 8-Mbyte area in the user space from the address H’0000 0000 to the address H’007F FFFF comprise the internal ROM and extended external areas. For the address mapping of these areas that differs with each operation mode, see Section 3.2, “Operation Modes.” 3.3.1 Internal ROM Area The internal ROM is allocated to the addresses shown below. Located at the beginning of this area is the EIT vector entry (and the ICU vector table). Table 3.3.1 Internal ROM Allocation Address Type Name M32182F3 M32182F8 Size 384 Kbytes 1 Mbyte Allocation Address H’0000 0000 to H’0005 FFFF H’0000 0000 to H’000F FFFF 3.3.2 Extended External Area The extended external area is only available when external extension or processor mode is selected by operation mode settings. When accessing the extended external area, the control signals necessary to access external devices are output. The CS0# through CS3# signals are output corresponding to the address mapping of the extended external area. The CS0#, CS1#, CS2# and CS3# signals are output for the CS0, CS1, CS2 and CS3 areas, respectively. Table 3.3.2 Address Mapping of the Extended External Area in Each Operation Mode Operation Mode Single-chip mode External extension mode Address Mapping of Extended External Area None H’0010 0000 to H’001F FFFF (CS0 area: 1 Mbyte) H’0020 0000 to H’003F FFFF (CS1 area: 2 Mbytes) H’0040 0000 to H’005F FFFF (CS2 area: 2 Mbytes) H’0060 0000 to H’007F FFFF (CS3 area: 2 Mbytes) Processor mode H’0000 0000 to H’001F FFFF (CS0 area: 2 Mbytes) H’0020 0000 to H’003F FFFF (CS1 area: 2 Mbytes) H’0040 0000 to H’005F FFFF (CS2 area: 2 Mbytes) H’0060 0000 to H’007F FFFF (CS3 area: 2 Mbytes) 3-9 32182 Group User’s Manual (Rev.1.0) 3 3.4 Internal RAM and SFR Areas ADDRESS SPACE 3.4 Internal RAM and SFR Areas The 8-Mbyte area from the address H’0080 0000 to the address H’00FF FFFF comprise the internal RAM and SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 128-Kbyte area from the address H’0080 0000 to the address H’0081 FFFF. The other areas here are ghosts in 128-Kbyte units. (Do not use the ghost area intentionally during programming.) 3.4.1 Internal RAM Area The internal RAM area is allocated to the addresses shown below. Table 3.4.1 Internal RAM Allocation Address Type Name M32182F3 M32182F8 Size 64 Kbytes 64 Kbytes Allocation Address H’0080 4000 to H’0081 3FFF H’0080 4000 to H’0081 3FFF 3.4.2 SFR (Special Function Register) Area The addresses H’0080 0000 to H’0080 3FFFF comprise the SFR (Special Function Register) area. Located in this area are the internal peripheral I/O registers. H'0080 0000 SFR area (16 Kbytes) H'0080 3FFF H'0080 4000 H'0080 7FFF H'0080 8000 Internal RAM (64 Kbytes) Virtual flash emulation areas separated in 4-Kbyte units can be allocated here. For details, see Section 6.6. H'0080 FFFF H'0081 0000 H'0081 3FFF Figure 3.4.1 Internal RAM and SFR (Special Function Register) Areas of the M32182F3 3-10 32182 Group User’s Manual (Rev.1.0) 3 0 78 15 +0 address +1 address H'0080 0000 Interrupt Controller (ICU) H'0080 007E H'0080 0080 A-D Converter H'0080 00EE ADDRESS SPACE 3.4 Internal RAM and SFR Areas 0 7 8 15 +0 address +1 address H'0080 0FE0 H'0080 0FFE H'0080 1000 MJT(TML1) CAN0 H'0080 11FE H'0080 1400 H'0080 0100 Serial I/O H'0080 0146 H'0080 15FE H'0080 0180 H'0080 0186 H'0080 01E0 H'0080 01F8 H'0080 0200 H'0080 023E H'0080 0240 Wait Controller H'0080 3FFE Flash control CAN1 MJT (common part) MJT(TOP) H'0080 02FE H'0000 0300 MJT(TIO) H'0080 03BE H'0080 03C0 H'0080 03DE H'0080 03E0 H'0080 03FE H'0080 0400 Multijunction timer (MJT) MJT(TMS) MJT(TML0) DMAC H'0080 0478 H'0080 0700 Input/output port H'0080 0786 Note: • The Real-time Debugger (RTD) is an independent module that is operated from the outside, and is transparent to the CPU. Figure 3.4.2 Outline Mapping of the SFR Area 3-11 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (1/21) Address b0 H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 +0 address b7 b8 Interrupt Vector Register (IVECT) (Use inhibited area) Interrupt Request Mask Register (IMASK) SBI Control Register (SBICR) (Use inhibited area) CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) (Use inhibited area) (Use inhibited area) SIO2, 3 Transmit/Receive Interrupt Control Register (ISIO23CR) (Use inhibited area) A-D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) TIO0–3 Output Interrupt Control Register (ITIO03CR) TOP0–5 Output Interrupt Control Register (ITOP05CR) TIO4–7 Output Interrupt Control Register (ITIO47CR) TIO8,9 Output Interrupt Control Register (ITOP89CR) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 5-5 (Use inhibited area) (Use inhibited area) 5-6 5-7 | H'0080 0060 (Use inhibited area) 5-8 | H'0080 0066 H'0080 0068 H'0080 006A H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E H'0080 0080 H'0080 0082 H'0080 0084 RTD Interrupt Control Register (IRTDCR) DMA5–9 Interrupt Control Register (IDMA59CR) 5-8 5-8 SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) DMA0–4 Interrupt Control Register (IDMA04CR) TOP6, 7 Output Interrupt Control Register (ITOP67CR) TIO8, 9 Output Interrupt Control Register (ITIO89CR) TOP10 Output Interrupt Control Register (ITOP10CR) TMS0, 1 Output Interrupt Control Register (ITMS01CR) TIN0–2 Input Interrupt Control Register (ITIN02CR) TIN12–19 Input Interrupt Control Register TIN20–29 Input Interrupt Control Register (ITIN1219CR) (ITIN2029CR) TIN3–6 Input Interrupt Control Register CAN1 Transmit/Receive & Error Interrupt Control Register (ITIN36CR) (ICAN1CR) A-D0 Single Mode Register 0 A-D0 Single Mode Register 1 (AD0SIM0) (AD0SIM1) (Use inhibited area) 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 11-14 11-16 A-D0 Scan Mode Register 0 A-D0 Scan Mode Register 1 (AD0SCM0) (AD0SCM1) H'0080 0086 A-D0 Disconnection Detection Assist Function Control Register A-D0 Conversion Speed Control Register (AD0DDACR) (AD0CVSCR) H'0080 0088 A-D0 Successive Approximation Register (AD0SAR) H'0080 008A A-D0 Disconnection Detection Assist Method Select Register (AD0DDASEL) H'0080 008C A-D0 Comparate Data Register (AD0CMP) H'0080 008E (Use inhibited area) H'0080 0090 H'0080 0092 H'0080 0094 H'0080 0096 H'0080 0098 H'0080 009A H'0080 009C 10-bit A-D0 Data Register (AD0DT0) 10-bit A-D0 Data Register (AD0DT1) 10-bit A-D0 Data Register (AD0DT2) 10-bit A-D0 Data Register (AD0DT3) 10-bit A-D0 Data Register (AD0DT4) 10-bit A-D0 Data Register (AD0DT5) 10-bit A-D0 Data Register (AD0DT6) 0 1 2 3 4 5 6 11-18 11-20 11-23 11-22 11-27 11-24 11-28 11-29 11-29 11-29 11-29 11-29 11-29 11-29 3-12 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (2/21) Address b0 H'0080 009E H'0080 00A0 H'0080 00A2 H'0080 00A4 H'0080 00A6 +0 address b7 b8 10-bit A-D0 Data Register 7 (AD0DT7) 10-bit A-D0 Data Register 8 (AD0DT8) 10-bit A-D0 Data Register 9 (AD0DT9) 10-bit A-D0 Data Register 10 (AD0DT10) 10-bit A-D0 Data Register 11 (AD0DT11) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 11-29 11-29 11-29 11-29 11-29 | H'0080 00D0 H'0080 00D2 H'0080 00D4 H'0080 00D6 H'0080 00D8 H'0080 00DA H'0080 00DC H'0080 00DE H'0080 00E0 H'0080 00E2 H'0080 00E4 H'0080 00E6 8-bit A-D0 Data Register 0 (AD08DT0) 8-bit A-D0 Data Register 1 (AD08DT1) 8-bit A-D0 Data Register 2 (AD08DT2) 8-bit A-D0 Data Register 3 (AD08DT3) 8-bit A-D0 Data Register 4 (AD08DT4) 8-bit A-D0 Data Register 5 (AD08DT5) 8-bit A-D0 Data Register 6 (AD08DT6) 8-bit A-D0 Data Register 7 (AD08DT7) 8-bit A-D0 Data Register 8 (AD08DT8) 8-bit A-D0 Data Register 9 (AD08DT9) 8-bit A-D0 Data Register 10 (AD08DT10) 8-bit A-D0 Data Register 11 (AD08DT11) 11-30 11-30 11-30 11-30 11-30 11-30 11-30 11-30 11-30 11-30 11-30 11-30 | H'0080 0100 H'0080 0102 | H'0080 0110 H'0080 0112 H'0080 0114 H'0080 0116 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Enable Register (SI23STAT) (SI03EN) SIO03 Interrupt Request Source Select Register (Use inhibited area) (SI03SEL) (Use inhibited area) SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register (S0TCNT) (S0MOD) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO0 Receive Control Register SIO0 Baud Rate Register (S0RCNT) (S0BAUR) (Use inhibited area) SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register (S1TCNT) (S1MOD) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Receive Control Register SIO1 Baud Rate Register (S1RCNT) (S1BAUR) (Use inhibited area) SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register (S2TCNT) (S2MOD) SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) 12-9 12-10 12-11 12-13 12-14 12-17 12-18 12-19 12-22 | H'0080 0120 H'0080 0122 H'0080 0124 H'0080 0126 12-13 12-14 12-17 12-18 12-19 12-22 | H'0080 0130 H'0080 0132 H'0080 0134 12-13 12-14 12-17 12-18 3-13 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (3/21) Address b0 H'0080 0136 SIO2 Receive Control Register (S2RCNT) (Use inhibited area) +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 SIO2 Baud Rate Register (S2BAUR) See Pages 12-19 12-22 | H'0080 0140 H'0080 0142 H'0080 0144 H'0080 0146 | H'0080 0180 H'0080 0182 SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register (S3TCNT) (S3MOD) SIO3 Transmit Buffer Register (S3TXB) SIO3 Receive Buffer Register (S3RXB) SIO3 Receive Control Register SIO3 Baud Rate Register (S3RCNT) (S3BAUR) (Use inhibited area) CS0 Area Wait Control Register (CS0WTCR) CS2 Area Wait Control Register (CS2WTCR) (Use inhibited area) Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) Flash Control Register 3 (FCNT3) (Use inhibited area) Virtual Flash S Bank Register 0 (FESBANK0) Virtual Flash S Bank Register 1 (FESBANK1) Virtual Flash S Bank Register 2 (FESBANK2) Virtual Flash S Bank Register 3 (FESBANK3) Virtual Flash S Bank Register 4 (FESBANK4) Virtual Flash S Bank Register 5 (FESBANK5) Virtual Flash S Bank Register 6 (FESBANK6) Virtual Flash S Bank Register 7 (FESBANK7) (Use inhibited area) (Use inhibited area) Prescaler Register 0 (PRS0) Prescaler Register 2 (PRS2) Clock Bus & Input Event Bus Control Register (CKIEBCR) Prescaler Register 1 (PRS1) Output Event Bus Control Register (OEBCR) (Use inhibited area) Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 4 (FCNT4) CS1 Area Wait Control Register (CS1WTCR) CS3 Area Wait Control Register (CS3WTCR) 12-13 12-14 12-17 12-18 12-19 12-22 16-4 16-4 | H'0080 01E0 H'0080 01E2 H'0080 01E4 H'0080 01E6 H'0080 01E8 H'0080 01EA H'0080 01EC H'0080 01EE H'0080 01F0 H'0080 01F2 H'0080 01F4 H'0080 01F6 6-5 6-6 6-8 6-9 6-10 6-12 6-12 6-12 6-12 6-12 6-12 6-12 6-12 | H'0080 0200 H'0080 0202 H'0080 0204 10-14 10-10 10-10 10-15 | H'0080 0210 H'0080 0212 | H'0080 0218 H'0080 021A TCLK Input Processing Control Register (TCLKCR) TIN0–4 Input Processing Control Register (TIN04CR) (Use inhibited area) TIN12–19 Input Processing Control Register (TIN1219CR) TIN20–23, TIN30–33 Input Processing Control Register (TIN2023_3033CR) (Use inhibited area) F/F6–15 Source Select Register (FF615S) (Use inhibited area) F/F16–19 Source Select Register (FF1619S) 10-18 10-19 10-20 10-20 | H'0080 0220 H'0080 0222 10-22 10-23 3-14 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (4/21) Address b0 H'0080 0224 H'0080 0226 H'0080 0228 H'0080 022A (Use inhibited area) (Use inhibited area) (Use inhibited area) +0 address b7 b8 F/F0–15 Protect Register (FF015P) F/F0–15 Data Register (FF015D) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 10-24 10-25 F/F16–20 Protect Register (FF1620P) F/F16–20 Data Register (FF1620D) 10-24 10-25 | H'0080 0230 H'0080 0232 H'0080 0234 H'0080 0236 H'0080 0238 H'0080 023A H'0080 023C H'0080 023E H'0080 0240 H'0080 0242 H'0080 0244 H'0080 0246 TOP0–5 Interrupt Request Status Register TOP0–5 Interrupt Request Mask Register (TOP05IST) (TOP05IMA) TOP6, 7 Interrupt Request Mask & Status Register TOP8, 9 Interrupt Request Mask & Status Register (TOP67IMS) (TOP89IMS) TIO0–3 Interrupt Request Mask & Status Register TIO4–7 Interrupt Request Mask & Status Register (TIO03IMS) (TIO47IMS) TIO8, 9 Interrupt Request Mask & Status Register TMS0, 1 Interrupt Request Mask & Status Register (TIO89IMS) (TMS01IMS) TIN0–2 Interrupt Request Mask & Status Register TIN3–6 Interrupt Request Mask & Status Register (TIN02IMS) (TIN36IMS) (Use inhibited area) TIN12–19 Interrupt Request Status Register TIN12–19 Interrupt Request Mask Register (TIN1219IST) (TIN1219IMA) TIN20–23 Interrupt Request Mask & Status Register (Use inhibited area) (TIN2023IMS) TOP0 Counter (TOP0CT) TOP0 Reload Register (TOP0RL) (Use inhibited area) TOP0 Correction Register (TOP0CC) (Use inhibited area) TOP1 Counter (TOP1CT) TOP1 Reload Register (TOP1RL) (Use inhibited area) TOP1 Correction Register (TOP1CC) (Use inhibited area) TOP2 Counter (TOP2CT) TOP2 Reload Register (TOP2RL) (Use inhibited area) TOP2 Correction Register (TOP2CC) (Use inhibited area) TOP3 Counter (TOP3CT) TOP3 Reload Register (TOP3RL) (Use inhibited area) TOP3 Correction Register (TOP3CC) (Use inhibited area) TOP4 Counter (TOP4CT) TOP4 Reload Register (TOP4RL) 10-30 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-42 10-54 10-55 10-56 | H'0080 0250 H'0080 0252 H'0080 0254 H'0080 0256 10-54 10-55 10-56 | H'0080 0260 H'0080 0262 H'0080 0264 H'0080 0266 10-54 10-55 10-56 | H'0080 0270 H'0080 0272 H'0080 0274 H'0080 0276 10-54 10-55 10-56 | H'0080 0280 H'0080 0282 10-54 10-55 3-15 32182 Group User’s Manual (Rev.1.0) 3 SFSFR Area Register Map (5/21) Address b0 H'0080 0284 H'0080 0286 +0 address b7 b8 (Use inhibited area) TOP4 Correction Register (TOP4CC) (Use inhibited area) TOP5 Counter (TOP5CT) TOP5 Reload Register (TOP5RL) (Use inhibited area) TOP5 Correction Register (TOP5CC) (Use inhibited area) TOP0–5 Control Register 0 (TOP05CR0) (Use inhibited area) (Use inhibited area) TOP6 Counter (TOP6CT) TOP6 Reload Register (TOP6CC) (Use inhibited area) TOP6 Correction Register (TOP6CC) (Use inhibited area) TOP6, 7 Control Register (TOP67CR) (Use inhibited area) TOP7 Counter (TOP7CT) TOP7 Reload Register (TOP7RL) (Use inhibited area) TOP7 Correction Register (TOP7CC) (Use inhibited area) TOP8 Counter (TOP8CT) TOP8 Reload Register (TOP8RL) (Use inhibited area) TOP8 Correction Register (TOP8CC) (Use inhibited area) TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) (Use inhibited area) TOP9 Correction Register (TOP9CC) (Use inhibited area) TOP10 Counter (TOP10CT) TOP10 Reload Register (TOP10RL) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages 10-56 | H'0080 0290 H'0080 0292 H'0080 0294 H'0080 0296 H'0080 0298 H'0080 029A H'0080 029C 10-54 10-55 10-56 10-50 TOP0–5 Control Register 1 (TOP05CR1) 10-50 | H'0080 02A0 H'0080 02A2 H'0080 02A4 H'0080 02A6 H'0080 02A8 H'0080 02AA 10-54 10-55 10-56 10-52 | H'0080 02B0 H'0080 02B2 H'0080 02B4 H'0080 02B6 10-54 10-55 10-56 | H'0080 02C0 H'0080 02C2 H'0080 02C4 H'0080 02C6 10-54 10-55 10-56 | H'0080 02D0 H'0080 02D2 H'0080 02D4 H'0080 02D6 10-54 10-55 10-56 | H'0080 02E0 H'0080 02E2 10-54 10-55 3-16 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (6/21) Address b0 H'0080 02E4 H'0080 02E6 H'0080 02E8 H'0080 02EA +0 address b7 b8 (Use inhibited area) TOP10 Correction Register (TOP10CC) (Use inhibited area) TOP8–10 Control Register (TOP810CR) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1address b15 See pages 10-56 10-53 | H'0080 02FA H'0080 02FC H'0080 02FE H'0080 0300 H'0080 0302 H'0080 0304 H'0080 0306 TOP External Enable Permit Register (TOPEEN) TOP Enable Protect Register (TOPPRO) TOP Count Enable Register (TOPCEN) TIO0 Counter (TIO0CT) (Use inhibited area) TIO0 Reload 1 Register (TIO0RL1) TIO0 Reload 0/ Measure Register (TIO0RL0) (Use inhibited area) TIO1 Counter (TIO1CT) (Use inhibited area) TIO1 Reload 1 Register (TIO1RL1) TIO1 Reload 0/ Measure Register (TIO1RL0) (Use inhibited area) TIO0–3 Control Register 0 (TIO03CR0) (Use inhibited area) (Use inhibited area) TIO2 Counter (TIO2CT) (Use inhibited area) TIO2 Reload 1 Register (TIO2RL1) TIO2 Reload 0/ Measure Register (TIO2RL0) (Use inhibited area) TIO3 Counter (TIO3CT) (Use inhibited area) TIO3 Reload 1 Register (TIO3RL1) TIO3 Reload 0/ Measure Register (TIO3RL0) (Use inhibited area) TIO4 Counter (TIO4CT) (Use inhibited area) TIO4 Reload 1 Register (TIO4RL1) TIO4 Reload 0/ Measure Register (TIO4RL0) TIO0–3 Control Register 1 (TIO03CR1) 10-57 10-57 10-58 10-88 10-90 10-89 | H'0080 0310 H'0080 0312 H'0080 0314 H'0080 0316 H'0080 0318 H'0080 031A H'0080 031C 10-88 10-90 10-89 10-81 10-82 | H'0080 0320 H'0080 0322 H'0080 0324 H'0080 0326 10-88 10-90 10-89 | H'0080 0330 H'0080 0332 H'0080 0334 H'0080 0336 10-88 10-90 10-89 | H'0080 0340 H'0080 0343 H'0080 0344 H'0080 0346 10-88 10-90 10-89 3-17 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (7/21) Address b0 H'0080 0348 H'0080 034A TIO4 Control Register (TIO4CR) (Use inhibited area) TIO5 Counter (TIO5CT) (Use inhibited area) +0 address b7 b8 (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 See pages TIO5 Control Register (TIO5CR) 10-83 10-85 | H'0080 0350 H'0080 0352 H'0080 0354 H'0080 0356 10-88 | H'0080 0360 H'0080 0362 H'0080 0364 H'0080 0366 H'0080 0368 H'0080 036A TIO6 Control Register (TIO6CR) TIO5 Reload 1 Register (TIO5RL1) TIO5 Reload 0/ Measure Register (TIO5RL0) (Use inhibited area) TIO6 Counter (TIO6CT) (Use inhibited area) TIO6 Reload 1 Register (TIO6RL1) TIO6 Reload 0/ Measure Register (TIO6RL0) (Use inhibited area) TIO7 Control Register (TIO7CR) (Use inhibited area) TIO7 Counter (TIO7CT) (Use inhibited area) TIO7 Reload 1 Register (TIO7RL1) TIO7 Reload 0/ Measure Register (TIO7RL0) (Use inhibited area) TIO8 Counter (TIO8CT) (Use inhibited area) TIO8 Reload 1 Register (TIO8RL1) TIO8 Reload 0/ Measure Register (TIO8RL0) (Use inhibited area) TIO8 Control Register (TIO8CR) (Use inhibited area) TIO9 Counter (TIO9CT) (Use inhibited area) TIO9 Reload 1 Register (TIO9RL1) TIO9 Reload 0/ Measure Register (TIO9RL0) (Use inhibited area) TIO Enable Protect Register (TIOPRO) TIO Count Enable Register (TIOCEN) TMS0 Counter (TMS0CT) TIO9 Control Register (TIO9CR) 10-90 10-89 10-88 10-90 10-89 10-86 10-87 | H'0080 0370 H'0080 0372 H'0080 0374 H'0080 0376 10-88 10-90 10-89 | H'0080 0380 H'0080 0382 H'0080 0384 H'0080 0386 H'0080 0388 H'0080 038A 10-88 10-90 10-89 10-87 10-88 | H'0080 0390 H'0080 0392 H'0080 0394 H'0080 0396 10-88 10-90 10-89 | H'0080 03BC H'0080 03BE H'0080 03C0 10-91 10-92 10-109 3-18 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (8/21) Address b0 H'0080 03C2 H'0080 03C4 H'0080 03C6 H'0080 03C8 H'0080 03CA TMS0 Control Register (TMS0CR) (Use inhibited area) TMS1 Counter (TMS1CT) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) (Use inhibited area) TML0 Counter (TML0CT) TMS0 TMS0 TMS0 TMS0 +0 address b7 b8 Measure 3 Register (TMS0MR3) Measure 2 Register (TMS0MR2) Measure 1 Register (TMS0MR1) Measure 0 Register (TMS0MR0) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1address b15 See pages 10-109 10-109 10-109 10-109 TMS1 Control Register (TMS1CR) 10-108 | H'0080 03D0 H'0080 03D2 H'0080 03D4 H'0080 03D6 H'0080 03D8 10-109 10-109 10-109 10-109 10-109 | H'0080 03E0 H'0080 03E2 (Upper) (Lower) 10-114 | H'0080 03EA (Use inhibited area) (Use inhibited area) TML0 Control Register (TML0CR) (Use inhibited area) TML0 Measure 3 Register (TML0MR3) (Upper) (Lower) TML0 Measure 2 Register (TML0MR2) (Upper) (Lower) TML0 Measure 1 Register (TML0MR1) (Upper) (Lower) TML0 Measure 0 Register (TML0MR0) (Upper) (Lower) DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register (DM04ITST) (DM04ITMK) (Use inhibited area) DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register (DM59ITST) (DM59ITMK) (Use inhibited area) DMA0 Channel Control Register 0 DMA0 Channel Control Register 1 (DM0CNT0) (DM0CNT1) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA0 Transfer Count Register (DM0TCT) DMA5 Channel Control Register 0 DMA5 Channel Control Register 1 (DM5CNT0) (DM5CNT1) DMA5 Source Address Register (DM5SA) 9-24 9-25 10-114 10-114 10-114 10-114 10-113 | H'0080 03F0 H'0080 03F2 H'0080 03F4 H'0080 03F6 H'0080 03F8 H'0080 03FA H'0080 03FC H'0080 03FE H'0080 0400 | H'0080 0408 9-24 9-25 | H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A 9-6 9-19 9-20 9-21 9-11 9-19 3-19 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (9/21) Address b0 H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 DMA9 DMA4 DMA8 DMA3 DMA7 DMA2 DMA6 DMA1 +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b7 b8 DMA5 Destination Address Register (DM5DA) DMA5 Transfer Count Register (DM5TCT) Channel Control Register 0 DMA1 Channel Control (DM1CNT0) (DM1CNT1) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA1 Transfer Count Register (DM1TCT) Channel Control Register 0 DMA6 Channel Control (DM6CNT0) (DM6CNT1) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA6 Transfer Count Register (DM6TCT) Channel Control Register 0 DMA2 Channel Control (DM2CNT0) (DM2CNT1) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA2 Transfer Count Register (DM2TCT) Channel Control Register 0 DMA7 Channel Control (DM7CNT0) (DM7CNT1) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA7 Transfer Count Register (DM7TCT) Channel Control Register 0 DMA3 Channel Control (DM3CNT0) (DM3CNT1) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA3 Transfer Count Register (DM3TCT) Channel Control Register 0 DMA8 Channel Control (DM8CNT0) (DM8CNT1) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA8 Transfer Count Register (DM8TCT) Channel Control Register 0 DMA4 Channel Control (DM4CNT0) (DM4CNT1) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA4 Transfer Count Register (DM4TCT) Channel Control Register 0 DMA9 Channel Control (DM9CNT0) (DM9CNT1) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA9 Transfer Count Register (DM9TCT) DMA0 Software Request Generation Register (DM0SRI) b15 See pages 9-20 9-21 Register 1 9-7 9-19 9-20 9-21 Register 1 9-12 9-19 9-20 9-21 Register 1 9-8 9-19 9-20 9-21 Register 1 9-13 9-19 9-20 9-21 Register 1 9-9 9-19 9-20 9-21 Register 1 9-14 9-19 9-20 9-21 Register 1 9-10 9-19 9-20 9-21 Register 1 9-15 9-19 9-20 9-21 9-18 3-20 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (10/21) Address b0 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 DMA1 DMA2 DMA3 DMA4 +0 address b7 b8 Software Request Generation (DM0SRI) Software Request Generation (DM2SRI) Software Request Generation (DM3SRI) Software Request Generation (DM4SRI) (Use inhibited area) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 Register Register Register Register See pages 9-18 9-18 9-18 9-18 | H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478 | H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 H'0080 0712 H'0080 0714 H'0080 0716 DMA5 Software Request Generation (DM5SRI) DMA6 Software Request Generation (DM6SRI) DMA7 Software Request Generation (DM7SRI) DMA8 Software Request Generation (DM8SRI) DMA9 Software Request Generation (DM9SRI) (Use inhibited area) P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P14 Data Register (P14DATA) P16 Data Register (P16DATA) P18 Data Register (P18DATA) P20 Data Register (P20DATA) P22 Data Register (P22DATA) (Use inhibited area) P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) P14 Direction Register (P14DIR) P16 Direction Register (P16DIR) P18 Direction Register (P18DIR) P20 Direction Register (P20DIR) Register Register Register Register Register 9-18 9-18 9-18 9-18 9-18 P1 Data Register (P1DATA) P3 Data Register (P3DATA) (Use inhibited area) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) P19 Data Register (P19DATA) P21 Data Register (P21DATA) (Use inhibited area) 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 | H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 H'0080 0732 H'0080 0734 P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) (Use inhibited area) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P19 Direction Register (P19DIR) P21 Direction Register (P21DIR) 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 3-21 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (11/21) Address b0 H'0080 0736 P22 Direction Register (P22DIR) (Use inhibited area) P0 Operation Mode Register (P0MOD) P2 Operation Mode Register (P2MOD) P4 Operation Mode Register (P4MOD) P6 Operation Mode Register (P6MOD) P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P12 Operation Mode Register (P12MOD) P14 Operation Mode Register (P14MOD) P16 Operation Mode Register (P16MOD) P18 Operation Mode Register (P18MOD) P20 Operation Mode Register (P20MOD) P22 Operation Mode Register (P22MOD) +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 (Use inhibited area) See pages 8-8 | H'0080 0740 H'0080 0742 H'0080 0744 H'0080 0746 H'0080 0748 H'0080 074A H'0080 074C H'0080 074E H'0080 0750 H'0080 0752 H'0080 0754 H'0080 0756 P1 Operation Mode Register (P1MOD) P3 Operation Mode Register (P3MOD) Port Input Special Function Control Register (PICNT) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) P19 Operation Mode Register (P19MOD) P21 Operation Mode Register (P21MOD) (Use inhibited area) (Use inhibited area) 8-9 8-10 8-11 8-21 8-11 8-12 8-12 8-13 8-13 8-14 8-14 8-15 8-15 8-16 8-16 8-17 8-17 8-18 8-18 8-19 | H'0080 0760 H'0080 0762 H'0080 0764 | H'0080 076A Port Group 0, 1 Input Level Setting Register Port Group 2, 3 Input Level Setting Register (PG01LEV) (PG23LEV) Port Group 4, 5 Input Level Setting Register Port Group 6, 7 Input Level Setting Register (PG45LEV) (PG67LEV) Port Group 8 Input Level Setting Register (Use inhibited area) (PG8LEV) (Use inhibited area) P10 Peripheral Output Select Register (P10SMOD) (Use inhibited area) P22 Peripheral Output Select Register (P22SMOD) (Use inhibited area) (Use inhibited area) (Use inhibited area) Clock Control Register (CLKCR) (Use inhibited area) TML1 Counter (TML1CT) (Upper) (Lower) (Use inhibited area) (Use inhibited area) (Use inhibited area) TML1 Measure 3 Register (TML1MR2) (Upper) (Lower) TML1 Control Register (TML1CR) (Use inhibited area) (Use inhibited area) 8-25 8-25 8-25 8-20 | H'0080 0776 (Use inhibited area) 8-20 | H'0080 077E Bus Mode Control Register (BUSMODC) 15-9 | H'0080 0786 18-5 | H'0080 0FE0 H'0080 0FE2 10-114 | H'0080 0FEA 10-113 | H'0080 0FF0 H'0080 0FF2 10-114 3-22 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (12/21) Address b0 H'0080 0FF4 H'0080 0FF6 H'0080 0FF8 H'0080 0FFA H'0080 0FFC H'0080 0FFE TML1 Measure 0 Register (TML1MR0) TML1 Measure 1 Register (TML1MR1) +0 address b7 b8 TML1 Measure 2 Register (TML1MR2) ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 (Upper) (Lower) (Upper) (Lower) (Upper) (Lower) (Use inhibited area) See pages 10-114 10-114 10-114 | H'0080 1000 H'0080 1002 H'0080 1004 H'0080 1006 H'0080 1008 H'0080 100A H'0080 100C H'0080 100E H'0080 1010 H'0080 1012 H'0080 1014 H'0080 1016 H'0080 1018 CAN0 Control Register (CAN0CNT) CAN0 Status Register (CAN0STAT) CAN0 Frame Format Select Register (CAN0FFS) CAN0 Configuration Register (CAN0CONF) CAN0 Timestamp Count Register (CAN0TSTMP) CAN0 Receive Error Count Register CAN0 Transmit Error Count Register (CAN0REC) (CAN0TEC) CAN0 Slot Interrupt Request Status Register (CAN0SLIST) (Use inhibited area) CAN0 Slot Interrupt Request Enable Register (CAN0SLIEN) (Use inhibited area) CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Enable Register (CAN0ERIST) (CAN0ERIEN) CAN0 Baud Rate Prescaler CAN0 Cause of Error Register (CAN0BRP) (CAN0EF) CAN0 Mode Register CAN0 DMA Transfer Request Select Register (CAN0MOD) (CAN0DMARQ) (Use inhibited area) CAN0 Global Mask Register Standard ID 0 CAN0 Global Mask Register Standard ID 1 (C0GMSKS0) (C0GMSKS1) CAN0 Global Mask Register Extended ID 0 CAN0 Global Mask Register Extended ID 1 (C0GMSKE0) (C0GMSKE1) CAN0 Global Mask Register Extended ID 2 (Use inhibited area) (C0GMSKE2) (Use inhibited area) CAN0 Local Mask Register A Standard ID 0 CAN0 Local Mask Register A Standard ID 1 (C0LMSKAS0) (C0LMSKAS1) CAN0 Local Mask Register A Extended ID 0 CAN0 Local Mask Register A Extended ID 1 (C0LMSKAE0) (C0LMSKAE1) CAN0 Local Mask Register A Extended ID 2 (Use inhibited area) (C0LMSKAE2) (Use inhibited area) CAN0 Local Mask Register B Standard ID 0 CAN0 Local Mask Register B Standard ID 1 (C0LMSKBS0) (C0LMSKBS1) CAN0 Local Mask Register B Extended ID 0 CAN0 Local Mask Register B Extended ID 1 (C0LMSKBE0) (C0LMSKBE1) CAN0 Local Mask Register B Extended ID 2 (Use inhibited area) (C0LMSKBE2) (Use inhibited area) CAN0 Single Shot Mode Control Register (CAN0SSMODE) (Use inhibited area) 13-15 13-18 13-21 13-22 13-24 13-25 13-29 13-30 13-31 13-32 13-26 13-45 13-46 13-47 | H'0080 1028 H'0080 102A H'0080 102C H'0080 102E H'0080 1030 H'0080 1032 H'0080 1034 H'0080 1036 H'0080 1038 H'0080 103A H'0080 103C H'0080 103E H'0080 1040 H'0080 1042 13-48 13-49 13-50 13-48 13-49 13-50 13-48 13-49 13-50 13-52 3-23 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (13/21) Address b0 H'0080 1044 H'0080 1046 H'0080 1048 H'0080 1050 H'0080 1052 H'0080 1054 H'0080 1056 H'0080 1058 H'0080 105A H'0080 105C H'0080 105E +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1address b7 b8 CAN0 Single-Shot Interrupt Request Status Register (CAN0SSIST) (Use inhibited area) b15 See pages 13-33 | H'0080 1100 H'0080 1102 H'0080 1104 H'0080 1106 H'0080 1108 H'0080 110A H'0080 110C H'0080 110E H'0080 1110 H'0080 1112 H'0080 1114 H'0080 1116 H'0080 1118 H'0080 111A H'0080 111C H'0080 111E H'0080 1120 H'0080 1122 H'0080 1124 H'0080 1126 H'0080 1128 H'0080 112A H'0080 112C CAN0 Single-Shot Interrupt Request Enable Register (CAN0SSIEN) CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register (C0MSL0CNT) (C0MSL1CNT) CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register (C0MSL2CNT) (C0MSL3CNT) CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register (C0MSL4CNT) (C0MSL5CNT) CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register (C0MSL6CNT) (C0MSL7CNT) CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register (C0MSL8CNT) (C0MSL9CNT) CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register (C0MSL10CNT) (C0MSL11CNT) CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register (C0MSL12CNT) (C0MSL13CNT) CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register (C0MSL14CNT) (C0MSL15CNT) (Use inhibited area) CAN0 Message Slot 0 Standard ID 0 CAN0 Message Slot 0 Standard ID 1 (C0MSL0SID0) (C0MSL0SID1) CAN0 Message Slot 0 Extended ID 0 CAN0 Message Slot 0 Extended ID 1 (C0MSL0EID0) (C0MSL0EID1) CAN0 Message Slot 0 Extended ID 2 CAN0 Message Slot 0 Data Length Register (C0MSL0EID2) (C0MSL0DLC) CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 (C0MSL0DT0) (C0MSL0DT1) CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 (C0MSL0DT2) (C0MSL0DT3) CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 (C0MSL0DT4) (C0MSL0DT5) CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 (C0MSL0DT6) (C0MSL0DT7) CAN0 Message Slot 0 Timestamp (C0MSL0TSP) CAN0 Message Slot 1 Standard ID 0 CAN0 Message Slot 1 Standard ID 1 (C0MSL1SID0) (C0MSL1SID1) CAN0 Message Slot 1 Extended ID 0 CAN0 Message Slot 1 Extended ID 1 (C0MSL1EID0) (C0MSL1EID1) CAN0 Message Slot 1 Extended ID 2 CAN0 Message Slot 1 Data Length Register (C0MSL1EID2) (C0MSL1DLC) CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 (C0MSL1DT0) (C0MSL1DT1) CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 (C0MSL1DT2) (C0MSL1DT3) CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 (C0MSL1DT4) (C0MSL1DT5) CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 (C0MSL1DT6) (C0MSL1DT7) CAN0 Message Slot 1 Timestamp (C0MSL1TSP) CAN0 Message Slot 2 Standard ID 0 CAN0 Message Slot 2 Standard ID 1 (C0MSL2SID0) (C0MSL2SID1) CAN0 Message Slot 2 Extended ID 0 CAN0 Message Slot 2 Extended ID 1 (C0MSL2EID0) (C0MSL2EID1) CAN0 Message Slot 2 Extended ID 2 CAN0 Message Slot 2 Data Length Register (C0MSL2EID2) (C0MSL2DLC) CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 (C0MSL2DT0) (C0MSL2DT1) CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 (C0MSL2DT2) (C0MSL2DT3) CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 (C0MSL2DT4) (C0MSL2DT5) CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 (C0MSL2DT6) (C0MSL2DT7) 13-34 13-53 13-53 13-53 13-53 13-53 13-53 13-53 13-53 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 3-24 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (14/21) Address b0 H'0080 112E H'0080 1130 H'0080 1132 H'0080 1134 H'0080 1136 H'0080 1138 H'0080 113A H'0080 113C H'0080 113E H'0080 1140 H'0080 1142 H'0080 1144 H'0080 1146 H'0080 1148 H'0080 114A H'0080 114C H'0080 114E H'0080 1150 H'0080 1152 H'0080 1154 H'0080 1156 H'0080 1158 H'0080 115A H'0080 115C H'0080 115E H'0080 1160 H'0080 1162 H'0080 1164 H'0080 1166 H'0080 1168 H'0080 116A H'0080 116C H'0080 116E H'0080 1170 H'0080 1172 +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b7 b8 b15 CAN0 Message Slot 2 Timestamp (C0MSL2TSP) CAN0 Message Slot 3 Standard ID 0 CAN0 Message Slot 3 Standard ID 1 (C0MSL3SID0) (C0MSL3SID1) CAN0 Message Slot 3 Extended ID 0 CAN0 Message Slot 3 Extended ID 1 (C0MSL3EID0) (C0MSL3EID1) CAN0 Message Slot 3 Extended ID 2 CAN0 Message Slot 3 Data Length Register (C0MSL3EID2) (C0MSL3DLC) CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 (C0MSL3DT0) (C0MSL3DT1) CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3 (C0MSL3DT2) (C0MSL3DT3) CAN0 Message Slot 3 Data 4 CAN0 Message Slot 3 Data 5 (C0MSL3DT4) (C0MSL3DT5) CAN0 Message Slot 3 Data 6 CAN0 Message Slot 3 Data 7 (C0MSL3DT6) (C0MSL3DT7) CAN0 Message Slot 3 Timestamp (C0MSL3TSP) CAN0 Message Slot 4 Standard ID 0 CAN0 Message Slot 4 Standard ID 1 (C0MSL4SID0) (C0MSL4SID1) CAN0 Message Slot 4 Extended ID 0 CAN0 Message Slot 4 Extended ID 1 (C0MSL4EID0) (C0MSL4EID1) CAN0 Message Slot 4 Extended ID 2 CAN0 Message Slot 4 Data Length Register (C0MSL4EID2) (C0MSL4DLC) CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 (C0MSL4DT0) (C0MSL4DT1) CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 (C0MSL4DT2) (C0MSL4DT3) CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 (C0MSL4DT4) (C0MSL4DT5) CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 (C0MSL4DT6) (C0MSL4DT7) CAN0 Message Slot 4 Timestamp (C0MSL4TSP) CAN0 Message Slot 5 Standard ID 0 CAN0 Message Slot 5 Standard ID 1 (C0MSL5SID0) (C0MSL5SID1) CAN0 Message Slot 5 Extended ID 0 CAN0 Message Slot 5 Extended ID 1 (C0MSL5EID0) (C0MSL5EID1) CAN0 Message Slot 5 Extended ID 2 CAN0 Message Slot 5 Data Length Register (C0MSL5EID2) (C0MSL5DLC) CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 (C0MSL5DT0) (C0MSL5DT1) CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 (C0MSL5DT2) (C0MSL5DT3) CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 (C0MSL5DT4) (C0MSL5DT5) CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 (C0MSL5DT6) (C0MSL5DT7) CAN0 Message Slot 5 Timestamp (C0MSL5TSP) CAN0 Message Slot 6 Standard ID 0 CAN0 Message Slot 6 Standard ID 1 (C0MSL6SID0) (C0MSL6SID1) CAN0 Message Slot 6 Extended ID 0 CAN0 Message Slot 6 Extended ID 1 (C0MSL6EID0) (C0MSL6EID1) CAN0 Message Slot 6 Extended ID 2 CAN0 Message Slot 6 Data Length Register (C0MSL6EID2) (C0MSL6DLC) CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 (C0MSL6DT0) (C0MSL6DT1) CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 (C0MSL6DT2) (C0MSL6DT3) CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 (C0MSL6DT4) (C0MSL6DT5) CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 (C0MSL6DT6) (C0MSL6DT7) CAN0 Message Slot 6 Timestamp (C0MSL6TSP) CAN0 Message Slot 7 Standard ID 0 CAN0 Message Slot 7 Standard ID 1 (C0MSL7SID0) (C0MSL7SID1) CAN0 Message Slot 7 Extended ID 0 CAN0 Message Slot 7 Extended ID 1 (C0MSL7EID0) (C0MSL7EID1) See pages 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 3-25 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (15/21) Address b0 H'0080 1174 H'0080 1176 H'0080 1178 H'0080 117A H'0080 117C H'0080 117E H'0080 1180 H'0080 1182 H'0080 1184 H'0080 1186 H'0080 1188 H'0080 118A H'0080 118C H'0080 118E H'0080 1190 H'0080 1192 H'0080 1194 H'0080 1196 H'0080 1198 H'0080 119A H'0080 119C H'0080 119E H'0080 11A0 H'0080 11A2 H'0080 11A4 H'0080 11A6 H'0080 11A8 H'0080 11AA H'0080 11AC H'0080 11AE H'0080 11B0 H'0080 11B2 H'0080 11B4 H'0080 11B6 H'0080 11B8 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 CAN0 Message Slot 7 Extended ID 2 CAN0 Message Slot 7 Data Length Register (C0MSL7EID2) (C0MSL7DLC) CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 (C0MSL7DT0) (C0MSL7DT1) CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 (C0MSL7DT2) (C0MSL7DT3) CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 (C0MSL7DT4) (C0MSL7DT5) CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 (C0MSL7DT6) (C0MSL7DT7) CAN0 Message Slot 7 Timestamp (C0MSL7TSP) CAN0 Message Slot 8 Standard ID 0 CAN0 Message Slot 8 Standard ID 1 (C0MSL8SID0) (C0MSL8SID1) CAN0 Message Slot 8 Extended ID 0 CAN0 Message Slot 8 Extended ID 1 (C0MSL8EID0) (C0MSL8EID1) CAN0 Message Slot 8 Extended ID 2 CAN0 Message Slot 8 Data Length Register (C0MSL8EID2) (C0MSL8DLC) CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 (C0MSL8DT0) (C0MSL8DT1) CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 (C0MSL8DT2) (C0MSL8DT3) CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 (C0MSL8DT4) (C0MSL8DT5) CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 (C0MSL8DT6) (C0MSL8DT7) CAN0 Message Slot 8 Timestamp (C0MSL8TSP) CAN0 Message Slot 9 Standard ID 0 CAN0 Message Slot 9 Standard ID 1 (C0MSL9SID0) (C0MSL9SID1) CAN0 Message Slot 9 Extended ID 0 CAN0 Message Slot 9 Extended ID 1 (C0MSL9EID0) (C0MSL9EID1) CAN0 Message Slot 9 Extended ID 2 CAN0 Message Slot 9 Data Length Register (C0MSL9EID2) (C0MSL9DLC) CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 (C0MSL9DT0) (C0MSL9DT1) CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 (C0MSL9DT2) (C0MSL9DT3) CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 (C0MSL9DT4) (C0MSL9DT5) CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 (C0MSL9DT6) (C0MSL9DT7) CAN0 Message Slot 9 Timestamp (C0MSL9TSP) CAN0 Message Slot 10 Standard ID 0 CAN0 Message Slot 10 Standard ID 1 (C0MSL10SID0) (C0MSL10SID1) CAN0 Message Slot 10 Extended ID 0 CAN0 Message Slot 10 Extended ID 1 (C0MSL10EID0) (C0MSL10EID1) CAN0 Message Slot 10 Extended ID 2 CAN0 Message Slot 10 Data Length Register (C0MSL10EID2) (C0MSL10DLC) CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 (C0MSL10DT0) (C0MSL10DT1) CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 (C0MSL10DT2) (C0MSL10DT3) CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 (C0MSL10DT4) (C0MSL10DT5) CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 (C0MSL10DT6) (C0MSL10DT7) CAN0 Message Slot 10 Timestamp (C0MSL10TSP) CAN0 Message Slot 11 Standard ID 0 CAN0 Message Slot 11 Standard ID 1 (C0MSL11SID0) (C0MSL11SID1) CAN0 Message Slot 11 Extended ID 0 CAN0 Message Slot 11 Extended ID 1 (C0MSL11EID0) (C0MSL11EID1) CAN0 Message Slot 11 Extended ID 2 CAN0 Message Slot 11 Data Length Register (C0MSL11EID2) (C0MSL11DLC) CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 (C0MSL11DT0) (C0MSL11DT1) CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 (C0MSL11DT2) (C0MSL11DT3) See pages 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 3-26 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (16/21) Address b0 H'0080 11BA H'0080 11BC H'0080 11BE H'0080 11C0 H'0080 11C2 H'0080 11C4 H'0080 11C6 H'0080 11C8 H'0080 11CA H'0080 11CC H'0080 11CE H'0080 11D0 H'0080 11D2 H'0080 11D4 H'0080 11D6 H'0080 11D8 H'0080 11DA H'0080 11DC H'0080 11DE H'0080 11E0 H'0080 11E2 H'0080 11E4 H'0080 11E6 H'0080 11E8 H'0080 11EA H'0080 11EC H'0080 11EE H'0080 11F0 H'0080 11F2 H'0080 11F4 H'0080 11F6 H'0080 11F8 H'0080 11FA H'0080 11FC +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 (C0MSL11DT4) (C0MSL11DT5) CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 (C0MSL11DT6) (C0MSL11DT7) CAN0 Message Slot 11 Timestamp (C0MSL11TSP) CAN0 Message Slot 12 Standard ID 0 CAN0 Message Slot 12 Standard ID 1 (C0MSL12SID0) (C0MSL12SID1) CAN0 Message Slot 12 Extended ID 0 CAN0 Message Slot 12 Extended ID 1 (C0MSL12EID0) (C0MSL12EID1) CAN0 Message Slot 12 Extended ID 2 CAN0 Message Slot 12 Data Length Register (C0MSL12EID2) (C0MSL12DLC) CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 (C0MSL12DT0) (C0MSL12DT1) CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 (C0MSL12DT2) (C0MSL12DT3) CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 (C0MSL12DT4) (C0MSL12DT5) CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 (C0MSL12DT6) (C0MSL12DT7) CAN0 Message Slot 12 Timestamp (C0MSL12TSP) CAN0 Message Slot 13 Standard ID 0 CAN0 Message Slot 13 Standard ID 1 (C0MSL13SID0) (C0MSL13SID1) CAN0 Message Slot 13 Extended ID 0 CAN0 Message Slot 13 Extended ID 1 (C0MSL13EID0) (C0MSL13EID1) CAN0 Message Slot 13 Extended ID 2 CAN0 Message Slot 13 Data Length Register (C0MSL13EID2) (C0MSL13DLC) CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 (C0MSL13DT0) (C0MSL13DT1) CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 (C0MSL13DT2) (C0MSL13DT3) CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 (C0MSL13DT4) (C0MSL13DT5) CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 (C0MSL13DT6) (C0MSL13DT7) CAN0 Message Slot 13 Timestamp (C0MSL13TSP) CAN0 Message Slot 14 Standard ID 0 CAN0 Message Slot 14 Standard ID 1 (C0MSL14SID0) (C0MSL14SID1) CAN0 Message Slot 14 Extended ID 0 CAN0 Message Slot 14 Extended ID 1 (C0MSL14EID0) (C0MSL14EID1) CAN0 Message Slot 14 Extended ID 2 CAN0 Message Slot 14 Data Length Register (C0MSL14EID2) (C0MSL14DLC) CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 (C0MSL14DT0) (C0MSL14DT1) CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 (C0MSL14DT2) (C0MSL14DT3) CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 (C0MSL14DT4) (C0MSL14DT5) CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 (C0MSL14DT6) (C0MSL14DT7) CAN0 Message Slot 14 Timestamp (C0MSL14TSP) CAN0 Message Slot 15 Standard ID 0 CAN0 Message Slot 15 Standard ID 1 (C0MSL15SID0) (C0MSL15SID1) CAN0 Message Slot 15 Extended ID 0 CAN0 Message Slot 15 Extended ID 1 (C0MSL15EID0) (C0MSL15EID1) CAN0 Message Slot 15 Extended ID 2 CAN0 Message Slot 15 Data Length Register (C0MSL15EID2) (C0MSL15DLC) CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 (C0MSL15DT0) (C0MSL15DT1) CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 (C0MSL15DT2) (C0MSL15DT3) CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 (C0MSL15DT4) (C0MSL15DT5) CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 (C0MSL15DT6) (C0MSL15DT7) See pages 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 3-27 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (17/21) Address b0 H'0080 11FE +0 address ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b7 b8 CAN0 Message Slot 15 Timestamp (C0MSL15TSP) (Use inhibited area) b15 See pages 13-71 | H'0080 1400 H'0080 1402 H'0080 1404 H'0080 1406 H'0080 1408 H'0080 140A H'0080 140C H'0080 140E H'0080 1410 H'0080 1412 H'0080 1414 H'0080 1416 H'0080 1418 CAN1 Control Register (CAN1CNT) CAN1 Status Register (CAN1STAT) CAN1 Frame Format Select Register (CAN1FFS) CAN1 Configuration Register (CAN1CONF) CAN1 Timestamp Count Register (CAN1TSTMP) CAN1 Receive Error Count Register CAN1 Transmit Error Count Register (CAN1REC) (CAN1TEC) CAN1 Slot Interrupt Request Status Register (CAN1SLIST) (Use inhibited area) CAN1 Slot Interrupt Request Enable Register (CAN1SLIEN) (Use inhibited area) CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Enable Register (CAN1ERIST) (CAN1ERIEN) CAN1 Baud Rate Prescaler CAN1 Cause of Error Register (CAN1BRP) (CAN1EF) CAN1 Mode Register (Use inhibited area) (CAN1MOD) (Use inhibited area) CAN1 Global Mask Register Standard ID 0 CAN1 Global Mask Register Standard ID 1 (C1GMSKS0) (C1GMSKS1) CAN1 Global Mask Register Extended ID 0 CAN1 Global Mask Register Extended ID 1 (C1GMSKE0) (C1GMSKE1) CAN1 Global Mask Register Extended ID 2 (Use inhibited area) (C1GMSKE2) (Use inhibited area) CAN1 Local Mask Register A Standard ID 0 CAN1 Local Mask Register A Standard ID 1 (C1LMSKAS0) (C1LMSKAS1) CAN1 Local Mask Register A Extended ID 0 CAN1 Local Mask Register A Extended ID 1 (C1LMSKAE0) (C1LMSKAE1) CAN1 Local Mask Register A Extended ID 2 (Use inhibited area) (C1LMSKAE2) (Use inhibited area) CAN1 Local Mask Register B Standard ID 0 CAN1 Local Mask Register B Standard ID 1 (C1LMSKBS0) (C1LMSKBS1) CAN1 Local Mask Register B Extended ID 0 CAN1 Local Mask Register B Extended ID 1 (C1LMSKBE0) (C1LMSKBE1) CAN1 Local Mask Register B Extended ID 2 (Use inhibited area) (C1LMSKBE2) (Use inhibited area) CAN1 Single-Shot Mode Control Register (CAN1SSMODE) (Use inhibited area) CAN1 Single-Shot Interrupt Request Status Register (CAN1SSIST) (Use inhibited area) CAN1 Single-Shot Interrupt Request Enable Register (CAN1SSIEN) (Use inhibited area) CAN1 Message Slot 0 Control Register (C1MSL0CNT) CAN1 Message Slot 1 Control Register (C1MSL1CNT) 13-15 13-18 13-21 13-22 13-24 13-25 13-29 13-30 13-31 13-32 13-26 13-45 13-46 | H'0080 1428 H'0080 142A H'0080 142C H'0080 142E H'0080 1430 H'0080 1432 H'0080 1434 H'0080 1436 H'0080 1438 H'0080 143A H'0080 143C H'0080 143E H'0080 1440 H'0080 1442 H'0080 1444 H'0080 1446 H'0080 1448 13-48 13-49 13-50 13-48 13-49 13-50 13-48 13-49 13-50 13-52 13-33 13-34 | H'0080 1450 13-53 3-28 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (18/21) Address b0 H'0080 1452 H'0080 1454 H'0080 1456 H'0080 1458 H'0080 145A H'0080 145C H'0080 145E +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 | H'0080 1500 H'0080 1502 H'0080 1504 H'0080 1506 H'0080 1508 H'0080 150A H'0080 150C H'0080 150E H'0080 1510 H'0080 1512 H'0080 1514 H'0080 1516 H'0080 1518 H'0080 151A H'0080 151C H'0080 151E H'0080 1520 H'0080 1522 H'0080 1524 H'0080 1526 H'0080 1528 H'0080 152A H'0080 152C H'0080 152E H'0080 1530 H'0080 1532 H'0080 1534 CAN1 Message Slot 2 Control Register CAN1 Message Slot 3 Control Register (C1MSL0CNT) (C1MSL3CNT) CAN1 Message Slot 4 Control Register CAN1 Message Slot 5 Control Register (C1MSL4CNT) (C1MSL5CNT) CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register (C1MSL6CNT) (C1MSL7CNT) CAN1 Message Slot 8 Control Register CAN1 Message Slot 9 Control Register (C1MSL8CNT) (C1MSL9CNT) CAN1 Message Slot 10 Control Register CAN1 Message Slot 11 Control Register (C1MSL10CNT) (C1MSL11CNT) CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register (C1MSL12CNT) (C1MSL13CNT) CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register (C1MSL14CNT) (C1MSL15CNT) (Use inhibited area) CAN1 Message Slot 0 Standard ID 0 CAN1 Message Slot 0 Standard ID 1 (C1MSL0SID0) (C1MSL0SID1) CAN1 Message Slot 0 Extended ID 0 CAN1 Message Slot 0 Extended ID 1 (C1MSL0EID0) (C1MSL0EID1) CAN1 Message Slot 0 Extended ID 2 CAN1 Message Slot 0 Data Length Register (C1MSL0EID2) (C1MSL0DLC) CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 (C1MSL0DT0) (C1MSL0DT1) CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 (C1MSL0DT2) (C1MSL0DT3) CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 (C1MSL0DT4) (C1MSL0DT5) CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 (C1MSL0DT6) (C1MSL0DT7) CAN1 Message Slot 0 Timestamp (C1MSL0TSP) CAN1 Message Slot 1 Standard ID 0 CAN1 Message Slot 1 Standard ID 1 (C1MSL1SID0) (C1MSL1SID1) CAN1 Message Slot 1 Extended ID 0 CAN1 Message Slot 1 Extended ID 1 (C1MSL1EID0) (C1MSL1EID1) CAN1 Message Slot 1 Extended ID 2 CAN1 Message Slot 1 Data Length Register (C1MSL1EID2) (C1MSL1DLC) CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 (C1MSL1DT0) (C1MSL1DT1) CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 (C1MSL1DT2) (C1MSL1DT3) CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 (C1MSL1DT4) (C1MSL1DT5) CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 (C1MSL1DT6) (C1MSL1DT7) CAN1 Message Slot 1 Timestamp (C1MSL1TSP) CAN1 Message Slot 2 Standard ID 0 CAN1 Message Slot 2 Standard ID 1 (C1MSL2SID0) (C1MSL2SID1) CAN1 Message Slot 2 Extended ID 0 CAN1 Message Slot 2 Extended ID 1 (C1MSL2EID0) (C1MSL2EID1) CAN1 Message Slot 2 Extended ID 2 CAN1 Message Slot 2 Data Length Register (C1MSL2EID2) (C1MSL2DLC) CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 (C1MSL2DT0) (C1MSL2DT1) CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 (C1MSL2DT2) (C1MSL2DT3) CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 (C1MSL2DT4) (C1MSL2DT5) CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 (C1MSL2DT6) (C1MSL2DT7) CAN1 Message Slot 2 Timestamp (C1MSL2TSP) CAN1 Message Slot 3 Standard ID 0 CAN1 Message Slot 3 Standard ID 1 (C1MSL3SID0) (C1MSL3SID1) CAN1 Message Slot 3 Extended ID 0 CAN1 Message Slot 3 Extended ID 1 (C1MSL3EID0) (C1MSL3EID1) CAN1 Message Slot 3 Extended ID 2 CAN1 Message Slot 3 Data Length Register (C1MSL3EID2) (C1MSL3DLC) See pages 13-53 13-53 13-53 13-53 13-53 13-53 13-53 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 3-29 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (19/21) Address b0 H'0080 1536 H'0080 1538 H'0080 153A H'0080 153C H'0080 153E H'0080 1540 H'0080 1542 H'0080 1544 H'0080 1546 H'0080 1548 H'0080 154A H'0080 154C H'0080 154E H'0080 1550 H'0080 1552 H'0080 1554 H'0080 1556 H'0080 1558 H'0080 155A H'0080 155C H'0080 155E H'0080 1560 H'0080 1562 H'0080 1564 H'0080 1566 H'0080 1568 H'0080 156A H'0080 156C H'0080 156E H'0080 1570 H'0080 1572 H'0080 1574 H'0080 1576 H'0080 1578 H'0080 157A +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 CAN1 Message Slot 3 Standard ID 0 CAN1 Message Slot 3 Standard ID 1 (C1MSL3DT0) (C1MSL3DT1) CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 (C1MSL3DT2) (C1MSL3DT3) CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 (C1MSL3DT4) (C1MSL3DT5) CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 (C1MSL3DT6) (C1MSL3DT7) CAN1 Message Slot 3 Timestamp (C1MSL3TSP) CAN1 Message Slot 4 Standard ID 0 CAN1 Message Slot 4 Standard ID 1 (C1MSL4SID0) (C1MSL4SID1) CAN1 Message Slot 4 Extended ID 0 CAN1 Message Slot 4 Extended ID 1 (C1MSL4EID0) (C1MSL4EID1) CAN1 Message Slot 4 Extended ID 2 CAN1 Message Slot 4 Data Length Register (C1MSL4EID2) (C1MSL4DLC) CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 (C1MSL4DT0) (C1MSL4DT1) CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 (C1MSL4DT2) (C1MSL4DT3) CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 (C1MSL4DT4) (C1MSL4DT5) CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 (C1MSL4DT6) (C1MSL4DT7) CAN1 Message Slot 4 Timestamp (C1MSL4TSP) CAN1 Message Slot 5 Standard ID 0 CAN1 Message Slot 5 Standard ID 1 (C1MSL5SID0) (C1MSL5SID1) CAN1 Message Slot 5 Extended ID 0 CAN1 Message Slot 5 Extended ID 1 (C1MSL5EID0) (C1MSL5EID1) CAN1 Message Slot 5 Extended ID 2 CAN1 Message Slot 5 Data Length Register (C1MSL5EID2) (C1MSL5DLC) CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 (C1MSL5DT0) (C1MSL5DT1) CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 (C1MSL5DT2) (C1MSL5DT3) CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 (C1MSL5DT4) (C1MSL5DT5) CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 (C1MSL5DT6) (C1MSL5DT7) CAN1 Message Slot 5 Timestamp (C1MSL5TSP) CAN1 Message Slot 6 Standard ID 0 CAN1 Message Slot 6 Standard ID 1 (C1MSL6SID0) (C1MSL6SID1) CAN1 Message Slot 6 Extended ID 0 CAN1 Message Slot 6 Extended ID 1 (C1MSL6EID0) (C1MSL6EID1) CAN1 Message Slot 6 Extended ID 2 CAN1 Message Slot 6 Data Length Register (C1MSL6EID2) (C1MSL6DLC) CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 (C1MSL6DT0) (C1MSL6DT1) CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 (C1MSL6DT2) (C1MSL6DT3) CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 (C1MSL6DT4) (C1MSL6DT5) CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 (C1MSL6DT6) (C1MSL6DT7) CAN1 Message Slot 6 Timestamp (C1MSL6TSP) CAN1 Message Slot 7 Standard ID 0 CAN1 Message Slot 7 Standard ID 1 (C1MSL7SID0) (C1MSL7SID1) CAN1 Message Slot 7 Extended ID 0 CAN1 Message Slot 7 Extended ID 1 (C1MSL7EID0) (C1MSL7EID1) CAN1 Message Slot 7 Extended ID 2 CAN1 Message Slot 7 Data Length Register (C1MSL7EID2) (C1MSL7DLC) CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 (C1MSL7DT0) (C1MSL7DT1) CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 (C1MSL7DT2) (C1MSL7DT3) CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 (C1MSL7DT4) (C1MSL7DT5) See pages 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 3-30 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (20/21) Address b0 H'0080 157C H'0080 157E H'0080 1580 H'0080 1582 H'0080 1584 H'0080 1586 H'0080 1588 H'0080 158A H'0080 158C H'0080 158E H'0080 1590 H'0080 1592 H'0080 1594 H'0080 1596 H'0080 1598 H'0080 159A H'0080 159C H'0080 159E H'0080 15A0 H'0080 15A2 H'0080 15A4 H'0080 15A6 H'0080 15A8 H'0080 15AA H'0080 15AC H'0080 15AE H'0080 15B0 H'0080 15B2 H'0080 15B4 H'0080 15B6 H'0080 15B8 H'0080 15BA H'0080 15BC H'0080 15BE H'0080 15C0 +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1address b15 CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 (C1MSL7DT6) (C1MSL7DT7) CAN1 Message Slot 7 Timestamp (C1MSL7TSP) CAN1 Message Slot 8 Standard ID 0 CAN1 Message Slot 8 Standard ID 1 (C1MSL8SID0) (C1MSL8SID1) CAN1 Message Slot 8 Extended ID 0 CAN1 Message Slot 8 Extended ID 1 (C1MSL8EID0) (C1MSL8EID1) CAN1 Message Slot 8 Extended ID 2 CAN1 Message Slot 8 Data Length Register (C1MSL8EID2) (C1MSL8DLC) CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 (C1MSL8DT0) (C1MSL8DT1) CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3 (C1MSL8DT2) (C1MSL8DT3) CAN1 Message Slot 8 Data 4 CAN1 Message Slot 8 Data 5 (C1MSL8DT4) (C1MSL8DT5) CAN1 Message Slot 8 Data 6 CAN1 Message Slot 8 Data 7 (C1MSL8DT6) (C1MSL8DT7) CAN1 Message Slot 8 Timestamp (C1MSL8TSP) CAN1 Message Slot 9 Standard ID 0 CAN1 Message Slot 9 Standard ID 1 (C1MSL9SID0) (C1MSL9SID1) CAN1 Message Slot 9 Extended ID 0 CAN1 Message Slot 9 Extended ID 1 (C1MSL9EID0) (C1MSL9EID1) CAN1 Message Slot 9 Extended ID 2 CAN1 Message Slot 9 Data Length Register (C1MSL9EID2) (C1MSL9DLC) CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 (C1MSL9DT0) (C1MSL9DT1) CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 (C1MSL9DT2) (C1MSL9DT3) CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 (C1MSL9DT4) (C1MSL9DT5) CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 (C1MSL9DT6) (C1MSL9DT7) CAN1 Message Slot 9 Timestamp (C1MSL9TSP) CAN1 Message Slot 10 Standard ID 0 CAN1 Message Slot 10 Standard ID 1 (C1MSL10SID0) (C1MSL10SID1) CAN1 Message Slot 10 Extended ID 0 CAN1 Message Slot 10 Extended ID 1 (C1MSL10EID0) (C1MSL10EID1) CAN1 Message Slot 10 Extended ID 2 CAN1 Message Slot 10 Data Length Register (C1MSL10EID2) (C1MSL10DLC) CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 (C1MSL10DT0) (C1MSL10DT1) CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 (C1MSL10DT2) (C1MSL10DT3) CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 (C1MSL10DT4) (C1MSL10DT5) CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 (C1MSL10DT6) (C1MSL10DT7) CAN1 Message Slot 10 Timestamp (C1MSL10TSP) CAN1 Message Slot 11 Standard ID 0 CAN1 Message Slot 11 Standard ID 1 (C1MSL11SID0) (C1MSL11SID1) CAN1 Message Slot 11 Extended ID 0 CAN1 Message Slot 11 Extended ID 1 (C1MSL11EID0) (C1MSL11EID1) CAN1 Message Slot 11 Extended ID 2 CAN1 Message Slot 11 Data Length Register (C1MSL11EID2) (C1MSL11DLC) CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 (C1MSL11DT0) (C1MSL11DT1) CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 (C1MSL11DT2) (C1MSL11DT3) CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 (C1MSL11DT4) (C1MSL11DT5) CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 (C1MSL11DT6) (C1MSL11DT7) CAN1 Message Slot 11 Timestamp (C1MSL11TSP) CAN1 Message Slot 12 Standard ID 0 CAN1 Message Slot 12 Standard ID 1 (C1MSL12SID0) (C1MSL12SID1) See pages 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 3-31 32182 Group User’s Manual (Rev.1.0) 3 SFR Area Register Map (21/21) Address b0 H'0080 15C2 H'0080 15C4 H'0080 15C6 H'0080 15C8 H'0080 15CA H'0080 15CC H'0080 15CE H'0080 15D0 H'0080 15D2 H'0080 15D4 H'0080 15D6 H'0080 15D8 H'0080 15DA H'0080 15DC H'0080 15DE H'0080 15E0 H'0080 15E2 H'0080 15E4 H'0080 15E6 H'0080 15E8 H'0080 15EA H'0080 15EC H'0080 15EE H'0080 15F0 H'0080 15F2 H'0080 15F4 H'0080 15F6 H'0080 15F8 H'0080 15FA H'0080 15FC H'0080 15FE +0 address b7 b8 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +1 address b15 CAN1 Message Slot 12 Extended ID 0 CAN1 Message Slot 12 Extended ID 1 (C1MSL12EID0) (C1MSL12EID1) CAN1 Message Slot 12 Extended ID 2 CAN1 Message Slot 12 Data Length Register (C1MSL12EID2) (C1MSL12DLC) CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 (C1MSL12DT0) (C1MSL12DT1) CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 (C1MSL12DT2) (C1MSL12DT3) CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 (C1MSL12DT4) (C1MSL12DT5) CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 (C1MSL12DT6) (C1MSL12DT7) CAN1 Message Slot 12 Timestamp (C1MSL12TSP) CAN1 Message Slot 13 Standard ID 0 CAN1 Message Slot 13 Standard ID 1 (C1MSL13SID0) (C1MSL13SID1) CAN1 Message Slot 13 Extended ID 0 CAN1 Message Slot 13 Extended ID 1 (C1MSL13EID0) (C1MSL13EID1) CAN1 Message Slot 13 Extended ID 2 CAN1 Message Slot 13 Data Length Register (C1MSL13EID2) (C1MSL13DLC) CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 (C1MSL13DT0) (C1MSL13DT1) CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 (C1MSL13DT2) (C1MSL13DT3) CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 (C1MSL13DT4) (C1MSL13DT5) CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 (C1MSL13DT6) (C1MSL13DT7) CAN1 Message Slot 13 Timestamp (C1MSL13TSP) CAN1 Message Slot 14 Standard ID 0 CAN1 Message Slot 14 Standard ID 1 (C1MSL14SID0) (C1MSL14SID1) CAN1 Message Slot 14 Extended ID 0 CAN1 Message Slot 14 Extended ID 1 (C1MSL14EID0) (C1MSL14EID1) CAN1 Message Slot 14 Extended ID 2 CAN1 Message Slot 14 Data Length Register (C1MSL14EID2) (C1MSL14DLC) CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 (C1MSL14DT0) (C1MSL14DT1) CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 (C1MSL14DT2) (C1MSL14DT3) CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 (C1MSL14DT4) (C1MSL14DT5) CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 (C1MSL14DT6) (C1MSL14DT7) CAN1 Message Slot 14 Timestamp (C1MSL14TSP) CAN1 Message Slot 15 Standard ID 0 CAN1 Message Slot 15 Standard ID 1 (C1MSL15SID0) (C1MSL15SID1) CAN1 Message Slot 15 Extended ID 0 CAN1 Message Slot 15 Extended ID 1 (C1MSL15EID0) (C1MSL15EID1) CAN1 Message Slot 15 Extended ID 2 CAN1 Message Slot 15 Data Length Register (C1MSL15EID2) (C1MSL15DLC) CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 (C1MSL15DT0) (C1MSL15DT1) CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 (C1MSL15DT2) (C1MSL15DT3) CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 (C1MSL15DT4) (C1MSL15DT5) CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 (C1MSL15DT6) (C1MSL15DT7) CAN1 Message Slot 15 Timestamp (C1MSL15TSP) See pages 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 3-32 32182 Group User’s Manual (Rev.1.0) 3 3.5 EIT Vector Entry ADDRESS SPACE 3.5 EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM/extended external areas. The branch instruction for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch instruction and not the jump address itself that is written here. For details, see Chapter 4, “EIT.” 0 31 H'0000 0000 H'0000 0004 RI (Reset Interrupt) H'0000 0008 H'0000 000C H'0000 0010 H'0000 0014 SBI (System Break Interrupt) H'0000 0018 H'0000 001C H'0000 0020 H'0000 0024 RIE (Reserved Instruction Exception) H'0000 0028 H'0000 002C H'0000 0030 H'0000 0034 AE (Address Exception) H'0000 0038 H'0000 003C H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0080 H'0000 0090 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 EI (External Interrupt) (Note 1) FPE (Floating-Point Exception) Note 1: When flash entry bit = 1 (flash E/W enable mode), the EI vector entry is located at H'0080 4000. Figure 3.5.1 EIT Vector Entry 3-33 32182 Group User’s Manual (Rev.1.0) 3 3.6 ICU Vector Table ADDRESS SPACE 3.6 ICU Vector Table The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the addresses shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set. For details, see Chapter 5, “Interrupt Controller.” ICU Vector Table Memory Map (1/2) Address b0 H'0000 0094 H'0000 0096 H'0000 0098 H'0000 009A H'0000 009C H'0000 009E H'0000 00A0 H'0000 00A2 H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 00B8 H'0000 00BA H'0000 00BC H'0000 00BE H'0000 00C0 H'0000 00C2 H'0000 00C4 H'0000 00C6 H'0000 00C8 H'0000 00CA H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 TMS0, 1 Output Interrupt Handler Start Address (A0–A15) TMS0, 1 Output Interrupt Handler Start Address (A16–A31) TOP8, 9 Output Interrupt Handler Start Address (A0–A15) TOP8, 9 Output Interrupt Handler Start Address (A16–A31) TOP10 Output Interrupt Handler Start Address (A0–A15) TOP10 Output Interrupt Handler Start Address (A16–A31) TIO4–7 Output Interrupt Handler Start Address (A0–A15) TIO4–7 Output Interrupt Handler Start Address (A16–A31) TIO8, 9 Output Interrupt Handler Start Address (A0–A15) TIO8, 9 Output Interrupt Handler Start Address (A16–A31) TOP0–5 Output Interrupt Handler Start Address (A0–A15) TOP0–5 Output Interrupt Handler Start Address (A16–A31) TOP6, 7 Output Interrupt Handler Start Address (A0–A15) TOP6, 7 Output Interrupt Handler Start Address (A16–A31) TIO0–3 Output Interrupt Handler Start Address (A0–A15) TIO0–3 Output Interrupt Handler Start Address (A16–A31) DMA0–4 Interrupt Handler Start Address (A0–A15) DMA0–4 Interrupt Handler Start Address (A16–A31) SIO1 Receive Interrupt Handler Start Address (A0–A15) SIO1 Receive Interrupt Handler Start Address (A16–A31) SIO1 Transmit Interrupt Handler Start Address (A0–A15) SIO1 Transmit Interrupt Handler Start Address (A16–A31) SIO0 Receive Interrupt Handler Start Address (A0–A15) SIO0 Receive Interrupt Handler Start Address (A16–A31) +0 address b7 b8 TIN3–6 Input Interrupt Handler Start Address (A0–A15) TIN3–6 Input Interrupt Handler Start Address (A16–A31) TIN20–29 Input Interrupt Handler Start Address (A0–A15) TIN20–29 Input Interrupt Handler Start Address (A16–A31) TIN12–19 Input Interrupt Handler Start Address (A0–A15) TIN12–19 Input Interrupt Handler Start Address (A16–A31) TIN0–2 Input Interrupt Handler Start Address (A0–A15) TIN0–2 Input Interrupt Handler Start Address (A16–A31) (Note 1) +1 address b15 3-34 32182 Group User’s Manual (Rev.1.0) 3 ICU Vector Table Memory Map (2/2) Address b0 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC H'0000 00EE H'0000 00F0 H'0000 00F2 H'0000 00F4 H'0000 00F6 H'0000 00F8 H'0000 00FA H'0000 00FC H'0000 00FE H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 H'0000 010A H'0000 010C H'0000 010E H'0000 0110 H'0000 0112 (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) DMA5–9 Interrupt Handler Start Address (A0–A15) DMA5–9 Interrupt Handler Start Address (A16–A31) (Note 1) +0 address b7 b8 SIO0 Transmit Interrupt Handler Start Address (A0–A15) ADDRESS SPACE 3.6 ICU Vector Table +1 address b15 SIO0 Transmit Interrupt Handler Start Address (A16–A31) A-D0 Conversion Interrupt Handler Start Address (A0–A15) A-D0 Conversion Interrupt Handler Start Address (A16–A31) (Note 1) SIO2, 3 Transmit/receive Interrupt Handler Start Address (A0–A15) SIO2, 3 Transmit/receive Interrupt Handler Start Address (A16–A31) RTD Interrupt Handler Start Address (A0–A15) RTD Interrupt Handler Start Address (A16–A31) (Note 1) CAN0 Transmit/receive & Error Interrupt Handler Start Address (A0–A15) CAN0 Transmit/receive & Error Interrupt Handler Start Address (A16–A31) CAN1 Transmit/receive & Error Interrupt Handler Start Address (A0–A15) CAN1 Transmit/receive & Error Interrupt Handler Start Address (A16–A31) Note 1: Valid for the interrupt requests in the 32180. No interrupt requests are generated in the 32182. 3-35 32182 Group User’s Manual (Rev.1.0) 3 3.7 Notes about Address Space • Virtual flash emulation function ADDRESS SPACE 3.7 Notes about Address Space The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the virtual flash emulation function. This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the flash memory contents at the addresses specified by the Virtual Flash Bank Register. For details about this function, see Section 6.6, “Virtual Flash Emulation Function.” 3-36 32182 Group User’s Manual (Rev.1.0) CHAPTER 4 EIT 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Outline of EIT EIT Events EIT Processing Procedure EIT Processing Mechanism Acceptance of EIT Events Saving and Restoring the PC and PSW EIT Vector Entry Exception Processing Interrupt Processing Trap Processing EIT Priority Levels Example of EIT Processing Precautions on EIT 4 4.1 Outline of EIT EIT 4.1 Outline of EIT If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt and Trap). (1) Exception This is an event related to the context being executed. It is generated by an error or violation during instruction execution. This type of event includes Address Exception (AE), Reserved Instruction Exception (RIE) and FloatingPoint Exception (FPE). (2) Interrupt This is an event generated irrespective of the context being executed. It is generated by a hardware-derived signal from an external source, as well as by the internal peripheral I/O. This type of event includes Reset Interrupt (RI), System Break Interrupt (SBI) and External Interrupt (EI). (3) Trap This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally generated in a program as in the OS’s system call by the programmer. EIT Exception (Exception) Reserved Instruction Exception (RIE) Address Exception (AE) Floating-Point Exception (FPE) Interrupt (Interrupt) Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap (Trap) Trap (TRAP) Figure 4.1.1 Classification of EITs 4-2 32182 Group User’s Manual (Rev.1.0) 4 4.2 EIT Events 4.2.1 Exception (1) Reserved Instruction Exception (RIE) EIT 4.2 EIT Events Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. (3) Floating-point Exception (FPE) Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in the IEEE 754 standard (OVF/UDF/IXCT/DIV0/IVLD) is detected. Each exception processing is outlined below. 1) Overflow Exception (OVF) The exception occurs when the absolute value of the operation result exceeds the largest describable precision in the floating-point format. The following table shows the operation results when an OVF occurs. Table 4.2.1 Operation Results When an OVF Occurred Operation Result (Conten t of the Destination Register) Rounding Mode Sign of the Result When the OVF EIT processing is masked (Note 1) +MAX -Infinity +Infinity -MAX +MAX -MAX +Infinity -Infinity No change When the OVF EIT processing is executed (Note 2) -Infinity +Infinity 0 Nearest + + + + - Note 1: When the overflow exception enable (EO) bit (FPSR register bit 20) = "0" Note 2: When the overflow exception enable (EO) bit (FPSR register bit 20) = "1" Note: • If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time. • +MAX = H’7F7F FFFF, –MAX = H’FF7F FFFF 2) Underflow Exception (UDF) The exception occurs when the absolute value of the operation result is less than the largest describable precision in the floating-point format. The following table shows the operation results when a UDF occurs. Table 4.2.2 Operation Results when a UDF Occurred Operation Result (Conten t of the Destination Register) When UDF EIT processing is masked (Note 1) When UDF EIT processing is executed (Note 2) DN = 0: An unimplemented exception occurs No change DN = 1: 0 is returned Note 1: When the underflow exception enable (EU) bit (FPSR register bit 18) = "0" Note 2: When the underflow exception enable (EU) bit (FPSR register bit 18) = "1" 4-3 32182 Group User’s Manual (Rev.1.0) 4 EIT 4.2 EIT Events 3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs. Table 4.2.3 Operation Results when an IXCT Occurred Operation Result (Content o f the Destination Register) Occurrence Condition When the IXCT EIT processing for is When the IXCT EIT processing is masked (Note 1) executed (Note 2) Reference OVF operation results Rounded value No change No change Overflow occurs in OVF masked condition Rounding occurs Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0" Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1" 4) Zero Division Exception (DIV0) The exception occurs when a finite nonzero value is divided by zero. The following table shows the operation results when a DIV0 is occurs. Table 4.2.4 Operation Results When a DIV0 Occurred Operation Result (Conten t of the Destination Register) Dividend When the DIV0 EIT processing is masked (Note 1) +-Infinity (Sign is derived by exclusive ORing the signs of the divisor and dividend.) When the DIV0 EIT processing is executed (Note 2) No change Nonzero finite value Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0" Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1" Please note that the DIV0 EIT processing does not occur in the following conditions. Table 4.2.5 Cases in Which No DIV0 Occur Dividend 0 Infinity Behavior An invalid operation exception occurs No exceptions occur (with the result = "Infinity") 4-4 32182 Group User’s Manual (Rev.1.0) 4 Table 4.2.6 Operation Results When an IVLD Occurred EIT 4.2 EIT Events 5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs. Operation Result (Content of the Destination Register) Occurrence Condition When the IVLD EIT When the IVLD EIT processing is masked (Note 1) processing is executed (Note 2) Operation for SNaN operand +Infinity-(+Infinity), -Infinity-(-Infinity) 0 x Infinity 0 / 0, Infinity / Infinity When FTOI Return value w hen pre-conversion signed bit is: instruction "0": H’7FFF FFFF overflow ed w as executed "1": H’8000 0000 • When NaN or Infinity w as converted When FTOS Return value w hen pre-conversion signed bit is: "0": H’0000 7FFF into an integer instruction w as executed "1": H’FFFF 8000 When < or > comparison w as performed on NaN Comparison results (comparison invalid) QNaN • When an integer conversion No change Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0" Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1" Note: • NaN (Not a Number) SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is "0". When SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used as the initial value in a variable. However, SNaNs cannot be generated by hardware. QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when QNaN is used as the source operand in an operation, an IVLD will not occur (excluding comparison and format conversion). Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without executing an EIT processing. QNaNs are created by hardware. 6) Unimplemented Exception (UIPL) The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and a denormalized number is given as an operation operand. (Note 1) Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination register remains unchanged. Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if the DN bit (FPSR register bit 23) = "0", an UIPL occurs. 4.2.2 Interrupt (1) Reset Interrupt (RI) Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the highest priority. For details about the reset interrupt, see Chapter 7, “Reset.” (2) System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) External Interrupt (EI) External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state. 4-5 32182 Group User’s Manual (Rev.1.0) 4 4.2.3 Trap EIT 4.2 EIT Events Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0–15. 4.3 EIT Processing Procedure EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below. EIT request generated Program execution restarted Instruction Instruction Instruction A B C Program suspended and EIT request accepted Instruction Instruction C D Instruction processing-canceled type (RIE, AE) Instruction processing-completed type (FPE, EI, TRAP) PC→BPC PSW→BPSW Hardware preprocessing (Note 1) Hardware postprocessing (Note 1) BPSW→PSW BPC→PC User-created EIT handler EIT vector entry Branch instruction BPC, PSW, FPSR and general-purpose registers are saved to the stack EIT handler except for SBI Processing by handler General-purpose registers, PSW, FPSR and BPC are restored from the stack RTE instruction (SBI) SBI (System Break Interrupt processing) Program terminated or system is reset Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields. Figure 4.3.1 Outline of the EIT Processing Procedure When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for the EIT handler (not the jump address itself) is written. In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register’s PSW field is transferred to the BPSW field in that register. Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remember that all these registers must be saved to the stack in a program by the user. When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register’s BPSW field is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register’s BPSW field after executing the RTE instruction are undefined. 4-6 32182 Group User’s Manual (Rev.1.0) 4 4.4 EIT Processing Mechanism EIT 4.4 EIT Processing Mechanism The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/ Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW register). The EIT processing mechanism is shown below. M32R/ECU M32R CPU core RESET# RI RI AE, RIE, FPE, TRAP High Priority SBI# Interrupt controller (ICU) SBI SBI Internal peripheral I/Os EI EI Low IE flag (PSW) BPC register BPSW PSW PC register PSW register Figure 4.4.1 EIT Processing Mechanism 4-7 32182 Group User’s Manual (Rev.1.0) 4 4.5 Acceptance of EIT Events EIT 4.5 Acceptance of EIT Events When an EIT event occurs, the CPU suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below. Table 4.5.1 Acceptance of EIT Events EIT Event Reserved Instruction Exception (RIE) Address Exception (AE) Floating-Point Exception (FPE) Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap (TRAP) Type of Processing Instruction processingcanceled type Instruction processingcanceled type Instruction processingcompleted type Instruction processingaborted type Instruction processingcompleted type Instruction processingcompleted type Instruction processingcompleted type Acceptance Timing During instruction execution During instruction execution Break in instructions Each machine cycle Break in instructions (word boundary only) Break in instructions (word boundary only) Break in instructions Values Set in BPC Register PC value of the instruction that generated RIE PC value of the instruction that generated AE PC value of the instruction that generated FPE + 4 Undefined value PC value of the next instruction PC value of the next instruction PC value of TRAP instruction + 4 4.6 Saving and Restoring the PC and PSW The following describes operation of the microcomputer at the time when it accepts an EIT and when it executes the RTE instruction. (1) Hardware preprocessing when an EIT is accepted [1] Save the PSW register’s SM, IE and C bits in its backup field. BSM ← SM BIE ← IE BC ← C [2] Update the PSW register’s SM, IE and C bits SM ← Remains unchanged (RIE, AE, FPE, TRAP) or cleared to "0" (SBI, EI, RI) IE ← Cleared to "0" C ← Cleared to "0" [3] Save the PC register BPC ← PC [4] Set the vector address in the PC register Branches to the EIT vector and executes the branch (BRA) instruction written in it, thereby transferring control to the user-created EIT handler. (2) Hardware postprocessing when the RTE instruction is executed [A] Restore the PSW register’s SM, IE and C bits from its backup field. SM ← BSM IE ← BIE C ← BC [B] Restore the PC register from the BPC register. PC ← BPC Note: • The values stored in the BPC and the PSW register’s BSM, BIE and BC bits after executing the RTE instruction are undefined. 4-8 32182 Group User’s Manual (Rev.1.0) 4 [1] Saving the SM, IE and C bits BSM BIE BC ← ← ← SM IE C EIT 4.6 Saving and Restoring the PC and PSW [3] Saving the PC BPC ← PC [4] Setting the vector address in the PC PC ← Vector address [2] Updating the SM, IE and C bits SM IE C ← ← ← Unchanged or 0 0 0 [A] Restoring the SM, IE and C bits from the backup field SM IE C ← ← ← BSM BIE BC [B] Restoring the PC from the BPC register The value stored in the BPC register after executing the RTE instruction is undefined. The values stored in the BSM, BIE and BC bits after executing the RTE instruction are undefined. PSW BPC PC When EIT is accepted [1] [2] [3] [4] When RTE instruction is executed [A] [B] BPSW field 0(MSB) 7 8 15 16 17 23 24 25 PSW field 31(LSB) PSW 0000000000000000 00000 00000 BSM BIE BC SM IE C Figure 4.6.1 Saving and Restoring the PC and PSW 4-9 32182 Group User’s Manual (Rev.1.0) 4 4.7 EIT Vector Entry EIT 4.7 EIT Vector Entry The EIT vector entry is located in the user space beginning with the address H’0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Name Reset Interrupt System Break Interrupt Reserved Instruction Exception Address Exception Trap AE TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 External Interrupt Floating-Point Exception EI FPE H'0000 0030 H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 0 PC of the instruction that generated AE PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of the next instruction PC of the instruction that generated FPE + 4 RIE H'0000 0020 Unchanged 0 PC of the instruction that generated RIE Abbreviation Vector Address RI SBI SM IE 0 0 BPC Undefined PC of the next instruction H'0000 0000 (Note 1) 0 H'0000 0010 0 H'0000 0080 (Note 2) 0 H'0000 0090 Unchanged 0 Note 1: During boot mode, the CPU starts executing the boot program after reset. For details, see Section 6.5, “Programming the Internal Flash Memory.” Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H’0080 4000). For details, see Section 6.5, “Programming the Internal Flash Memory.” 4-10 32182 Group User’s Manual (Rev.1.0) 4 4.8 Exception Processing 4.8.1 Reserved Instruction Exception (RIE) EIT 4.8 Exception Processing [Occurrence Conditions] Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction that generated it is not executed. If an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC register. For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the reserved instruction exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) +0 Address H'00 Return address +1 +2 +3 Address H'00 Return address +0 +1 +2 +3 H'04 H'08 H'0C RIE occurred H'04 H'08 H'0C RIE occurred BPC H'04 BPC H'06 Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) 4-11 32182 Group User’s Manual (Rev.1.0) 4 EIT 4.8 Exception Processing (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure 4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruction exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the reserved instruction exception handler to the program that was being executed when the exception occurred. 4.8.2 Address Exception (AE) [Occurrence Conditions] Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur. • Two low-order address bits accessed in the LDH, LDUH or STH instruction are ‘01’ or ‘11’ • Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are ‘01,’ ‘10’ or ‘11’ When an address exception occurs, memory access by the instruction that generated the exception is not performed. If an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the address exception is set in the BPC register. For example, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) 4-12 32182 Group User’s Manual (Rev.1.0) 4 +0 Address H'00 Return address EIT 4.8 Exception Processing +1 +2 +3 Address H'00 Return address +0 +1 +2 +3 H'04 H'08 H'0C AE occurred H'04 H'08 H'0C AE occurred BPC H'04 BPC H'06 Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0030 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0030 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated an AE (see Figure 4.8.2). Except when using address exceptions intentionally, occurrence of an address exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the address exception handler to the program that was being executed when the exception occurred. 4.8.3 Floating-Point Exception (FPE) [Occurrence Conditions] Floating-Point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in IEEE 754 standards (OVF, UDF, IXCT, DIV0 or IVLD) is detected. Note, however, that the EIT processing described below is executed only when the exception that occurred is one whose exception enable bit in the FPSR register is set to "1" or an unimplemented exception. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 4-13 32182 Group User’s Manual (Rev.1.0) 4 EIT 4.8 Exception Processing (3) Saving the PC The PC value of the instruction that generated the FPE exception + 4 is set in the BPC register. Because all of the instructions that generate an FPE exception are 32 bits long, the address to which the RTE returns is always the instruction next to the one that generated the FPE exception. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0090 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0090 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC, PSW and FPSR registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. 4-14 32182 Group User’s Manual (Rev.1.0) 4 4.9 Interrupt Processing 4.9.1 Reset Interrupt (RI) EIT 4.9 Interrupt Processing [Occurrence Conditions] A reset interrupt is accepted in machine cycle by pulling the RESET# input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE and C bits The PSW register’s SM, IE and C bits are initialized as shown below. SM ← 0 IE ← 0 C ← 0 For the reset interrupt, the values of BSM, BIE and BC bits are undefined. (2) Branching to the EIT vector entry The CPU branches to the address H’0000 0000 in the user space. However, when operating in boot mode, the CPU jumps to the boot program. For details, see Section 6.5, “Programming the Internal Flash Memory.” (3) Jumping from the EIT vector entry to the user program The CPU executes the instruction written by the user at the address H’0000 0000 of the EIT vector entry. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of the user program. 4.9.2 System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. [Occurrence Conditions] A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt cannot be masked by the PSW register IE bit.) In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Note also that because of the instruction processing-completed type, a system break interrupt is accepted after the instruction is completed. 4-15 32182 Group User’s Manual (Rev.1.0) 4 Order in which instructions are executed Address 1000 Address 1002 Address 1004 EIT 4.9 Interrupt Processing Address 1008 16-bit instruction 16-bit instruction 32-bit instruction × Interrupt may be accepted Interrupt cannot Interrupt may be accepted be accepted Interrupt may be accepted Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The address of the next instruction (always on word boundary) following one in which the interrupt was detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then the next instruction is one that exists at the jump address. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT vector entry to jump to the start address of the user-created handler. The system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. 4-16 32182 Group User’s Manual (Rev.1.0) 4 4.9.3 External Interrupt (EI) EIT 4.9 Interrupt Processing An external interrupt is generated upon an interrupt request which is output by the microcomputer’s internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, see Chapter 5, “Interrupt Controller.” For details about the interrupt request sources, see each section in which the relevant internal peripheral I/O is described. [Occurrence Conditions] External interrupts are managed based on interrupt requests from each internal peripheral I/O by the microcomputer’s internal interrupt controller, and are sent to the CPU via the interrupt controller. The CPU checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the PSW register IE flag = "1", accepts it as an external interrupt. In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Order in which instructions are executed Address 1000 Address 1002 Address 1004 Address 1008 16-bit instruction 16-bit instruction 32-bit instruction × Interrupt may be accepted Interrupt cannot be accepted Interrupt may be accepted Interrupt may be accepted Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The content of the PC register (always on word boundary) is saved to the BPC register. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0080 in the user space. However, when operating in flash E/W enable mode, the CPU goes to the beginning of the internal RAM (address H’0080 4000). (For details, see Section 6.5, “Programming the Internal Flash Memory.”) This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0080 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. 4-17 32182 Group User’s Manual (Rev.1.0) 4 EIT 4.9 Interrupt Processing (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. 4.10 Trap Processing 4.10.1 Trap [Occurrence Conditions] Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps are generated, each corresponding to one of TRAP instruction operands 0–15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register. For example, if the TRAP instruction is located at address 4, the value H’08 is set in the BPC register. Similarly, if the TRAP instruction is located at address 6, the value H’0A is set in the BPC register. The value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) +0 Address +1 +2 +3 Address H'00 Return address +0 +1 +2 +3 Return address H'00 H'04 TRAP instruction H'08 H'0C H'04 H'08 H'0C TRAP instruction BPC H'08 BPC H'0A Figure 4.10.1 Example of a Return Address for Trap (TRAP) 4-18 32182 Group User’s Manual (Rev.1.0) 4 EIT 4.10 Trap Processing (4) Branching to the EIT vector entry The CPU branches to the addresses H’0000 0040–H’0000 007C in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the addresses H’0000 0040–H’0000 007C of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the usercreated EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from the next word-boundary instruction including the instruction that generates a trap (see Figure 4.10.1). 4.11 EIT Priority Levels The table below lists the priority levels of EIT events. When two or more EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Priority 2 EIT Event Address Exception (AE) Reserved Instruction Exception (RIE) Floating-Point Exception (FPE) Trap (TRAP) 3 4 System Break Interrupt (SBI) External Interrupt (EI) Instruction processing-completed type PC of the next instruction Instruction processing-completed type Instruction processing-completed type Instruction processing-completed type Type of Processing Instruction processing-aborted type Instruction processing-canceled type Instruction processing-canceled type Values Set in BPC Register Undefined PC of the instruction that generated AE PC of the instruction that generated RIE PC of the instruction that generated FPE + 4 TRAP instruction + 4 PC of the next instruction 1 (Highest) Reset Interrupt (RI) Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the microcomputer’s internal interrupt controller. For details, see Chapter 5, “Interrupt Controller.” 4-19 32182 Group User’s Manual (Rev.1.0) 4 4.12 Example of EIT Processing (1) When RIE, AE, FPE, SBI, EI or TRAP occurs singly EIT 4.12 Example of EIT Processing IE = 1 BPC register = Return address A IE = 0 RIE, AE, FPE, SBI, EI or TRAP occurs singly Return address A: IE = 1 RTE instruction If IE = 0, no events but reset and SBI are accepted. : EIT handler Figure 4.12.1 Processing of Events When RIE, AE, FPE, SBI, EI or TRAP Occurs Singly (2) When RIE, AE, FPE or TRAP and EI occur simultaneously IE = 1 IE = 0 RIE, AE, FPE or TRAP and EI occur simultaneously Return address A: RIE, AE, FPE or TRAP is accepted first. BPC register = Return address A RTE instruction IE = 1 IE = 0 IE = 1 EI is accepted next. BPC register = Return address A RTE instruction : EIT handler Figure 4.12.2 Processing of Events When RIE, AE, FPE or TRAP and EI Occur Simultaneously 4-20 32182 Group User’s Manual (Rev.1.0) 4 EIT vector entry BRA instruction EIT 4.12 Example of EIT Processing (Other than SBI) EIT handler (SBI) PC→BPC Hardware PSW→BPSW preprocessing (Note 1) Save BPC to the stack Save PSW to the stack System Break Interrupt (SBI) processing Program being executed Save general-purpose registers to the stack EIT event occurs Processing by EIT handler Program terminated or system reset Restore general-purpose registers from the stack (Note 1) Hardware BPSW→PSW postprocessing BPC→PC Restore PSW from the stack Restore BPC from the stack RTE Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields. Figure 4.12.3 Example of EIT Processing 4-21 32182 Group User’s Manual (Rev.1.0) 4 4.13 Precautions on EIT EIT 4.13 Precautions on EIT The Address Exception (AE) requires caution because if one of the instructions that use “register indirect + register update” addressing mode (following three) generates an address exception when it is executed, the values of the registers to be automatically updated (Rsrc and Rsrc2) become undefined. Except that the values of Rsrc and Rsrc2 become undefined, these instructions behave the same way as when used in other addressing modes. • Applicable instructions LD Rdest, @Rsrc+ ST Rsrc1, @-Rsrc2 ST Rsrc1, @+Rsrc2 If the above case applies, consider the fact that the register values become undefined when you design the processing to be performed after executing said instructions. (If an address exception occurs, it means that the system has some fatal fault already existing in it. Therefore, address exceptions must be used on condition that control will not be returned from the address exception handler to the program that was being executed when the exception occurred.) 4-22 32182 Group User’s Manual (Rev.1.0) CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 5.2 5.3 5.4 5.5 5.6 Outline of the Interrupt Controller ICU Related Registers Interrupt Request Sources in Internal Peripheral I/O ICU Vector Table Description of Interrupt Operation Description of System Break Interrupt (SBI) Operation 5 5.1 Outline of the Interrupt Controller INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external interrupts (EI). The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for internal peripheral I/Os. On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI# signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register IE bit status. After processing of an SBI, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. Specifications of the Interrupt Controller are outlined below. Table 5.1.1 Outline of the Interrupt Controller (ICU) Item Interrupt request source Priority management Specification Maskable interrupt requests from internal peripheral I/Os: 23 sources (Note 1) System break interrupt request: 1 source (input from SBI# pin) 8 priority levels including an interrupt-disabled state (However, interrupts with the same priority level have their priorities resolved by fixed hardware priority.) Note 1: There are actually a total of 123 interrupt request resources when counted individually, which are grouped into 23 interrupt request resources. 5-2 32182 Group User’s Manual (Rev.1.0) 5 Interrupt Controller INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller System Break Interrupt (SBI) request generated (nonmaskable) SBI Control Register (SBICR) SBI# SBIREQ SBI To the CPU core Peripheral circuits Interrupt request Interrupt request Interrupt request Edge Edge Edge IREQ Priority resolved by interrupt priority levels set ILEVEL IREQ IREQ Priority resolved by fixed hardware priority External Interrupt (EI) request generated (maskable) Interrupt Vector Register (IVECT) IMASK comparison EI To the CPU core NEW_IMASK IREQ Interrupt control circuit Interrupt control circuit Interrupt control circuit Level IREQ Level IREQ Level Interrupt Request Mask Register (IMASK) Interrupt Control Register Figure 5.1.1 Block Diagram of the Interrupt Controller 5-3 32182 Group User’s Manual (Rev.1.0) 5 5.2 ICU Related Registers INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers The diagram below shows a register map associated with the Interrupt Controller (ICU). ICU Related Register Map Address b0 H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 +0 address b7 b8 Interrupt Vector Register (IVECT) (Use inhibited area) Interrupt Request Mask Register (IMASK) SBI Control Register (SBICR) (Use inhibited area) CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) (Use inhibited area) (Use inhibited area) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) (Use inhibited area) A-D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) TIO0–3 Output Interrupt Control Register (ITIO03CR) TOP0–5 Output Interrupt Control Register (ITOP05CR) TIO4–7 Output Interrupt Control Register (ITIO47CR) TOP8,9 Output Interrupt Control Register (ITOP89CR) (Use inhibited area) TIN12–19 Input Interrupt Control Register (ITIN1219CR) TIN3–6 Input Interrupt Control Register (ITIN36CR) (Use inhibited area) 5-8 (Use inhibited area) (Use inhibited area) +1 address b15 5-5 See pages 5-6 5-7 | H'0080 0060 | H'0080 0066 H'0080 0068 H'0080 006A H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E RTD Interrupt Control Register (IRTDCR) DMA5–9 Interrupt Control Register (IDMA59CR) 5-8 5-8 SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) DMA0–4 Interrupt Control Register (IDMA04CR) TOP6,7 Output Interrupt Control Register (ITOP67CR) TIO8,9 Output Interrupt Control Register (ITIO89CR) TOP10 Output Interrupt Control Register (ITOP10CR) TMS0,1 Output Interrupt Control Register (ITMS01CR) TIN0–2 Input Interrupt Control Register (ITIN02CR) TIN20–29 Input Interrupt Control Register (ITIN2029CR) CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-4 32182 Group User’s Manual (Rev.1.0) 5 5.2.1 Interrupt Vector Register Interrupt Vector Register (IVECT) b0 ? INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5 ? 1 ? 2 ? 3 ? 4 ? 6 ? 7 IVECT ? 8 ? 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? b 0-15 Bit Name IVECT Function When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are stored in this register. Note: • This register must always be accessed in halfwords (2 bytes). (This is a read-only register.) R R W N 16 low-order bits of ICU vector table address The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-low-order bits of the ICU vector table address for the accepted interrupt request source. Before this function can work, the ICU vector table (addresses H’0000 0094 through H’0000 0113) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are stored in the IVECT register. In the EIT handler, read the content of this IVECT register using the LDH instruction to get the ICU vector table address. When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware. (1) The interrupt priority level of the accepted interrupt request source (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) (2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). (3) The interrupt request (EI) to the CPU core is deasserted. (4) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: • Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are disabled (PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request Mask Register (IMASK) first before reading the IVECT register. • To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. (The ICU vector table readout in the EI handler processing example in Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O is an access to the internal ROM and, therefore, does not require adding a dummy access.) 5-5 32182 Group User’s Manual (Rev.1.0) 5 5.2.2 Interrupt Request Mask Register Interrupt Request Mask Register (IMASK) b0 0 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 6 b7 1 1 0 2 0 3 0 4 0 5 1 IMASK 1 b 0–4 5–7 Bit Name No function assigned. Fix to "0" IMASK Interrupt request mask bit 000: Disable maskable interrupts 001: Accept interrupts with priority level 0 010: Accept interrupts with priority levels 0–1 011: Accept interrupts with priority levels 0–2 100: Accept interrupts with priority levels 0–3 101: Accept interrupts with priority levels 0–4 110: Accept interrupts with priority levels 0–5 111: Accept interrupts with priority levels 0–6 Function R 0 R W 0 W The Interrupt Request Mask Register (IMASK) is used to finally determine whether or not to accept an interrupt request after comparing its priority with the priority levels (Interrupt Control Register ILEVEL bits) that have been set for each interrupt request source. When the Interrupt Vector Register (IVECT) described above is read, the interrupt priority level of the accepted interrupt request source is set in this IMASK register as a new mask value. When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in hardware. (1) The interrupt request (EI) to the CPU core is deasserted. (2) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: • Do not write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = "0"). • To reenable interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts. 5-6 32182 Group User’s Manual (Rev.1.0) 5 SBI (System Break Interrupt) Control Register (SBICR) b0 0 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5.2.3 SBI (System Break Interrupt) Control Register 1 0 2 0 3 0 4 0 5 0 6 0 b7 SBIREQ 0 b 0–6 7 Bit Name No function assigned. Fix to "0" SBIREQ SBI request bit Function 0: SBI not requested 1: SBI requested R W 0 0 R(Note 1) Note 1: This bit can only be cleared (see below) The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin. When a falling edge on the SBI# signal input pin is detected and this bit is set to "1", a system break interrupt (SBI) request is generated to the CPU. This bit cannot be set to "1" in software, it can only be cleared. To clear this bit to "0", follow the procedure described below. 1. Write "1" to the SBI request bit. 2. Write "0" to the SBI request bit. Note: • Unless this bit is set to "1", do not perform the above clearing operation. 5-7 32182 Group User’s Manual (Rev.1.0) 5 5.2.4 Interrupt Control Registers INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) RTD Interrupt Control Register (IRTDCR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) DMA5–9 Interrupt Control Register (IDMA59CR) A-D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) DMA0–4 Interrupt Control Register (IDMA04CR) TIO0–3 Output Interrupt Control Register (ITIO03CR) TOP6,7 Output Interrupt Control Register (ITOP67CR) TOP0–5 Output Interrupt Control Register (ITOP05CR) TIO8,9 Output Interrupt Control Register (ITIO89CR) TIO4–7 Output Interrupt Control Register (ITIO47CR) TOP10 Output Interrupt Control Register (ITOP10CR) TOP8,9 Output Interrupt Control Register (ITOP89CR) TMS0,1 Output Interrupt Control Register (ITMS01CR) TIN0–2 Input Interrupt Control Register (ITIN02CR) TIN12–19 Input Interrupt Control Register (ITIN1219CR) TIN20–29 Input Interrupt Control Register (ITIN2029CR) TIN3–6 Input Interrupt Control Register (ITIN36CR) CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) b0 (b8 0 1 9 0 2 10 0 3 11 IREQ 0 4 12 0 5 13 1 6 14 ILEVEL 1 b7 b15) 1 b 0–2 (8–10) 3 (11) Bit Name No function assigned. Fix to "0" IREQ Interrupt request bit At read 0: Interrupt not requested 1: Interrupt requested At write 0: Clear interrupt request 1: Generate interrupt request At read 0: Interrupt not requested 1: Interrupt requested 4 (12) 5–7 (13–15) No function assigned. Fix to "0" ILEVEL Interrupt priority level bits 000: 001: 010: 011: 100: 101: 110: 111: Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt priority priority priority priority priority priority priority priority level 0 level 1 level 2 level 3 level 4 level 5 level 6 level 7 (interrupt disabled) Function R 0 R W 0 W R 0 0 R 0 W 5-8 32182 Group User’s Manual (Rev.1.0) 5 (1) IREQ (Interrupt Request) bit (Bit 3 or 11) INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Request) bit is set to "1". This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt request generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt request). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority. Note: • External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External Interrupt (EI) to the CPU core can only be deasserted by the following operation: (1) Reset (2) IVECT register read (3) Write to the IMASK register Interrupt request from each internal peripheral I/O Bit 3 or 11 IREQ Set Set/clear Data bus F/F Interrupt enabled Reset IVECT read IMASK write Clear Bits 5-7 or bits 13-15 3 ILEVEL (levels 0-7) Interrupt priority resolving circuit Set F/F EI To the CPU core Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type) Interrupt request from each group internal peripheral I/O Group interrupt Read Data bus b3, b11 Read-only circuit IREQ Reset IVECT read IMASK write Interrupt enabled Clear b5-b7, b13-b15 3 ILEVEL (levels 0-7) Interrupt priority resolving circuit Set F/F EI To the CPU core Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type) 5-9 32182 Group User’s Manual (Rev.1.0) 5 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers (2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to ‘111’ to disable or any value ‘000’ through ‘110’ to enable the interrupt from some internal peripheral I/O. When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether to forward an EI request to the CPU or keep the interrupt request pending. The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted. Table 5.2.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set 0 (ILEVEL = "000") 1 (ILEVEL = "001") 2 (ILEVEL = "010") 3 (ILEVEL = "011") 4 (ILEVEL = "100") 5 (ILEVEL = "101") 6 (ILEVEL = "110") 7 (ILEVEL = "111") IMASK values at which interrupts are accepted Accepted when IMASK is 1–7 Accepted when IMASK is 2–7 Accepted when IMASK is 3–7 Accepted when IMASK is 4–7 Accepted when IMASK is 5–7 Accepted when IMASK is 6–7 Accepted when IMASK is 7 Not accepted (interrupts disabled) 5-10 32182 Group User’s Manual (Rev.1.0) 5 INTERRUPT CONTROLLER (ICU) 5.3 Interrupt Request Sources in Internal Peripheral I/O 5.3 Interrupt Request Sources in Internal Peripheral I/O The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal peripheral I/O is described. Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O Interrupt Request Sources TIN3–6 input interrupt request TIN20–29 input interrupt request TIN12–19 input interrupt request TIN0–2 input interrupt request TMS0,1 output interrupt request TOP8,9 output interrupt request TOP10 output interrupt request TIO4–7 output interrupt request TIO8,9 output interrupt request TOP0–5 output interrupt request TOP6,7 output interrupt request TIO0–3 output interrupt request DMA0-4 interrupt request SIO1 receive interrupt request SIO1 transmit interrupt request Contents Number of Input Sources 1 4 4 1 2 2 1 4 2 6 2 4 5 1 1 1 1 1 5 4 1 35 35 ICU Type of Input Source ( Note 1) Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized TIN3 input TIN20–TIN23 inputs TIN16–TIN19 inputs TIN0 input TMS0, TMS1 output TOP8, TOP9 output TOP10 output TIO4–TIO7 outputs TIO8, TIO9 outputs TOP0–TOP5 outputs TOP6–TOP7 outputs TIO0–TIO3 outputs DMA0–4 transfer completed SIO1 reception-completed or receive error interrupt SIO1 transmission-completed or transmit buffer empty interrupt SIO0 receive interrupt request SIO0 reception-completed or receive error interrupt SIO0 transmit interrupt request SIO0 transmission-completed or transmit buffer empty interrupt A-D0 conversion interrupt request A-D0 converter’s scan mode one-shot operation, single mode or comparate mode completed DMA5–9 interrupt request DMA5–9 transfer completed SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt, request transmission-completed or transmit buffer empty interrupt RTD interrupt request RTD interrupt generation command CAN0 transmit/receive & error CAN0 transmission or reception completed, CAN0 error interrupt request passive, CAN0 error bus-off, CAN0 bus error, single shot CAN1 transmit/receive & error CAN1 transmission or reception completed, CAN1 error interrupt request passive, CAN1 error bus-off, CAN1 bus error, single shot Note 1: ICU type of input source • Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU. • Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software. 5-11 32182 Group User’s Manual (Rev.1.0) 5 5.4 ICU Vector Table INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 32-source interrupt requests (of these, 23 sources are used in the 32182) are assigned the following vector table addresses. Table 5.4.1 ICU Vector Table Addresses Interrupt Request Source TIN3–6 input interrupt request TIN20–23 input interrupt request TIN12–19 input interrupt request TIN0–2 input interrupt request (Note 1) TMS0,1 output interrupt request TOP8,9 output interrupt request TOP10 output interrupt request TIO4–7 output interrupt request TIO8,9 output interrupt request TOP0–5 output interrupt request TOP6,7 output interrupt request TIO0–3 output interrupt request DMA0–4 interrupt request SIO1 receive interrupt request SIO1 transmit interrupt request SIO0 receive interrupt request SIO0 transmit interrupt request A-D0 conversion interrupt request (Note 1) (Note 1) DMA5–9 interrupt request SIO2,3 transmit/receive interrupt request RTD interrupt request (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) CAN0 transmit/receive & error interrupt request CAN1 transmit/receive & error interrupt request ICU Vector Table Addresses H'0000 0094 H'0000 0098 H'0000 009C H'0000 00A0 H'0000 00A4 H'0000 00A8 H'0000 00AC H'0000 00B0 H'0000 00B4 H'0000 00B8 H'0000 00BC H'0000 00C0 H'0000 00C4 H'0000 00C8 H'0000 00CC H'0000 00D0 H'0000 00D4 H'0000 00D8 H'0000 00DC H'0000 00E0 H'0000 00E4 H'0000 00E8 H'0000 00EC H'0000 00F0 H'0000 00F4 H'0000 00F8 H'0000 00FC H'0000 0100 H'0000 0104 H'0000 0108 H'0000 010C H'0000 0110 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – H'0000 0097 H'0000 009B H'0000 009F H'0000 00A3 H'0000 00A7 H'0000 00AB H'0000 00AF H'0000 00B3 H'0000 00B7 H'0000 00BB H'0000 00BF H'0000 00C3 H'0000 00C7 H'0000 00CB H'0000 00CF H'0000 00D3 H'0000 00D7 H'0000 00DB H'0000 00DF H'0000 00E3 H'0000 00E7 H'0000 00EB H'0000 00EF H'0000 00F3 H'0000 00F7 H'0000 00FB H'0000 00FF H'0000 0103 H'0000 0107 H'0000 010B H'0000 010F H'0000 0113 Note 1: Valid for the interrupt requests in the 32180. No interrupt requests are generated in the 32182. 5-12 32182 Group User’s Manual (Rev.1.0) 5 5.5 Description of Interrupt Operation INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.1 Acceptance of Internal Peripheral I/O Interrupts An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, if two or more interrupt requests occur simultaneously, the Interrupt Controller resolves priority between these interrupt requests following the procedure described below. 1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are compared with each other. 2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority. 3) The ILEVEL and IMASK values are compared. If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels set in each Interrupt Control Register’s ILEVEL bit to select an interrupt request that has the highest priority. If the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU. Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control Register’s ILEVEL bit (disabled at level 7) provided for each internal peripheral I/O and the PSW register IE bit. 1) Interrupt requested or not Resolve priority according to Interrupt Priority Level (ILEVEL) 2) Resolve priority according to hardware priority 3) Compare with IMASK value Accept interrupt if PSW register IE bit = 1 (ILEVEL settings) TIN3-6 input interrupt request TIO4-7 output interrupt request TOP8,9 output interrupt request SIO0 transmit interrupt request DMA0-4 interrupt request A-D0 conversion interrupt request Level 3 Level 4 Level 5 Level 3 Level 1 Level 3 Requested Requested Requested Requested Not requested Requested Level 3 Level 3 Hardware fixed priority Level 3 Can be accepted when IMASK = 4-7 Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests 5-13 32182 Group User’s Manual (Rev.1.0) 5 Table 5.5.1 Hardware Fixed Priority Levels Priority High Interrupt Request Source TIN3–6 input interrupt request TIN20–23 input interrupt request TIN12–19 input interrupt request TIN0–2 input interrupt request TMS0,1 output interrupt request TOP8,9 output interrupt request TOP10 output interrupt request TIO4–7 output interrupt request TIO8,9 output interrupt request TOP0–5 output interrupt request TOP6,7 output interrupt request TIO0–3 output interrupt request DMA0–4 interrupt request SIO1 receive interrupt request SIO1 transmit interrupt request SIO0 receive interrupt request SIO0 transmit interrupt request A-D0 conversion interrupt request DMA5–9 interrupt request RTD interrupt request CAN0 transmit/receive & error interrupt request CAN1 transmit/receive & error interrupt Low request H'0000 0110 H'0000 0094 H'0000 0098 H'0000 009C H'0000 00A0 H'0000 00A8 H'0000 00AC H'0000 00B0 H'0000 00B4 H'0000 00B8 H'0000 00BC H'0000 00C0 H'0000 00C4 H'0000 00C8 H'0000 00CC H'0000 00D0 H'0000 00D4 H'0000 00D8 H'0000 00DC H'0000 00E8 H'0000 00F0 H'0000 010C INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation ICU Vector Table Address – – – – – – – – – – – – – – – – – – – – – – – H'0000 0097 H'0000 009B H'0000 009F H'0000 00A3 H'0000 00AB H'0000 00AF H'0000 00B3 H'0000 00B7 H'0000 00BB H'0000 00BF H'0000 00C3 H'0000 00C7 H'0000 00CB H'0000 00CF H'0000 00D3 H'0000 00D7 H'0000 00DB H'0000 00DF H'0000 00EB H'0000 00EF H'0000 00F3 H'0000 010F H'0000 0113 ICU Type of Input Source Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized SIO2,3 transmit/receive interrupt request H'0000 00EC Table 5.5.2 ILEVEL Settings and Accepted IMASK Values ILEVEL values set 0 (ILEVEL = "000") 1 (ILEVEL = "001") 2 (ILEVEL = "010") 3 (ILEVEL = "011") 4 (ILEVEL = "100") 5 (ILEVEL = "101") 6 (ILEVEL = "110") 7 (ILEVEL = "111") IMASK values at which interrupts are accepted Accepted when IMASK is 1–7 Accepted when IMASK is 2–7 Accepted when IMASK is 3–7 Accepted when IMASK is 4–7 Accepted when IMASK is 5–7 Accepted when IMASK is 6–7 Accepted when IMASK is 7 Not accepted (interrupts disabled) 5-14 32182 Group User’s Manual (Rev.1.0) 5 (1) Branching to the interrupt handler INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hardware preprocessing as described in Section 4.3, “EIT Processing Procedure.” The EIT vector entry for External Interrupt (EI) is located at the address H’0000 0080. This address is where the instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is written. (2) Processing in the External Interrupt (EI) handler A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is shown in Figure 5.5.2. [1] Saving each register to the stack Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator and FPSR register to the stack as necessary. [2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack Read the Interrupt Request Mask Register and save its content to the stack. [3] Reading the Interrupt Vector Register (IVECT) Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the Interrupt Vector Register is read, the following processing is automatically performed in hardware: • The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) • The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). • The interrupt request (EI) to the CPU core is dropped. • The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). [4] Reading and overwriting the Interrupt Request Mask Register (IMASK) Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK register causes the following processing to be automatically performed in hardware: • The interrupt request (EI) to the CPU core is dropped. • The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Note: • Processing in [4] here is unnecessary when multiple interrupts are to be enabled in [6] below. [5] Reading the ICU vector table Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source). The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) [6] Enabling multiple interrupts To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling multiple interrupts), set the PSW register IE bit to "1". [7] Branching to the internal peripheral I/O interrupt handler Branch to the start address of the interrupt handler that was read out in [5]. [8] Processing in the internal peripheral I/O interrupt handler [9] Disabling interrupts Clear the PSW register IE bit to "0" to disable interrupts. 5-15 32182 Group User’s Manual (Rev.1.0) 5 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation [10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing. The program returns to the state in which it was before the currently processed interrupt request was accepted. (3) Identifying the source of the interrupt request generated If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status Register provided for each internal peripheral I/O to identify the source of the interrupt request generated. (4) Enabling multiple interrupts To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack. Note: • Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU vector table, as shown in Figure 5.5.2, “Typical Handler Operation for Interrupts from Internal Peripheral I/O.” 5-16 32182 Group User’s Manual (Rev.1.0) 5 EI (External Interrupt) vector entry INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation H'0000 0080 BRA instruction EI (External Interrupt) handler Hardware preprocessing when EIT is accepted (Note 1) Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack [1] Program being executed [2] Interrupt generated Read and save Interrupt Request Mask Register (IMASK) to the stack Read Interrupt Vector Register (IVECT) Read and overwrite Interrupt Request Mask Register (IMASK) H'0080 0004 IMASK [3] H'0080 0000 (Note 2) IVECT [4] (Note 2) (Note 3) [5] [6] [7] Hardware postprocessing when RTE instruction is executed (Note 1) ICU vector table Read ICU vector table H'0000 0094 Set PSW register IE bit to 1 (Note 4) (Note 5) Interrupt handler start address H'0000 0113 Branch to the interrupt handler for each internal peripheral I/O Interrupt handler Interrupt handler [8] [9] [10] Clear PSW register IE bit to 0 Restore Interrupt Request Mask Register (IMASK) from the stack Restore general-purpose registers from the stack (Note 4) (Note 2) [11] Restore PSW from the stack [1] to [12]: Processing of EI by interrupt handler Restore BPC from the stack [12] RTE Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure." Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = 0). Note 3: When multiple interrupts are disabled, execute processing in [4]. Processing in [4] is unnecessary if multiple interrupts are enabled by executing processing in [6] and [9]. Note 4: To enable multiple interrupts, execute processing in [6] and [9]. Note 5: To reenable interrupts (by setting the IE bit to 1) after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. In the example here, there is no need to add a dummy access because the ICU vector table is read after reading the IVECT register. Similarly, to reenable interrupts (by setting the IE bit to 1) after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts. Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O 5-17 32182 Group User’s Manual (Rev.1.0) 5 5.6.1 Acceptance of SBI INTERRUPT CONTROLLER (ICU) 5.6 Description of System Break Interrupt (SBI) Operation 5.6 Description of System Break Interrupt (SBI) Operation System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is accepted anytime upon detection of a falling edge on the SBI# signal input pin no matter how the PSW register IE bit is set, and cannot be masked. 5.6.2 SBI Processing by Handler When the system break interrupt generated has been serviced, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. SBI (System Break Interrupt) vector entry H'0000 0010 BRA instruction SBI (System Break Interrupt) handler Program being executed Processing to shut down the system (Note 1) SBI generated Shut down or reset the system Note 1: Do not return to the program that was being executed when the interrupt occurred. Figure 5.6.1 Typical SBI Operation 5-18 32182 Group User’s Manual (Rev.1.0) CHAPTER 6 INTERNAL MEMORY 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Outline of the Internal Memory Internal RAM Internal Flash Memory Registers Associated with the Internal Flash Memory Programming the Internal Flash Memory Virtual Flash Emulation Function Connecting to A Serial Programmer Internal Flash Memory Protect Function Precautions To Be Taken when Rewriting the Internal Flash Memory 6 6.1 Outline of the Internal Memory The 32182 internally contains the following types of memory: • 64-Kbyte RAM • 384-Kbytes flash memory INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.2 Internal RAM Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Size Location address Wait insertion Internal bus connection Dual port Specification 64 Kbytes H’0080 4000 to H’0081 3FFF Operates with zero wait states Connected by 32-bit bus By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of the internal RAM via serial communication from external devices independently of the CPU. (See Chapter 14, “Real-Time Debugger.”) Notes: • Immediately after power-on reset (for the power-on case in which VDDE also goes up from GND), the value of the RAM is undefined. • If the RAM is reset during RAM backup (power for only VDDE is on), the RAM retains the value it had immediately before being reset. 6.3 Internal Flash Memory Specifications of the internal flash memory are shown below. Table 6.3.1 Specifications of the Internal Flash Memory Item Size Location address Wait insertion Durability Internal bus connection Specification M32182F3: 384 Kbytes M32182F8: 1 Mbyte M32182F3: H’0000 0000 to H’0005 FFFF M32182F8: H’0000 0000 to H’000F FFFF Operates with one wait state Can be rewritten 100 times Instruction access: Connected by 64-bit bus (Transfer rates equivalent to zero wait states on 32-bit bus are possible.) Data access: Connected by 32-bit bus Other Virtual flash emulation function is incorporated. (See Section 6.6, “Virtual Flash Emulation Function.”) 6-2 32182 Group User’s Manual (Rev.1.0) 6 H'0000 0000 H'0000 4000 H'0000 6000 H'0000 8000 H'0001 0000 INTERNAL MEMORY 6.3 Internal Flash Memory Internal flash memory area of the M32182F3 (384 Kbytes) 16KB 8KB 8KB 32KB 64KB Block 0 Block 1 Block 2 Block 3 Unequal blocks Block 4 H'0002 0000 64KB H'0003 0000 Block 5 64KB H'0004 0000 Block 6 Equal blocks 64KB H'0005 0000 Block 7 64KB H'0005 FFFF Block 8 Figure 6.3.1 Block Configuration of the M32182F3’s Internal Flash Memory 6-3 32182 Group User’s Manual (Rev.1.0) 6 Internal flash memory area of the M32182F8 (1 Mbyte) H'0000 0000 H'0000 4000 H'0000 6000 H'0000 8000 H'0001 0000 INTERNAL MEMORY 16KB 8KB 8KB 32KB 64KB Block 0 Block 1 Block 2 Unequal blocks Block 3 Block 4 H'0002 0000 64KB H'0003 0000 Block 5 64KB H'0004 0000 Block 6 64KB H'0005 0000 Block 7 64KB H'0006 0000 Block 8 64KB H'0007 0000 Block 9 64KB H'0008 0000 Block 10 64KB H'0009 0000 Block 11 Equal blocks 64KB H'000A 0000 Block 12 64KB H'000B 0000 Block 13 64KB H'000C 0000 Block 14 64KB H'000D 0000 Block 15 64KB H'000E 0000 Block 16 64KB H'000F 0000 Block 17 64KB H'000F FFFF Block 18 Figure 6.3.2 Block Configuration of the M32182F8’s Internal Flash Memory 6-4 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4 Registers Associated with the Internal Flash Memory A register map associated with the internal flash memory is shown below. Internal Flash Memory Related Register Map Address b0 H'0080 01E0 H'0080 01E2 H'0080 01E4 H'0080 01E6 H'0080 01E8 H'0080 01EA H'0080 01EC H'0080 01EE H'0080 01F0 H'0080 01F2 H'0080 01F4 H'0080 01F6 Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) Flash Control Register 3 (FCNT3) (Use inhibited area) Virtual Flash S Bank Register (FESBANK0) Virtual Flash S Bank Register (FESBANK1) Virtual Flash S Bank Register (FESBANK2) Virtual Flash S Bank Register (FESBANK3) Virtual Flash S Bank Register (FESBANK4) Virtual Flash S Bank Register (FESBANK5) Virtual Flash S Bank Register (FESBANK6) Virtual Flash S Bank Register (FESBANK7) 0 1 2 3 4 5 6 7 6-12 6-12 6-12 6-12 6-12 6-12 6-12 6-12 +0 address b7 b8 Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 4 (FCNT4) +1 address b15 6-5 6-6 6-8 6-9 6-10 See pages 6.4.1 Flash Mode Register Flash Mode Register (FMOD) b0 0 4 0 1 0 2 0 3 0 5 0 6 0 b7 FPMOD ? b 0–6 7 Bit Name No function assigned. Fix to "0" FPMOD External FP pin status bit 0: FP pin = "low" 1: FP pin = "high" Function R 0 R W 0 – The Flash Mode Register (FMOD) is a read-only status register, with its FPMOD bit indicating the FP (Flash Protect) pin status. The internal flash memory is enabled for programming or erase operation only when FPMOD = "1", and is protected against programming or erase operation when FPMOD = "0". 6-5 32182 Group User’s Manual (Rev.1.0) 6 6.4.2 Flash Status Registers INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory There are two registers to indicate the status of the internal flash memory: Flash Status Register 1 (FSTAT1) located in the SFR area (H’0080 01E1) and Flash Status Register 2 (FSTAT2) included in the internal flash memory. Use these two status registers (FSTAT1 and FSTAT2) to control the programming or erase operation performed on the internal flash memory. Flash Status Register 1 (FSTAT1) b8 0 13 0 9 0 10 0 11 0 12 0 14 0 b15 FSTAT 1 b 8–14 15 Bit Name No function assigned. Fix to "0". FSTAT Ready/busy status bit 0: Busy 1: Ready Function R 0 R W 0 – Flash Status Register 1 (FSTAT1) is a read-only status register used to know the status of the programming or erase operation performed on the internal flash memory. When FSTAT = "0" (busy), the internal flash memory is being programmed or erased, during which time do not start a new programming or erase operation on it. When FSTAT = "1" (ready), a new programming or erase operation can be started on it. Furthermore, while FSTAT = "0" (busy), do not operate on the FCNT4 register FRESET bit described later. 6.4.3 Flash Status Register 2 (FSTAT2) Flash Status Register 2 (FSTAT2) b8 FBUSY 1 0 9 10 0 11 0 12 0 13 0 14 0 b15 0 ERASE WRERR1 WRERR2 b 8 9 10 11 12 13–15 Bit Name FBUSY Flash busy bit No function assigned. Fix to "0". ERASE Erase status confirmation bit WRERR1 Write status confirmation bit 1 WRERR2 Write status confirmation bit 2 No function assigned. Fix to "0". 0: Erase normally operating or terminated 1: Erase error occurred 0: Programming normally operating or terminated 1: Programming error occurred 0: Programming normally operating or terminated 1: Over-programming occurred R R 0 – – 0 Function 0: Being programmed or erased 1: Ready state R R 0 R W – – – 6-6 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory This status register is included in the internal flash memory, and can be enabled for read by writing the Read Status command (H’7070) to any address of the internal flash memory. For details, see Section 6.5, “Programming the Internal Flash Memory.” Flash Status Register 2 (FSTAT2) consists of the following four read-only status bits that indicate the operation condition of the internal flash memory. (1) FBUSY (Flash Busy) bit (Bit 8) The FBUSY bit is used to determine whether the operation on the internal flash memory is finished when it is being programmed or erased. When FBUSY = "0", it means that the programming or erase operation is being executed; when FBUSY = "1", the operation is finished. (2) ERASE (Erase status) bit (Bit 10) The ERASE bit is used to determine after execution of processing whether the erase operation performed on the internal flash memory resulted in an error. When ERASE = "0", it means that the erase operation terminated normally; when ERASE = "1", the erase operation terminated in an error. (3) WRERR1 (Write status 1) bit (Bit 11) The WRERR1 bit is used to determine after completion of processing whether the programming operation performed on the internal flash memory resulted in an error. When WRERR1 = "0", it means that the programming operation terminated normally; when WRERR1 = "1", the programming operation terminated in an error. The condition under which WRERR1 is set to "1" is when any bit other than those that must be "0" is found to be "0" by comparison between the write data and the data in the internal flash memory. (4) WRERR2 (Write status 2) bit (Bit 12) The WRERR2 bit is used to determine after execution of processing whether the programming operation performed on the internal flash memory resulted in an error. When WRERR2 = "0", it means that the programming operation terminated normally; when WRERR2 = "1", the programming operation terminated in an error. The condition under which WRERR2 is set to "1" is when the internal flash memory cannot be written to even by repeating the programming operation a specified number of times. 6-7 32182 Group User’s Manual (Rev.1.0) 6 6.4.4 Flash Control Registers Flash Control Register 1 (FCNT1) b0 0 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 5 0 1 0 2 0 3 FENTRY 0 4 0 6 0 b7 FEMMOD 0 b 0–2 3 4–6 7 Bit Name No function assigned. Fix to "0". FENTRY Flash E/W enable mode entry bit No function assigned. Fix to "0". FEMMOD Virtual flash emulation mode bit 0: Normal mode 1: Virtual flash emulation mode 0: Normal read 1: Program/erase enable Function R 0 R 0 R W 0 W 0 W Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory. (1) FENTRY (Flash Mode Entry) bit (Bit 3) The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can only be entered when FENTRY = "1". To set the FENTRY bit to "1", write "0" and then "1" to the FENTRY bit in succession while the FP pin = "high". To clear the FENTRY bit, check to see that the FSTAT1 register FSTAT bit = "1" (ready) and then write "0" to the FENTRY bit. Note that the following operations cannot be performed while programming or erasing the internal flash memory (FSTAT1 register FSTAT bit = "0" (busy)). If one of these operations is attempted, the FENTRY bit is cleared to "0" in hardware. 1) Writing "0" to the FENTRY bit 2) Entering a low-level signal to the FP pin 3) Entering a low-level signal to the RESET# pin When running a program resident in the internal flash memory while the FENTRY bit = "0", the EI vector entry is located at the address H’0000 0080 of the internal flash memory. When running the flash write/erase program in the RAM while the FENTRY bit = "1", the EI vector entry is located at the address H’0080 4000 of the RAM, allowing the flash programming/erase operation to be controlled using interrupts. Table 6.4.1 Changes of the EI Vector Entry by FENTRY FENTRY 0 1 EI Vector Entry Internal flash memory area Internal RAM area Address H'0000 0080 H'0080 4000 (2) FEMMOD (Virtual Flash Emulation Mode) bit (Bit 7) The FEMMOD bit controls entry to virtual flash emulation mode. Virtual flash emulation mode is entered by setting the FEMMOD bit to "1" while the FENTRY bit = "0". (For details, see Section 6.6, “Virtual Flash Emulation Function.”) 6-8 32182 Group User’s Manual (Rev.1.0) 6 Flash Control Register 2 (FCNT2) b8 0 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 13 0 9 0 10 0 11 0 12 0 14 0 b15 FPROT 0 b 8–14 15 Bit Name No function assigned. Fix to "0". FPROT Unlock bit 0: Protection by lock bit effective 1: Protection by lock bit invalidated Function R 0 R W 0 W Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection by a lock bit (protection against programming/erase operation). Protection of the internal flash memory is invalidated by setting the FPROT bit to "1", so that any blocks protected by a lock bit can now be programmed or erased. To set the FPROT bit to "1", write "0" and then "1" to the FPROT bit in succession while the FENTRY bit = "1". To clear the FPROT bit to "0", write "0" to the FPROT bit. If one of the following operations is attempted, the FPROT bit is cleared to "0". 1) Writing "0" to the FPROT bit 2) Entering a low-level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a low-level signal to the RESET# pin FENTRY = 1 YES NO FENTRY = 1 FPROT = 0 FPROT = 0 FPROT is not set to 1 if a write cycle to any other area occurs during this time. FPROT = 1 Figure 6.4.1 Protection Unlocking Flow FPROT = 1 6-9 32182 Group User’s Manual (Rev.1.0) 6 Flash Control Register 3 (FCNT3) b0 0 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 5 0 1 0 2 0 3 0 4 0 6 0 b7 FELEVEL 0 b 0–6 7 Bit Name No function assigned. Fix to "0". FELEVEL Erase margin-up bit 0: Normal level 1: Raise erase margin up Function R 0 R W 0 W Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands. The internal flash memory erase level can be deepened by setting the FELEVEL bit to "1". Flash Control Register 4 (FCNT4) b8 0 13 0 9 0 10 0 11 0 12 0 14 0 b15 FRESET 0 b 8–14 15 Bit Name No function assigned. Fix to "0". FRESET Flash reset bit 0: No operation 1: Reset Function R 0 R W 0 W Flash Control Register 4 (FCNT4) controls initializing each status bit of Flash Status Register 2 (FSTAT2) or canceling a programming/erase operation. Setting the FRESET bit to "1" initializes each status bit of the FSTAT2 register or cancels a programming/erase operation. The FRESET bit is effective only when the FENTRY bit = "1". If the FENTRY bit = "0", the FRESET bit information is ignored. When programming or easing the internal flash memory, make sure the FRESET bit remains "0". An example for clearing each status of FSTAT2 during a programming/erase operation, and an example for forcibly terminating (canceling) a programming/erase operation due to time-out are shown below. 6-10 32182 Group User’s Manual (Rev.1.0) 6 FENTRY = 0 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory FENTRY = 1 Program/erase the flash memory * At this point in time, the FSTAT1 register FSTAT bit = 1 (ready). Error found YES FRESET = 1 Programming/erase operation terminated normally NO FRESET = 0 Program/erase the flash memory Figure 6.4.2 Example of FCNT4 Register Operation 1 (Clearing each status of the FSTAT2 register) Flash programming/erase operation has timed out Forcibly terminate FRESET = 1 FRESET = 0 Figure 6.4.3 Example of FCNT4 Register Operation 2 (Forcibly terminating operation when programming/ erasing the internal flash memory) 6-11 32182 Group User’s Manual (Rev.1.0) 6 Virtual Virtual Virtual Virtual Virtual Virtual Virtual Virtual b0 MODENS INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.5 Virtual Flash S Bank Registers Flash Flash Flash Flash Flash Flash Flash Flash 1 0 S S S S S S S S Bank Bank Bank Bank Bank Bank Bank Bank 2 0 Register Register Register Register Register Register Register Register 3 0 0 1 2 3 4 5 6 7 4 0 (FESBANK0) (FESBANK1) (FESBANK2) (FESBANK3) (FESBANK4) (FESBANK5) (FESBANK6) (FESBANK7) 5 0 7 0 6 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 SBANKAD 0 b 0 1–7 8-15 Bit Name MODENS Virtual flash emulation enable bit No function assigned. Fix to "0". SBANKAD S bank address Start address A12–A19 of the relevant S bank Function 0: Disable virtual flash emulation function 1: Enable virtual flash emulation function 0 R 0 W R R W W Note: • These registers must always be accessed in halfwords. (1) MODENS (Virtual Flash Emulation Enable) bit (Bit 0) The MODENS bit can be set to "1" after entering virtual flash emulation mode (by setting the FEMMOD bit to "1" while the FENTRY bit = "0"). This causes the virtual flash emulation function to be enabled for the S bank area selected by the SBANKAD bits. (2) SBANKAD (S Bank Address) bits (Bits 8–15) The SBANKAD bits are provided for selecting one of the S banks that are separated every 4 KB. Use these SBANKAD bits to set the eight bits A12–A19 of the 32-bit start address of the desired S bank. Note: • For details, see Section 6.6, “Virtual Flash Emulation Function.” 6-12 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5 Programming the Internal Flash Memory 6.5.1 Outline of Internal Flash Memory Programming To program or erase the internal flash memory, there are following two methods to choose depending on the situation: (1) When the flash write/erase program does not exist in the internal flash memory (2) When the flash write/erase program already exists in the internal flash memory For (1), set the FP pin = "high", MOD0 = "high" and MOD1 = "low" to enter boot mode. In this case, the CPU starts running the boot program immediately after reset. The boot program transfers the flash write/erase program into the internal RAM. After the transfer, jump to a location in the RAM and use the RAM-resident program to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in boot mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. For (2), set the FP pin = "high", MOD0 = "low" and MOD1 = "low" to enter single-chip mode. Transfer the flash write/erase program from the internal flash memory in which it has been prepared into the internal RAM. After the transfer, jump to the RAM and use the program transferred into the RAM to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in single-chip mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. Or flash E/W enable mode can be entered from external extension mode by setting the FP pin = "high", MOD0 = "low" and MOD1 = "high". During flash E/W enable mode (FP pin = 1, FENTRY = 1), the EIT vector entry for External Interrupt (EI) is relocated to the start address (H’0080 4000) of the internal RAM. During normal mode, it is located in the flash area (H’0000 0080). Flash E/W enable mode (FENTRY = 1) Normal mode (FENTRY = 0) H'0000 0000 Internal ROM area H'0000 0000 Internal ROM area EI vector entry (H'0000 0080) H'0080 3FFF H'0080 4000 Internal RAM EI vector entry (H'0080 4000) H'0080 3FFF H'0080 4000 Internal RAM H'00FF FFFF H'00FF FFFF Figure 6.5.1 EI Vector Entry during Flash E/W Enable Mode 6-13 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (1) When the flash write/erase program does not exist in the internal flash memory In this case, the boot program is used to program or erase the internal flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode. To program or erase the internal flash memory using a flash programmer, follow the procedure described below. FP = L or H MOD1 = L MOD0 = L RESET = L • Initial state (Flash write/erase program nonexistent in the internal flash memory) RAM CPU Flash memory Boot program Write data SIO1 External device (e.g., flash programmer) M32R/ECU FP = H MOD1 = L MOD0 = H RESET = H • Set the FP pin high, MOD0 pin high and MOD1 pin low to place the flash memory in boot mode + flash E/W enable mode. • Dessert reset signal and start up with the boot program. • Transfer the flash write/erase program into the RAM. • Jump to the flash write/erase program in the RAM. RAM Flash write/ erase program CPU Flash memory Boot program Write data SIO1 External device (e.g., flash programmer) M32R/ECU FP = H MOD1 = L MOD0 = H RESET = H RAM Flash write/ erase program CPU • Using the flash write/erase program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. • Program or erase the internal flash memory using the flash write/erase program. • When finished, reset MOD0 low and jump to the internal flash memory or apply a reset to enter normal mode. Flash memory Flash write data Boot program SIO1 M32R/ECU Write data External device (e.g., flash programmer) Figure 6.5.2 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program does not exist in it) 6-14 32182 Group User’s Manual (Rev.1.0) 6 POWER ON Mode selected INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Reset signal deasserted (Boot program starts) Reset signal deasserted Mode selected RESET# pin MOD0 pin MOD1 pin FP pin Settings by the boot program FENTRY bit Flash programming/erasing by the boot program Figure 6.5.3 Internal Flash Memory Write/Erase Timing (when the flash write/erase program does not exist in it) 6-15 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (2) When the flash write/erase program already exists in the internal flash memory In this case, the flash write/erase program prepared in the internal flash memory is used to program or erase the internal flash memory. For programming/erase operation here, use the internal peripheral circuits in the manner suitable for the programming system. (All resources of the internal peripheral circuits such as the data bus, serial I/O and ports can be used.) The following shows an example for programming or erasing the internal flash memory by using serial I/O0 in single-chip mode. FP = L or H MOD1 = L MOD0 = L • Initial state (Flash write/erase program existing in the internal flash memory) • An ordinary program in the internal flash memory is being executed. RAM CPU Flash write/ erase program SIO0 Write data External device M32R/ECU FP = H MOD1 = L MOD0 = L • Set the FP pin high, MOD1 pin low and MOD0 pin low to place the flash memory in single-chip + flash E/W enable mode. • After determining the FP pin and MOD1 pin levels, transfer the flash write/erase program from the internal flash memory area into the RAM. • Jump to the flash write/erase program in the RAM. RAM Flash write/ erase program CPU Flash memory SIO0 Write data External device M32R/ECU FP = H MOD1 = L MOD0 = L RAM Flash write/ erase program • Using the flash write/erase program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. • Program or erase the internal flash memory using the flash write/erase program in the RAM. • When finished, jump to the program in the flash memory or apply a reset to enter normal mode. CPU Flash memory Flash write data SIO0 Write data External device M32R/ECU Figure 6.5.4 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program already exists in it) 6-16 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Flash rewrite Flash mode turned on starts Flash mode turned off RESET# pin High or low MOD0 pin Low MOD1 pin High or low (single-chip or external extension) FP pin High or low FENTRY bit Flash programming/erasing by the flash write/erase program Flash write/erase program transferred into the RAM Figure 6 .5.5 Internal Flash Memory Write/Erase Timing (when the flash write/erase program already exists in it) 6-17 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.2 Controlling Operation Modes during Flash Programming The microcomputer’s operation mode is set by MOD0, MOD1 and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be used when programming or erasing the internal flash memory. Table 6.5.1 Operation Modes Set during Flash Programming/Erase FP 0 1 0 MOD0 MOD1 FENTRY (Note 1) Operation Mode 0 0 1 0 0 0 0 0 0 Processor mode Single-chip mode Reset Vector Entry Start address of internal flash memory (H'0000 0000) Start address of external area (H'0000 0000) 0 1 1 0 0 0 1 1 0 0 0 1 External extension mode Single-chip mode + flash E/W enable 1 1 1 1 1 0 0 0 1 0 1 1 Boot mode Boot mode + flash E/W enable External extension mode + flash E/W enable – 1 1 – Use inhibited Start address of internal flash memory (H'0000 0000) Start address of internal flash memory (H'0000 0000) Boot program starts running Boot program starts running Start address of internal flash memory (H'0000 0000) – – Flash area (H'0000 0080) Beginning of internal RAM (H'0080 4000) Beginning of internal RAM (H'0080 4000) Beginning of internal RAM (H'0080 4000) (H'0000 0080) Flash area (H'0000 0080) External area EI Vector Entry Flash area (H'0000 0080) Note 1: Indicates the Flash Control Register 1 (FCNT1) FENTRY bit status (– denotes “Don’t care”). However, if FP = "0", writing "1" to FENTRY only results in it cleared to "0". (1) Flash E/W enable mode Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, the necessary program must be transferred into the internal RAM before entering flash E/W enable mode, so that it can be executed in the RAM. (2) Entering flash E/W enable mode Flash E/W enable mode can only be entered when operating in single-chip, external extension or boot mode. Furthermore, it is only when the FP pin = "high" and the Flash Control Register 1 (FCNT1) FENTRY bit = "1" that flash E/W enable mode can be entered. Flash E/W enable mode cannot be entered when operating in processor mode or the FP pin = "low". 6-18 32182 Group User’s Manual (Rev.1.0) 6 (3) Detecting the MOD0 and MOD1 pin levels INTERNAL MEMORY 6.5 Programming the Internal Flash Memory The MOD0 and MOD1 pin levels ("high" or "low") can be known by checking the P8 Data Register (Port Data Register, H’0080 0708) MOD0DT and MOD1DT bits. P8 Data Register (P8DATA) b0 ? 4 P84DT ? 1 ? 2 ? 3 P83DT ? 5 P85DT ? 6 P86DT ? b7 P87DT ? MOD0DT MOD1DT P82DT b 0 1 2 3 4 5 6 7 Bit Name MOD0DT MOD0 data bit MOD1DT MOD1 data bit P82DT Port P82 data bit P83DT Port P83 data bit P84DT Port P84 data bit P85DT Port P85 data bit P86DT Port P86 data bit P87DT Port P87 data bit Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL). Function 0: MOD0 pin = "low" 1: MOD0 pin = "high" 0: MOD1 pin = "low" 1: MOD1 pin = "high" At read Depends on how the Port Direction Register is set • If direction bit = "0" (input mode) 0: Port input pin = "low" 1: Port input pin = "high" • If direction bit = "1" (output mode) (Note 1) 0: Port output latch = "0" / Port pin level = "low" 1: Port output latch = "1" / Port pin level = "high" At write Write to the port output latch R R R R W – – W 6-19 32182 Group User’s Manual (Rev.1.0) 6 START INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Enter one of the following modes: • Single-chip mode • Boot mode • External extension mode FMOD(H'0080 01E0) FPMOD P8DATA(H'0080 0708) D0 = MOD0DT D1 = MOD1DT Check MOD0/1 and FP pin levels OK NO END Transfer the flash write/erase program into the internal RAM Set the Flash Control Register in SFR area (FCNT1, H'0080 01E2) FENTRY bit to 0 Switched to the flash write/erase program Set the Flash Control Register in SFR area (FCNT1, H'0080 01E2) FENTRY bit to 1 → Go to flash E/W enable mode Wait for 1 µs (using a hardware or software timer) Execute flash write/erase command and various read commands (Note 1) Jump to the flash memory or apply reset Switched to normal mode END Note 1: For details about each command, see Section 6.5.4, "Procedure for Programming/Erasing the Internal Flash Memory." Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode 6-20 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.3 Procedure for Programming/Erasing the Internal Flash Memory To program or erase the internal flash memory, set up chip mode to enter flash E/W enable mode and execute the flash write/erase program in the internal RAM into which it has been transferred from the internal flash memory. In flash E/W enable mode, because the internal flash memory cannot be accessed for read as in normal mode, no programs present in it can be executed. Therefore, the flash write/erase program must be made available in the internal RAM before entering flash E/W enable mode. (Once flash E/W enable mode is entered into, only flash commands and no other commands can be used to access the internal flash memory.) To access the internal flash memory in flash E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash E/W enable mode. Note: • During flash E/W enable mode, the internal flash memory cannot be accessed for read or write wordwise. Table 6.5.2 Commands in Flash E/W Enable Mode Command Name Read Array command Page Program command Lock Bit Program command Block Erase command Erase All Unlocked Blocks command Read Status Register command Clear Status Register command Read Lock Bit Status command Verify command (Note 1) Issued Command Data H'FFFF H'4141 H'7777 H'2020 H'A7A7 H'7070 H'5050 H'7171 H'D0D0 Note 1: • This command is used in conjunction with Lock Bit Program, Block Erase and Erase All Unlocked Blocks operations. • This command must be issued immediately after the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command. • If the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is followed by the Read Array command (H’FFFF), the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is canceled. • If the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is followed by other than the Verify (H'D0D0) or Read Array (H'FFFF) command, the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is not executed normally and terminated in error. (1) Read Array command Writing the command (H’FFFF) to any address of the internal flash memory places it in read mode. Then read the desired flash memory address, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command. START Write the Read Array command (H'FFFF) to any address of the internal flash memory Read the desired flash memory address END Figure 6.5.7 Read Array Command 6-21 32182 Group User’s Manual (Rev.1.0) 6 (2) Page Program command INTERNAL MEMORY 6.5 Programming the Internal Flash Memory The internal flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H’00 to H’FF). To program the flash memory, write the Page Program command (H’4141) to any address of the internal flash memory and then the program data to the address to be programmed. The protected flash memory blocks cannot be accessed for write by the Page Program command. Page programming is automatically performed by the internal control circuit, and whether the Page Program command has finished can be known by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (See Section 6.4.2, “Flash Status Registers.”) While the FSTAT bit = "0" (busy), the next programming (by the Page Program command) cannot be performed. START Write the Page Program command (H'4141) to any address of the internal flash memory Write the program data to the internal flash memory address to be programmed (Note 1) Write the next program data to the previously programmed address + 2 NO Finished programming one page? YES Internal flash memory is programmed by Page Program (Note 2) Wait for 1 µs (using a hardware or software timer) NO FSTAT bit = 1 YES Read any address of the internal flash memory (Note 3) to check for programming error (see Figure 6.4.2) TIME OUT? 0.5s YES NO To next page NO Forcibly terminated (see Figure 6.4.3.) Last address? YES END Note 1: Start programming from the beginning of a 256-byte boundary (lower address H'00). Note 2: When a programming operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 3: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error. Figure 6.5.8 Page Program Command 6-22 32182 Group User’s Manual (Rev.1.0) 6 (3) Lock Bit Program command INTERNAL MEMORY 6.5 Programming the Internal Flash Memory The internal flash memory can be protected against programming/erase operation one block at a time. The Lock Bit Program command is provided for protecting the flash memory blocks. Write the Lock Bit Program command (H’7777) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be protected, and this memory block is thereby protected against programming/erase operation. To remove protection, use the Flash Control Register 2 (FCNT2) FPROT bit to invalidate protection by a lock bit (see Section 6.4.3, “Flash Control Registers”) and erase the flash memory block whose protection is to be removed. (The content of that memory block is also erased.) Executing a programming/erase operation on flash memory blocks protected by a lock bit results in an error. If erased, the FSTAT2 register ERASE bit is set to "1" (erase error occurred); if programmed, the FSTAT2 register WRERR1 bit is set to "1" (programming error occurred). The table below lists the target flash memory blocks and their addresses to be specified when writing the Verify command. Table 6.5.3 M32182F3 Target Blocks and Specified Addresses Target Block 0 1 2 3 4 5 6 7 8 Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE Table 6.5.4 M32182F8 Target Blocks and Specified Addresses Target Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE H'0008 FFFE H'0009 FFFE H'000A FFFE H'000B FFFE H'000C FFFE H'000D FFFE H'000E FFFE H'000F FFFE 6-23 32182 Group User’s Manual (Rev.1.0) 6 START INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Write the Lock Bit Program command (H'7777) to any address of the internal flash memory Write the Verify command (H'D0D0) to the last even address of the flash memory block to be protected Lock bit is programmed by Lock Bit Program (Note 1) Wait for 1 µs (using a hardware or software timer) NO FSTAT bit = 1 YES TIME OUT? 0.5s Read any address of the internal flash memory (Note 2) to check for programming error (see Figure 6.4.2) YES Forcibly terminated (see Figure 6.4.3.) NO END Note 1: When a programming operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error. Figure 6.5.9 Lock Bit Program Command 6-24 32182 Group User’s Manual (Rev.1.0) 6 (4) Block Erase command INTERNAL MEMORY 6.5 Programming the Internal Flash Memory The Block Erase command erases the content of the internal flash memory one block at a time. To perform this operation, write the Block Erase command (H’2020) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be erased (see Table 6.5.3, “M32182F3 Target Blocks and Specified Addresses”). The protected flash memory blocks cannot be erased by the Block Erase command. Block erase operation is automatically performed by the internal control circuit, and whether the Block Erase command has finished can be known by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (See Section 6.4.2, “Flash Status Registers.”) While the FSTAT bit = "0" (busy), the next block erase operation (by the Block Erase command) cannot be performed. START Write the Block Erase command (H'2020) to any address of the internal flash memory Write the Verify command (H'D0D0) to the last even address of the flash memory block to be erased Internal flash memory contents are erased by the Block Erase command (Note 1) Wait for 1 µs (using a hardware or software timer) NO FSTAT bit = 1 YES TIME OUT? 1s Read any address of the internal flash memory (Note 2) to check for erase error (see Figure 6.4.2) YES Forcibly terminated (see Figure 6.4.3.) NO END Note 1: When an erase operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for erase error. Figure 6.5.10 Block Erase Command 6-25 32182 Group User’s Manual (Rev.1.0) 6 (5) Erase All Unlocked Blocks command INTERNAL MEMORY 6.5 Programming the Internal Flash Memory The Erase All Unlocked Blocks command erases all flash memory blocks that are not protected. To erase all unlocked blocks, write the command (H’A7A7) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to any address of the internal flash memory, and all unlocked memory blocks are thereby erased. START Write the Erase All Unlocked Blocks command (H'A7A7) to any address of the internal flash memory Write the Verify command (H'D0D0) to any address of the internal flash memory Flash memory contents are erased by Erase All Unlocked Blocks (Note 1) Wait for 1 µs (using a hardware or software timer) NO FSTAT bit = 1 YES TIME OUT? 10s Read any address of the internal flash memory (Note 2) to check for erase error (see Figure 6.4.2) YES Forcibly terminated (see Figure 6.4.3.) NO END Note 1: When an erase operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for erase error. Figure 6.5.11 Erase All Unlocked Blocks Command 6-26 32182 Group User’s Manual (Rev.1.0) 6 (6) Read Status Register command INTERNAL MEMORY 6.5 Programming the Internal Flash Memory The Read Status Register command reads the content of Flash Status Register 2 (FSTAT2) that indicates whether flash memory programming or erase operation has terminated normally. To read Flash Status Register 2, write the Read Status Register command (H’7070) to any address of the internal flash memory. Next, read any address of the internal flash memory, and Flash Status Register 2 (FSTAT2) will be read out. START Write the Read Status Register command (H'7070) to any address of the internal flash memory Read any address of the internal flash memory END Figure 6.5.12 Read Status Register Command (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to "0". Write the Clear Status Register command (H’5050) to any address of the internal flash memory, and Flash Status Register 2 is thereby initialized. If an error occurs when programming or erasing the internal flash memory and the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) or WRERR2 (write status 2) bit is set to "1", the next programming or erase operation cannot be executed unless each status bit is cleared to "0". START Write the Clear Status Register command (H'5050) to any address of the internal flash memory END Figure 6.5.13 Clear Status Register Command 6-27 32182 Group User’s Manual (Rev.1.0) 6 (8) Read Lock Bit Status command INTERNAL MEMORY 6.5 Programming the Internal Flash Memory The Read Lock Bit Status command is provided for checking whether a flash memory block is protected against programming/erase operation. Write the Read Lock Bit Status command (H’7171) to any address of the internal flash memory. Next, read the last even address of the flash memory block to be checked (see Table 6.5.3, “M32182F3 Target Blocks and Specified Addresses”), and the read data shows whether the target block is protected. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) in the read data both are "0", it means that the target memory block is protected. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) both are "1", it means that the target memory block is not protected. START Write the Read Lock Bit Status command (H'7171) to any address of the internal flash memory Read the last even address of the flash memory block to be checked END Figure 6.5.14 Read Lock Bit Status Command 6-28 32182 Group User’s Manual (Rev.1.0) 6 Lock Bit Status Register (FLBST) b0 ? INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 1 FLBST0 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 FLBST1 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? ? ? b 0 1 2–8 9 Bit Name No function assigned. FLBST0 Lock bit 0 No function assigned. FLBST1 Lock bit 1 No function assigned. 0: Protected 1: Not protected (Same content as FLBST0 is output) 10–15 ? – 0: Protected 1: Not protected Function R ? R ? R W – – – – The Lock Bit Status Register is a read-only register, which is included for each memory block independently of one another. The following shows how the lock bits in this register are set. a) Setting the lock bit to "0" (protected) Issue the Lock Bit Program command (H’7777) to the memory block to be protected. b) Setting the lock bit to "1" (not protected) Set the Flash Control Register 2 FPROT bit to invalidate protection by a lock bit, then issue the Block Erase command (H’2020) or Erase All Unlocked Blocks command (H’A7A7) to erase the memory block which is to be unprotected. This is the only way to set the lock bit to "1". In no way can the lock bit alone be set to "1". c) Lock bit status after reset Because the lock bits are nonvolatile, they are unaffected by a reset and power-off. 6-29 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.4 Flash Programming Time (Reference) The following shows the time needed to program internal flash memory for reference. (1) Time required for transfer by SIO (for a transfer data size of 384 KB) 1/57,600 bps × 1 (frame) × 11 (number of bits transferred) × 384 KB = approx. 75.1 [s] (2) Time required for programming the flash memory 384 KB / 256-byte block × 8 ms = approx. 12.3 [s] (3) Time required for erasing the entire area 50 ms × 9 (blocks) = approx. 450 [ms] (4) Total flash programming time (entire 384 KB area) When communicating at 57,600 bps via UART, the flash programming time can be ignored because it is very short compared to the serial communication time. Therefore, the total flash programming time can be calculated using the equation below. (1) + (3) = approx. 76 [s] If the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. (2) + (3) = approx. 13 [s] 6-30 32182 Group User’s Manual (Rev.1.0) 6 6.6 Virtual Flash Emulation Function INTERNAL MEMORY 6.6 Virtual Flash Emulation Function The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function. This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the contents of internal flash memory at the addresses specified by the Virtual Flash S Bank Register. That way, the relevant RAM data can read out by reading the content of internal flash memory. For applications that require modifying the contents of internal flash memory (e.g., data table) during operation, this function enables dynamic data modification by modifying the relevant RAM data. The RAM blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual RAM. This function, when used in combination with the microcomputer’s internal Real-Time Debugger (RTD), allows the data table, etc. created in the internal flash memory to be referenced or rewritten from the outside, thereby facilitating data table tuning from an external device. Note: • Before programming/erasing the internal flash memory, always be sure to exit this virtual flash emulation mode. H'0080 4000 (Cannot be used for virtual flash emulation) H'0080 8000 H'0080 9000 H'0080 A000 RAM bank block 0 (FESBANK0) 4 Kbytes RAM bank block 1 (FESBANK1) 4 Kbytes RAM bank block 2 (FESBANK2) 4 Kbytes RAM bank block 3 (FESBANK3) 4 Kbytes RAM bank block 4 (FESBANK4) 4 Kbytes RAM bank block 5 (FESBANK5) 4 Kbytes RAM bank block 6 (FESBANK6) 4 Kbytes RAM bank block 7 (FESBANK7) 4 Kbytes H'0080 B000 H'0080 C000 H'0080 D000 H'0080 E000 H'0080 F000 H'0081 0000 Internal RAM area (Cannot be used for virtual flash emulation) H'0081 3FFF Figure 6.6.1 Internal RAM Bank Configuration of the M32182F3 6-31 32182 Group User’s Manual (Rev.1.0) 6 6.6.1 Virtual Flash Emulation Area INTERNAL MEMORY 6.6 Virtual Flash Emulation Function The following shows the internal flash memory areas in which the Virtual Flash Emulation Function is applicable. Using the Virtual Flash S Bank Register (FESBANK0–FESBANK7), select one among all S banks of internal flash memory that are divided in 4-Kbyte units (by setting the eight start address bits A12–A19 of the desired S bank in the Virtual Flash S Bank Register SBANKAD bits). Then set the Virtual Flash S Bank Register’s flash emulation enable bit (MODENS) to "1", and the selected S bank area will be replaced with 4-Kbyte blocks of the internal RAM beginning with the address H’0080 8000, up to eight such blocks in all. Notes: • If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0– FESBANK7) and each register’s flash emulation enable bit (MODENS) is set to "1" (enabled), the bank is assigned the corresponding internal RAM area (4-Kbyte) according to the priority of Virtual Flash S Bank Registers given below. FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7 • During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the flash emulation areas set in the internal flash memory. • Before reading any flash emulation area after setting the Flash Control Register 1 (FCNT1) flash emulation mode bit (FEMMOD) to "1", be sure to check that the flash emulation mode bit (FEMMOD) has been set to "1" by reading it once. • Before reading any flash emulation area after setting the Virtual Flash S Bank Register (FESBANK0–FESBANK7) flash emulation enable bit (MODENS) and bank address bits (SBANKAD), be sure to check that those MODENS and SBANKAD bits have been set to the intended values by reading them once. 6-32 32182 Group User’s Manual (Rev.1.0) 6 H'0000 0000 INTERNAL MEMORY 6.6 Virtual Flash Emulation Function S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) H'0080 4000 H'0000 1000 H'0000 2000 H'0005 D000 S bank 93 (4 Kbytes) S bank 94 (4 Kbytes) S bank 95 (4 Kbytes) H'0005 E000 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes H'0080 8000 H'0080 9000 H'0080 A000 H'0080 B000 H'0080 C000 H'0080 D000 H'0080 E000 H'0080 F000 H'0005 F000 H'0081 3FFF Notes: • If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0-FESBANK7) and each register's flash emulation enable bit (MODENS) is set to 1, the bank is assigned the corresponding internal RAM area in order of priority: FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7. • If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Register is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the flash emulation areas set in the internal flash memory. Figure 6.6.2 Virtual Flash Emulation Area of the M32182F3 H'0000 0000 S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) H'0080 4000 H'0000 1000 H'0000 2000 H'000F D000 S bank 253 (4 Kbytes) S bank 254 (4 Kbytes) S bank 255 (4 Kbytes) H'000F E000 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes H'0080 8000 H'0080 9000 H'0080 A000 H'0080 B000 H'0080 C000 H'0080 D000 H'0080 E000 H'0080 F000 H'000F F000 H'0081 3FFF Notes: • If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0-FESBANK7) and each register's flash emulation enable bit (MODENS) is set to 1, the bank is assigned the corresponding internal RAM area in order of priority: FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7. • If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Register is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the flash emulation areas set in the internal flash memory. Figure 6.6.3 Virtual Flash Emulation Area of the M32182F8 6-33 32182 Group User’s Manual (Rev.1.0) 6 S bank S bank 0 S bank 1 S bank 2 Start address of S bank in flash memory H'0000 0000 (Note 1) H'0000 1000 (Note 1) H'0000 2000 (Note 1) Values set in S bank address (SBANKAD) bits H'00 H'01 H'02 INTERNAL MEMORY S bank 94 S bank 95 H'0005 E000 (Note 1) H'0005 F000 (Note 1) H'5E H'5F Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.6.4 Values Set in the M32182F3’s Virtual Flash S Bank Register S bank S bank 0 S bank 1 S bank 2 Start address of S bank in flash memory H'0000 0000 (Note 1) H'0000 1000 (Note 1) H'0000 2000 (Note 1) Values set in S bank address (SBANKAD) bits H'00 H'01 H'02 S bank 254 S bank 255 H'000F E000 (Note 1) H'000F F000 (Note 1) H'FE H'FF Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.6.5 Values Set in the M32182F8’s Virtual Flash S Bank Register 6-34 32182 Group User’s Manual (Rev.1.0) 6 6.6.2 Entering Virtual Flash Emulation Mode INTERNAL MEMORY 6.6 Virtual Flash Emulation Function To enter virtual flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit by writing "1". After entering virtual flash emulation mode, set the Virtual Flash S Bank Register MODENS bit to "1" to enable the Virtual Flash Emulation Function. Even during virtual flash emulation mode, the internal RAM area (H’0080 8000 through H’0080 FFFF) can be accessed the same way as in usual internal RAM. Settings start Write flash data to RAM Enter virtual flash emulation mode FEMMOD ← 1 Set RAM location address in Virtual Flash S Bank Register SBANKADn ← Address A12–A19 Enable virtual flash emulation MODENS ← 1 Settings completed Figure 6.6.6 Virtual Flash Emulation Mode Sequence 6-35 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.6 Virtual Flash Emulation Function 6.6.3 Application Example of Virtual Flash Emulation Mode By using two RAM areas that have been set in the same flash area by the Virtual Flash Emulation Function, the data in the flash memory can be replaced successively. (1) Operation when reset Flash memory Bank xx Initial value Replace area RAM block 0 RAM block 1 Data write to RAM0 (2) Programming operation using RAM block 0 Flash memory Replaced Bank xx Initial value RAM block 0 Bank xx specified RAM block 0 RAM block 1 Data write to RAM1 (3) Programming operation switched from RAM block 0 to RAM block 1 Flash memory Replaced Bank xx Initial value RAM block 0 RAM block 1 Bank xx specified RAM block 0 RAM block 1 Bank xx specified (settings invalid) Figure 6.6.7 Application Example of Virtual Flash Emulation Mode (1/2) 6-36 32182 Group User’s Manual (Rev.1.0) 6 (4) Programming operation using RAM block 1 Flash memory INTERNAL MEMORY 6.6 Virtual Flash Emulation Function Replaced Bank xx Initial value RAM block 1 RAM block 0 RAM block 1 (Bank specification cleared) Data write to RAM0 Bank xx specified (5) Programming operation switched from RAM block 1 to RAM block 0 Flash memory Replaced Bank xx Initial value RAM block 0 RAM block 1 Bank xx specified RAM block 0 RAM block 1 Bank xx specified (settings invalid) (6) Go to (2) Note: Enclosed in are the valid area. Figure 6.6.8 Application Example of Virtual Flash Emulation Mode (2/2) 6-37 32182 Group User’s Manual (Rev.1.0) 6 6.7 Connecting to A Serial Programmer INTERNAL MEMORY 6.7 Connecting to A Serial Programmer For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.7.1 Processing Microcomputer Pins before Using a Serial Programmer Pin Name SCLKI1 RXD1 TXD1 P84 FP MOD0 MOD1 RESET# JTRST XIN XOUT VCNT OSC-VCC OSC-VSS VREF0 AVCC0 AVSS0 VDDE VCCE VCC-BUS EXCVCC EXCVDD VSS Pin No. 103 104 105 106 111 112 113 19 26 16 18 14 15 17 38 37 47 117 13,58,101,119 78,143 59,116 114 56,57,77,102,115,118,144 Function Transfer clock input Serial data input (received data) Serial data output (transmit data) Transmit/receive enable output Flash memory protect Operation mode 0 Operation mode 1 Reset JTAG reset Clock input Clock output Control input for PLL circuit PLL circuit power supply PLL circuit ground Reference voltage input for A-D converter Analog power supply Analog ground RAM backup power supply Main power supply Bus power supply Internal power supply Ground Remark Need to be pulled high Need to be pulled high Need to be pulled high Connect to the main power supply Connect to the main power supply Connect to ground After setting MOD0/MOD1, ground an d back to main power supply Pull low via resistor Connect to the main power supply Connect to ground Connect to the main power supply Connect to the main power supply Connect to ground Connect to the main power supply 5 V + - 10% or 3.3 V + - 10% Depends on the target system Need to be grounded to earth via bypass capacitor 0V 6-38 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.7 Connecting to A Serial Programmer The diagram below shows an example of a user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the internal flash memory in clocksynchronized serial mode. No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H’0000 0084 through H’0000 008F as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area. User system board Connect to the VCCE (5 or 3.3 V) power supply rail VCCE VDDE OSC-VCC AVCC0 VREF0 Connect to Main power supply the user Connect to the system power VCCE (5 or 3.3V) supply rail power supply rail EXCVCC EXCVDD Flash programmer signals Main power supply (for reference) Connector VCC-BUS P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 MOD0 FP RESET# VSS AVSS0 OSC-VSS RxD (input) TxD (output) SCLK0 (output) BUSY (input) MOD0 (output) FP (output) RESET (output) GND (common) To system circuit Set microcomputer operating conditions 2kW MOD1 JTRST XIN XOUT VCNT 32182 Notes: • Turn on the power for the user system before writing to the internal flash memory. • If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration. • SBI# must be fixed high or low to ensure that no interrupts will be generated. • The pullup resistance values of P84, P86 and P87 must be selected to suit the system design condition. • The typical pullup resistance values of P84, P86 and P87 are 4.7 to 10 KW. • The status of any other ports that are not shown here will not affect flash memory programming. • Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory. Figure 6.7.1 Pin Connection Diagram 6-39 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.8 Internal Flash Memory Protect Function 6.8 Internal Flash Memory Protect Function The internal flash memory has the following four types of protect functions to prevent it from being inadvertently rewritten or illegally copied, programmed or erased. (1) Flash memory protect ID When using a tool to program/erase the internal flash memory such as a general-purpose programmer or emulator, the ID entered by a tool and the ID stored in the internal flash memory are collated. Unless the correct ID is entered, no programming/erase operations can be performed. (For some tools, tool execution is enabled after erasing the entire flash memory area, and the internal flash memory becomes accessible for write.) (2) Protection by FP pin The internal flash memory is protected in hardware against programming/erase operation by pulling the FP (Flash Protect) pin low. Furthermore, because the FP pin level can be known by reading the Flash Mode Register (FMOD)’s FPMOD (external FP pin status) bit in the flash write/erase program, the internal flash memory can also be protected in software. For systems that do not require protection by setting external pins, the FP pin may be fixed high to simplify the operation to program/erase the internal flash memory. (3) Protection by FENTRY bit Flash E/W enable mode cannot be entered into unless the Flash Control Register 1 (FCNT1)’s FENTRY (flash mode entry) bit is set to "1". To set the FENTRY bit to "1", write "0" and then "1" in succession while the FP pin is high. (4) Protection by a lock bit Any block of internal flash memory can be protected by setting the lock bit provided for it to "0". That memory block is disabled against programming/erase operation. 6-40 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory The following describes precautions to be taken when programming/erasing the internal flash memory. • When the internal flash memory is programmed or erased, a high voltage is generated internally. Because mode transitions during programming/erase operation may cause the chip to break down, make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes. • If the system uses any pins that are to be used by a general-purpose programming/erase tool, care must be taken to prevent adverse effects on the system when the tool is connected. • If the internal flash memory needs to be protected while using a general-purpose programming/erase tool, set any ID in the flash memory protect ID verification area (H’0000 0084 to H’0000 008F). • If the internal flash memory does not need to be protected while using a general-purpose programming/erase tool, fill the entire flash memory protect ID verification area (H’0000 0084 to H’0000 008F) with H’FF. • If the Flash Status Register 2 (FSTAT2)’s each error status is to be cleared (initialized to H’80) by resetting the Flash Control Register 4 (FCNT4) FRESET bit, check to see that the Flash Status Register 1 (FSTAT1) FSTAT bit = "1" (ready) before clearing the error status. • Before resetting the Flash Control Register 1 (FCNT1) FENTRY bit from "1" to "0", check to see that the Flash Status Register 1 (FSTAT1) FSTAT bit = "1" (ready) or the Flash Status Register 2 (FSTAT2) FBUSY bit = "1" (ready). • Do not clear the FENTRY bit if the Flash Control Register 1 (FCNT1) FENTRY bit = "1" and the Flash Status Register 1 (FSTAT1) FSTAT bit = "0" (busy), or the Flash Status Register 2 (FSTAT2) FBUSY bit = "0" (being programmed or erased). 6-41 32182 Group User’s Manual (Rev.1.0) 6 INTERNAL MEMORY 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory This page is blank for reasons of layout. 6-42 32182 Group User’s Manual (Rev.1.0) CHAPTER 7 RESET 7.1 7.2 7.3 7.4 Outline of Reset Reset Operation Internal State Immediately after Reset Things to Be Considered after Reset 7 7.1 Outline of Reset RESET 7.1 Outline of Reset The microcomputer is reset by applying a low-level signal to the RESET# input pin. The microcomputer is gotten out of a reset state by releasing the RESET# input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the CPU starts executing from the reset vector entry. 7.2 Reset Operation When a low-level signal in width of more than 200 ns (a duration needed for noise cancellation) is applied to the RESET# pin, the microcomputer is reset. At this time, pins on the microcomputer are reset (see the Pin State When Reset in Table 1.4.1, “Pin Assignments”), and an internal bus hold request signal is output internally. Furthermore, the internal circuits (including the CPU) are reset 9–10 BCLK periods later. When the RESET# input is returned high, the microcomputer pins get out of a reset state and the internal bus hold request is deasserted 17–18 BCLK periods later. Then the internal circuits get out of a reset state 15 BCLK periods after that. Flip-flop RESET# Noise Canceller S R Counter Pin reset signal OVF Internal circuit reset signal Figure 7.2.1 Reset Circuit Duration needed for noise cancellation (Note 1) RESET# pin 200ns Reset signal (internal signal) past the noise canceller Pin reset (Note 2) and internal bus hold request (internal signal) Internal circuit reset (internal signal) 9–10BCLK Extended for a duration during which the RESET# input is held low 17–18BCLK 15BCLK Note 1: If the low level duration of the reset signal is less than 200 ns, it is cancelled by the noise canceller. Note 2: The port-related registers also are reset. Figure 7.2.2 Reset Sequence 7-2 32180 Group User’s Manual (Rev.1.0) 7 7.2.1 Reset at Power-on RESET 7.2 Reset Operation When powering on the microcomputer, hold the RESET# signal input pin low until the rated power supply voltage is reached and the microcomputer’s internal x8 clock generator becomes oscillating stably. 7.2.2 Reset during Operation To reset the microcomputer during operation, hold the RESET# signal input pin low for more than 200 ns. 7.2.3 Reset at Entering RAM Backup Mode To prevent the RAM access by the CPU or DMA from becoming interrupted by a reset, first an internal bus hold request is output internally after accepting the reset input. Then the internal circuits are reset after the internal bus is placed in a hold state. Note: • Reset input at entering RAM backup mode cannot be used in the following cases (because the internal bus hold request may not be accepted and the RAM contents may be corrupted): • When the lock bit = 1 (see Section 2.7, “Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution”) • When executing any instruction present in external memory 7.2.4 Reset Vector Relocation during Flash Programming When entering the boot mode, the reset vector entry address is relocated to the start address (H'8000 0000) of the boot program space. For details, see Section 6.5, “Programming the Internal Flash Memory.” 7-3 32180 Group User’s Manual (Rev.1.0) 7 RESET 7.3 Internal State Immediately after Reset 7.3 Internal State Immediately after Reset The table below lists the internal state of the microcomputer immediately after it has gotten out of a reset state. For details about the initial register state of each internal peripheral I/O, see each section in this manual in which the relevant internal peripheral I/O is described. Table 7.3.1 Internal State Immediately after Reset Register PSW CBR SPI SPU BPC FPSR PC R0–R15 ACC (accumulator) RAM (CR0) (CR1) (CR2) (CR3) (CR6) (CR7) State after Reset B'0000 0000 0000 0000 ??00 000? 0000 0000 H'0000 0000 (C bits = 0) Undefined Undefined Undefined H'0000 0100 H'0000 0000 Undefined Undefined Undefined when reset at power-on. (However, if the RAM is gotten out of reset after returning from backup mode, it retains the content it had before being reset.) Note 1: When in boot mode, the CPU executes the boot program. (Only DN bit = 1) (Executed beginning with the address H’0000 0000) (Note 1) (BSM, BIE, BC bits = undefined) 7.4 Things to Be Considered after Reset • Input/output ports After reset, the microcomputer’s input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, set the Port Input Special Function Control Register (PICNT) PIEN0 bit to enable them for input. For details, see Section 8.3, “Input/Output Port Related Registers.” 7-4 32180 Group User’s Manual (Rev.1.0) CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 8.2 8.3 8.4 8.5 8.6 Outline of Input/Output Ports Selecting Pin Functions Input/Output Port Related Registers Port Input Level Switching Function Port Peripheral Circuits Precautions on Input/Output Ports 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports The 32182 has a total of 97 input/output ports from P0-P13, P15, P17 and P22 (except P5, which is reserved for future use). These input/output ports can be used as input or output ports by setting the respective direction registers. Each input/output port is a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or extended external bus signal line. Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. (If any internal peripheral I/O has still another function, it is also necessary to set the register provided for that peripheral I/O.) The microcomputer also has a port input function enable bit that can be used to prevent current from flowing into the input ports. This helps to simplify the software and hardware processing to be performed immediately after reset or during flash programming. Note that before any ports can be used in input mode, this port input function enable bit must be set accordingly. The input/output ports are outlined below. Table 8.1.1 Outline of Input/Output Ports Item Number of ports Specification Total 97 ports P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P15 P17 P22 Port function Pin function Pin function selection : : : : : : : : : : : : : : : : P00–P07 P10–P17 P20–P27 P30–P37 P41–P47 P61–P63 P70–P77 P82–P87 P93–P97 P100–P107 P110–P117 P124–P127 P130–P137 P150, P153 P174, P175 (8 ports) (8 ports) (8 ports) (8 ports) (7 ports) (3 ports) (8 ports) (6 ports) (5 ports) (8 ports) (8 ports) (4 ports) (8 ports) (2 ports) (2 ports) (4 ports) P220, P221, P224, P225 The input/output ports can individually be set for input or output mode using the direction control register provided for each input/output port. (However, P221 is input-only port.) Shared with peripheral I/O or extended external signals to serve dual-functions (or shared with two or more peripheral I/O functions to serve triple-functions) P0–P4, P224, P225: Depends on the CPU operation mode (that is set by MOD0 and MOD1 pins). (Note 1) P6–P22: As set by each input/output port’s operation mode register. (However, peripheral I/O pin functions are selected by peripheral I/O registers.) Note 1: If the CPU operation mode is external extension mode, P0–P3, P44–P47, P224 and P225 initially are input/output port pins, and are switched to extended external signal pin functions by setting the respective port operation mode registers. P41–P43, when in external extension mode, serve as dedicated external bus interface signal pins. Note: • P14, P16, P18-P21 are nonexist. 8-2 32182 Group User’s Manual (Rev.1.0) 8 8.2 Selecting Pin Functions INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions). Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. P0–P4, P224 and P225, when the CPU is set to operate in processor mode, all are switched to serve as signal pins for external access. The CPU operation mode is determined depending on how the MOD0 and MOD1 pins are set (see the table below). Table 8.2.1 CPU Operation Modes and P0–P4, P224 and P225 Pin Functions MOD0 VSS VSS VCCE VCCE MOD1 VSS VCCE VSS VCCE Operation Mode Single-chip mode External extension mode Processor mode (FP pin = VSS) Reserved (use inhibited) P0–P4, P224 and P225 Pin Function Input/output port pin Input/output port pin or extended external signal pin (Note 1) Extended external signal pin – Note 1: P41–P43 serve as dedicated external bus interface signal pins. Note: • VCCE and VSS are connected to 5 or 3.3 V and GND, respectively. Each input/output port has their functions switched between input/output port pins and internal peripheral I/O pins by setting the respective port operation mode registers. If any internal peripheral I/O has two or more pin functions, use the register provided for that peripheral I/O to select the desired pin function. Note that FP and MOD1 pin settings during internal flash memory programming do not affect the pin functions. 8-3 32182 Group User’s Manual (Rev.1.0) 8 0 P0 P1 CPU operation mode settings (Note 1) P2 P3 P4 (Reserved) P5 P6 P7 P8 P9 P10 P11 P12 P13 Input/output port operation mode setting P14 P15 P16 P17 P18 P19 P20 P21 P22 TO29 TIN26 TXD4 TO37 CTX0 TO30 TIN27 RXD4 TO38 CRX0 TIN16 TIN8 TIN0 TO21 TIN17 TIN9 TIN1 TO22 TO8 TO0 BCLK / WR# MOD0 (Note 3) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 1 DB1 DB9 A24 A16 BLW# / BLE# 2 DB2 DB10 A25 A17 BHW# / BHE# 3 DB3 DB11 A26 A18 RD# 4 DB4 DB12 A27 A19 CS0# 5 DB5 DB13 A28 A20 CS1# 6 DB6 DB14 A29 A21 A13 7 DB7 DB15 A30 A22 A14 DB0 DB8 A23 A15 (P61) WAIT# MOD1 (Note 3) (P62) HREQ# TXD0 (P63) HACK# RXD0 TO16 SBI# (Note 3) SCLKI4 / SCLKI5 / SCLKO4 SCLKO5 (P67) RTDTXD RTDRXD RTDACK RTDCLK SCLKI0 / SCLKO0 TO17 TO12 TO4 TCLK0 TXD1 TO18 TO13 TO5 TCLK1 TIN21 / RXD3 TIN13 TIN5 TO26 RXD2 TO34 TIN31 RXD1 TO19 TO14 TO6 TCLK2 TIN22 / CRX1 TIN14 TIN6 TO27 TXD3 TO35 TIN32 SCLKI1 / SCLKO1 TO20 TO15 TO7 TCLK3 TIN23 TIN15 TIN7 TO28 RXD3 TO36 TIN33/ PWMOFF2 TO9 / TO10 / TXD3(Note 2) CTX1(Note 2) TO1 TO2 TO11 TO3 TIN18 TIN10 TIN2 TO23 TIN24 TO31 TIN28 TXD5 TO39 CTX1 TIN19 TIN11 TIN3 TO24 TIN25 TO32 TIN29 RXD5 TO40 CRX1 TIN20 TIN12 TIN4 TO25 TXD2 TO33 TIN30 TO41 TO42 TO43 CS2# TO44 CS3# A11 / A12 / CS2#(Note 2)CS3#(Note 2) (Note 1) Note 1: During processor mode, these ports are switched to function as extended external signal pins. During external extension mode, only P41-P43 are switched to function as external bus interface pins. Other pins become input/output port pins when reset, so that some of these pins, if needed, must be set to function as external bus interface pins. Note 2: These are triple-function pins. Their desired output function must be selected using the peripheral output select register. Note 3: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Note: • No pins are available for those in shaded sections . However, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port). These pins exist in only the 32180 and are nonexistent in the 32182. However, P223 is an input-only pin and internally pulled high, so that there is no need to set it for output. Figure 8.2.1 Input/Output Ports and Pin Function Assignments 8-4 32182 Group User’s Manual (Rev.1.0) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers The input/output port related registers included in the microcomputer consists of the port data register, port direction register and port operation mode register. Note that P5 is reserved for future use. The tables below show an input/output port related register map. Input/Output Port Related Register Map (1/2) Address b0 H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 H'0080 0712 H'0080 0714 H'0080 0716 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P14 Data Register (P14DATA) P16 Data Register (P16DATA) P18 Data Register (P18DATA) P20 Data Register (P20DATA) P22 Data Register (P22DATA) (Use inhibited area) P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) P14 Direction Register (P14DIR) P16 Direction Register (P16DIR) P18 Direction Register (P18DIR) P20 Direction Register (P20DIR) P22 Direction Register (P22DIR) (Use inhibited area) Note: • Although no pins are available for P65–P67, P140–P147, P151, P152, P154–P157, P160–P167, P172, P173, P176, P177, P180–P187, P190–P197, P200–P203, P210–P217, P222, P226 and P227, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port). P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) (Use inhibited area) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P19 Direction Register (P19DIR) P21 Direction Register (P21DIR) (Use inhibited area) 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 +0 address b7 b8 P1 Data Register (P1DATA) P3 Data Register (P3DATA) (Use inhibited area) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) P19 Data Register (P19DATA) P21 Data Register (P21DATA) (Use inhibited area) +1 address b15 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 See pages | H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 H'0080 0732 H'0080 0734 H'0080 0736 | 8-5 32182 Group User’s Manual (Rev.1.0) 8 Input/Output Port Related Register Map (2/2) Address b0 H'0080 0740 H'0080 0742 H'0080 0744 H'0080 0746 H'0080 0748 H'0080 074A H'0080 074C H'0080 074E H'0080 0750 H'0080 0752 H'0080 0754 H'0080 0756 +0 address INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers +1 address b7 b8 b15 P1 Operation Mode Register (P1MOD) P3 Operation Mode Register (P3MOD) Port Input Special Function Control Register (PICNT) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) P19 Operation Mode Register (P19MOD) P21 Operation Mode Register (P21MOD) (Use inhibited area) (Use inhibited area) See pages 8-9 8-10 8-11 8-21 8-11 8-12 8-12 8-13 8-13 8-14 8-14 8-15 8-15 8-16 8-16 8-17 8-17 8-18 8-18 8-19 P0 Operation Mode Register (P0MOD) P2 Operation Mode Register (P2MOD) P4 Operation Mode Register (P4MOD) P6 Operation Mode Register (P6MOD) P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P12 Operation Mode Register (P12MOD) P14 Operation Mode Register (P14MOD) P16 Operation Mode Register (P16MOD) P18 Operation Mode Register (P18MOD) P20 Operation Mode Register (P20MOD) P22 Operation Mode Register (P22MOD) | H'0080 0760 H'0080 0762 H'0080 0764 | H'0080 076A Port Group 0,1 Input Level Setting Register Port Group 2,3 Input Level Setting Register (PG01LEV) (PG23LEV) Port Group 4,5 Input Level Setting Register Port Group 6,7 Input Level Setting Register (PG45LEV) (PG67LEV) Port Group 8 Input Level Setting Register (Use inhibited area) (PG8LEV) (Use inhibited area) P10 Peripheral Output Select Register (P10SMOD) (Use inhibited area) P22 Peripheral Output Select Register (P22SMOD) (Use inhibited area) 8-25 8-25 8-25 8-20 | H'0080 0776 (Use inhibited area) 8-20 Note: • Although no pins are available for P65–P67, P140–P147, P151, P152, P154–P157, P160–P167, P172, P173, P176, P177, P180–P187, P190–P197, P200–P203, P210–P217, P222, P226 and P227, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port). 8-6 32182 Group User’s Manual (Rev.1.0) 8 8.3.1 Port Data Registers P0 Data Register (P0DATA) P1 Data Register (P1DATA) P2 Data Register (P2DATA) P3 Data Register (P3DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P7 Data Register (P7DATA) P8 Data Register (P8DATA) P9 Data Register (P9DATA) P10 Data Register (P10DATA) P11 Data Register (P11DATA) P12 Data Register (P12DATA) P13 Data Register (P13DATA) P14 Data Register (P14DATA) P15 Data Register (P15DATA) P16 Data Register (P16DATA) P17 Data Register (P17DATA) P18 Data Register (P18DATA) P19 Data Register (P19DATA) P20 Data Register (P20DATA) P21 Data Register (P21DATA) P22 Data Register (P22DATA) b0 (b8 ? 1 9 ? 2 10 ? 3 11 ? 4 12 ? 5 13 ? 6 14 ? INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers b7 b15) Pn7DT ? Pn0DT Pn1DT Pn2DT Pn3DT Pn4DT Pn5DT Pn6DT n = 0–22 (not including P5) b 0(b8) 1(b9) 2(b10) 3(b11) 4(b12) 5(b13) 6(b14) 7(b15) Bit Name Pn0DT (Port Pn0 data bit) Pn1DT (Port Pn1 data bit) Pn2DT (Port Pn2 data bit) Pn3DT (Port Pn3 data bit) Pn4DT (Port Pn4 data bit) Pn5DT (Port Pn5 data bit) Pn6DT (Port Pn6 data bit) Pn7DT (Port Pn7 data bit) Function Depends on how the Port Direction Register is set If direction bit = "0" (input mode) 0: Port input pin = "low" 1: Port input pin = "high" If direction bit = "1" (output mode) (Note 1) 0: Port output latch = "0" / Port pin level = "low" 1: Port output latch = "1" / Port pin level = "high" Write to the port output latch R R W W Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL). Notes: • No data bits are provided for the following ports (read as "0", writing has no effect): P40, P60, P90–P92, P120–P123, P170, P171, P204–P207 • The SBI# pin level can be read out by reading the P64DT bit. Writing to the P64DT bit has no effect. • The MOD0 and MOD1 pin levels can be read out by reading the P80DT and P81DT bits, respectively. Writing to the P80DT and P81DT bits has no effect. • P221 is input-only port. Writing to the P221DT bit has no effect. • Although no pins are available for P65–P67, P140–P147, P151, P152, P154–P157, P160–P167, P172, P173, P176, P177, P180–P187, P190–P197, P200–P203, P210–P217, P222, P226 and P227, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port). • Alhough no pins are available for P223, it is internally pulled high (read as "0", writing has no effect). 8-7 32182 Group User’s Manual (Rev.1.0) 8 8.3.2 Port Direction Registers P0 Direction Register (P0DIR) P1 Direction Register (P1DIR) P2 Direction Register (P2DIR) P3 Direction Register (P3DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P7 Direction Register (P7DIR) P8 Direction Register (P8DIR) P9 Direction Register (P9DIR) P10 Direction Register (P10DIR) P11 Direction Register (P11DIR) P12 Direction Register (P12DIR) P13 Direction Register (P13DIR) P14 Direction Register (P14DIR) P15 Direction Register (P15DIR) P16 Direction Register (P16DIR) P17 Direction Register (P17DIR) P18 Direction Register (P18DIR) P19 Direction Register (P19DIR) P20 Direction Register (P20DIR) P21 Direction Register (P21DIR) P22 Direction Register (P22DIR) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers b0 (b8 0 1 9 0 2 10 0 3 11 0 4 12 0 5 13 0 6 14 0 b7 b15) 0 Pn0DR Pn1DR Pn2DR Pn3DR Pn4DR Pn5DR Pn6DR Pn7DR n = 0–22 (not including P5) b 0(b8) 1(b9) 2(b10) 3(b11) 4(b12) 5(b13) 6(b14) 7(b15) Bit Name Pn0DR (Port Pn0 direction bit) Pn1DR (Port Pn1 direction bit) Pn2DR (Port Pn2 direction bit) Pn3DR (Port Pn3 direction bit) Pn4DR (Port Pn4 direction bit) Pn5DR (Port Pn5 direction bit) Pn6DR (Port Pn6 direction bit) Pn7DR (Port Pn7 direction bit) Function 0: Input mode 1: Output mode R R W W Notes: • No direction bits are provided for the following ports (read as 0, writing has no effect): P40, P60, P64, P80, P81, P90–P92, P120–P123, P170, P171, P204–P207, P221, P223 • After reset, all ports are set for input mode. • Although no pins are available for P65–P67, P140–P147, P151, P152, P154–P157, P160–P167, P172, P173, P176, P177, P180–P187, P190–P197, P200–P203, P210–P217, P222, P226 and P227, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port). 8-8 32182 Group User’s Manual (Rev.1.0) 8 P0 Operation Mode Register (P0MOD) b0 P00MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.3 Port Operation Mode Registers 6 P06MD 0 1 P01MD 0 2 P02MD 0 3 P03MD 0 4 P04MD 0 5 P05MD 0 b7 P07MD 0 b 0 1 2 3 4 5 6 7 Bit Name P00MD Port P00 operation mode bit P01MD Port P01 operation mode bit P02MD Port P02 operation mode bit P03MD Port P03 operation mode bit P04MD Port P04 operation mode bit P05MD Port P05 operation mode bit P06MD Port P06 operation mode bit P07MD Port P07 operation mode bit Function 0: P00 1: DB0 0: P01 1: DB1 0: P02 1: DB2 0: P03 1: DB3 0: P04 1: DB4 0: P05 1: DB5 0: P06 1: DB6 0: P07 1: DB7 R W R R R W W W R R R R R W W W W W Note: • P0 Operation Mode Register is useful only when the CPU operates in external extension mode. P1 Operation Mode Register (P1MOD) b8 P10MD 0 14 P16MD 0 9 P11MD 0 10 P12MD 0 11 P13MD 0 12 P14MD 0 13 P15MD 0 b15 P17MD 0 b 8 9 10 11 12 13 14 15 Bit Name P10MD Port P10 operation mode bit P11MD Port P11 operation mode bit P12MD Port P12 operation mode bit P13MD Port P13 operation mode bit P14MD Port P14 operation mode bit P15MD Port P15 operation mode bit P16MD Port P16 operation mode bit P17MD Port P17 operation mode bit Function 0: P10 1: DB8 0: P11 1: DB9 0: P12 1: DB10 0: P13 1: DB11 0: P14 1: DB12 0: P15 1: DB13 0: P16 1: DB14 0: P17 1: DB15 R R R R R R R R R W W W W W W W W W Note: • P1 Operation Mode Register is useful only when the CPU operates in external extension mode. 8-9 32182 Group User’s Manual (Rev.1.0) 8 P2 Operation Mode Register (P2MOD) b0 P20MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 6 P26MD 0 1 P21MD 0 2 P22MD 0 3 P23MD 0 4 P24MD 0 5 P25MD 0 b7 P27MD 0 b 0 1 2 3 4 5 6 7 Bit Name P20MD Port P20 operation mode bit P21MD Port P21 operation mode bit P22MD Port P22 operation mode bit P23MD Port P23 operation mode bit P24MD Port P24 operation mode bit P25MD Port P25 operation mode bit P26MD Port P26 operation mode bit P27MD Port P27 operation mode bit Function 0: P20 1: A23 0: P21 1: A24 0: P22 1: A25 0: P23 1: A26 0: P24 1: A27 0: P25 1: A28 0: P26 1: A29 0: P27 1: A30 R R R R W W W W R R R R R W W W W W Note: • P2 Operation Mode Register is useful only when the CPU operates in external extension mode. P3 Operation Mode Register (P3MOD) b8 P30MD 0 14 P36MD 0 9 P31MD 0 10 P32MD 0 11 P33MD 0 12 P34MD 0 13 P35MD 0 b15 P37MD 0 b 8 9 10 11 12 13 14 15 Bit Name P30MD Port P30 operation mode bit P31MD Port P31 operation mode bit P32MD Port P32 operation mode bit P33MD Port P33 operation mode bit P34MD Port P34 operation mode bit P35MD Port P35 operation mode bit P36MD Port P36 operation mode bit P37MD Port P37 operation mode bit Function 0: P30 1: A15 0: P31 1: A16 0: P32 1: A17 0: P33 1: A18 0: P34 1: A19 0: P35 1: A20 0: P36 1: A21 0: P37 1: A22 R R R R R W W W W W R R R R W W W W Note: • P3 Operation Mode Register is useful only when the CPU operates in external extension mode. 8-10 32182 Group User’s Manual (Rev.1.0) 8 P4 Operation Mode Register (P4MOD) b0 1 2 3 4 P44MD 0 0 0 0 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 6 P46MD 0 5 P45MD 0 b7 P47MD 0 b 0–3 4 5 6 7 Bit Name No function assigned. Fix to "0". P44MD Port P44 operation mode bit P45MD Port P45 operation mode bit P46MD Port P46 operation mode bit P47MD Port P47 operation mode bit 0: P44 1: CS0# 0: P45 1: CS1# 0: P46 1: A13 0: P47 1: A14 R W Function R 0 R R R W 0 W W W Note: • P4 Operation Mode Register is useful only when the CPU operates in external extension mode. P6 Operation Mode Register (P6MOD) b0 1 2 3 4 5 P65MD 0 0 0 0 0 0 6 P66MD 0 0 b7 b 0–4 5, 6 7 Bit Name No function assigned. Fix to "0". Fix to "0". No function assigned. Fix to "0". Function R 0 0 0 W 0 0 0 Notes: • Port P60 is nonexistent. • P61–P63 are always input/output ports (single-function pins). • Port P64 is the SBI# input-only pin. The pin level can be known by reading the data register for P64. • Although no pins are available for P65 and P66, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port). 8-11 32182 Group User’s Manual (Rev.1.0) 8 P7 Operation Mode Register (P7MOD) b8 P70MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 14 P76MD 0 9 P71MD 0 10 P72MD 0 11 P73MD 0 12 P74MD 0 13 P75MD 0 b15 P77MD 0 b 8 9 10 11 12 13 14 15 Bit Name P70MD Port P70 operation mode bit P71MD Port P71 operation mode bit P72MD Port P72 operation mode bit P73MD Port P73 operation mode bit P74MD Port P74 operation mode bit P75MD Port P75 operation mode bit P76MD Port P76 operation mode bit P77MD Port P77 operation mode bit Function 0: P70 1: BCLK/WR# 0: P71 1: WAIT# 0: P72 1: HREQ# 0: P73 1: HACK# 0: P74 1: RTDTXD 0: P75 1: RTDRXD 0: P76 1: RTDACK 0: P77 1: RTDCLK R R R R W W W W R R R R R W W W W W P8 Operation Mode Register (P8MOD) b0 1 2 P82MD 0 0 0 6 P86MD 0 3 P83MD 0 4 P84MD 0 5 P85MD 0 b7 P87MD 0 b 0,1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". P82MD Port P82 operation mode bit P83MD Port P83 operation mode bit P84MD Port P84 operation mode bit P85MD Port P85 operation mode bit P86MD Port P86 operation mode bit P87MD Port P87 operation mode bit 0: P82 1: TXD0 0: P83 1: RXD0 0: P84 1: SCLKI0/SCLKO0 0: P85 1: TXD1 0: P86 1: RXD1 0: P87 1: SCLKI1/SCLKO1 Function R 0 R R R R R R W 0 W W W W W W Note: • Ports P80 and P81 are nonexistent. 8-12 32182 Group User’s Manual (Rev.1.0) 8 P9 Operation Mode Register (P9MOD) b8 9 10 11 P93MD 0 0 0 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 14 P96MD 0 12 P94MD 0 13 P95MD 0 b15 P97MD 0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". P93MD Port P93 operation mode bit P94MD Port P94 operation mode bit P95MD Port P95 operation mode bit P96MD Port P96 operation mode bit P97MD Port P97 operation mode bit 0: P93 1: TO16 0: P94 1: TO17 0: P95 1: TO18 0: P96 1: TO19 0: P97 1: TO20 R R W W Function R 0 R R R W 0 W W W Note: • Ports P90–P92 are nonexistent. P10 Operation Mode Register (P10MOD) b0 P100MD 0 6 P106MD 0 1 P101MD 0 2 P102MD 0 3 P103MD 0 4 P104MD 0 5 P105MD 0 b7 P107MD 0 b 0 1 2 3 4 5 6 7 Bit Name P100MD Port P100 operation mode bit P101MD Port P101 operation mode bit P102MD Port P102 operation mode bit P103MD Port P103 operation mode bit P104MD Port P104 operation mode bit P105MD Port P105 operation mode bit P106MD Port P106 operation mode bit P107MD Port P107 operation mode bit Function 0: P100 1: TO8 0: P101 1: TO9/TXD3 (Note 1) 0: P102 1: TO10/CTX1 (Note 1) 0: P103 1: TO11 0: P104 1: TO12 0: P105 1: TO13 0: P106 1: TO14 0: P107 1: TO15 R R R W W W R R W W R R W W R R W W Note 1: These functions are selected using the P10 Peripheral Output Select Register. 8-13 32182 Group User’s Manual (Rev.1.0) 8 P11 Operation Mode Register (P11MOD) b8 P110MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 14 P116MD 0 9 P111MD 0 10 P112MD 0 11 P113MD 0 12 P114MD 0 13 P115MD 0 b15 P117MD 0 b 8 9 10 11 12 13 14 15 Bit Name P110MD Port P110 operation mode bit P111MD Port P111 operation mode bit P112MD Port P112 operation mode bit P113MD Port P113 operation mode bit P114MD Port P114 operation mode bit P115MD Port P115 operation mode bit P116MD Port P116 operation mode bit P117MD Port P117 operation mode bit Function 0: P110 1: TO0 0: P111 1: TO1 0: P112 1: TO2 0: P113 1: TO3 0: P114 1: TO4 0: P115 1: TO5 0: P116 1: TO6 0: P117 1: TO7 R R R R W W W W R R R R R W W W W W P12 Operation Mode Register (P12MOD) b0 0 6 P126MD 0 1 0 2 0 3 0 4 P124MD 0 5 P125MD 0 b7 P127MD 0 b 0–3 4 5 6 7 Bit Name No function assigned. Fix to "0". P124MD Port P124 operation mode bit P125MD Port P125 operation mode bit P126MD Port P126 operation mode bit P127MD Port P127 operation mode bit 0: P124 1: TCLK0 0: P125 1: TCLK1 0: P126 1: TCLK2 0: P127 1: TCLK3 Function R 0 R R R R W 0 W W W W Note: • Ports P120–P123 are nonexistent. 8-14 32182 Group User’s Manual (Rev.1.0) 8 P13 Operation Mode Register (P13MOD) b8 P130MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 14 P136MD 0 9 P131MD 0 10 P132MD 0 11 P133MD 0 12 P134MD 0 13 P135MD 0 b15 P137MD 0 b 8 9 10 11 12 13 14 15 Bit Name P130MD Port P130 operation mode bit P131MD Port P131 operation mode bit P132MD Port P132 operation mode bit P133MD Port P133 operation mode bit P134MD Port P134 operation mode bit P135MD Port P135 operation mode bit P136MD Port P136 operation mode bit P137MD Port P137 operation mode bit Function 0: P130 1: TIN16 0: P131 1: TIN17 0: P132 1: TIN18 0: P133 1: TIN19 0: P134 1: TIN20 0: P135 1: TIN21/RXD3 (Note 1) 0: P136 1: TIN22/CRX1 (Note 1) 0: P137 1: TIN23 R R R R W W W W R R R R R W W W W W Note 1: Both inputs are enabled. P14 Operation Mode Register (P14MOD) b0 P140MD 0 6 P146MD 0 1 P141MD 0 2 P142MD 0 3 P143MD 0 4 P144MD 0 5 P145MD 0 b7 P147MD 0 b 0-7 Bit Name Fix to "0". Function R 0 W 0 Note : • Although no pins are available for P140 to P147, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port). 8-15 32182 Group User’s Manual (Rev.1.0) 8 P15 Operation Mode Register (P15MOD) b8 P150MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 14 P156MD 0 9 P151MD 0 10 P152MD 0 11 P153MD 0 12 P154MD 0 13 P155MD 0 b15 P157MD 0 b 8 9, 10 11 12-15 Bit Name P150MD Port P150 operation mode bit Fix to "0". P153MD Port P153 operation mode bit Fix to "0". 0: P153 1: TIN3 Function 0: P150 1: TIN0 R R 0 R 0 W W 0 W 0 Note : • Although no pins are available for P151, P152 and P154-P157, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port). P16 Operation Mode Register (P16MOD) b0 P160MD 0 6 P166MD 0 1 P161MD 0 2 P162MD 0 3 P163MD 0 4 P164MD 0 5 P165MD 0 b7 P167MD 0 b 0-7 Bit Name Fix to "0". Function R 0 W 0 Note : • Although no pins are available for P160 to P167, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port). 8-16 32182 Group User’s Manual (Rev.1.0) 8 P17 Operation Mode Register (P17MOD) b8 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 14 P176MD 0 9 0 10 P172MD 0 11 P173MD 0 12 P174MD 0 13 P175MD 0 b15 P177MD 0 b 8, 9 10, 11 12 13 14, 15 Bit Name No function assigned. Fix to "0". Fix to "0". P174MD Port P174 operation mode bit P175MD Port P175 operation mode bit Fix to "0". 0: P174 1: TXD2 0: P175 1: RXD2 0 0 Function R 0 0 R R W 0 0 W W Notes: • Ports P170 and P171 are nonexistent. • Although no pins are available for P172, P173, P176 and P177, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port). P18 Operation Mode Register (P18MOD) b0 P180MD 0 6 P186MD 0 1 P181MD 0 2 P182MD 0 3 P183MD 0 4 P184MD 0 5 P185MD 0 b7 P187MD 0 b 0-7 Bit Name Fix to "0". Function R 0 W 0 Note : • Although no pins are available for P180 to P187, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port). 8-17 32182 Group User’s Manual (Rev.1.0) 8 P19 Operation Mode Register (P19MOD) b8 P190MD 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 14 P196MD 0 9 P191MD 0 10 P192MD 0 11 P193MD 0 12 P194MD 0 13 P195MD 0 b15 P197MD 0 b 8–15 Bit Name Fix to "0" Function R 0 W 0 Note : • Although no pins are available for P190 to P197, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port). P20 Operation Mode Register (P20MOD) b0 P200MD 0 6 0 1 P201MD 0 2 P202MD 0 3 P203MD 0 4 0 5 0 b7 0 b 0–3 4–7 Bit Name Fix to "0". No function assigned. Fix to "0". Function R 0 0 W 0 0 Notes : • Although no pins are available for P200 to P203, because internal circuits are included, make sure the ports are set for low level output when initialized (to prevent current from flowing in through the port). • Ports P204–P207 are nonexistent. P21 Operation Mode Register (P21MOD) b8 P210MD 0 14 P216MD 0 9 P211MD 0 10 P212MD 0 11 P213MD 0 12 P214MD 0 13 P215MD 0 b15 P217MD 0 b 8–15 Bit Name Fix to "0". Function R 0 W 0 Note : • Although no pins are available for P210 to P217, because internal circuits are included, make sure the ports are set for lowlevel output when initialized (to prevent current from flowing in through the port). 8-18 32182 Group User’s Manual (Rev.1.0) 8 P22 Operation Mode Register (P22MOD) b0 P220MD 0 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 6 P226MD 0 1 2 P222MD 0 3 P223MD 0 4 P224MD 0 5 P225MD 0 b7 P227MD 0 b 0 1 2, 3 4 5 6, 7 Bit Name P220MD Port P220 operation mode bit No function assigned. Fix to "0". Fix to "0". P224MD Port P224 operation mode bit (Note 1) P225MD Port P225 operation mode bit (Note 1) Fix to "0". 0: P224 1: A11/CS2# (Note 2) 0: P225 1: A12/CS3# (Note 2) R 0 W 0 Function 0: P220 1: CTX0 R R 0 0 R W W 0 0 W Note 1: Port P224, P225 operation mode bits are useful only when the CPU operates in external extension mode. Note 2: These functions are selected using the P22 Peripheral Output Select Register. Notes: • P221 is the CAN input-only pin. • Although no pins are available for P222, P223, P226 and P227, because internal circuits are included, make sure the ports are set for low-level output when initialized (to prevent current from flowing in through the port). Port 223 is an input-only pin so that there is no need to set it for output. 8-19 32182 Group User’s Manual (Rev.1.0) 8 b0 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.4 Port Peripheral Output Select Registers P10 Peripheral Output Select Register (P10SMOD) 1 P101 SMD 0 2 P102 SM D 0 3 0 4 0 5 0 6 0 b7 0 b 0 1 2 3–7 Bit Name No function assigned. Fix to "0". P101SMD Port P101 peripheral output select mode bit P102SMD Port P102 peripheral output select mode bit No function assigned. Fix to "0". 0: TO9 1: TXD3 0: TO10 1: CTX1 Function R 0 R R 0 W 0 W W 0 P22 Peripheral Output Select Register (P22SMOD) b0 0 1 0 2 0 3 0 4 P224 SM D 0 5 P225 SM D 0 6 0 b7 0 b 0–3 4 5 6–7 Bit Name No function assigned. Fix to "0". P224SMD Port P224 peripheral output select mode bit P225SMD Port P225 peripheral output select mode bit No function assigned. Fix to "0". 0: A11 1: CS2# 0: A12 1: CS3# Function R 0 R R 0 W 0 W W 0 8-20 32182 Group User’s Manual (Rev.1.0) 8 b8 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.5 Port Input Special Function Control Register Port Input Special Function Control Register (PICNT) 9 0 10 0 11 XSTAT 0 12 0 13 0 14 PISEL 0 b15 PIEN0 0 b 8–10 11 12–13 14 15 Bit Name No function assigned. Fix to "0". XSTAT XIN oscillation status bit No function assigned. Fix to "0". PISEL Port input data select bit PIEN0 Port input enable bit 0: Content of port output latch 1: Port pin level 0: Disable input 1: Enable input R W 0: XIN oscillating 1: XIN inactive Function R 0 W 0 R(Note 1) 0 R 0 W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. (1) XSTAT (XIN oscillation status) bit (Bit 11) 1) Conditions under which XSTAT is set to "1" XSTAT is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for a predetermined time (3 BCLK periods up to 4 BCLK periods), XIN oscillation is assumed to have stopped. When operating normally, XIN changes state (high or low) once every BCLK period. 2) Conditions under which XSTAT is cleared to "0" XSTAT is cleared to "0" by a system reset or by writing "0". If XSTAT is cleared at the same time it is set in (1) above, the former has priority. Writing "1" to XSTAT is ignored. 3) Method for using XSTAT to detect XIN oscillation stoppage Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscillation has stopped. By reading XSTAT without clearing it never once after reset, it is possible to know whether XIN has ever stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it by writing "0", it is possible to know the current oscillating status of XIN. (However, there must be an interval of at least 5 BCLK periods (20 CPU clock periods) between read and write.) 8-21 32182 Group User’s Manual (Rev.1.0) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers (1) To know whether XIN oscillation has ever stopped after being reset Read XSTAT (2) To know the current status of XIN oscillation Write XSTAT = 0 Wait before inspecting XSTAT Wait for 20 CPU clock periods or more Read XSTAT Figure 8.3.1 Procedure for Setting XSTAT (2) PISEL (Port input data select) bit (Bit 14) When the Port Direction Register is set for output, this bit selects the target data to be read from the Port Data Register. This bit is unaffected by the Port Operation Mode Register. Table 8.3.1 PISEL Bit Settings and the Target Data To Be Read from the Port Data Register Direction Register 0 (input) 1 (output) PISEL Settings 0/1 0 1 Target Data to Be Read Port pin level Port output latch Port pin level 8-22 32182 Group User’s Manual (Rev.1.0) 8 (3) PIEN0 (Port input enable) bit (Bit 15) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers This bit is used to prevent current from flowing into the port input pins. Because the input/output ports are disabled against input after reset, if any ports need to be used in input mode they must be enabled for input by setting this bit to "1". When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. Consequently, if a peripheral input function is selected for any port (uncontrolled pin) while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the low-level input on it. The following shows the procedure for selecting a peripheral input function. (1) Enable the port for input when its pin level is valid (high or low) (2) Select a function using the port operation mode bit During boot mode, the pins shared with serial I/O functions are enabled for input and can therefore be protected against current flowing in from the pins other than serial I/O functions during flash programming by clearing PIEN0. The table below lists the pins that can be controlled by the PIEN0 bit in each operation mode. Table 8.3.2 Pins Controllable by PIEN0 Bit Mode Name Controllable Pins P00–P07, P10–P17, P20–P27 P30–P37, P41–P47, P61–P63 P65–P67, P70–P77, P82–P87 P93–P97, P100–P107, P110–P117 P124–P127, P130–P137, P140–P147 P150–P157, P160–P167, P172–P177 P180–P187, P190–P197, P200–P203 P210–P217, P220, P222, P224–P227 P61–P63, P65–P67, P70–P77 P82–P87, P93–P97, P100–P107 P110–P117, P124–P127, P130–P137 P140–P147, P150–P157, P160–P167 P172–P177, P180–P187, P190–P197 P200–P203, P210–P217, P220, P222 P00–P07, P10–P17, P20–P27 P30–P37, P41–P47, P61–P63 P67, P70–P77, P93–P97 P100, P102–P107, P110–P117, P124–P127 P130–P134, P137, P140–P147, P150–P157 P160–P167, P172–P173, P180–P187 P190–P197, P210–P217, P220 P222, P224–P227 Uncontrolled Pins P221, P223, FP, MOD0, MOD1, SBI#, RESET# Single-chip External extension Microprocessor P00–P07, P10–P17 P20–P27, P30–P37 P41–P47, P221, P223–P227 FP, MOD0, MOD1, SBI#, RESET# Boot (single-chip) P65, P66, P82–P87, P101 P135–P136, P174–P177, P200–P203 P221, P223, FP, MOD0, MOD1, SBI#, RESET# Note : • No pins are available for P65-P67, P140-P147, P151, P152, P154-P157, P160-P167, P172, P173, P176, P177, P180-P187, P190-P197, P200-P203, P210-P217, P222, P223, P226 and P227. 8-23 32182 Group User’s Manual (Rev.1.0) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Input Level Switching Function 8.4 Port Input Level Switching Function The port input level switching function allows the port threshold to be switched to one of three voltage levels (with or without Schmitt as selected) in units of the following port group. Group 0: P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224-P227 Group 1: P65–P67, P82–P87, P172–P177 Group 2: P160–P167, P210–P217 Group 3: P93–P97, P110–P117 Group 4: P124–P127, P140–P147, P190–P197 Group 5: P61–P63, SBI# Group 6: P74–P77, P180–P187, P100–P107 Group 7: P136, P220–P223 Group 8: P130–P135, P137, P150–P157, P200–P203 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 VSS VCCE P44/CS0# P45/CS1# P224/A11/CS2# P225/A12/CS3# P46/A13 P47/A14 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 P20/A23 P21/A24 P22/A25 P23/A26 P24/A27 P25/A28 P26/A29 P27/A30 VCC-BUS VSS P93/TO16 P94/TO17 P95/TO18 P96/TO19 P174/TXD2 P175/RXD2 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P12/DB10 P11/DB9 P10/DB8 P07/DB7 P06/DB6 P05/DB5 P04/DB4 P03/DB3 P02/DB2 P01/DB1 P00/DB0 P73/HACK# P72/HREQ# P71/WAIT# P70/BCLK/WR# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# VCC-BUS VSS 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Port group 3 Port group 4 32182 Group Port group 5 Port group 0 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 P97/TO20 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 EXCVCC VCCE VSS VSS SBI# P63 P62 P61 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 VREF0 AVCC0 Port group 1 Port group 7 Port group 8 Port group 0 Port group 7 Port group 6 Figure 8.4.1 Port Input Level Switching Groups P150/TIN0 P153/TIN3 P130/TIN16 P131/TIN17 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23 P220/CTX0 P221/CRX0 VCCE VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI JTDO JTRST JTCK JTMS P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Port group 8 8-24 32182 Group User’s Manual (Rev.1.0) Port group 6 8 b0 0 1 0 2 0 3 1 4 0 5 0 6 0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Input Level Switching Function Port Group 0,1 Input Level Setting Register (PG01LEV) b7 1 WF0SEL PT0SEL VT0SEL0 VT0SEL1 WF1SEL PT1SEL VT1SEL0 VT1SEL1 Port Group 2,3 Input Level Setting Register (PG23LEV) b8 0 9 0 10 0 11 1 12 0 13 0 14 0 b15 1 WF2SEL PT2SEL VT2SEL0 VT2SEL1 WF3SEL PT3SEL VT3SEL0 VT3SEL1 Port Group 4,5 Input Level Setting Register (PG45LEV) b0 0 1 0 2 0 3 1 4 0 5 0 6 0 b7 1 WF4SEL PT4SEL VT4SEL0 VT4SEL1 WF5SEL PT5SEL VT5SEL0 VT5SEL1 Port Group 6,7 Input Level Setting Register (PG67LEV) b8 0 9 0 10 0 11 1 12 0 13 0 14 0 b15 1 WF6SEL PT6SEL VT6SEL0 VT6SEL1 WF7SEL PT7SEL VT7SEL0 VT7SEL1 Port Group 8 Input Level Setting Register (PG8LEV) b0 0 1 0 2 0 3 1 4 0 5 0 6 0 b7 0 WF8SEL PT8SEL VT8SEL0 VT8SEL1 Note: • The PG8LEV register bits 4–7 have no functions assigned. b 0(4) 8(12) 1(5) 9(13) 2–3 (6–7) 10–11 (14–15) Bit Name WFnSEL Group n dual-function input select bit PTnSEL Group n port input select bit VTnSEL Group n input threshold select bit Function 0: Select standard input for each pin 1: Select threshold switching function 0: Select CMOS input 1: Select Schmitt input 00: Select 0.35 VCCE 01: Select 0.5 VCCE 10: Select 0.7 VCCE 11: Settings inhibited 00: VT+ = 0.5 VCCE VT– = 0.35 VCCE 01: Settings inhibited 10: VT+ = 0.7 VCCE VT– = 0.35 VCCE 11: VT+ = 0.7 VCCE VT– = 0.5VCCE R R R R W W W W Notes: • The following ports operate with the VCC-BUS power supply, and not with the VCCE power supply. Therefore, the reference voltages for these ports are the VCC-BUS input voltage. P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224–P227 • No pins are available for P65-P67, P140-P147, P151, P152, P154-P157, P160-P167, P172, P173, P176, P177, P180P187, P190-P197, P200-P203, P210-P217, P222, P223, P226 and P227. 8-25 32182 Group User’s Manual (Rev.1.0) 8 0.7VCCE 0.5VCCE Pin Input function enable INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Input Level Switching Function S S VT+ Schmitt VTS Port input 0.35VCCE Threshold S VTnSELL CMOS PTnSEL Standard input level for each peripheral function pin S WFnSEL Peripheral function input Figure 8.4.2 Port Level Switching Function 8-26 32182 Group User’s Manual (Rev.1.0) 8 8.5 Port Peripheral Circuits INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Peripheral Circuits Figures 8.5.1 through 8.5.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. P00–P07(DB0–DB7) P10–P17(DB8–DB15) P20–P27(A23–A30) P30–P37(A15–A22) P46, P47(A13, A14) P71(WAIT#) P73(HACK#) P74(RTDTXD) P76(RTDACK) P224(A11/CS2#) P225(A12/CS3#) Direction register Data bus Port output latch Input data select bit Operation mode register (Note 1) Port level switching function (Standard: peripheral TTL) Input function enable Peripheral function input P44(CS0#) P45(CS1#) P70(BCLK/WR#) P82(TXD0) P85(TXD1) P93–P97(TO16–TO20) P100(TO8) P103–P107(TO11–TO15) P110–P117(TO0–TO7) P174(TXD2) P220(CTX0) Direction register Data bus Port output latch Input data select bit Operation mode register (Note 1) Port level switching function (No peripheral input) Input function enable Peripheral function output Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes: • During processor mode, P00-P07, P10-P17, P20-P27, P30-P37, P45-P47, P224, and P225 are external bus interface control signal pins, but their functional description in this block diagram is omitted. • Although P224 and P225 serve triple functions, their functional description in this block diagram is omitted. • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. • The input capacitance of each pin is approximately 10 pF. Figure 8.5.1 Port Peripheral Circuit Diagram (1) 8-27 32182 Group User’s Manual (Rev.1.0) 8 P101(TO9/TXD3) P102(TO10/CTX1) Data bus INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Peripheral Circuits Direction register Port output latch Input data select bit Operation mode register (Note 1) Peripheral output select register Input function enable Port level switching function (No peripheral input) Peripheral function output 1 Peripheral function output 2 P72(HREQ#) P75(RTDRXD) P77(RTDCLK) P83(RXD0) P86(RXD1) P124–P127(TCLK0–TCLK3) P130–P134(TIN16–TIN20) P137(TIN23) P150, P153(TIN0, TIN3) P175(RXD2) Direction register Data bus Port output latch Input data select bit Operation mode register Peripheral function input Input function enable (Note 1) Port level switching function (Standard: peripheral Schmitt) P135(TIN21/RXD3) P136(TIN22/CRX1) Data bus Direction register Port output latch Input data select bit Operation mode register Peripheral function input 1 Peripheral function input 2 Input function enable (Note 1) Port level switching function (Standard: peripheral Schmitt) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes: • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. • The input capacitance of each pin is approximately 10 pF. Figure 8.5.2 Port Peripheral Circuit Diagram (2) 8-28 32182 Group User’s Manual (Rev.1.0) 8 P41(BLW#/BLE#) P42(BHW#/BHE#) P43(RD#) P61-P63 Data bus INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Peripheral Circuits Direction register Port output latch Input data select bit (Note 1) Port level switching function (No peripheral input) Input function enable Direction register Data bus Port output latch Input data select bit P84(SCLKI0/SCLKO0) P87(SCLKI1/SCLKO1) Operation mode register UART/CSIO function select bit Internal/external clock select bit SCLKOi output SCLKIi input Input function enable (Note 1) Port level switching function (Standard: peripheral Schmitt) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes: • During processor and external extension modes, P41-P43 are external bus interface control signal pins, but their functional description in this block diagram is omitted. • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. • The input capacitance of each pin is approximately 10 pF. Figure 8.5.3 Port Peripheral Circuit Diagram (3) 8-29 32182 Group User’s Manual (Rev.1.0) 8 SBI# P221(CRX0) Data bus INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Peripheral Circuits Port level switching function (Standard: peripheral Schmitt) SBI#, CRX0 MOD0, MOD1 FP JTDI, JTCK, JTMS Output control JTDO RESET#, XIN, JTRST OSC-VCC, VCCE, VDDE VCC-BUS, EXCVCC, EXCVDD AD0IN0–12, VREF0, XOUT Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes: • The circle denotes a pin. • The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. Figure 8.5.4 Port Peripheral Circuit Diagram (4) 8-30 32182 Group User’s Manual (Rev.1.0) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.6 Precautions on Input/Output Ports 8.6 Precautions on Input/Output Ports • When using input/output ports in output mode Because the value of the Port Data Register is undefined after reset, the Port Data Register must have its initial value set in it before the Port Direction Register can be set for output. Conversely, if the Port Direction Register is set for output before setting data in the Port Data Register, the Port Data Register outputs an undefined value until any data is written into it. • About the port input disable function Because the input/output ports are disabled against input after reset, they must be enabled for input by setting the Port Input Enable (PIEN0) bit to "1" before their input functions can be used. When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. Consequently, if a peripheral input function is selected for any port (uncontrolled pin) while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the low-level input on it. 8-31 32182 Group User’s Manual (Rev.1.0) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.6 Precautions on Input/Output Ports This page is blank for reasons of layout. 8-32 32182 Group User’s Manual (Rev.1.0) CHAPTER 9 DMAC 9.1 9.2 9.3 9.4 Outline of the DMAC DMAC Related Registers Functional Description of the DMAC Precautions about the DMAC 9 9.1 Outline of the DMAC DMAC 9.1 Outline of the DMAC The microcomputer internally contains a 10-channel DMAC (Direct Memory Access Controller). It allows data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Number of channels Description 10 channels • Request from internal peripheral I/Os: A-D converter, multijunction timer, serial I/O (reception completed, transmit buffer empty) or CAN • DMA channels can be cascaded (Note 1) Maximum number of times transferred Transferable address space Transfer data size Transfer method Transfer mode Direction of transfer • 64 Kbytes (address space from H’0080 0000 to H’0080 FFFF) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs are supported. 16 or 8 bits Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dualaddress transfer Single transfer mode One of three modes can be selected for the source and destination: • Address fixed • Address incremental • Ring buffered Channel priority Maximum transfer rate Interrupt request Transfer area DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 (Priority is fixed) 13.3 Mbytes per second (when internal peripheral clock BCLK = 20 MHz) Group interrupt request can be generated when each transfer count register underflows. 64 Kbytes from H’0080 0000 to H’0080 FFFF (Note 2) 65,536 times Transfer request sources • Software trigger Note 1: The DMA channels can be cascaded in the manner described below. • Start DMA transfer on DMA1 upon completion of one DMA transfer on DMA0 • Start DMA transfer on DMA5 upon completion of all DMA transfers on DMA0 (upon underflow of the transfer count register) • Start DMA transfer on DMA2 upon completion of one DMA transfer on DMA1 • Start DMA transfer on DMA0 upon completion of one DMA transfer on DMA2 • Start DMA transfer on DMA3 upon completion of one DMA transfer on DMA2 • Start DMA transfer on DMA4 upon completion of one DMA transfer on DMA3 • Start DMA transfer on DMA6 upon completion of one DMA transfer on DMA5 • Start DMA transfer on DMA7 upon completion of one DMA transfer on DMA6 • Start DMA transfer on DMA5 upon completion of one DMA transfer on DMA7 • Start DMA transfer on DMA8 upon completion of one DMA transfer on DMA7 • Start DMA transfer on DMA9 upon completion of one DMA transfer on DMA8 Note 2: Address space from H'0081 0000 to H'0081 3FFF cannot be transferred into the internal RAM area. 9-2 32182 Group User’s Manual (Rev.1.0) 9 Input event bus 3210 DMAC 9.1 Outline of the DMAC Output event bus 0123 AD0 conversion completed TIO8_udf TIN0S S AD0 conversion completed TIO8_udf Software start S DMA0 udf end CAN0_S0/S15 TIN3S S Software start S DMA1 udf end CAN0_S1/S14 S TIN18S Software start S DMA2 udf end TIN0S S SIO0_TXD SIO1_RXD Software start S DMA3 udf end TIN19S SIO0_TXD S SIO0_RXD Software start S DMA4 udf end DMA0–4 interrupt TIN20S Software start S SIO2_RXD S DMA5 udf end SIO1_RXD SIO1_TXD S Software start S DMA6 udf end SIO3_TXD SIO2_TXD S Software start S DMA7 udf end S SIO3_RXD Software start S DMA8 udf end SIO3_TXD S Software start S DMA9 udf end DMA5–9 interrupt 0123 3210 Figure 9.1.1 Block Diagram of the DMAC 9-3 32182 Group User’s Manual (Rev.1.0) 9 9.2 DMAC Related Registers The diagram below shows a memory map of the DMAC related registers. DMAC Related Register Map (1/2) Address b0 H'0080 0400 +0 address b7 b8 DMAC 9.2 DMAC Related Registers +1 address b15 See pages 9-24 9-25 | H'0080 0408 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register (DM04ITST) (DM04ITMK) (Use inhibited area) DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register (DM59ITST) (DM59ITMK) (Use inhibited area) DMA0 Channel Control Register 0 DMA0 Channel Control (DM0CNT0) (DM0CNT1) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA0 Transfer Count Register (DM0TCT) DMA5 Channel Control Register 0 DMA5 Channel Control (DM5CNT0) (DM5CNT1) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA5 Transfer Count Register (DM5TCT) DMA1 Channel Control Register 0 DMA1 Channel Control (DM1CNT0) (DM1CNT1) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA1 Transfer Count Register (DM1TCT) DMA6 Channel Control Register 0 DMA6 Channel Control (DM6CNT0) (DM6CNT1) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA6 Transfer Count Register (DM6TCT) DMA2 Channel Control Register 0 DMA2 Channel Control (DM2CNT0) (DM2CNT1) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA2 Transfer Count Register (DM2TCT) DMA7 Channel Control Register 0 DMA7 Channel Control (DM7CNT0) (DM7CNT1) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA7 Transfer Count Register (DM7TCT) Register 1 9-24 9-25 | H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E 9-6 9-19 9-20 9-21 Register 1 9-11 9-19 9-20 9-21 Register 1 9-7 9-19 9-20 9-21 Register 1 9-12 9-19 9-20 9-21 Register 1 9-8 9-19 9-20 9-21 Register 1 9-13 9-19 9-20 9-21 9-4 32182 Group User’s Manual (Rev.1.0) 9 DMAC Related Register Map (2/2) Address b0 H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 +0 address b7 b8 DMAC 9.2 DMAC Related Registers +1 address b15 Register 1 See pages 9-9 9-19 9-20 9-21 Register 1 9-14 9-19 9-20 9-21 Register 1 9-10 9-19 9-20 9-21 Register 1 9-15 9-19 9-20 9-21 9-18 9-18 9-18 9-18 9-18 | H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478 DMA3 Channel Control Register 0 DMA3 Channel Control (DM3CNT0) (DM3CNT1) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA3 Transfer Count Register (DM3TCT) DMA8 Channel Control Register 0 DMA8 Channel Control (DM8CNT0) (DM8CNT1) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA8 Transfer Count Register (DM8TCT) DMA4 Channel Control Register 0 DMA4 Channel Control (DM4CNT0) (DM4CNT1) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA4 Transfer Count Register (DM4TCT) DMA9 Channel Control Register 0 DMA9 Channel Control (DM9CNT0) (DM9CNT1) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA9 Transfer Count Register (DM9TCT) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) (Use inhibited area) DMA5 Software Request Generation (DM5SRI) DMA6 Software Request Generation (DM6SRI) DMA7 Software Request Generation (DM7SRI) DMA8 Software Request Generation (DM8SRI) DMA9 Software Request Generation (DM9SRI) Register Register Register Register Register 9-18 9-18 9-18 9-18 9-18 9-5 32182 Group User’s Manual (Rev.1.0) 9 9.2.1 DMA Channel Control Registers DMA0 Channel Control Register 0 (DM0CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL0 0 3 0 4 TENL0 0 5 0 6 0 MDSEL0 TREQF0 TSZSL0 SADSL0 DADSL0 b 0 1 2, 3 Bit Name MDSEL0 DMA0 transfer mode select bit TREQF0 DMA0 transfer request flag bit REQSL0 DMA0 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start or one DMA2 transfer completed A-D0 conversion completed MJT (TIO8_udf) Extended DMA0 transfer request source select (DMA0 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL0 DMA0 transfer enable bit TSZSL0 DMA0 transfer size select bit SADSL0 DMA0 source address direction select bit DADSL0 DMA0 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA0 Channel Control Register 1 (DM0CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL0 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL0 Extended DMA0 transfer request source select bit 0000: MJT (input event bus 2) 0001: Settings inhibited 0010: CAN (CAN0_S0/S15) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W 9-6 32182 Group User’s Manual (Rev.1.0) 9 DMA1 Channel Control Register 0 (DM1CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL1 0 3 0 4 TENL1 0 5 0 6 0 MDSEL1 TREQF1 TSZSL1 SADSL1 DADSL1 b 0 1 2, 3 Bit Name MDSEL1 DMA1 transfer mode select bit TREQF1 DMA1 transfer request flag bit REQSL1 DMA1 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start MJT (output event bus 0) Settings inhibited Extended DMA1 transfer request source select (DMA1 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL1 DMA1 transfer enable bit TSZSL1 DMA1 transfer size select bit SADSL1 DMA1 source address direction select bit DADSL1 DMA1 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA1 Channel Control Register 1 (DM1CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL1 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL1 Extended DMA1 transfer request source select bit 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: | One DMA0 transfer completed MJT(TIN3S) Settings inhibited Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) AD0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Settings inhibited | Function R 0 R W 0 W 1111: Settings inhibited 9-7 32182 Group User’s Manual (Rev.1.0) 9 DMA2 Channel Control Register 0 (DM2CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL2 3 0 4 TENL2 5 TSZSL2 6 0 MDSEL2 TREQF2 SADSL2 DADSL2 0 0 0 b 0 1 2, 3 Bit Name MDSEL2 DMA2 transfer mode select bit TREQF2 DMA2 transfer request flag bit REQSL2 DMA2 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start MJT (output event bus 1) MJT (TIN18S) Extended DMA2 transfer request source select (DMA2 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL2 DMA2 transfer enable bit TSZSL2 DMA2 transfer size select bit SADSL2 DMA2 source address direction select bit DADSL2 DMA2 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA2 Channel Control Register 1 (DM2CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL2 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL2 Extended DMA2 transfer request source select bit 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: | One DMA1 transfer completed Settings inhibited CAN(CAN0_S1/S14) Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) AD0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Settings inhibited | Function R 0 R W 0 W 1111: Settings inhibited 9-8 32182 Group User’s Manual (Rev.1.0) 9 DMA3 Channel Control Register 0 (DM3CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL3 0 3 0 4 TENL3 0 5 TSZSL3 0 6 0 MDSEL3 TREQF3 SADSL3 DADSL3 b 0 1 2, 3 Bit Name MDSEL3 DMA3 transfer mode select bit TREQF3 DMA3 transfer request flag bit REQSL3 DMA3 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start SIO0_TXD (transmit buffer empty) SIO1_RXD Extended DMA3 transfer request source select (DMA3 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL3 DMA3 transfer enable bit TSZSL3 DMA3 transfer size select bit SADSL3 DMA3 source address direction select bit DADSL3 DMA3 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA3 Channel Control Register 1 (DM3CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL3 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL3 Extended DMA3 transfer request source select bit 0000: MJT(TIN0) 0001: One DMA2 transfer completed 0010: Settings inhibited 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W 9-9 32182 Group User’s Manual (Rev.1.0) 9 DMA4 Channel Control Register 0 (DM4CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL4 3 0 4 TENL4 5 TSZSL4 6 0 MDSEL4 TREQF4 SADSL4 DADSL4 0 0 0 b 0 1 2, 3 Bit Name MDSEL4 DMA4 transfer mode select bit TREQF4 DMA4 transfer request flag bit REQSL4 DMA4 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: One DMA3 transfer completed 10: SIO0_RXD 11: Extended DMA4 transfer request source select (DMA4 Channel Control Register 1) 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R W W W R R W W R(Note 1) R W 4 5 6 7 TENL4 DMA4 transfer enable bit TSZSL4 DMA4 transfer size select bit SADSL4 DMA4 source address direction select bit DADSL4 DMA4 destination address direction select bit R W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA4 Channel Control Register 1 (DM4CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL4 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL4 Extended DMA4 transfer request source select bit 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: | MJT(TIN19S) SIO0_TXD (transmit buffer empty) Settings inhibited Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) AD0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Settings inhibited | Function R 0 R W 0 W 1111: Settings inhibited 9-10 32182 Group User’s Manual (Rev.1.0) 9 DMA5 Channel Control Register 0 (DM5CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 DADSL5 1 0 2 REQSL5 3 0 4 TENL5 5 TSZSL5 6 SADSL5 MDSEL5 TREQF5 0 0 0 0 0 b 0 1 2, 3 Bit Name MDSEL5 DMA5 transfer mode select bit TREQF5 DMA5 transfer request flag bit REQSL5 DMA5 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start or one DMA7 transfer completed All DMA0 transfers completed SIO2_RXD Extended DMA5 transfer request source select (DMA5 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL5 DMA5 transfer enable bit TSZSL5 DMA5 transfer size select bit SADSL5 DMA5 source address direction select bit DADSL5 DMA5 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA5 Channel Control Register 1 (DM5CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL5 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL5 Extended DMA5 transfer request source select bit 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: | MJT(TIN20S) Settings inhibited Settings inhibited Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) AD0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Settings inhibited | Function R 0 R W 0 W 1111: Settings inhibited 9-11 32182 Group User’s Manual (Rev.1.0) 9 DMA6 Channel Control Register 0 (DM6CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL6 3 0 4 TENL6 5 0 6 0 MDSEL6 TREQF6 TSZSL6 SADSL6 DADSL6 0 0 b 0 1 2, 3 Bit Name MDSEL6 DMA6 transfer mode select bit TREQF6 DMA6 transfer request flag bit REQSL6 DMA6 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start SIO1_TXD (transmit buffer empty) Settings inhibited Extended DMA6 transfer request source select (DMA6 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL6 DMA6 transfer enable bit TSZSL6 DMA6 transfer size select bit SADSL6 DMA6 source address direction select bit DADSL6 DMA6 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA6 Channel Control Register 1 (DM6CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL6 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL6 Extended DMA6 transfer request source select bit 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: | One DMA5 transfer completed Settings inhibited SIO1_RXD Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) AD0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Settings inhibited | Function R 0 R W 0 W 1111: Settings inhibited 9-12 32182 Group User’s Manual (Rev.1.0) 9 DMA7 Channel Control Register 0 (DM7CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL7 3 0 4 TENL7 5 TSZSL7 6 0 MDSEL7 TREQF7 SADSL7 DADSL7 0 0 0 b 0 1 2, 3 Bit Name MDSEL7 DMA7 transfer mode select bit TREQF7 DMA7 transfer request flag bit REQSL7 DMA7 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start SIO2_TXD (transmit buffer empty) Settings inhibited Extended DMA7 transfer request source select (DMA7 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL7 DMA7 transfer enable bit TSZSL7 DMA7 transfer size select bit SADSL7 DMA7 source address direction select bit DADSL7 DMA7 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA7 Channel Control Register 1 (DM7CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL7 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL7 Extended DMA7 transfer request source select bit 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: | One DMA6 transfer completed Settings inhibited SIO3_TXD (transmit buffer empty) Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) AD0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Settings inhibited | Function R 0 R W 0 W 1111: Settings inhibited 9-13 32182 Group User’s Manual (Rev.1.0) 9 DMA8 Channel Control Register 0 (DM8CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL8 3 0 4 TENL8 5 TSZSL8 6 0 MDSEL8 TREQF8 SADSL8 DADSL8 0 0 0 b 0 1 2, 3 Bit Name MDSEL8 DMA8 transfer mode select bit TREQF8 DMA8 transfer request flag bit REQSL8 DMA8 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start MJT (input event bus 0) SIO3_RXD Extended DMA8 transfer request source select (DMA8 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL8 DMA8 transfer enable bit TSZSL8 DMA8 transfer size select bit SADSL8 DMA8 source address direction select bit DADSL8 DMA8 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA8 Channel Control Register 1 (DM8CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL8 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL8 Extended DMA8 transfer request source select bit 0000: Settings inhibited 0001: Settings inhibited 0010: One DMA7 transfer completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W 9-14 32182 Group User’s Manual (Rev.1.0) 9 DMA9 Channel Control Register 0 (DM9CNT0) b0 0 DMAC 9.2 DMAC Related Registers b7 0 1 0 2 REQSL9 3 0 4 TENL9 5 0 6 0 MDSEL9 TREQF9 TSZSL9 SADSL9 DADSL9 0 0 b 0 1 2, 3 Bit Name MDSEL9 DMA9 transfer mode select bit TREQF9 DMA9 transfer request flag bit REQSL9 DMA9 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: 01: 10: 11: Software start SIO3_TXD (transmit buffer empty) Settings inhibited Extended DMA9 transfer request source select (DMA9 Channel Control Register 1) R R W W R(Note 1) R W 4 5 6 7 TENL9 DMA9 transfer enable bit TSZSL9 DMA9 transfer size select bit SADSL9 DMA9 source address direction select bit DADSL9 DMA9 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R R R W W W W Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA9 Channel Control Register 1 (DM9CNT1) b8 0 b15 0 9 0 10 0 11 0 12 0 13 0 14 0 REQESEL9 b 8–11 12–15 Bit Name No function assigned. Fix to "0". REQESEL9 Extended DMA9 transfer request source select bit 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: | One DMA8 transfer completed Settings inhibited Settings inhibited Common 1) MJT (input event bus 1) Common 2) MJT (input event bus 3) Common 3) MJT (output event bus 2) Common 4) MJT (output event bus 3) Common 5) AD0 conversion completed Common 6) MJT (TIN0S) Common 7) MJT (TIO8_udf) Settings inhibited | Function R 0 R W 0 W 1111: Settings inhibited 9-15 32182 Group User’s Manual (Rev.1.0) 9 [DMnCNT0 Register] (1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0) DMAC 9.2 DMAC Related Registers The DMA Channel Control Register consists of the bits to select DMA transfer mode on each channel, set the DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as those to set the transfer size and the source/destination address directions. When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer mode. Setting this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode. In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer Count Register counts in free-run mode, during which time transfer operation is continued until the transfer enable bit is reset to "0" (to disable transfer). In ring buffer mode, no interrupt is generated at completion of DMA transfer. (2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1) This flag is set to "1" when a DMA transfer request occurs, and is cleared to "0" when the transfer for that transfer request is completed. Reading this flag helps to know DMA transfer requests on each channel. Writing "0" to this bit clears the generated DMA transfer request. Writing "1" has no effect; the bit retains the value it had before the write. If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has already been set to "1", the next DMA transfer request is not accepted until the transfer being performed on that channel is completed. (3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2–3) These bits select the cause or source of DMA transfer request on each DMA channel. (4) TENLn (DMAn Transfer Enable) bit (Bit 4) Setting this bit to "1" enables transfer, and the channel is made ready for DMA transfer. When all transfers on that channel are completed (i.e., the Transfer Counter Register underflows), the bit is cleared to "0". Setting this bit to "0" disables transfer. However, if a transfer request has already been accepted, transfers on that channel are not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5) This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one transfer). The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1". (6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6) This bit selects the direction in which the source address changes. This mode can be selected from two choices: Address fixed or Address incremental. (7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7) This bit selects the direction in which the destination address changes. This mode can be selected from two choices: Address fixed or Address incremental. [DMnCNT1 Register] (1) REQESELn (Extended DMAn Transfer Request Source Select) bits (Bits 12–15) These bits select the cause or source of extended DMA transfer request on each DMA channel. Note: • The extended DMA transfer request sources selected by the REQESELn (Extended DMAn Transfer Request Source Select) bits have no effect unless the “Extended” DMA transfer request source is selected with the DMA Channel Control Register’s DMA Request Source Select (REQSLn) bits. 9-16 32182 Group User’s Manual (Rev.1.0) 9 DMAC 9.2 DMAC Related Registers Extended DMA transfer request source selected S DMAn transfer request source S DMAn Figure 9.2.1 Block Diagram of Extended DMAn Transfer Request Source Selection 9-17 32182 Group User’s Manual (Rev.1.0) 9 9.2.2 DMA Software Request Generation Registers DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 Software Software Software Software Software Software Software Software Software Software 1 ? DMAC 9.2 DMAC Related Registers Request Request Request Request Request Request Request Request Request Request 2 ? Generation Generation Generation Generation Generation Generation Generation Generation Generation Generation 3 ? 4 ? Register Register Register Register Register Register Register Register Register Register 5 ? (DM0SRI) (DM1SRI) (DM2SRI) (DM3SRI) (DM4SRI) (DM5SRI) (DM6SRI) (DM7SRI) (DM8SRI) (DM9SRI) 6 7 8 9 10 ? 11 ? b15 ? b0 ? DM0SRI–DM9SRI ? ? ? ? b 0–15 Bit Name DM0SRI–DM9SRI DMA software request generation bits Function DMA transfer request is generated by writing any data to these bits. R ? W W Note: • This register may be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when “Software start” has been selected for the cause of DMA transfer request. (1) DM0SRI–DM9SRI (DMA Software Request Generation) bits A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when “Software start” is selected as the cause of DMA transfer request (by setting the DMAn Channel Control Register 0 bits 2–3 to ‘00’). 9-18 32182 Group User’s Manual (Rev.1.0) 9 9.2.3 DMA Source Address Registers DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 Source Source Source Source Source Source Source Source Source Source 1 ? DMAC 9.2 DMAC Related Registers Address Address Address Address Address Address Address Address Address Address 2 ? Register Register Register Register Register Register Register Register Register Register 3 ? (DM0SA) (DM1SA) (DM2SA) (DM3SA) (DM4SA) (DM5SA) (DM6SA) (DM7SA) (DM8SA) (DM9SA) 4 ? 5 ? 6 ? 7 8 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? b0 ? DM0SA–DM9SA ? ? b 0–15 Bit Name DM0SA–DMA9SA Function Source address bits A16–A31 (A0–A15 are fixed to H’0080) R R W W Note: • This register must always be accessed in halfwords. The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0SA–DM9SA (Source Address bits A16–A31) Set this register to specify the source address of DMA transfer in the internal I/O or RAM space from the address H’0080 0000 to the address H’0080 FFFF. The 16 high-order source address bits (A0–A15) are always fixed to H’0080. Use this register to set the 16 low-order source address bits (with bit 0 corresponding to the source address A16, and bit 15 corresponding to the source address A31). 9-19 32182 Group User’s Manual (Rev.1.0) 9 9.2.4 DMA Destination Address Registers DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 Destination Destination Destination Destination Destination Destination Destination Destination Destination Destination 1 ? DMAC 9.2 DMAC Related Registers Address Address Address Address Address Address Address Address Address Address 2 ? 3 ? Register Register Register Register Register Register Register Register Register Register 4 ? (DM0DA) (DM1DA) (DM2DA) (DM3DA) (DM4DA) (DM5DA) (DM6DA) (DM7DA) (DM8DA) (DM9DA) 5 ? 6 ? 7 8 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? b0 ? DM0DA–DM9DA ? ? b 0–15 Bit Name DM0DA–DM9DA Function Destination address bits A16–A31 (A0–A15 are fixed to H’0080) R R W W Note: • This register must always be accessed in halfwords The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0DA–DM9DA (Destination Address bits A16–A31) Set this register to specify the destination address of DMA transfer in the internal I/O or RAM space from the address H’0080 0000 to the address H’0080 FFFF. The 16 high-order destination address bits (A0–A15) are always fixed to H’0080. Use this register to set the 16 low-order destination address bits (with bit 0 corresponding to the destination address A16, and bit 15 corresponding to the destination address A31). 9-20 32182 Group User’s Manual (Rev.1.0) 9 9.2.5 DMA Transfer Count Registers DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer 1 ? DMAC 9.2 DMAC Related Registers Count Count Count Count Count Count Count Count Count Count 2 ? Register Register Register Register Register Register Register Register Register Register 3 ? (DM0TCT) (DM1TCT) (DM2TCT) (DM3TCT) (DM4TCT) (DM5TCT) (DM6TCT) (DM7TCT) (DM8TCT) (DM9TCT) 4 ? 5 ? 6 7 8 9 10 ? 11 ? 12 ? 13 ? 14 ? b15 ? b0 ? DM0TCT–DM15TCT ? ? ? ? b 0–15 Bit Name DM0TCT–DM9TCT (Has no effect during ring buffer mode) Function DMA transfer count R R W W Note: • This register must always be accessed in halfwords. The DMA Transfer Count Register is used to set the number of times data is transferred on each channel. However, the value in this register has no effect during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the values read from this register are always the current value. (However, if the register is read in a cycle immediately after transfer, the value obtained is one that was stored in the count register before the transfer began.) When transfer finishes, this count register underflows and the value read from it is H’FFFF. When transfer is enabled, this register is protected in hardware and cannot be accessed for write. During ring buffer mode, the transfer count register counts down in free-run mode and continues counting until transfer is disabled. No interrupt is generated at underflow. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all transfers on a channel are completed (i.e., the transfer count register underflows), transfer on the cascaded channel starts. 9-21 32182 Group User’s Manual (Rev.1.0) 9 9.2.6 DMA Interrupt Related Registers DMAC 9.2 DMAC Related Registers The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to the Interrupt Controller. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests. Group interrupt Interrupt request from each peripheral function Set Data = 0 clear Interrupt request status Data bus F/F F/F Interrupt request enabled To the Interrupt Controller Figure 9.2.2 Interrupt Request Status and Mask Registers 9-22 32182 Group User’s Manual (Rev.1.0) 9 Example for clearing interrupt request status Interrupt request status b4 5 0 6 0 b7 0 DMAC 9.2 DMAC Related Registers Initial state 0 Interrupt request Event occurs on bit 6 0 0 1 0 Event occurs on bit 4 Write to the interrupt request status b4 1 5 1 6 0 b7 1 1 0 1 0 1 0 0 0 Only bit 6 cleared Bit 4 data retained Program example • To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */ Interrupt request status b4 5 0 6 1 b7 0 Event occurs on bit 6 0 Read 0 0 1 0 Event occurs on bit 4 1 0 1 0 Clear bit 6 (AND'ing with 1101) 0 0 0 0 0 0 0 0 Write Only bit 6 cleared Bit 4 also cleared Figure 9.2.3 Example for Clearing Interrupt Request Status 9-23 32182 Group User’s Manual (Rev.1.0) 9 DMA0–4 Interrupt Request Status Register (DM04ITST) b0 0 DMAC 9.2 DMAC Related Registers 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 b 0–2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". DMITST4 (DMA4 interrupt request status bit) DMITST3 (DMA3 interrupt request status bit) DMITST2 (DMA2 interrupt request status bit) DMITST1 (DMA1 interrupt request status bit) DMITST0 (DMA0 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA5–9 Interrupt Request Status Register (DM59ITST) b0 0 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 b 0–2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". DMITST9 (DMA9 interrupt request status bit) DMITST8 (DMA8 interrupt request status bit) DMITST7 (DMA7 interrupt request status bit) DMITST6 (DMA6 interrupt request status bit) DMITST5 (DMA5 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. The Interrupt Request Status Register helps to know the status of interrupt requests on each channel. If the DMAn interrupt request status bit (n = 0–9) is set to "1", it means that a DMA interrupt request on the corresponding channel has been generated. (1) DMITSTn (DMAn Interrupt Request Status) bit (n = 0–9) [Setting the DMAn interrupt request status bit] This bit is set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing "0" in software. Note: • The DMAn interrupt request status bit cannot be cleared by writing "0" to the DMA Interrupt Control Register’s “interrupt request bit” included in the Interrupt Controller. When writing to the DMA Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. 9-24 32182 Group User’s Manual (Rev.1.0) 9 DMA0–4 Interrupt Request Mask Register (DM04ITMK) b8 0 DMAC 9.2 DMAC Related Registers 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". DMITMK4 (DMA4 interrupt request mask bit) DMITMK3 (DMA3 interrupt request mask bit) DMITMK2 (DMA2 interrupt request mask bit) DMITMK1 (DMA1 interrupt request mask bit) DMITMK0 (DMA0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W DMA5–9 Interrupt Request Mask Register (DM59ITMK) b8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". DMITMK9 (DMA9 interrupt request mask bit) DMITMK8 (DMA8 interrupt request mask bit) DMITMK7 (DMA7 interrupt request mask bit) DMITMK6 (DMA6 interrupt request mask bit) DMITMK5 (DMA5 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W The DMA Interrupt Request Mask Register is used to mask interrupt requests on each DMA channel. (1) DMITMKn (DMAn Interrupt Request Mask) bit (n = 0–9) Setting the DMAn interrupt request mask bit to "1" masks the interrupt requests on DMAn channel. However, if an interrupt request occurs, the DMAn interrupt request status bit is always set to "1" irrespective of the contents of this mask register. 9-25 32182 Group User’s Manual (Rev.1.0) 9 DM04ITST (H'0080 0400) DM04ITMK (H'0080 0401) DMA4UDF Data bus b3 b11 DMA3UDF b4 b12 DMA2UDF b5 b13 DMA1UDF b6 b14 DMA0UDF b7 b15 DMITST0 F/F DMITMK0 F/F DMITST1 F/F DMITMK1 F/F DMITST2 F/F DMITMK2 F/F DMITST3 F/F DMITMK3 F/F DMITST4 F/F DMITMK4 F/F 5-source inputs (Level) DMAC 9.2 DMAC Related Registers DMA transfer interrupt request 0 Figure 9.2.4 Block Diagram of DMA Transfer Interrupt Request 0 DM59ITST (H'0080 0408) DM59ITMK (H'0080 0409) DMA9UDF Data bus b3 b11 DMA8UDF b4 b12 DMA7UDF b5 b13 DMA6UDF b6 b14 DMA5UDF b7 b15 DMITST5 F/F DMITMK5 F/F DMITST6 F/F DMITMK6 F/F DMITST7 F/F DMITMK7 F/F DMITST8 F/F DMITMK8 F/F DMITST9 F/F DMITMK9 F/F 5-source inputs (Level) DMA transfer interrupt request 1 Figure 9.2.5 Block Diagram of DMA Transfer Interrupt Request 1 9-26 32182 Group User’s Manual (Rev.1.0) 9 9.3 Functional Description of the DMAC 9.3.1 DMA Transfer Request Sources DMAC 9.3 Functional Description of the DMAC For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers on another DMA channel (cascade mode). The causes or sources of DMA transfer requests are selected using the transfer request source select bits REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request source select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the causes or sources of DMA transfer requests on each channel. Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0 REQSL0 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start or one DMA2 transfer completed A-D0 conversion completed MJT (TIO8_udf) Extended DMA0 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA0 Software Request Generation Register (software start) or when one DMA2 transfer is completed (cascade mode) When A-D0 conversion is completed When MJT TIO8 underflows The source selected by the DMA0 Channel Control Register 1 (DM0CNT1) REQESEL0 bits (see below) REQESEL0 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (input event bus 2) Settings inhibited CAN (CAN0_S0/S15) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) DMA Transfer Request Generation Timing When MJT input event bus 2 signal is generated – When CAN0 slot 0 transmission failed or slot 15 transmission reception finished When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – 9-27 32182 Group User’s Manual (Rev.1.0) 9 REQSL1 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (output event bus 0) Settings inhibited Extended DMA1 transfer request source selected DMAC 9.3 Functional Description of the DMAC Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1 DMA Transfer Request Generation Timing When any data is written to the DMA1 Software Request Generation Register When MJT output event bus 0 signal is generated – The source selected by the DMA1 Channel Control Register 1 (DM1CNT1) REQESEL1 bits (see below) REQESEL1 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA0 transfer completed MJT (TIN3 input signal) Settings inhibited MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) DMA Transfer Request Generation Timing When one DMA0 transfer is completed (cascade mode) When MJT TIN3 input signal is generated – When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2 REQSL2 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (output event bus 1) MJT (TIN18 input signal) Extended DMA2 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA2 Software Request Generation Register When MJT output event bus 1 signal is generated When MJT TIN18 input signal is generated The source selected by the DMA2 Channel Control Register 1 (DM2CNT1) REQESEL2 bits (see below) REQESEL2 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA1 transfer completed Settings inhibited CAN(CAN0_S1/S14) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) DMA Transfer Request Generation Timing When one DMA1 transfer is completed (cascade mode) – When CAN0 slot 1 transmission failed or slot 14 transmission reception finished When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – 9-28 32182 Group User’s Manual (Rev.1.0) 9 REQSL3 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start DMAC 9.3 Functional Description of the DMAC Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3 DMA Transfer Request Generation Timing When any data is written to the DMA3 Software Request Generation Register Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty Serial I/O1 (reception completed) When serial I/O1 reception is completed Extended DMA3 transfer request source selected The source selected by the DMA3 Channel Control Register 1 (DM3CNT1) REQESEL3 bits (see below) REQESEL3 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (TIN0 input signal) One DMA2 transfer completed Settings inhibited MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) DMA Transfer Request Generation Timing When MJT TIN0 input signal is generated When one DMA2 transfer is completed (cascade mode) – When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4 REQSL4 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start One DMA3 transfer completed Extended DMA4 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA4 Software Request Generation Register When one DMA3 transfer is completed (cascade mode) The source selected by the DMA4 Channel Control Register 1 (DM4CNT1) REQESEL4 bits (see below) Serial I/O0 (reception completed) When serial I/O0 reception is completed REQESEL4 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (TIN19 input signal) DMA Transfer Request Generation Timing When MJT TIN19 input signal is generated Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty Settings inhibited MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) – When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – 9-29 32182 Group User’s Manual (Rev.1.0) 9 REQSL5 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start or one DMA7 transfer completed All DMA0 transfers completed Extended DMA5 transfer request source selected DMAC 9.3 Functional Description of the DMAC Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5 DMA Transfer Request Generation Timing When any data is written to the DMA5 Software Request Generation Register (software start) or when one DMA7 transfer is completed (cascade mode) When all DMA0 transfers are completed (cascade mode) The source selected by the DMA5 Channel Control Register 1 (DM5CNT1) REQESEL5 bits (see below) Serial I/O2 (reception completed) When serial I/O2 reception is completed REQESEL5 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (TIN20 input signal) Settings inhibited Settings inhibited MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) DMA Transfer Request Generation Timing When MJT TIN20 input signal is generated – – When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6 REQSL6 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start Settings inhibited Extended DMA6 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA6 Software Request Generation Register – The source selected by the DMA6 Channel Control Register 1 (DM6CNT1) REQESEL6 bits (see below) Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is empty REQESEL6 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA5 transfer completed Settings inhibited DMA Transfer Request Generation Timing When one DMA5 transfer is completed (cascade mode) – Serial I/O1 (reception completed) When serial I/O1 reception is completed MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – 9-30 32182 Group User’s Manual (Rev.1.0) 9 REQSL7 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start Settings inhibited Extended DMA7 transfer request source selected DMAC 9.3 Functional Description of the DMAC Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7 DMA Transfer Request Generation Timing When any data is written to the DMA7 Software Request Generation Register – The source selected by the DMA7 Channel Control Register 1 (DM7CNT1) REQESEL7 bits (see below) Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is empty REQESEL7 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA6 transfer completed Settings inhibited DMA Transfer Request Generation Timing When one DMA6 transfer is completed (cascade mode) – Serial I/O3 (reception completed) When serial I/O3 reception is completed MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8 REQSL8 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (input event bus 0) Extended DMA8 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA8 Software Request Generation Register When MJT input event bus 0 signal is generated The source selected by the DMA8 Channel Control Register 1 (DM8CNT1) REQESEL8 bits (see below) Serial I/O3 (reception completed) When serial I/O3 reception is completed REQESEL8 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited Settings inhibited Settings inhibited One DMA7 transfer completed MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) DMA Transfer Request Generation Timing – – When one DMA7 transfer is completed (cascade mode) When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – 9-31 32182 Group User’s Manual (Rev.1.0) 9 REQSL9 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start Settings inhibited Extended DMA9 transfer request source selected DMAC 9.3 Functional Description of the DMAC Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9 DMA Transfer Request Generation Timing When any data is written to the DMA9 Software Request Generation Register – The source selected by the DMA9 Channel Control Register 1 (DM9CNT1) REQESEL9 bits (see below) Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is empty REQESEL9 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA8 transfer completed Settings inhibited Settings inhibited MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf) DMA Transfer Request Generation Timing When one DMA8 transfer is completed (cascade mode) – – When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs – 9-32 32182 Group User’s Manual (Rev.1.0) 9 9.3.2 DMA Transfer Processing Procedure DMAC 9.3 Functional Description of the DMAC Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0. DMA transfer processing starts Setting interrupt controller-related registers Set the interrupt controller's DMA0-4 Interrupt Control Register • Interrupt priority level Set DMA0 Channel Control Register 0 • Transfers disabled Set DMA0-4 Interrupt Request Status Registers 0 and 1 • Interrupt request status bits cleared • Interrupt request enabled Set DMA0-4 Interrupt Request Mask Register Setting DMAC-related registers Set DMA0 Source Address Register • Source address of transfer Set DMA0 Destination Address Register • Destination address of transfer Set DMA0 Count Register • Number of times DMA transfer is performed • Transfer mode, request source, transfer size, address direction and transfer enable Set DMA0 Channel Control Registers 0 and 1 Starting DMA transfer DMA transfer starts as requested by internal peripheral I/O Transfer count register underflows DMA transfer completed Interrupt request generated DMA operation completed Figure 9.3.1 Example of a DMA Transfer Processing Procedure 9-33 32182 Group User’s Manual (Rev.1.0) 9 9.3.3 Starting DMA DMAC 9.3 Functional Description of the DMAC Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Channel Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or source of DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1". DMA transfer begins when the specified cause or source of DMA transfer request becomes effective after setting the TENL (DMA transfer enable) bit to "1". Note: • If the transfer request source selected by the REQSL (DMA transfer request source select) and REQESEL (extended DMA transfer request source select) bits is MJT (TIN input signal), the time required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN input signal is three cycles (150 ns when the internal peripheral clock = 20 MHz) at the shortest. Or, depending on the preceding or following bus usage condition, up to five cycles (250 ns when the internal peripheral clock = 20 MHz) may be required. (However, this applies when the external bus, HOLD and the LOCK instruction all are unused.) To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Section 21.7, “AC Characteristics (when VCCE = 5 V),” and Section 21.8, “AC Characteristics (when VCCE = 3.3 V).”) 9.3.4 DMA Channel Priority DMA0 has the highest priority. The priority of this and other channels is shown below. DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 This order of priority is fixed and cannot be changed. Among channels on which DMA transfer is requested, the channel that has the highest priority is selected. 9.3.5 Gaining and Releasing Control of the Internal Bus For any channel, control of the internal bus is gained and released in “single transfer DMA” mode. In single transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA transfer request is accepted and after executing one DMA transfer (in one read and one write internal clock cycle), returns bus control to the CPU. The diagram below shows the operation in single transfer DMA. Requested Internal bus arbitration (requests from the DMAC) Gained Requested Gained Requested Gained CPU Internal bus Released Released Released DMAC R W R W R W One DMA transfer One DMA transfer R: Read W: Write One DMA transfer Figure 9.3.2 Gaining and Releasing Control of the Internal Bus 9-34 32182 Group User’s Manual (Rev.1.0) 9 9.3.6 Transfer Units DMAC 9.3 Functional Description of the DMAC Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer. 9.3.7 Transfer Counts Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 65,536 times. The value of the DMA Transfer Count Register is decremented by one every time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored. 9.3.8 Address Space The address space in which data can be transferred by DMA is 64 Kbytes of internal peripheral I/O or RAM space (H’0080 0000 through H’0080 FFFF) for both source and destination. To set the source and destination addresses on each DMA channel, use the DMA Source Address Register and DMA Destination Address Register. 9.3.9 Transfer Operation (1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (The transfer data is taken into the DMAC’s internal temporary register before being transferred.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, DMA transfer is performed with the same bus protocol and the same bus timing as when peripheral modules are accessed by the CPU. (3) Transfer rate Transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the bus and one read and one write cycle to perform one transfer. Therefore, the maximum transfer rate is calculated by the equation below: 1 Maximum transfer rate [bytes per second] = 2 bytes × 1/f(BCLK) × 3 cycles (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds (“Address fixed” or “Address incremental”) is set for each channel using the SADSL (source address direction select) and DADSL (destination address direction select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Address fixed Address incremental Transfer Unit 8 bits 16 bits 8 bits 16 bits Address Change for One DMA 0 0 +1 +2 9-35 32182 Group User’s Manual (Rev.1.0) 9 (5) Transfer count value (6) Transfer byte positions DMAC 9.3 Functional Description of the DMAC The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits). When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid byte positions in DMA transfer. +0 b0 Source 8 bits b7 b8 8 bits +1 b15 +0 b0 b7 b8 16 bits +1 b15 Destination 8 bits 8 bits 16 bits Figure 9.3.3 Transfer Byte Positions (7) Ring buffer mode When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control returns to the transfer start address, from which transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start address must always be B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000). The following describes how addresses are incremented in ring buffer mode. [1] When the transfer size is 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B’11111, they are recycled to B’00000 by the next increment operation, thus returning to the start address again. [2] When the transfer size is 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B’111110, they are recycled to B’000000 by the next increment operation, thus returning to the start address again. If the source address has been set to be incremented, it is the source address that recycles to the start address; if the destination address has been set to be incremented, it is the destination address that recycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low-order bits initially set to B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000). During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). 9-36 32182 Group User’s Manual (Rev.1.0) 9 Transfer count 1 2 3 Transfer address H'0080 1000 H'0080 1001 H'0080 1002 DMAC 9.3 Functional Description of the DMAC Transfer count 1 2 3 Transfer address H'0080 1000 H'0080 1002 H'0080 1004 | 31 32 ↓ 1 2 | H'0080 101E H'0080 101F ↓ H'0080 1000 H'0080 1001 | 31 32 ↓ 1 2 | H'0080 103C H'0080 103E ↓ H'0080 1000 H'0080 1002 | | | | Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode 9.3.10 End of DMA and Interrupt In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer finishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, if interrupt requests on any channel have been masked by the DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests are generated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests are generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit. 9.3.11 Each Register Status after Completion of DMA Transfer When DMA transfer is completed, the status of the source and destination address registers becomes as follows: (1) Address fixed • The values set in the address registers before DMA transfer started remain intact (fixed). (2) Address incremental • For 8-bit transfer, the values of the address registers are the last transfer address + 1. • For 16-bit transfer, the values of the address registers are the last transfer address + 2. The transfer count register at completion of DMA transfer is in an underflow state (H’FFFF). Therefore, before another DMA transfer can be performed, the transfer count register must be set newly again, except when trying to perform transfers 65,536 times (H’FFFF). 9-37 32182 Group User’s Manual (Rev.1.0) 9 9.4 Precautions about the DMAC • About writing to the DMAC related registers DMAC 9.4 Precautions about the DMAC Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0"). When transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer request flag and the DMA Transfer Count Register that is protected in hardware. This is a precaution necessary to ensure stable DMA operation. The table below lists the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status Transfer enabled Transfer disabled Transfer enable bit Can be accessed Can be accessed Transfer request flag Can be accessed Can be accessed Other DMAC related registers Cannot be accessed Can be accessed Even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be observed: (1) DMA Channel Control Register 0 transfer enable bit and transfer request flag For all other bits in this register, be sure to write the same data that those bits had before the write. Note, however, that only writing "0" is effective for the transfer request flag. (2) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored. (3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer Although this operation means accessing the DMAC related registers while DMA is enabled, there is no problem. Note, however, that no data can be transferred by DMA to the DMAC related registers on the currently active channel itself. • Manipulating the DMAC related registers by DMA transfer When manipulating the DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers with the initial values by DMA transfer), do not write to the DMAC related registers on the currently active channel through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) It is only the DMAC related registers on other channels that can be rewritten by means of DMA transfer. (For example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by DMA transfer through channel 0.) • About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write "1" to all bits, except those to be cleared. Writing "1" to any bits in this register has no effect, so that they retain the data they had before the write. • About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the channel control register’s transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, the DMA Source Address and DMA Destination Address Registers can be rewritten by DMA transfer from one channel to another. 9-38 32182 Group User’s Manual (Rev.1.0) CHAPTER 10 MULTIJUNCTION TIMERS 10.1 10.2 10.3 10.4 10.5 10.6 Outline of Multijunction Timers Common Units of Multijunction Timers TOP (Output-Related 16-Bit Timer) TIO (Input/Output-Related 16-Bit Timer) TMS (Input-Related 16-Bit Timer) TML (Input-Related 32-Bit Timer) 10 10.1 Outline of Multijunction Timers MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event buses at multiple points that they are called the “multijunction” timers. The 32182 has four types of MJT as listed in the table below, providing a total of 37-channel timers. Table 10.1.1 Outline of MJT Name TOP (Timer OutPut) Type Output-related 16-bit timer (down-counter) No. of Channels 11 Description One of three output modes can be selected by software. • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TIO (Timer Input OutPut) Input/output-related 16-bit timer (down-counter) 10 One of three input modes or four output modes can be selected by software. • Measure clear input mode • Measure free-run input mode • Noise processing input mode • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TMS (Timer Measure Small) TML (Timer Measure Large) Input-related 32-bit timer (up-counter) 8 32-bit input measure timer Input-related 16-bit timer (up-counter) 8 16-bit input measure timer 10-2 32182 Group User’s Manual (Rev.1.0) 10 Table 10.1.2 Interrupt Generation Functions of MJT Signal Name MJT Interrupt Request Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 TIO0–3 output TOP6, TOP7 output TOP0–5 output TIO8, TIO9 output TIO4–7 output TOP10 output TOP8, TOP9 output TMS0, TMS1 output TIN0 input TIN16–TIN19 input TIN20–TIN23 input TIN3 input Source of Interrupt MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers No. of ICU Input Sources 4 2 6 2 4 1 2 2 1 4 4 1 TIO0–3 output interrupt TOP6, 7 output interrupt TOP0–5 output interrupt TIO8, 9 output interrupt TIO4–7 output interrupt TOP10 output interrupt TOP8, 9 output interrupt TMS0, 1 output interrupt TIN0–2 input interrupt TIN12–19 input interrupt TIN20–29 input interrupt TIN3–6 input interrupt Table 10.1.3 DMA Transfer Request Generation by MJT Corresponding DMAC Channel No. DMA0 DMA Transfer Request Source TIO8_udf Input event bus 2 Common transfer request source (see Table 10.1.4) DMA1 Output event bus 0 TIN3 input signal Common transfer request source (see Table 10.1.4) DMA2 Output event bus 1 TIN18 input signal Common transfer request source (see Table 10.1.4) DMA3 DMA4 DMA5 TIN0 input signal Common transfer request source (see Table 10.1.4) TIN19 input signal Common transfer request source (see Table 10.1.4) TIN20 input signal Common transfer request source (see Table 10.1.4) DMA6 DMA7 DMA8 DMA9 Common transfer request source (see Table 10.1.4) Common transfer request source (see Table 10.1.4) Input event bus 0 Common transfer request source (see Table 10.1.4) Common transfer request source (see Table 10.1.4) 10-3 32182 Group User’s Manual (Rev.1.0) 10 Corresponding DMAC Channel No. DMAn Input event bus 1 Input event bus 3 Output event bus 2 Output event bus 3 TIN0 input signal TIO8_udf MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Table 10.1.4 DMA Transfer Request Generation by MJT (Common) DMA Transfer Request Source Table 10.1.5 A-D Conversion Start Request by MJT Signal Name AD0TRG A-D Conversion Start Request Source Input event bus 2, input event bus 3, output event bus 3, TIN23 A-D Converter Can be input to A-D0 conversion start trigger 10-4 32182 Group User’s Manual (Rev.1.0) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus S TCLK0 (P124) TCLK0S IRQ9 clk clk clk IRQ2 0123 en en en en en en en en TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 TOP 7 udf IRQ2 F/F0 F/F1 IRQ2 TO0 (P110) TO1 (P111) TO2 (P112) TO3 (P113) TO4 (P114) TO5 (P115) TO6 (P116) TO7 (P117) udf udf IRQ2 F/F2 F/F3 TIN0 (P150) TIN0S DMA3,DMA commom PRS0 S clk clk clk udf IRQ2 udf IRQ2 F/F4 F/F5 IRQ1 BCLK/2 PRS1 PRS2 udf udf IRQ1 S S S S S clk clk S S IRQ6 F/F6 F/F7 udf clk clk clk en en en en/cap en/cap en/cap en/cap en/cap TOP 8 TOP 9 TOP 10 TIO 0 TIO 1 TIO 2 TIO 3 TIO 4 udf udf udf IRQ0 IRQ6 S S IRQ5 F/F8 F/F9 F/F10 F/F11 F/F12 F/F13 F/F14 F/F15 TO8 (P100) TO9 (P101) TO10 (P102) TO11 (P103) TO12 (P104) TO13 (P105) TO14 (P106) TO15 (P107) S S IRQ0 IRQ12 S S clk clk S clk S clk udf udf IRQ0 TIN3 (P153) TIN3S DMA1 S S IRQ0 udf udf udf S IRQ4 S S clk S S TCLK1 (P125) TCLK1S IRQ4 S S clk en/cap TIO 5 udf IRQ4 S F/F16 TO16 (P93) TCLK2 (P126) TCLK2S S S clk en/cap TIO 6 udf IRQ4 S F/F17 TO17 (P94) S S S S S S 3210 3210 clk en/cap TIO 7 udf DMA0 DMA common IRQ3 S F/F18 TO18 (P95) clk en/cap TIO 8 udf S IRQ3 F/F19 TO19 (P96) clk en/cap TIO 9 udf F/F20 TO20 (P97) 0123 PRS0-5 : Prescalers F/F : Output flip-flop S : Selector Notes: • IRQ0-18 denotes interrupt signals, of which the same number represents the same group of interrupts. • DMA0-9 and DMA common denote DMA request signals to the DMAC. • AD0TRG denotes trigger signal to the A-D0 converter. Figure 10.1.1 Block Diagram of MJT (1/3) 10-5 32182 Group User’s Manual (Rev.1.0) 10 Clock bus Input event bus 3210 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus 0123 TCLK3 (P127) TCLK3S S S clk cap3 TMS 0 cap2 cap1 cap0 ovf IRQ7 S S S S IRQ10 clk cap3 S TMS 1 cap2 cap1 cap0 ovf IRQ7 TIN16(P130) TIN16S IRQ10 TIN17(P131) TIN17S IRQ10 S TIN18 (P132) TIN18S DMA2 IRQ10 S TIN19 (P133) TIN19S DMA4 S BCLK/2 IRQ11 S TIN20S DMA5 IRQ11 clk cap3 S TML 0 (32-bit) cap2 cap1 cap0 TIN20 (P134) TIN21 (P135) TIN21S IRQ11 S TIN22 (P136) TIN22S IRQ11 S TIN23 (P137) TIN23S S (To A-D0 converter) AD0TRG (To A-D1 converter)AD1TRG BCLK/2 S S clk cap3 TML 1 (32-bit) cap2 cap1 cap0 S S AD0TRG (to A-D0 converter) S AD0TRG (to A-D0 converter) AD0TRG (to A-D0 converter) 3210 3210 0123 Figure 10.1.2 Block Diagram of MJT (2/3) 10-6 32182 Group User’s Manual (Rev.1.0) 10 Input event bus 3210 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus 0123 AD0 conversion completed TIO8_udf TIN0S S AD0 conversion completed TIO8_udf Software start S DMA0 udf end CAN0_S0/S15 TIN3S S Software start S DMA1 udf end CAN0_S1/S14 S TIN18S Software start S DMA2 udf end TIN0S S SIO0_TXD SIO1_RXD Software start S DMA3 udf end TIN19S SIO0_TXD S SIO0_RXD Software start S DMA4 udf end DMA0–4 interrupt TIN20S Software start S SIO2_RXD S DMA5 udf end SIO1_RXD S SIO1_TXD Software start S DMA6 udf end SIO3_TXD S SIO2_TXD Software start S DMA7 udf end S SIO3_RXD Software start S DMA8 udf end S SIO3_TXD Software start S DMA9 3210 udf end DMA5–9 interrupt 0123 Figure 10.1.3 Block Diagram of MJT (3/3) 10-7 32182 Group User’s Manual (Rev.1.0) 10 The common units of MJT include the following: MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2 Common Units of Multijunction Timers • Prescaler Unit • Clock Bus and Input/Output Event Bus Control Unit • Input Processing Control Unit • Output Flip-flop Control Unit • Interrupt Control Unit 10-8 32182 Group User’s Manual (Rev.1.0) 10 10.2.1 MJT Common Unit Register Map MJT Common Unit Register Map Address b0 H'0080 0200 H'0080 0202 H'0080 0204 (Use inhibited area) Prescaler Register 0 (PRS0) Prescaler Register 2 (PRS2) +0 address MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The table below shows a common unit register map of MJT. +1 address b7 b8 Clock Bus & Input Event Bus Control Register (CKIEBCR) Prescaler Register 1 (PRS1) Output Event Bus Control Register (OEBCR) (Use inhibited area) b15 See pages 10-14 10-10 10-10 10-15 | H'0080 0210 H'0080 0212 | H'0080 0218 H'0080 021A TCLK Input Processing Control Register (TCLKCR) TIN0–4 Input Processing Control Register (TIN04CR) (Use inhibited area) TIN12–19 Input Processing Control Register (TIN1219CR) TIN20–23, TIN30–33 Input Processing Control Register (TIN2023_3033CR) (Use inhibited area) F/F6–15 Source Select Register (FF615S) (Use inhibited area) F/F16–19 Source Select Register (FF1619S) F/F0–15 Protect Register (FF015P) F/F0–15 Data Register (FF015D) (Use inhibited area) F/F16–20 Protect Register (FF1620P) (Use inhibited area) F/F16–20 Data Register (FF1620D) (Use inhibited area) TOP0–5 Interrupt Request Status Register TOP0–5 Interrupt Request Mask Register (TOP05IST) (TOP05IMA) TOP6,7 Interrupt Request Mask & Status Register TOP8,9 Interrupt Request Mask & Status Register (TOP67IMS) (TOP89IMS) TIO0–3 Interrupt Request Mask & Status Register TIO4–7 Interrupt Request Mask & Status Register (TIO03IMS) (TIO47IMS) TIO8,9 Interrupt Request Mask & Status Register TMS0,1 Interrupt Request Mask & Status Register (TIO89IMS) (TMS01IMS) TIN0–2 Interrupt Request Mask & Status Register TIN3–6 Interrupt Request Mask & Status Register (TIN02IMS) (TIN36IMS) (Use inhibited area) TIN12–19 Interrupt Request Status Register (TIN1219IST) TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS) TIN12–19 Interrupt Request Mask Register (TIN1219IMA) (Use inhibited area) 10-18 10-19 10-20 10-20 | H'0080 0220 H'0080 0222 H'0080 0224 H'0080 0226 H'0080 0228 H'0080 022A 10-22 10-23 10-24 10-25 10-24 10-25 | H'0080 0230 H'0080 0232 H'0080 0234 H'0080 0236 H'0080 0238 H'0080 023A H'0080 023C H'0080 023E 10-30 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-42 10-9 32182 Group User’s Manual (Rev.1.0) 10 10.2.2 Prescaler Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The Prescalers PRS0–2 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS and TML) from the internal peripheral clock (BCLK) divided by 2 (10 MHz when f(BCLK) = 20 MHz). The values of prescaler registers are initialized to H’00 immediately after reset. When the set value of any prescaler register is rewritten, the prescaler starts operating with the new value at the same time it has underflowed. Values H’00 to H’FF can be set in the prescaler register. The prescaler’s divide-by ratio is given by the equation below: 1 Prescaler divide-by ratio = prescaler set value + 1 Prescaler Register 0 (PRS0) Prescaler Register 1 (PRS1) Prescaler Register 2 (PRS2) b0 b8 0 1 9 0 2 10 0 3 11 0 4 12 0 5 13 0 6 14 0 b7 b15 0 PRS0–PRS5 b 0–7 (8–15) Bit Name PRS0–PRS2 Prescaler Function Set the prescaler divide-by value R R W W Prescaler Registers 0–2 start counting immediately after reset. If the prescaler register is accessed for read during operation, the value written into it, not the current count, is read out. 10-10 32182 Group User’s Manual (Rev.1.0) 10 (1) Clock bus MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2.3 Clock Bus and Input/Output Event Bus Control Unit The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0–3. Each timer can use these clock bus signals as clock input signals. The table below lists the signals that can be fed into the clock bus. Table 10.2.1 Acceptable Clock Bus Signals Clock Bus 3 2 1 0 Acceptable Signal TCLK0 input Internal prescaler (PRS2) or TCLK3 input Internal prescaler (PRS1) Internal prescaler (PRS0) (2) Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0–3. Each timer can use these input event bus signals as enable (or capture) input. Furthermore, they can also be used as request signals to start A-D conversion or DMA transfer. The table below lists the signals that can be fed into the input event bus. Table 10.2.2 Connectable (Acceptable) Input Event Bus Signals Input Event Bus 3 2 1 0 Connectable (Acceptable) Signal (Note 1) TIN3 input, output event bus 2 or TIO7 underflow signal TIN0 input TIO6 underflow signal TIO5 underflow signal Note 1: For the destination (output) to which the input event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” (3) Output event bus The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0–3. Output event bus signals are connected to output flip-flops, and can also be connected to the A-D converter and DMAC. Furthermore, output event bus 2 can be connected to input event bus 3. The table below lists the signals that can be connected to the output event bus. Table 10.2.3 Connectable (Acceptable) Output Event Bus Signals Input Event Bus 3 2 1 0 Connectable (Acceptable) Signal (Note 1) TOP8, TIO3, TIO4 or TIO8 underflow signal TOP9 or TIO2 underflow signal TOP7 or TIO1 underflow signal TOP6 or TIO0 underflow signal Note 1: For the destination (output) to which the output event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” Note that the signals from each timer to the output event bus (and TIO5, 6 signals to the input event bus) are generated with the timing shown in Table 10.2.4, and not the timing at which signals are output from the timer to the output flip-flop. 10-11 32182 Group User’s Manual (Rev.1.0) 10 Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO(Note 1) Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML (16-bit measure input) (32-bit measure input) MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Table 10.2.4 Timing at Which Signals are Generated to the Output Event Bus by Each Timer Timing at which signals are generated to the output event bus When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows No signals generated No signals generated Note 1: TIO5–7 output an underflow signal to the input event bus. 10-12 32182 Group User’s Manual (Rev.1.0) 10 Clock bus 3210 3210 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Input event bus Output event bus 0123 TCLK0 (P124) TIN0 (P150) BCLK/2 TCLK0S clk clk clk clk en en en en TOP 6 TOP 7 TOP 8 TOP 9 udf udf udf udf TIN0S PRS0 PRS1 PRS2 TIO 0 TIN3 (P153) TIN3S TIO 1 TIO 2 TIO 3 TIO 4 udf udf udf udf udf S TIO 5 TCLK3 (P127) TCLK3S TIO 6 3210 3210 udf udf udf udf 0123 TIO 7 TIO 8 PRS0-2 : Prescaler S : Selector Figure 10.2.1 Conceptual Diagram of the Clock Bus and Input/Output Event Bus 10-13 32182 Group User’s Manual (Rev.1.0) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The Clock Bus and Input/Output Event Bus Control Unit has the following registers: • Clock Bus & Input Event Bus Control Register (CKIEBCR) • Output Event Bus Control Register (OEBCR) Clock Bus & Input Event Bus Control Register (CKIEBCR) b8 IEB3S 0 0 0 9 10 11 0 12 IEB1S 0 13 IEB0S 0 14 0 b15 CKB2S 0 IEB2S b 8, 9 Bit Name IEB3S Input event bus 3 input select bit Function 00: Select external input 3 (TIN3) 01: – ditto – 10: Select output event bus 2 11: Select TIO7 output 00: Select external input 0 (TIN0) 01: Select external input 2 (TIN2) (Note 1) 10: Select external input 4 (TIN4) (Note 1) 11: – ditto – (Note 1) 0: Select external input 5 (TIN5) (Note 1) 1: Select TIO6 output 0: Select external input 6 (TIN6) (Note 1) 1: Select TIO5 output R 0 0: Select prescaler 2 1: Select external clock 3 (TCLK3) R W 0 W R R W W 10, 11 IEB2S Input event bus 2 input select bit R W 12 13 14 15 IEB1S Input event bus 1 input select bit IEB0S Input event bus 0 input select bit No function assigned. Fix to "0". CKB2S Clock bus 2 input select bit R W Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function therefore has no effect. The CKIEBCR register is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus. 10-14 32182 Group User’s Manual (Rev.1.0) 10 Output Event Bus Control Register (OEBCR) b8 OEB3S 0 0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers b15 OEB0S 0 0 9 10 11 OEB2S 0 12 0 13 OEB1S 0 14 b 8, 9 Bit Name OEB3S Output event bus 3 input select bit Function 00: Select TOP8 output 01: Select TIO3 output 10: Select TIO4 output 11: Select TIO8 output 10 11 12 13 14 15 No function assigned. Fix to "0". OEB2S Output event bus 2 input select bit No function assigned. Fix to "0". OEB1S Output event bus 1 input select bit No function assigned. Fix to "0". OEB0S Output event bus 0 input select bit 0: Select TOP6 output 1: Select TIO0 output 0: Select TOP7 output 1: Select TIO1 output 0: Select TOP9 output 1: Select TIO2 output 0 R 0 R 0 R 0 W 0 W 0 W R R W W The OEBCR register is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus. 10.2.4 Input Processing Control Unit The Input Processing Control Unit processes TCLK and TIN input signals to the MJT. In TCLK input processing, it selects the source of TCLK signal, and for external input, it selects the active edge (rising or falling or both) or level (high or low) of the signal, at which to generate the clock signal supplied to the clock bus. In TIN input processing, the unit selects the active edge (rising or falling or both) or level (high or low) of the signal, at which to generate the enable, measure or count source signal for each timer or the signal supplied to each event bus. Following input processing registers are included: • TLCK Input Processing Control Register (TCLKCR) • TIN0–4 Input Processing Control Register (TIN04CR) • TIN12–19 Input Processing Control Register (TIN1219CR) • TIN20–23, TIN30–33 Input Processing Control Register (TIN2023_3033CR) 10-15 32182 Group User’s Manual (Rev.1.0) 10 Item BCLK/2 BCLK/2 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers (1) Functions of TCLK Input Processing Control Registers Function Count clock Rising edge TCLK Count clock Falling edge TCLK Count clock Both edges TCLK Count clock Low level TCLK BCLK/2 Count clock High level TCLK BCLK/2 Count clock 10-16 32182 Group User’s Manual (Rev.1.0) 10 Item Rising edge TIN MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers (2) Functions of TIN Input Processing Control Registers Function Internal edge signal Falling edge TIN Internal edge signal Both edges TIN Internal edge signal Low level TIN Prescaler output period or TCLK input period Internal edge signal High level TIN Prescaler output period or TCLK input period Internal edge signal 10-17 32182 Group User’s Manual (Rev.1.0) 10 TLCK Input Processing Control Register (TCLKCR) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 7 0 1 0 2 0 3 0 4 0 5 0 6 TCLK2S 0 8 0 9 0 10 TCLK1S 0 11 0 12 0 13 0 14 0 b15 0 TCLK3S TCLK0S b 0, 1 2, 3 Bit Name No function assigned. Fix to "0". TCLK3S TCLK3 input processing select bit 00: BCLK/2 01: Rising edge 10: Falling edge 11: Both edges Function R 0 R W 0 W 4 5–7 No function assigned. Fix to "0". TCLK2S TCLK2 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 0 R 0 W 8 9–11 No function assigned. Fix to "0". TCLK1S TCLK1 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 0 R 0 W 12,13 14,15 No function assigned. Fix to "0". TCLK0S TCLK0 input processing select bit 00: BCLK/2 01: Rising edge 10: Falling edge 11: Both edges110 0 R 0 W Note: • This register must always be accessed in halfwords. 10-18 32182 Group User’s Manual (Rev.1.0) 10 TIN0–4 Input Processing Control Register (TIN04CR) b0 1 2 TIN4S 0 0 0 0 0 0 3 4 5 6 TIN3S 0 0 7 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 8 9 10 11 TIN2S 0 0 0 0 0 12 13 TIN1S 0 0 14 b15 TIN0S 0 b 0 1–3 4 5–7 Bit Name No function assigned. Fix to "0". Fix to "0". No function assigned. Fix to "0". TIN3S TIN3 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level Function R 0 0 0 R W 0 0 0 W 8,9 10,11 12,13 14,15 No function assigned. Fix to "0". Fix to "0". Fix to "0". TIN0S TIN0 input processing select bit 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges 0 0 0 R 0 0 0 W Note: • This register must always be accessed in halfwords. 10-19 32182 Group User’s Manual (Rev.1.0) 10 b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 8 0 TIN12–19 Input Processing Control Register (TIN1219CR) 1 0 2 0 3 TIN18S 0 4 0 5 TIN17S 0 6 0 7 TIN16S 0 9 TIN15S 0 10 0 11 0 12 0 13 0 14 0 b15 0 TIN19S TIN14S TIN13S TIN12S b 0, 1 2, 3 4, 5 6, 7 8-15 Bit Name TIN19S (TIN19 input processing select bit) TIN18S (TIN18 input processing select bit) TIN17S (TIN17 input processing select bit) TIN16S (TIN16 input processing select bit) Fix to "0". Function 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges 0 0 R R W W Note: • This register must always be accessed in halfwords. TIN20–23, TIN30–33 Input Processing Control Register (TIN2023_3033CR) b0 0 11 0 1 0 2 0 3 TIN32S 0 4 0 5 TIN31S 0 6 0 7 TIN30S 0 8 0 9 TIN23S 0 10 0 12 0 13 0 14 0 b15 0 TIN33S TIN22S TIN21S TIN20S b 0-7 8, 9 10, 11 12, 13 14, 15 Bit Name Fix to "0". TIN23S (TIN23 input processing select bit) TIN22S (TIN22 input processing select bit) TIN21S (TIN21 input processing select bit) TIN20S (TIN20 input processing select bit) 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Function R 0 R W 0 W Note: • This register must always be accessed in halfwords. 10-20 32182 Group User’s Manual (Rev.1.0) 10 10.2.5 Output Flip-flop Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control registers are included: • F/F6–15 Source Select Register (FF615S) • F/F16–19 Source Select Register (FF1619S) • F/F0–15 Protect Register (FF015P) • F/F16–20 Protect Register (FF1620P) • F/F0–15 Data Register (FF015D) • F/F16–20 Data Register (FF1620D) The timing at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5. (Note that this timing is different from one at which signals are output from the timer to the output event bus.) 10.2.5 Timing at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML (16-bit measure input) (32-bit measure input) Timing at which signals are generated to the output flip-flop When count is enabled or underflows When counter underflows When count is enabled or underflows When counter underflows When counter underflows When counter underflows When count is enabled or underflows When count is enabled or underflows When counter underflows When count is enabled or underflows No signals generated No signals generated F/F source selection (FSn) TOP/TIO Output event bus 0 Output event bus 1 Output event bus 2 Output event bus 3 Data bus WR F/F protect (FPn) Data bus F/F Port operation mode register (PnMOD) F/F Internal edge signal F/Fn output data (FDn) F/F Output control (ON/OFF) TOn Figure 10.2.2 Configuration of the F/F Output Circuit Table 10-21 32182 Group User’s Manual (Rev.1.0) 10 F/F6–15 Source Select Register (FF615S) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 6 FS12 0 1 0 2 0 3 FS15 0 4 FS14 0 5 FS13 0 7 FS11 0 8 FS10 0 9 0 10 FS9 0 11 0 12 FS8 0 13 0 14 FS7 0 b15 FS6 0 b 0–2 3 4 5 6 7 8, 9 Bit Name No function assigned. Fix to "0". FS15 F/F15 source select bit FS14 F/F14 source select bit FS13 F/F13 source select bit FS12 F/F12 source select bit FS11 F/F11 source select bit FS10 F/F10 source select bit 0: TIO4 output 1: Output event bus 0 0: TIO3 output 1: Output event bus 0 0: TIO2 output 1: Output event bus 3 0: TIO1 output 1: Output event bus 2 0: TIO0 output 1: Output event bus 1 00: TOP10 output 01: TOP10 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS9 F/F9 source select bit 00: 01: 10: 11: 00: 01: 10: 11: TOP9 output TOP9 output Output event bus 0 Output event bus 1 TOP8 output Output event bus 0 Output event bus 1 Output event bus 2 R W Function R 0 R R R R R R W 0 W W W W W W 12, 13 FS8 F/F8 source select bit R W 14 15 FS7 F/F7 source select bit FS6 F/F6 source select bit 0: TOP7 output 1: Output event bus 0 0: TOP6 output 1: Output event bus 1 R R W W Note: • This register must always be accessed in halfwords. 10-22 32182 Group User’s Manual (Rev.1.0) 10 F/F16–19 Source Select Register (FF1619S) b8 FS19 0 0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers b15 FS16 0 0 0 9 10 FS18 11 0 12 FS17 0 13 14 b 8, 9 Bit Name FS19 F/F19 source select bit Function 00: TIO8 output 01: TIO8 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS18 F/F18 source select bit 00: 01: 10: 11: 00: 01: 10: 11: 00: 01: 10: 11: TIO7 output TIO7 output Output event bus 0 Output event bus 1 TIO6 output TIO6 output Output event bus 0 Output event bus 1 TIO5 output Output event bus 0 Output event bus 1 Output event bus 3 R W R R W W 12, 13 FS17 F/F17 source select bit R W 14, 15 FS16 F/F16 source select bit R W These registers select the signal source for each output F/F (flip-flop). This signal source can be chosen to be a signal from the internal output bus or an underflow output from each timer. 10-23 32182 Group User’s Manual (Rev.1.0) 10 F/F0–15 Protect Register (FF015P) b0 FP15 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 5 FP10 0 1 FP14 0 2 FP13 0 3 FP12 0 4 FP11 0 6 FP9 0 7 FP8 0 8 FP7 0 9 FP6 0 10 FP5 0 11 FP4 0 12 FP3 0 13 FP2 0 14 FP1 0 b15 FP0 0 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FP15 (F/F15 protect bit) FP14 (F/F14 protect bit) FP13 (F/F13 protect bit) FP12 (F/F12 protect bit) FP11 (F/F11 protect bit) FP10 (F/F10 protect bit) FP9 (F/F9 protect bit) FP8 (F/F8 protect bit) FP7 (F/F7 protect bit) FP6 (F/F6 protect bit) FP5 (F/F5 protect bit) FP4 (F/F4 protect bit) FP3 (F/F3 protect bit) FP2 (F/F2 protect bit) FP1 (F/F1 protect bit) FP0 (F/F0 protect bit) Function 0: Enable write to F/F output bit 1: Disable write to F/F output bit R R W W Note: • This register must always be accessed in halfwords. F/F16–20 Protect Register (FF1620P) b8 0 14 FP17 0 9 0 10 0 11 FP20 0 12 FP19 0 13 FP18 0 b15 FP16 0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". FP20 (F/F20 protect bit) FP19 (F/F19 protect bit) FP18 (F/F18 protect bit) FP17 (F/F17 protect bit) FP16 (F/F16 protect bit) 0: Enable write to F/F output bit 1: Disable write to F/F output bit Function R 0 R W 0 W This register enables or disables write to each output F/F (flip-flop). If write to any output F/F is disabled, writing to the corresponding F/F data register has no effect. 10-24 32182 Group User’s Manual (Rev.1.0) 10 F/F0–15 Data Register (FF015D) b0 FD15 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 5 FD10 0 1 FD14 0 2 FD13 0 3 FD12 0 4 FD11 0 6 FD9 0 7 FD8 0 8 FD7 0 9 FD6 0 10 FD5 0 11 FD4 0 12 FD3 0 13 FD2 0 14 FD1 0 b15 FD0 0 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FD15 (F/F15 output data bit) FD14 (F/F14 output data bit) FD13 (F/F13 output data bit) FD12 (F/F12 output data bit) FD11 (F/F11 output data bit) FD10 (F/F10 output data bit) FD9 (F/F9 output data bit) FD8 (F/F8 output data bit) FD7 (F/F7 output data bit) FD6 (F/F6 output data bit) FD5 (F/F5 output data bit) FD4 (F/F4 output data bit) FD3 (F/F3 output data bit) FD2 (F/F2 output data bit) FD1 (F/F1 output data bit) FD0 (F/F0 output data bit) Function 0: F/F output data = 0 1: F/F output data = 1 R R W W Note: • This register must always be accessed in halfwords. F/F16–20 Data Register (FF1620D) b8 0 14 FD17 0 9 0 10 0 11 FD20 0 12 FD19 0 13 FD18 0 b15 FD16 0 b 8–10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". FD20 (F/F20 output data bit) FD19 (F/F19 output data bit) FD18 (F/F18 output data bit) FD17 (F/F17 output data bit) FD16 (F/F16 output data bit) 0: F/F output data = 0 1: F/F output data = 1 Function R 0 R W 0 W This register is used to set the data for each output F/F (flip-flop). Although the F/F outputs normally change state depending on timer outputs, the F/F outputs can be set to 1 or cleared to 0 as necessary by writing to this register. The F/F data register can only be operated on when the F/F protect register described above is enabled for write. 10-25 32182 Group User’s Manual (Rev.1.0) 10 10.2.6 Interrupt Control Unit MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer. Following timer interrupt control registers are provided for each timer: • TOP0–5 Interrupt Request Status Register (TOP05IST) • TOP0–5 Interrupt Request Mask Register (TOP05IMA) • TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS) • TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS) • TIO0–3 Interrupt Request Mask & Status Register (TIO03IMS) • TIO4–7 Interrupt Request Mask & Status Register (TIO47IMS) • TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS) • TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS) • TIN0–2 Interrupt Request Mask & Status Register (TIN02IMS) • TIN3–6 Interrupt Request Mask & Status Register (TIN36IMS) • TIN12–19 Interrupt Request Status Register (TIN1219IST) • TIN12–19 Interrupt Request Mask Register (TIN1219IMA) • TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS) For interrupts which have only one interrupt request source in the interrupt vector table, no interrupt control registers are included in the timer, and the interrupt request status flags are automatically managed within the Interrupt Controller. For details, see Chapter 5, “Interrupt Controller.” • TOP10 TOP10 Output Interrupt Request (IRQ5) 10-26 32182 Group User’s Manual (Rev.1.0) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and cannot be accessed for write. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupts within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests. Group interrupt Timer or TIN input interrupt request Set Data = 0 clear Interrupt request status Data bus F/F F/F Interrupt request enabled To the Interrupt Controller Figure 10.2.3 Interrupt Request Status and Mask Registers 10-27 32182 Group User’s Manual (Rev.1.0) 10 Example for clearing interrupt request status MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Interrupt request status b4 5 0 6 0 b7 0 Initial state 0 Interrupt request Event occurs on bit 6 0 0 1 0 Event occurs on bit 4 Write to the interrupt request status b4 1 5 1 6 0 b7 1 1 0 1 0 1 0 0 0 Only bit 6 cleared Bit 4 data retained Program example • To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */ Interrupt request status b4 5 0 6 1 b7 0 Event occurs on bit 6 0 Read 0 0 1 0 Event occurs on bit 4 1 0 1 0 Clear bit 6 (ANDing with 1101) 0 0 0 0 0 0 0 0 Write Only bit 6 cleared Bit 4 also cleared Figure 10.2.4 Example for Clearing Interrupt Request Status 10-28 32182 Group User’s Manual (Rev.1.0) 10 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The table below shows the relationship between the interrupt request signals generated by multijunction timers and the interrupt sources input to the Interrupt Controller (ICU). Table 10.2.6 Interrupt Request Signals Generated by MJT Signal Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 Generated by TIO0, TIO1, TIO2, TIO3 TOP6, TOP7 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 TIO8, TIO9 TIO4, TIO5, TIO6, TIO7 TOP8, TOP9 TMS0, TMS1 TIN0 TIN16, TIN17, TIN18, TIN19 TIN20, TIN21, TIN22, TIN23 TIN3 Interrupt Request Source (Note 1) TIO0–3 output interrupt TOP6, 7 output interrupt TOP0–5 output interrupt TIO8, 9 output interrupt TIO4–7 output interrupt TOP8, 9 output interrupt TMS0, 1 output interrupt TIN0–2 input interrupt TIN12–19 input interrupt TIN20–29 input interrupt TIN3–6 input interrupt No. of ICU Input Sources 4 2 6 2 4 2 2 1 4 4 1 Note 1: See Chapter 5, “Interrupt Controller (ICU).” Note: • TOP10 has only one interrupt source in each interrupt group, so that their status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.) 10-29 32182 Group User’s Manual (Rev.1.0) 10 TOP0–5 Interrupt Request Status Register (TOP05IST) b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPIS0 b 0, 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". TOPIS5 (TOP5 interrupt request status bit) TOPIS4 (TOP4 interrupt request status bit) TOPIS3 (TOP3 interrupt request status bit) TOPIS2 (TOP2 interrupt request status bit) TOPIS1 (TOP1 interrupt request status bit) TOPIS0 (TOP0 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TOP0–5 Interrupt Request Mask Register (TOP05IMA) b8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 TOPIM5 TOPIM4 TOPIM3 TOPIM2 TOPIM1 TOPIM0 b 8, 9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". TOPIM5 (TOP5 interrupt request mask bit) TOPIM4 (TOP4 interrupt request mask bit) TOPIM3 (TOP3 interrupt request mask bit) TOPIM2 (TOP2 interrupt request mask bit) TOPIM1 (TOP1 interrupt request mask bit) TOPIM0 (TOP0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W 10-30 32182 Group User’s Manual (Rev.1.0) 10 TOP05IST TOP5udf Data bus b2 b10 TOP4udf b3 b11 TOP3udf b4 b12 TOP2udf b5 b13 TOP1udf b6 b14 TOP0udf b7 b15 TOPIS0 F/F TOPIM0 F/F TOPIS1 F/F TOPIM1 F/F TOPIS2 F/F TOPIM2 F/F TOPIS3 F/F TOPIM3 F/F TOPIS4 F/F TOPIM4 F/F TOPIS5 F/F TOPIM5 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 6-source inputs TOP0-5 output interrupt request IRQ2 (Level) Figure 10.2.5 Block Diagram of TOP0–5 Output Interrupt Request 10-31 32182 Group User’s Manual (Rev.1.0) 10 b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS) 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 TOPIS7 TOPIS6 TOPIM7 TOPIM6 b 0, 1 2 3 4, 5 6 7 Bit Name No function assigned. Fix to "0". TOPIS7 (TOP7 interrupt request status bit) TOPIS6 (TOP6 interrupt request status bit) No function assigned. Fix to "0". TOPIM7 (TOP7 interrupt request mask bit) TOPIM6 (TOP6 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0: Interrupt not requested 1: Interrupt requested 0 R 0 W Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TOP67IMS TOP9udf Data bus TOPIS9 b10 b14 TOP8udf b11 b15 TOPIS8 F/F TOPIM8 F/F F/F TOPIM9 F/F (Level) 2-source inputs TOP8,9 output interrupt request IRQ6 Figure 10.2.7 Block Diagram of TOP8,9 Output Interrupt Request 10-33 32182 Group User’s Manual (Rev.1.0) 10 b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIO0–3 Interrupt Request Mask & Status Register (TIO03IMS) 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 TIOIS3 TIOIS2 TIOIS1 TIOIS0 TIOIM3 TIOIM2 TIOIM1 TIOIM0 b 0 1 2 3 4 5 6 7 Bit Name TIOIS3 (TIO3 interrupt request status bit) TIOIS2 (TIO2 interrupt request status bit) TIOIS1 (TIO1 interrupt request status bit) TIOIS0 (TIO0 interrupt request status bit) TIOIM3 (TIO3 interrupt request mask bit) TIOIM2 (TIO2 interrupt request mask bit) TIOIM1 (TIO1 interrupt request mask bit) TIOIM0 (TIO0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIO03IMS TIO7udf Data bus b8 b12 TIO6udf b9 b13 TIO5udf b10 b14 TIO4udf b11 b15 TIOIS4 F/F TIOIM4 F/F TIOIS5 F/F TIOIM5 F/F TIOIS6 F/F TIOIM6 F/F TIOIS7 F/F TIOIM7 F/F 4-source inputs TIO4–7 output interrupt request IRQ4 (Level) Figure 10.2.9 Block Diagram of TIO4–7 Output Interrupt Request 10-35 32182 Group User’s Manual (Rev.1.0) 10 b0 0 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 TIOIS9 TIOIS8 TIOIM9 TIOIM8 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS) b 0, 1 2 3 4, 5 6 7 Bit Name No function assigned. Fix to "0". TIOIS9 (TIO9 interrupt request status bit) TIOIS8 (TIO8 interrupt request status bit) No function assigned. Fix to "0". TIOIM9 (TIO9 interrupt request mask bit) TIOIM8 (TIO8 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0: Interrupt not requested 1: Interrupt requested 0 R 0 W Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIO89IMS TMS1ovf Data bus b10 b14 TMS0ovf TMSIS0 b11 b15 F/F TMSIM0 F/F TMSIS1 F/F TMSIM1 F/F (Level) 2-source inputs TMS0, 1 output interrupt request IRQ7 Figure 10.2.11 Block Diagram of TMS0,1 Output Interrupt Request 10-37 32182 Group User’s Manual (Rev.1.0) 10 b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN0–2 Interrupt Request Mask & Status Register (TIN02IMS) 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 TINIS2 TINIS1 TINIS0 TINIM2 TINIM1 TINIM0 b 0 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". TINIS2 (TIN2 interrupt request status bit) (Note 2) TINIS1 (TIN1 interrupt request status bit) (Note 2) TINIS0 (TIN0 interrupt request status bit) No function assigned. Fix to "0". TINIM2 (TIN2 interrupt request mask bit) (Note 2) TINIM1 (TIN1 interrupt request mask bit) (Note 2) TINIM0 (TIN0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0 R 0 W 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note 2: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function therefore has no effect. TIN02IMS Data bus TIN6edge (Note 1) b8 b12 TIN5edge (Note 1) b9 b13 TIN4edge (Note 1) b10 b14 TIN3edge b11 b15 TINIS3 F/F TINIM3 F/F TINIS6 F/F TINIM6 F/F 4-source inputs TIN3–6 input interrupt request IRQ12 (Level) TINIS5 F/F TINIM5 F/F TINIS4 F/F TINIM4 F/F Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function therefore has no effect. Figure 10.2.13 Block Diagram of TIN3–6 Input Interrupt Request 10-39 32182 Group User’s Manual (Rev.1.0) 10 b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN12–19 Interrupt Request Status Register (TIN1219IST) 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 TINIS19 TINIS18 TINIS17 TINIS16 TINIS15 TINIS14 TINIS13 TINIS12 b 0 1 2 3 4 5 6 7 Bit Name TINIS19 (TIN19 interrupt request status bit) TINIS18 (TIN18 interrupt request status bit) TINIS17 (TIN17 interrupt request status bit) TINIS16 (TIN16 interrupt request status bit) TINIS15 (TIN15 interrupt request status bit) (Note 2) TINIS14 (TIN14 interrupt request status bit) (Note 2) TINIS13 (TIN13 interrupt request status bit) (Note 2) TINIS12 (TIN12 interrupt request status bit) (Note 2) Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note 2: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function therefore has no effect. TIN12–19 Interrupt Request Mask Register (TIN1219IMA) b8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 TINIM19 TINIM18 TINIM17 TINIM16 TINIM15 TINIM14 TINIM13 TINIM12 b 8 9 10 11 12 13 14 15 Bit Name TINIM19 (TIN19 interrupt request mask bit) TINIM18 (TIN18 interrupt request mask bit) TINIM17 (TIN17 interrupt request mask bit) TINIM16 (TIN16 interrupt request mask bit) TINIM15 (TIN15 interrupt request mask bit) (Note 1) TINIM14 (TIN14 interrupt request mask bit) (Note 1) TINIM13 (TIN13 interrupt request mask bit) (Note 1) TINIM12 (TIN12 interrupt request mask bit) (Note 1) Function 0: Enable interrupt request 1: Mask (disable) interrupt request R R W W Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function therefore has no effect. 10-40 32182 Group User’s Manual (Rev.1.0) 10 TIN1219IST TIN19edge Data bus b0 b8 TIN18edge TINIS18 b1 b9 TIN17edge b2 b10 TIN16edge b3 b11 TINIS16 F/F TINIM16 F/F TINIS17 F/F TINIM17 F/F F/F TINIM18 F/F TINIS19 F/F TINIM19 F/F MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 8-source inputs TIN12–19 input interrupt request IRQ10 (Level) TIN15edge (Note 1) TINIS15 b4 F/F TINIM15 b12 TIN14edge (Note 1) b5 b13 TIN13edge (Note 1) b6 b14 F/F TINIS14 F/F TINIM14 F/F TINIS13 F/F TINIM13 F/F TIN12edge (Note 1) TINIS12 b7 F/F b15 TINIM12 F/F Note 1: Although the 32180 has pins for these functions, the 32182 does not have corresponding pins and the selected function therefore has no effect. Figure 10.2.14 Block Diagram of TIN12–19 Input Interrupt Request 10-41 32182 Group User’s Manual (Rev.1.0) 10 b0 0 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS) 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20 b 0 1 2 3 4 5 6 7 Bit Name TINIS23 (TIN23 interrupt request status bit) TINIS22 (TIN22 interrupt request status bit) TINIS21 (TIN21 interrupt request status bit) TINIS20 (TIN20 interrupt request status bit) TINIM23 (TIN23 interrupt request mask bit) TINIM22 (TIN22 interrupt request mask bit) TINIM21 (TIN21 interrupt request mask bit) TINIM20 (TIN20 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN2023IMS VIN, then the comparate result flag = 1 4. The comparate operation is stopped after storing the comparison result. The comparison result is stored in the A-D Comparate Data Register (AD0CMP)’s corresponding bit. Note 1: The comparison voltage, Vref (the voltage fed from the D-A Converter into the comparator), is determined according to changes of the A-D Successive Approximation Register content. Shown below are the equations used to calculate the comparison voltage, Vref. • If the A-D Successive Approximation Register content = 0 Vref [V] = 0 • If the A-D Successive Approximation Register content = 1 to 1,023 Vref [V] = (reference voltage VREF / 1,024) x (A-D Successive Approximation Register content – 0.5) 11-33 32182 Group User's Manual (Rev.1.0) 11 A-D Converter 11.3 Functional Description of A-D Converter 11.3.4 Calculating the A-D Conversion Time The A-D conversion time is expressed by the sum of dummy cycle time and actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. 1. Start dummy time A time from when the CPU executed the A-D conversion start instruction to when the A-D Converter starts A-D conversion 2. A-D conversion execution cycle time If sample-and-hold is enabled, the sampling time is included in this execution cycle time. 3. Comparate execution cycle time 4. End dummy time A time from when the A-D Converter has finished A-D conversion to when the CPU can stably read out the conversion result from the A-D data register. 5. Scan to scan dummy time A time during single-shot or continuous scan mode from when the A-D Converter has finished A-D conversion on a channel to when it starts A-D conversion on the next channel. The equation to calculate the A-D conversion time is as follows: A-D conversion time = Start dummy time + Execution cycle time (+ Scan to scan dummy time + Execution cycle time + Scan to scan dummy time + Execution cycle time + Scan to scan dummy time .... + Execution cycle time) + End dummy time Note: • Enclosed in ( ) are the conversion time required for the second and subsequent channels to be converted in scan mode. (1) Calculating the conversion time during A-D conversion mode The following schematically shows the method for calculating the conversion time during A-D conversion mode. A-D conversion Convert operation start trigger starts Transferred to the A-D data register Completed Start dummy Execution cycle End dummy (Channel 0) Start dummy Execution cycle Scan to scan dummy (Channel 1) Execution cycle (Last channel) Scan to scan dummy Execution cycle End dummy Figure 11.3.3 Conceptual Diagram of A-D Conversion Time 11-34 32182 Group User's Manual (Rev.1.0) 11 Conversion speed Slow mode Fast mode Normal speed Double speed Normal speed Double speed 4 4 4 4 294 168 126 84 A-D Converter 11.3 Functional Description of A-D Converter Unit: BCLK End dummy 1 1 1 1 Scan to scan dummy (Note 2) 4 4 4 4 Table 11.3.1 Conversion Clock Periods in A-D Conversion Mode Start dummy (Note 1) Execution cycle Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan operation, execution time per channel is added. (2) Calculating the conversion time when sample-and-hold is enabled The following schematically shows the method for calculating the conversion time when the sample-and-hold function is enabled. A-D conversion start trigger Convert operation starts Execution cycle Completed Start dummy Sampling time End dummy Figure 11.3.4 Conceptual Diagram of A-D Conversion Time when Sample-and-Hold is Enabled Table 11.3.2 Conversion Clock Periods during Normal Sample-and-Hold Mode Conversion speed Slow mode Fast mode Normal speed Double speed Normal speed Double speed Start dummy (Note 1) Execution cycle 4 4 4 4 294 168 126 84 End dummy 1 1 1 1 4 4 4 4 Unit: BCLK Scan to scan dummy (Note 2) Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan operation, execution time per channel is added. Table 11.3.3 Conversion Clock Periods during Fast Sample-and-Hold Mode Conversion speed Slow mode Fast mode Normal speed Double speed Normal speed Double speed Start dummy (Note 1) Execution cycle 4 4 4 4 186 96 90 48 End dummy 1 1 1 1 4 4 4 4 Unit: BCLK Scan to scan dummy (Note 2) Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan operation, execution time per channel is added. 11-35 32182 Group User's Manual (Rev.1.0) 11 A-D Converter 11.3 Functional Description of A-D Converter (3) Calculating the conversion time during comparator mode The following schematically shows the method for calculating the conversion time during comparator mode. A-D conversion Convert operation starts start trigger Transferred to the comparate data register Completed Start dummy Execution cycle End dummy Figure 11.3.5 Conceptual Diagram of A-D Conversion Time during Comparator Mode Table 11.3.4 Conversion Clock Periods during Comparator Mode Conversion speed Slow mode Fast mode Normal speed Double speed Normal speed Double speed Start dummy 4 4 4 4 Execution cycle 42 24 18 12 End dummy 1 1 1 1 Unit: BCLK (4) A-D conversion time A total A-D conversion time in various modes are shown in the table below. Table 11.3.5 A-D Conversion Time (Total Time) Conversion start method Software and hardware triggers (Note 2) Slow Mode Conversion speed Conversion mode (Note 1) Conversion time 299 (298 × n)+1 47 173 (172 × n)+1 29 131 (130 × n)+1 23 89 (88 × n)+1 17 Unit: BCLK When fast sampleand-hold enabled 191 (190 × n)+1 47 101 (100 × n)+1 29 95 (94 × n)+1 23 53 (52 × n)+1 17 Normal speed Single mode n-channel single-shot scan/ continuous scan mode Comparator mode Double speed Single mode n-channel single-shot scan/ continuous scan mode Comparator mode Normal speed Single mode n-channel single-shot scan/ continuous scan mode Fast Mode Comparator mode Double speed Single mode n-channel single-shot scan/ continuous scan mode Comparator mode Note 1: For single mode and comparator mode, this indicates an A-D conversion or comparate time per channel. For singleshot and continuous scan modes, this indicates an A-D conversion time per scan loop. Note 2: This indicates a time from when a register write cycle has finished to when an A-D conversion completion interrupt request is generated, or a time from when an event bus or other MJT event has occurred to when an A-D conversion completion interrupt request is generated. 11-36 32182 Group User's Manual (Rev.1.0) 11 11.3.5 Accuracy of A-D Conversion A-D Converter 11.3 Functional Description of A-D Converter The accuracy of the A-D Converter is indicated by an absolute accuracy. The absolute accuracy refers to a difference expressed by LSB between the output code obtained by A-D converting the analog input voltages and the output code expected for an A-D converter with ideal characteristics. The analog input voltages used during accuracy measurement are the midpoint values of the voltage width in which an A-D converter with ideal characteristics produces the same output code. If VREF = 5.12 V, for example, the width of 1 LSB for a 10-bit A-D converter is 5 mV, so that 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV and so on are selected as midpoints of the analog input voltage. If an A-D converter is said to have the absolute accuracy of ±2 LSB, it means that if the input voltage is 25 mV, for example, the output code expected for an A-D converter with ideal characteristics is H’005, and the actual AD conversion result is in the range of H’003 to H’007. Note that the absolute accuracy includes zero and fullscale errors. When actually using the A-D Converter, the analog input voltages are in the range of AVSS to VREF. Note, however, that low VREF voltages result in a poor resolution. Note also that output codes for the analog input voltages from VREF to AVCC are always H’3FF. → A-D conversion result (hexadecimal) H'3FF H'3FE Ideal A-D conversion characteristics H'003 H'002 A-D conversion characteristics with infinite resolution H'001 H'000 0 VREF ×1 1024 VREF ×2 1024 VREF ×3 1024 VREF × 1023 1024 VREF × 1022 1024 VREF × 1024 1024 → Analog input voltage [V] Figure 11.3.6 Ideal A-D Conversion Characteristics Relative to the 10-bit A-D Converter’s Analog Input Voltages 11-37 32182 Group User's Manual (Rev.1.0) 11 → Output code (hexadecimal) A-D Converter 11.3 Functional Description of A-D Converter H'00B Ideal A-D conversion characteristics H'00A H'009 H'008 H'007 H'006 H'005 H'004 H'003 H'002 H'001 H'000 0 5 10 15 20 25 30 35 40 45 50 55 A-D conversion characteristics with infinite resolution +2 LSB -2 LSB → Analog input voltage [mV] Figure 11.3.7 Absolute Accuracy of A-D Converter 11-38 32182 Group User's Manual (Rev.1.0) 11 11.4 Inflow Current Bypass Circuit A-D Converter 11.4 Inflow Current Bypass Circuit If when the A-D Converter is A-D converting a selected analog input an overvoltage exceeding the converter’s absolute maximum rating is applied to any unselected analog input, the selector for the unselected analog input is inadvertently turned on by that overvoltage. This causes current to leak to the selected analog input, and the accuracy of the A-D conversion result is thereby deteriorated. The Inflow Current Bypass Circuit fixes the internal signals of unselected analog inputs to the GND level, so that when an overvoltage is applied, this circuit lets the current flow into the GND and prevents it from leaking to the selected analog input. That way, the accuracy of the A-D conversion result is prevented from being deteriorated by extreme voltages. This circuit is always active while the A-D Converter is operating, and does not need to be controlled in software. OFF Unselected channel Fixed to GND level ON OFF To the internal logic of the A-D Converter ON Selected channel External input latched into OFF ON Assist circuit Figure 11.4.1 Configuration of the Inflow Current Bypass Circuit VCCE + 0.7 V or more Leakage current generated Unselected channel OFF Leakage current generated ON Unaffected by leakage To the internal logic of the A-D Converter OFF Sensor input Selected channel ON ON OFF Assist circuit Figure 11.4.2 Example of an Inflow Current Bypass Circuit where VCCE + 0.7 V or More is Applied 11-39 32182 Group User's Manual (Rev.1.0) 11 Leakage current generated Unselected channel OFF Leakage current generated ON OFF A-D Converter 11.4 Inflow Current Bypass Circuit Unaffected by leakage GND - 0.7V or less Sensor input Selected channel To the internal logic of the A-D Converter ON ON OFF Assist circuit Figure 11.4.3 Example of an Inflow Current Bypass Circuit where GND – 0.7 V or Less is Applied Table 11.4.1 Accuracy Errors (Actual Performance Values) when Current is Injected into AD0IN0 Accuracy error on overcurrent injected ports (Unit: LSB) Analog input pin AD0IN0 Injection 10mA current (Note 1) 9mA 8mA 7mA 6mA 5mA 4mA 3mA 2mA 1mA 0mA -1mA -2mA -3mA -4mA -5mA -6mA -7mA -8mA -9mA -10mA AD0IN1 0 0 0 0 0 0 0 0 0 0 0 0 -1 -1 -1 -2 -3 -3 -3 -4 -5 AD0IN2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1 -1 -1 -1 -1 -1 AD0IN3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0IN4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0IN5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0IN6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0IN7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0IN8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0IN9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0IN10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD0IN11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1: The conversion accuracy is not affected unless the injection current is greater than 1 mA. 11-40 32182 Group User's Manual (Rev.1.0) 11 • Forcible termination during scan operation A-D Converter 11.5 Precautions on Using A-D Converter 11.5 Precautions on Using A-D Converter If A-D conversion is forcibly terminated by setting the A-D conversion stop bit (AD0CSTP) to "1" during scan mode operation and the A-D data register for the channel that was in the middle of conversion is accessed for read, the read value shows the last conversion result that had been transferred to the data register before the conversion was forcibly terminated. • Modification of the A-D converter related registers If the content of any register—A-D Conversion Interrupt Control Register, Single or Scan Mode Registers or A-D Successive Approximation Register, except the A-D conversion stop bit—is modified in the middle of A-D conversion, the conversion result cannot be guaranteed. Therefore, do not modify the contents of these registers while AD conversion is in progress, or be sure to restart A-D conversion if register contents have been modified. • Handling of analog input signals When using the A-D Converter with its sample-and-hold function disabled, make sure the analog input level is fixed during A-D conversion. • A-D conversion completed bit read timing To read the A-D conversion completed bit (Single Mode Register 0 bit 5 or Scan Mode Register 0 bit 5) immediately after A-D conversion has started, be sure to adjust the timing 2 BCLK periods by, for example, inserting a NOP instruction before read. • Regarding the analog input pins Figure 11.5.1 shows the internal equivalent circuit of the A-D Converter’s analog input part. To obtain accurate A-D conversion results, make sure the internal capacitor C2 of the A-D conversion circuit is charged up within a predetermined time (sampling time). To meet this sampling time requirement, it is recommended that a stabilizing capacitor C1 be connected external to the chip. The method for determining the necessary value of this external stabilizing capacitor with respect to the output impedance of an analog output device is described below. Also, an explanation is made of the case where the output impedance of an analog output device is low and the external stabilizing capacitor C1 is unnecessary. • Rated value of the absolute accuracy The rated value of the absolute accuracy is the actual performance value of the microcomputer alone, with influences of the power supply wiring and noise on the board not taken into account. When designing the application system, use caution for the board layout by, for example, separating the analog circuit power supply and ground (AVCC, AVSS and VREF) from those of the digital circuit and incorporating measures to prevent the analog input pins from being affected by noise, etc. from other digital signals. Inside the microcomputer 10-bit A-D Successive Approximation Register (ADiSAR) VREF Analog output device 10-bit D-A Converter V2 C2 ADIN n R1 E i→ C1 i1 ↓ i2→ Cin R2 Selector Comparator C1 : parasitic capacitance of the board R2 : parasitic resistance of the + stabilizing capacitance selector (1-2 KΩ) R1 : resistance of analog output device C2 : comparator capacitance (approx. 2.9 pF) Cin : input pin capacitance (approx. 10 pF) VREF : analog reference voltage V2 : voltage across C2 E : voltage of analog output device Figure 11.5.1 Internal Equivalent Circuit of the Analog Input Part 11-41 32182 Group User's Manual (Rev.1.0) 11 A-D Converter 11.5 Precautions on Using A-D Converter (a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recommended) Assuming the R1 in Figure 11.5.1 is infinitely large and that the current necessary to charge the internal capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance division of C1 and C2 is to be within 0.1 LSB, then what amount of capacitance C1 should have. For a 10-bit A-D Converter where VREF is 5.12 V, 1 LSB determination voltage = 5.12 V / 1,024 = 5 mV. The potential fluctuation of 0.1 LSB means a 0.5 mV fluctuation. The relationship between the capacitance division of C1 and C2 and the potential fluctuation, Vp, is obtained by the equation below: C2 Eq. A-1 Vp = × (E - V2) C1 + C2 Vp is also obtained by the equation below: x-1 1 VREF ∑ Vp = Vp1 × < 2i 10 × 2× i=0 Eq. A-2 where Vp1 = potential fluctuation in the first A-D conversion performed and x = 10 for a 10-bit resolution A-D converter When Eq. A-1 and Eq. A-2 are solved, the following results: E - V2 - 1 } C1 = C2 { Vp1 x-1 1 ∴ C1 > C2 {10 × 2× × ∑ 2 i - 1 } i=0 Eq. A-3 Eq. A-4 Thus, for a 10-bit resolution A-D Converter where C2 = 2.9 pF, C1 is 0.06 µF or more. Use this value for reference when setting up C1. (b) Maximum value of the output impedance R1 when C1 is not added If the external capacitor C1 in Figure 11.5.1 is not used, examination must be made to see if the analog input device can fully charge C2 within a predetermined time. First, the equation to find i2 when C1 in Figure 11.5.1 does not exist is shown below. i2 = C2(E - V2) Cin × R1+C2(R1+R2) × exp { -t } ------------------------ Eq. B-1 Cin × R1+C2(R1+R2) When sample-and-hold is disabled Conversion time for the first bit Second bit ADINi Sampling time Comparison Sampling time time Repeated (10 times) for 10 bits * When sample-and-hold is enabled, the analog input is sampled for only the first bit. Figure 11.5.2 A-D Conversion Timing Diagram Figure 11.5.2 shows an A-D conversion timing diagram. C2 must be charged up within the sampling time shown in this diagram. When the sample-and-hold function is disabled, the sampling time for the second and subsequent bits is about half that of the first bit. The sampling times at the respective conversion speeds are listed in the table 11.5.1. Note that when the sample-and-hold function is enabled, the analog input is sampled for only the first bit. 11-42 32182 Group User's Manual (Rev.1.0) 11 Table 11.5.1 Sampling Time (in Which C2 Needs to Be Charged) Conversion start method Conversion speed A-D Converter 11.5 Precautions on Using A-D Converter Sampling time for the first bit Sampling time for the second and subsequent bits Single mode (when sample-and -hold disabled) Single mode (when sample-and -hold enabled) Slow mode Normal speed Double speed 27.5BCLK 15.5BCLK 11.5BCLK 7.5BCLK 27.5BCLK 15.5BCLK 11.5BCLK 7.5BCLK 27.5BCLK 15.5BCLK 11.5BCLK 7.5BCLK 13.5BCLK 7.5BCLK 5.5BCLK 3.5BCLK – – – – – – – – Fast mode Slow mode Fast mode Normal speed Double speed Normal speed Double speed Normal speed Double speed Comparator mode Slow mode Fast mode Normal speed Double speed Normal speed Double speed Therefore, the time in which C2 needs to be charged is found from Eq. B-1, as follows: Sampling time (in which C2 needs to be charged) > Cin × R1 + C2(R1 + R2) --- Eq. B2 Thus, the maximum value of R1 can be obtained as a criterion from the equation below. Note, however, that for single mode (when sample-and-hold is disabled), the sampling time for the second and subsequent bits (C2 charging time) must be applied. C2 charging time - C2 × R 2 Cin + C2 R1 < 11-43 32182 Group User's Manual (Rev.1.0) 11 A-D Converter 11.5 Precautions on Using A-D Converter This page is blank for reasons of layout. 11-44 32182 Group User's Manual (Rev.1.0) CHAPTER 12 SERIAL I/O 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Outline of Serial I/O Serial I/O Related Registers Transmit Operation in CSIO Mode Receive Operation in CSIO Mode Precautions on Using CSIO Mode Transmit Operation in UART Mode Receive Operation in UART Mode Fixed Period Clock Output Function Precautions on Using UART Mode 12 12.1 Outline of Serial I/O Serial I/O 12.1 Outline of Serial I/O The 32182 contains a total of four serial I/O channels, SIO0–SIO3. Channels SIO0 and SIO1 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (clock-asynchronous serial I/O). Channels SIO2 and SIO3 are UART mode only. • CSIO mode (clock-synchronous serial I/O) Communication is performed synchronously with a transfer clock, using the same clock on both transmit and receive sides. The transfer data is 8 bits long (fixed). • UART mode (clock-asynchronous serial I/O) Communication is performed at any transfer rate in any transfer data format. The transfer data length can be selected from 7, 8 and 9 bits. Channels SIO0–SIO3 each have a transmit DMA transfer and a receive DMA transfer request. These serial I/Os, when combined with the internal DMA Controller (DMAC), allow serial communication to be performed at high speed, as well as reduce the data communication load of the CPU. Serial I/O is outlined below. Table 12.1.1 Outline of Serial I/O Item Number of channels Clock Transfer mode BRG count source (when internal clock selected) Data format Description CSIO mode/UART mode : 2 channels (SIO0, SIO1) UART only : 2 channels (SIO2, SIO3) During CSIO mode : Internal clock or external clock as selected (Note 1) During UART mode : Internal clock only Transmit half-duplex, receive half-duplex, transmit/receive full-duplex f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BLCK)/256 (Note 2) f(BCLK): Peripheral clock operating frequency CSIO mode : Data length = 8 bits (fixed) Order of transfer = LSB first (fixed) UART mode : Start bit = 1 bit Character length = 7, 8 or 9 bits Parity bit = Added (odd, even) or not added Stop bit = 1 or 2 bits Order of transfer = LSB first (fixed) Baud rate Error detection CSIO mode : 152 bits/sec to 2 Mbits/sec (when f(BCLK) = 20 MHz) UART mode : 19 bits/sec to 156 Kbits/sec (when f(BCLK) = 20 MHz) CSIO mode : Overrun error only UART mode : Overrun, parity and framing errors (Occurrence of any of these errors is indicated by an error sum bit) Fixed period clock output function When using SIO0 and SIO1 as UART, this function outputs a divided-by-2 BRG clock from the SCLK pin. Note 1: The maximum input frequency of an external clock during CSIO mode is f(BCLK)/16. Note 2: If f(BCLK) is selected as the count source, the BRG set value is subject to limitations. 12-2 32182 Group User's Manual (Rev.1.0) 12 Table 12.1.2 Interrupt Generation Functions of Serial I/O Serial I/O Interrupt Request Source SIO0 transmit buffer empty or transmission finished SIO0 reception finished or receive error SIO1 transmit buffer empty or transmission finished SIO1 reception finished or receive error SIO2 transmit buffer empty or transmission finished SIO2 reception finished or receive error SIO3 transmit buffer empty or transmission finished SIO3 reception finished or receive error Serial I/O 12.1 Outline of Serial I/O ICU Interrupt Sources SIO0 transmit interrupt SIO0 receive interrupt SIO1 transmit interrupt SIO1 receive interrupt SIO2,3 transmit/receive interrupt (group interrupt) SIO2,3 transmit/receive interrupt (group interrupt) SIO2,3 transmit/receive interrupt (group interrupt) SIO2,3 transmit/receive interrupt (group interrupt) Note: • The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode. Table 12.1.3 DMA Transfer Request Generation Functions of Serial I/O Serial I/O DMA Transfer Request SIO0 transmit buffer empty SIO0 reception finished SIO1 transmit buffer empty SIO1 reception finished SIO2 transmit buffer empty SIO2 reception finished SIO3 transmit buffer empty SIO3 reception finished DMAC Input Channels DMA3, DMA4 DMA4 DMA6 DMA3, DMA6 DMA7 DMA5 DMA7, DMA9 DMA8 12-3 32182 Group User's Manual (Rev.1.0) 12 SIO0 SIO0 Transmit Buffer Register Transmit interrupt request TXD0 SIO0 Transmit Shift Register Transmit/ Receive Control Circuit Receive interrupt request Serial I/O 12.1 Outline of Serial I/O To the Interrupt Controller (ICU) Transmit DMA transfer request Receive DMA transfer request RXD0 SIO0 Receive Shift Register To DMA3, DMA4 To DMA4 SIO0 Receive Buffer Register UART mode CSIO mode When external clock selected When internal clock selected BCLK Clock Divider Baud Rate Generator (BRG) CSIO mode When internal clock selected When UART mode selected SIO1 TXD1 SIO1 Transmit Shift Register Transmit/ Receive Control Circuit Transmit interrupt request Receive interrupt request Transmit DMA transfer request Receive DMA transfer request Internal data bus BCLK, BCLK/8, BCLK/32, BCLK/256 1/16 1 (set value + 1) 1/2 SCLKI0/SCLKO0 To the Interrupt Controller (ICU) To DMA6 To DMA3, DMA6 SCLKI1/SCLKO1 RXD1 SIO1 Receive Shift Register SIO2 TXD2 SIO2 Transmit Shift Register Transmit interrupt request Transmit/ Receive Control Circuit Receive interrupt request Transmit DMA transfer request Receive DMA transfer request To DMA7 To DMA5 RXD2 SIO2 Receive Shift Register SIO3 TXD3 SIO3 Transmit Shift Register Transmit/ Receive Control Circuit Transmit interrupt request Receive interrupt request Transmit DMA transfer request Receive DMA transfer request To the Interrupt Controller (ICU) To DMA7, DMA9 To DMA8 RXD3 SIO3 Receive Shift Register Notes: • When BCLK is selected, the BRG set value is subject to limitations. • SIO2 and SIO3 do not have the SCLKI/SCLKO function. Figure 12.1.1 Block Diagram of SIO0–SIO3 12-4 32182 Group User's Manual (Rev.1.0) 12 12.2 Serial I/O Related Registers Shown below is a serial I/O related register map. Serial I/O Related Register Map Address b0 H'0080 0100 H'0080 0102 | H'0080 0110 H'0080 0112 H'0080 0114 H'0080 0116 | H'0080 0120 H'0080 0122 H'0080 0124 H'0080 0126 | H'0080 0130 H'0080 0132 H'0080 0134 H'0080 0136 | H'0080 0140 H'0080 0142 H'0080 0144 H'0080 0146 +0 address b7 b8 Serial I/O 12.2 Serial I/O Related Registers +1 address b15 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Enable Register (SI23STAT) (SI03EN) SIO03 Interrupt Source Select Register (Use inhibited area) (SI03SEL) (Use inhibited area) SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register (S0TCNT) (S0MOD) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO0 Receive Control Register SIO0 Baud Rate Register (S0RCNT) (S0BAUR) (Use inhibited area) SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register (S1TCNT) (S1MOD) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Receive Control Register SIO1 Baud Rate Register (S1RCNT) (S1BAUR) (Use inhibited area) SIO2Transmit Control Register SIO2 Transmit/Receive Mode Register (S2TCNT) (S2MOD) SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Receive Control Register SIO2 Baud Rate Register (S2RCNT) (S2BAUR) (Use inhibited area) SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register (S3TCNT) (S3MOD) SIO3 Transmit Buffer Register (S3TXB) SIO3 Receive Buffer Register (S3RXB) SIO3 Receive Control Register SIO3 Baud Rate Register (S3RCNT) (S3BAUR) See pages 12-9 12-10 12-11 12-13 12-14 12-17 12-18 12-19 12-22 12-13 12-14 12-17 12-18 12-19 12-22 12-13 12-14 12-17 12-18 12-19 12-22 12-13 12-14 12-17 12-18 12-19 12-22 12-5 32182 Group User's Manual (Rev.1.0) 12 12.2.1 SIO Interrupt Related Registers Serial I/O 12.2 Serial I/O Related Registers The SIO interrupt related registers are used to control the interrupt request signals output from SIO to the Interrupt Controller (ICU), as well as select the source of each interrupt request. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request enable bit, it can also be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request enable bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "1" to enable interrupt requests or "0" to disable interrupt requests. • Group interrupt Interrupt request from each peripheral function Set Data=0 clear Interrupt request status Data bus F/F F/F Interrupt request enable To the Interrupt Controller Figure 12.2.1 Interrupt Request Status and Enable Registers 12-6 32182 Group User's Manual (Rev.1.0) 12 Example for clearing interrupt request status b4 5 0 6 0 b7 0 Serial I/O 12.2 Serial I/O Related Registers Interrupt request status Initial state 0 Interrupt request Bit 6 event occurs 0 0 1 0 Bit 4 event occurs Write to the interrupt request status b4 1 5 1 6 0 b7 1 1 0 1 0 1 0 0 0 Only bit 6 cleared Bit 4 data retained Program example • To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1: ISTAT1 (0x02 bit) ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */ Interrupt request status b4 5 0 6 1 b7 0 Bit 6 event occurs 0 Read 0 0 1 0 Bit 4 event occurs 1 0 1 0 Clear bit 6 (ANDing with 1101) 0 0 0 0 0 0 0 0 Write Only bit 6 cleared Bit 4 also cleared Figure 12.2.2 Example for Clearing Interrupt Request Status 12-7 32182 Group User's Manual (Rev.1.0) 12 (3) Selecting the source of an interrupt request Serial I/O 12.2 Serial I/O Related Registers The interrupt request signals sent from each SIO to the Interrupt Controller (ICU) are classified into transmit interrupts and receive interrupts. Transmit interrupt requests can be generated when the transmit buffer is empty or transmission is finished, and the receive interrupt requests can be generated when reception is finished or an receive error is detected, as selected by the Interrupt Source Select Register (SI03SEL). Notes: • No interrupt request signals are generated unless interrupts are generated by the SIO Interrupt Request Enable Register after enabling the TEN (Transmit Enable) bit or REN (Receive Enable) bit for the corresponding SIO. • SIO2 and SIO3 together comprise one interrupt group. • The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode. (4) Notes on using transmit interrupts While the SIO Interrupt Request Enable Register is set to enable interrupts, a transmit interrupt request is generated upon enabling the corresponding TEN (Transmit Enable) bit. (5) About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a reception-finished DMA transfer request. These DMA transfer requests can be generated by enabling each SIO’s corresponding TEN (Transmit Enable) bit or REN (Receive Enable) bit. When using DMA transfers to communicate with external devices, be sure to set the DMA Controller (DMAC) before enabling the TEN or REN bit. No reception-finished DMA transfer requests are generated if a receive error occurs. • Transmit DMA transfer request Generated when the transmit buffer is empty and the TEN bit is enabled. TEN (Transmit Enable bit) TBE (Transmit Buffer Empty bit) Transmit DMA transfer request Figure 12.2.3 Transmit DMA Transfer Request • Reception-finished DMA transfer request A DMA transfer request is generated when the receive buffer is filled. RFIN (Reception Finished bit) Receive DMA transfer request Note: • No reception-finished DMA transfer requests are generated if a receive error occurs. Figure 12.2.4 Reception-finished DMA Transfer Request 12-8 32182 Group User's Manual (Rev.1.0) 12 SIO23 Interrupt Request Status Register (SI23STAT) b0 0 Serial I/O 12.2 Serial I/O Related Registers 1 0 2 0 3 0 4 IRQT2 0 5 IRQR2 0 6 IRQT3 0 b7 IRQR3 0 b 0–3 4 5 6 7 Bit Name No function assigned. Fix to "0". IRQT2 SIO2 transmit interrupt request status bit IRQR2 SIO2 receive interrupt request status bit IRQT3 SIO3 transmit interrupt request status bit IRQR3 SIO3 receive interrupt request status bit 0: Interrupt not requested 1: Interrupt requested 0: Interrupt not requested 1: Interrupt requested 0: Interrupt not requested 1: Interrupt requested 0: Interrupt not requested 1: Interrupt requested R (Note 1) Function R 0 W 0 R (Note 1) R (Note 1) R (Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. The register indicates the transmit/receive interrupt requests from each SIO. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing "0" in software. Note: • If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. 12-9 32182 Group User's Manual (Rev.1.0) 12 SIO03 Interrupt Request Enable Register (SI03EN) b8 T0EN 0 Serial I/O 12.2 Serial I/O Related Registers 9 R0EN 0 10 T1EN 0 11 R1EN 0 12 T2EN 0 13 R2EN 0 14 T3EN 0 b15 R3EN 0 b 8 9 10 11 12 13 14 15 Bit Name T0EN SIO0 transmit interrupt request enable bit R0EN SIO0 receive interrupt request enable bit T1EN SIO1 transmit interrupt request enable bit R1EN SIO1 receive interrupt request enable bit T2EN SIO2 transmit interrupt request enable bit R2EN SIO2 receive interrupt request enable bit T3EN SIO3 transmit interrupt request enable bit R3EN SIO3 receive interrupt request enable bit Function 0: Mask (disable) interrupt request 1: Enable interrupt request 0: Mask (disable) interrupt request 1: Enable interrupt request 0: Mask (disable) interrupt request 1: Enable interrupt request 0: Mask (disable) interrupt request 1: Enable interrupt request 0: Mask (disable) interrupt request 1: Enable interrupt request 0: Mask (disable) interrupt request 1: Enable interrupt request 0: Mask (disable) interrupt request 1: Enable interrupt request 0: Mask (disable) interrupt request 1: Enable interrupt request R R R R W W W W R R R R R W W W W W These registers enable or disable the interrupt requests generated by each SIO. Interrupt requests from any SIO are enabled by setting its corresponding interrupt request enable bit to "1". 12-10 32182 Group User's Manual (Rev.1.0) 12 SIO03 Interrupt Request Source Select Register (SI03SEL) b0 IST0 0 Serial I/O 12.2 Serial I/O Related Registers 1 IST1 0 2 IST2 0 3 IST3 0 4 ISR0 0 5 ISR1 0 6 ISR2 0 b7 ISR3 0 b 0 1 2 3 4 5 6 7 Bit Name IST0 SIO0 transmit interrupt request source select bit IST1 SIO1 transmit interrupt request source select bit IST2 SIO2 transmit interrupt request source select bit IST3 SIO3 transmit interrupt request source select bit ISR0 SIO0 receive interrupt request source select bit ISR1 SIO1 receive interrupt request source select bit ISR2 SIO2 receive interrupt request source select bit ISR3 SIO3 receive interrupt request source select bit Function 0: Transmit buffer empty interrupt 1: Transmission finished interrupt 0: Transmit buffer empty interrupt 1: Transmission finished interrupt 0: Transmit buffer empty interrupt 1: Transmission finished interrupt 0: Transmit buffer empty interrupt 1: Transmission finished interrupt 0: Reception finished interrupt 1: Receive error interrupt 0: Reception finished interrupt 1: Receive error interrupt 0: Reception finished interrupt 1: Receive error interrupt 0: Reception finished interrupt 1: Receive error interrupt R R R R W W W W R R R R R W W W W W These registers select the source of interrupt requests generated by each SIO when transmit or receive operation is completed. (1) SIOn transmit interrupt request source select bit [When set to "0"] The transmit buffer empty interrupt is selected. A transmit buffer empty interrupt request is generated when data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt request is generated when the TEN (Transmit Enable) bit is set to "1" (interrupt enabled). [When set to "1"] The transmission finished (transmit shift buffer empty) interrupt is selected. A transmission finished interrupt request is generated when all of the data in the transmit shift register has been transferred. Note: • Do not select the transmission finished interrupt when an external clock is selected in CSIO mode. (2) SIOn receive interrupt request source select bit [When set to "0"] The reception finished (receive buffer full) interrupt is selected. A reception finished interrupt request is also generated when a receive error (except overrun error) occurs. [When set to "1"] The receive error interrupt is selected. Following types of errors constitute a receive error: • CSIO mode: Overrun error • UART mode: Overrun, parity and framing errors 12-11 32182 Group User's Manual (Rev.1.0) 12 6 PH1 0 1 2 3 PH2 0 4 0 5 0 7 0 8 0 9 PRB 0 10 0 11 SAM 0 12 0 13 0 14 0 b15 0 b 0–1 Bit Name SJW reSynchronization Jump Width setting bit Function 00: 01: 10: 11: SJW SJW SJW SJW = = = = 1Tq 2Tq 3Tq 4Tq = = = = = = = = = = = = = = = 1Tq 2Tq 3Tq 4Tq 5Tq 6Tq 7Tq 8Tq 1Tq 2Tq 3Tq 4Tq 5Tq 6Tq 7Tq R R W W 2–4 PH2 Phase Segment2 setting bit 000: Phase Segment2 001: Phase Segment2 010: Phase Segment2 011: Phase Segment2 100: Phase Segment2 101: Phase Segment2 110: Phase Segment2 111: Phase Segment2 000: Phase Segment1 001: Phase Segment1 010: Phase Segment1 011: Phase Segment1 100: Phase Segment1 101: Phase Segment1 110: Phase Segment1 R W 5–7 PH1 Phase Segment1 setting bit R W 111: Phase Segment1 = 8Tq 8–10 PRB Propagation Segment setting bit 000: Propagation Segment = 1Tq 001: Propagation Segment = 2Tq 010: Propagation Segment = 3Tq 011: Propagation Segment = 4Tq 100: Propagation Segment = 5Tq 101: Propagation Segment = 6Tq 110: Propagation Segment = 7Tq 111: Propagation Segment = 8Tq 0: Sampled one time 1: Sampled three times R W 11 12–15 SAM Sampling count select bit No function assigned. Fix to "0". R 0 W 0 Notes: • Do not change settings of the CAN Configuration Register (CAN0CONF or CAN1CONF) during CAN operation (CAN Status Register CRS bit = "0"). • When setting the bits in this register, make sure the conditions given below are met: • Number of Tq’s for one bit: 8–25 Tq’s • SJW ≤ min (Phase Segment1, Phase Segment2) • Phase Segment2 = max (Phase Segment1, IPT) where IPT = 1 for the internal CAN modules of the 32182 min() is the function that returns the smaller of two values; max() is the function that returns the maximum value. 13-22 32182 Group User’s Manual (Rev.1.0) 13 (1) SJW bits (Bits 0–1) These bits set the reSynchronization Jump Width. (2) PH2 bits (Bits 2–4) These bits set the width of Phase Segment2. (3) PH1 bits (Bits 5–7) These bits set the width of Phase Segment1. (4) PRB bits (Bits 8–10) These bits set the width of Propagation Segment. (5) SAM bit (Bit 11) CAN MODULE 13.2 CAN Module Related Registers This bit sets the number of times each bit is sampled. When SAM = "0", the value sampled at the end of Phase Segment1 is assumed to be the value of the bit. When SAM = "1", the value of the bit is determined by a majority circuit from three sampled values, each sampled 2 Tq’s before, 1 Tq before, and at the end of Phase Segment1. Table 13.2.1 Typical Settings of Bit Timing when CPU Clock = 80 MHz Baud Rate 1M bps BRP Set Value 1 3 3 3 4 4 500K bps 4 4 4 7 7 7 9 9 Tq Period (ns) 50 100 100 100 125 125 125 125 125 200 200 200 250 250 No. of Tq’s in 1 Bit 20 10 10 10 8 8 16 16 16 10 10 10 8 8 PROP + PH1 13 7 6 5 5 4 13 12 11 7 6 5 5 4 PH2 6 2 3 4 2 3 2 3 4 2 3 4 2 3 Sampling Point 70% 80% 70% 60% 75% 63% 88% 81% 75% 80% 70% 60% 75% 63% Table 13.2.2 Typical Settings of Bit Timing when CPU Clock = 64 MHz Baud Rate 1M bps BRP Set Value 1 3 3 500K bps 3 3 7 7 Tq Period (ns) 62.5 125 125 125 125 250 250 No. of Tq’s in 1 Bit 16 8 8 16 16 8 8 PROP + PH1 10 5 4 13 11 5 4 PH2 5 2 3 2 4 2 3 Sampling Point 69% 75% 63% 88% 75% 75% 63% 13-23 32182 Group User’s Manual (Rev.1.0) 13 13.2.5 CAN Timestamp Count Registers CAN0 Timestamp Count Register (CAN0TSTMP) CAN1 Timestamp Count Register (CAN1TSTMP) b0 0 CAN MODULE 13.2 CAN Module Related Registers 7 0 1 0 2 0 3 0 4 0 5 0 6 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 CANTSTMP b 0–15 Bit Name CANTSTMP Function 16-bit timestamp count value R R W – The CAN module contains a 16-bit up-count register. The count period can be selected from the CAN bus bit period divided by 1, 2, 3 or 4 by setting the CAN Control Register (CANnCNT) TSP (Timestamp Prescaler) bits. When the CAN module finishes sending or receiving, it captures the count register value and stores the value in a message slot. The counter is made to start counting by clearing the CAN Control Register (CANnCNT) RST bit to "0". Notes: • The CAN protocol control unit can be reset and the counter initialized to H’0000 by setting the CAN Control Register (CANnCNT) RST (CAN Reset) bit to "1". Or the counter can be initialized to H’0000 while the CAN module remains operating by setting the TSR (Timestamp Counter Reset) bit to "1". • If any slot with the matching ID exists during loopback mode, the CAN module stores the timestamp value in that slot when it finished receiving. (No timestamp values are stored this way when the CAN module finished sending.) • The count period of the CAN Timestamp Count Register varies with the CAN resynchronization function. 13-24 32182 Group User’s Manual (Rev.1.0) 13 13.2.6 CAN Error Count Registers CAN0 Receive Error Count Register (CAN0REC) CAN1 Receive Error Count Register (CAN1REC) b0 0 CAN MODULE 13.2 CAN Module Related Registers b7 0 1 0 2 0 3 REC 0 4 0 5 0 6 0 b 0–7 Bit Name REC Function Receive error count value R R W – During an error active/error passive state, a receive error count value is stored in this register. The count is decremented when frames are received normally or incremented when an error occurred. If the CAN module finished receiving normally when REC ≥ 128 (error passive), REC is set to 127. During a bus off state, an undefined value is stored in this register. The count is reset to H’00 upon returning to an error active state. CAN0 Transmit Error Count Register (CAN0TEC) CAN1 Transmit Error Count Register (CAN1TEC) b8 0 b15 0 9 0 10 0 11 TEC 0 12 0 13 0 14 0 b 8–15 Bit Name TEC Function Transmit error count value R R W – During an error active/error passive state, a transmit error count value is stored in this register. The count is decremented when frames are transmitted normally or incremented when an error occurred. During a bus off state, an undefined value is stored in this register. The count is reset to H’00 upon returning to an error active state. 13-25 32182 Group User’s Manual (Rev.1.0) 13 13.2.7 CAN Baud Rate Prescalers CAN0 Baud Rate Prescaler (CAN0BRP) CAN1 Baud Rate Prescaler (CAN1BRP) b0 0 CAN MODULE 13.2 CAN Module Related Registers 6 0 1 0 2 0 3 BRP 0 4 0 5 0 b7 1 b 0–7 Bit Name BRP Function Baud rate prescaler value R R W W This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period × number of Tq’s in one bit). Tq period = (BRP + 1) / (CPU clock/2) CAN transfer baud rate = 1 Tq period × number of Tq’s in one bit Number of Tq’s in one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Notes: • Setting H’00 (divide by 1) is inhibited. • Do not change settings of the CAN Baud Rate Prescaler (CANnBRP) during CAN operation (CAN Status Register CRS bit = "0"). 13-26 32182 Group User’s Manual (Rev.1.0) 13 13.2.8 CAN Interrupt Related Registers CAN MODULE 13.2 CAN Module Related Registers The CAN interrupt related registers are used to control the interrupt request signals output to the Interrupt Controller by CAN. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request enable bit, it can also be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request enable bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "1" to enable interrupt requests or "0" to disable interrupt requests. • Group interrupt Interrupt request from each peripheral function Set Data = 0 clear Interrupt request status Data bus F/F F/F Interrupt request enable To the Interrupt Controller Figure 13.2.1 Interrupt Request Status and Enable Registers 13-27 32182 Group User’s Manual (Rev.1.0) 13 Example for clearing interrupt request status CAN MODULE 13.2 CAN Module Related Registers Interrupt request status b4 5 0 6 0 b7 0 Initial state 0 Interrupt request Event occurs on bit 6 0 0 1 0 Event occurs on bit 4 Write to the interrupt request status b4 1 5 1 6 0 b7 1 1 0 1 0 1 0 0 0 Only bit 6 cleared Bit 4 data retained Program example • To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */ Interrupt request status b4 5 0 6 1 b7 0 Event occurs on bit 6 0 Read 0 0 1 0 Event occurs on bit 4 1 0 1 0 Clear bit 6 (AND'ing with 1101) 0 0 0 0 0 0 0 0 Write Only bit 6 cleared Bit 4 also cleared Figure 13.2.2 Example for Clearing Interrupt Request Status 13-28 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Slot Interrupt Request Status Register (CAN0SLIST) CAN1 Slot Interrupt Request Status Register (CAN1SLIST) b0 SSB0 CAN MODULE 13.2 CAN Module Related Registers 8 SSB8 1 SSB1 2 SSB2 3 SSB3 4 SSB4 5 SSB5 6 SSB6 7 SSB7 9 SSB9 10 SSB10 11 SSB11 12 SSB12 13 SSB13 14 SSB14 b15 SSB15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name SSB0 (slot 0 interrupt request status bit) SSB1 (slot 1 interrupt request status bit) SSB2 (slot 2 interrupt request status bit) SSB3 (slot 3 interrupt request status bit) SSB4 (slot 4 interrupt request status bit) SSB5 (slot 5 interrupt request status bit) SSB6 (slot 6 interrupt request status bit) SSB7 (slot 7 interrupt request status bit) SSB8 (slot 8 interrupt request status bit) SSB9 (slot 9 interrupt request status bit) SSB10 (slot 10 interrupt request status bit) SSB11 (slot 11 interrupt request status bit) SSB12 (slot 12 interrupt request status bit) SSB13 (slot 13 interrupt request status bit) SSB14 (slot 14 interrupt request status bit) SSB15 (slot 15 interrupt request status bit) Function 0: Interrupt not requested 1: Interrupt requested R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. When using CAN interrupts, this register helps to know which slot requested an interrupt. • Slots set for transmission The corresponding bit is set to "1" when the CAN module finished sending. This bit is cleared by writing "0" in software. • Slots set for reception The corresponding bit is set to "1" when the CAN module finished receiving and finished storing the received message in the message slot. This bit is cleared by writing "0" in software. When writing to the CAN slot interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. Notes: • If the automatic response function is enabled for remote frame receive slots, the request status is set after the CAN module finished receiving a remote frame and after it finished sending a data frame. • For remote frame transmit slots, the request status is set after the CAN module finished sending a remote frame and after it finished receiving a data frame. • If the request status is set by an interrupt request at the same time it is cleared in software, the former has priority so that the request status is set. 13-29 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Slot Interrupt Request Enable Register (CAN0SLIEN) CAN1 Slot Interrupt Request Enable Register (CAN1SLIEN) b0 IRB0 CAN MODULE 13.2 CAN Module Related Registers 8 IRB8 1 IRB1 2 IRB2 3 IRB3 4 IRB4 5 IRB5 6 IRB6 7 IRB7 9 IRB9 10 IRB10 11 IRB11 12 IRB12 13 IRB13 14 IRB14 b15 IRB15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name IRB0 (slot 0 interrupt request enable bit) IRB1 (slot 1 interrupt request enable bit) IRB2 (slot 2 interrupt request enable bit) IRB3 (slot 3 interrupt request enable bit) IRB4 (slot 4 interrupt request enable bit) IRB5 (slot 5 interrupt request enable bit) IRB6 (slot 6 interrupt request enable bit) IRB7 (slot 7 interrupt request enable bit) IRB8 (slot 8 interrupt request enable bit) IRB9 (slot 9 interrupt request enable bit) IRB10 (slot 10 interrupt request enable bit) IRB11 (slot 11 interrupt request enable bit) IRB12 (slot 12 interrupt request enable bit) IRB13 (slot 13 interrupt request enable bit) IRB14 (slot 14 interrupt request enable bit) IRB15 (slot 15 interrupt request enable bit) Function 0: Mask (disable) interrupt request 1: Enable interrupt request R R W W This register is used to enable or disable the interrupt requests that will be generated when data transmission or reception in each corresponding slot is completed. Setting IRBn (n = 0–15) to "1" enables the interrupt request to be generated when data transmission or reception in the corresponding slot is completed. The CAN Slot Interrupt Request Status Register (CANnSLIST) helps to know which slot requested the interrupt. 13-30 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Error Interrupt Request Status Register (CAN0ERIST) CAN1 Error Interrupt Request Status Register (CAN1ERIST) b0 0 CAN MODULE 13.2 CAN Module Related Registers 1 0 2 0 3 0 4 0 5 BEIS 0 6 EPIS 0 b7 EOIS 0 b 0–4 5 6 7 Bit Name No function assigned. Fix to "0". BEIS CAN bus error interrupt request status bit EPIS Error passive interrupt request status bit EOIS Bus off interrupt request status bit Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0 R(Note 1) When using CAN interrupts, if the interrupt request sources are associated with errors, this register helps to know which source generated the interrupt. (1) BEIS (CAN Bus Error Interrupt Request Status) bit (Bit 5) The BEIS bit is set to "1" when a communication error is detected. This bit is cleared by writing "0" in software. (2) EPIS (Error Passive Interrupt Request Status) bit (Bit 6) The EPIS bit is set to "1" when the CAN module goes to an error passive state. This bit is cleared by writing "0" in software. (3) EOIS (Bus Off Interrupt Request Status) bit (Bit 7) The EOIS bit is set to "1" when the CAN module goes to a bus off passive state. This bit is cleared by writing "0" in software. When writing to the CAN error interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. 13-31 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Error Interrupt Request Enable Register (CAN0ERIEN) CAN1 Error Interrupt Request Enable Register (CAN1ERIEN) b8 0 CAN MODULE 13.2 CAN Module Related Registers 9 0 10 0 11 0 12 0 13 BEIEN 0 14 0 b15 0 EPIEN EOIEN b 8–12 13 14 15 Bit Name No function assigned. Fix to "0". BEIEN CAN bus error interrupt request enable bit EPIEN Error passive interrupt request enable bit EOIEN Bus off interrupt request enable bit 0: Mask (disable) interrupt request 1: Enable interrupt request Function R 0 R W 0 W (1) BEIEN (CAN Bus Error Interrupt Request Enable) bit (Bit 5) The BEIEN bit enables or disables the interrupt requests to be generated when CAN bus errors occurred. CAN bus error interrupt requests are enabled by setting this bit to "1". (2) EPIEN (Error Passive Interrupt Request Enable) bit (Bit 6) The EPIEN bit enables or disables the interrupt requests to be generated when the CAN module entered an error passive state. Error passive interrupt requests are enabled by setting this bit to "1". (3) EOIEN (Bus Off Interrupt Request Enable) bit (Bit 7) The EOIEN bit enables or disables the interrupt requests to be generated when the CAN module entered a bus off state. Bus off interrupt requests are enabled by setting this bit to "1". 13-32 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Single-Shot Interrupt Request Status Register (CAN0SSIST) CAN1 Single-Shot Interrupt Request Status Register (CAN1SSIST) b0 SSIST0 CAN MODULE 13.2 CAN Module Related Registers 9 SSIST9 1 SSIST1 2 SSIST2 3 SSIST3 4 SSIST4 5 SSIST5 6 SSIST6 7 SSIST7 8 SSIST8 10 0 11 0 12 0 13 0 14 0 b15 0 SSIST10 SSIST11 SSIST12 SSIST13 SSIST14 SSIST15 0 0 0 0 0 0 0 0 0 0 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name SSIST0 Slot 0 single-shot interrupt request status SSIST1 Slot 1 single-shot interrupt request status SSIST2 Slot 2 single-shot interrupt request status SSIST3 Slot 3 single-shot interrupt request status SSIST4 Slot 4 single-shot interrupt request status SSIST5 Slot 5 single-shot interrupt request status SSIST6 Slot 6 single-shot interrupt request status SSIST7 Slot 7 single-shot interrupt request status SSIST8 Slot 8 single-shot interrupt request status SSIST9 Slot 9 single-shot interrupt request status SSIST10 Slot 10 single-shot interrupt request status SSIST11 Slot 11 single-shot interrupt request status SSIST12 Slot 12 single-shot interrupt request status SSIST13 Slot 13 single-shot interrupt request status SSIST14 Slot 14 single-shot interrupt request status SSIST15 Slot 15 single-shot interrupt request status Function 0: No arbitration-lost or transmit error 1: Arbitration-lost or transmit error occurred R W R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. If transmission in any slot failed for reasons of a detection of arbitration-lost or a transmit error, the corresponding bit in this register is set to "1". The bit is cleared by writing "0" in software. Furthermore, if the corresponding bit in the CAN single-shot interrupt request enable register has been set to "1", an interrupt request can be generated when transmission failed. When writing to the CAN single-shot interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. 13-33 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Single-Shot Interrupt Request Enable Register (CAN0SSIEN) CAN1 Single-Shot Interrupt Request Enable Register (CAN1SSIEN) b0 SSIEN0 CAN MODULE 13.2 CAN Module Related Registers 10 0 1 SSIEN1 2 SSIEN2 3 SSIEN3 4 SSIEN4 5 SSIEN5 6 SSIEN6 7 SSIEN7 8 SSIEN8 9 0 11 0 12 0 13 0 14 0 b15 0 SSIEN9 SSIEN10 SSIEN11 SSIEN12 SSIEN13 SSIEN14 SSIEN15 0 0 0 0 0 0 0 0 0 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name SSIEN0 Slot 0 single-shot interrupt request enable bit SSIEN1 Slot 1 single-shot interrupt request enable bit SSIEN2 Slot 2 single-shot interrupt request enable bit SSIEN3 Slot 3 single-shot interrupt request enable bit SSIEN4 Slot 4 single-shot interrupt request enable bit SSIEN5 Slot 5 single-shot interrupt request enable bit SSIEN6 Slot 6 single-shot interrupt request enable bit SSIEN7 Slot 7 single-shot interrupt request enable bit SSIEN8 Slot 8 single-shot interrupt request enable bit SSIEN9 Slot 9 single-shot interrupt request enable bit SSIEN10 Slot 10 single-shot interrupt request enable bit SSIEN11 Slot 11 single-shot interrupt request enable bit SSIEN12 Slot 12 single-shot interrupt request enable bit SSIEN13 Slot 13 single-shot interrupt request enable bit SSIEN14 Slot 14 single-shot interrupt request enable bit SSIEN15 Slot 15 single-shot interrupt request enable bit Function 0: Disable interrupt request 1: Enable interrupt request R R W W This register is used to enable or disable the interrupt requests that will be generated when transmission in each corresponding slot has failed. Setting any bit in this register to "1" enables the interrupt request to be generated when transmission in the corresponding slot (in single-shot mode only) has failed. The CAN Single-Shot Interrupt Request Status Register helps to know which slot requested the interrupt. 13-34 32182 Group User’s Manual (Rev.1.0) 13 CAN0SLIST (H'0080 100C) CAN0SLIEN (H'0080 1010) Slot 0 transmission/reception completed Data bus b0 b0 SSB0 F/F IRB0 F/F CAN MODULE 13.2 CAN Module Related Registers 35-source inputs (Level) CAN0 transmit/receive & error interrupt request Slot 1 transmission/reception completed SSB1 F/F IRB1 F/F b1 b1 Slot 2 transmission/reception completed b2 b2 SSB2 F/F IRB2 F/F Slot 3 transmission/reception completed SSB3 F/F IRB3 F/F b3 b3 Slot 4 transmission/reception completed b4 b4 SSB4 F/F IRB4 F/F Slot 5 transmission/reception completed b5 b5 SSB5 F/F IRB5 F/F Slot 6 transmission/reception completed b6 b6 SSB6 F/F IRB6 F/F Slot 7 transmission/reception completed b7 b7 SSB7 F/F IRB7 F/F To the remaining 27-source inputs in the next page Figure 13.2.3 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (1/5) 13-35 32182 Group User’s Manual (Rev.1.0) 13 CAN0SLIST (H'0080 100C) CAN0SLIEN (H'0080 1010) Slot 8 transmission/reception completed Data bus b8 b8 SSB8 F/F IRB8 F/F CAN MODULE 13.2 CAN Module Related Registers 27-source inputs (Level) To the preceding page Slot 9 transmission/reception completed SSB9 F/F IRB9 F/F b9 b9 Slot 10 transmission/reception completed b10 b10 SSB10 F/F IRB10 F/F Slot 11 transmission/reception completed SSB11 F/F IRB11 F/F b11 b11 Slot 12 transmission/reception completed b12 b12 SSB12 F/F IRB12 F/F Slot 13 transmission/reception completed b13 b13 SSB13 F/F IRB13 F/F Slot 14 transmission/reception completed b14 b14 SSB14 F/F IRB14 F/F Slot 15 transmission/reception completed b15 b15 SSB15 F/F IRB15 F/F To the remaining 19-source inputs in the next page Figure 13.2.4 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (2/5) 13-36 32182 Group User’s Manual (Rev.1.0) 13 CAN0ERIST (H'0080 1014) CAN0ERIEN (H'0080 1015) CAN bus error occurs Data bus b5 b13 BEIS F/F BEIEN F/F CAN MODULE 13.2 CAN Module Related Registers 19-source inputs (Level) To the preceding page Go to error passive state EPIS F/F EPIEN F/F b6 b14 Go to bus off state b7 b15 EOIS F/F EOIEN F/F To the remaining 16-source inputs in the next page Figure 13.2.5 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (3/5) 13-37 32182 Group User’s Manual (Rev.1.0) 13 CAN0SSIST (H'0080 1044) CAN0SSIEN (H'0080 1048) Slot 0 arbitration-lost/transmit error occurs Data bus b0 b0 SSIST0 F/F SSIEN0 F/F CAN MODULE 13.2 CAN Module Related Registers 16-source inputs (Level) To the preceding page Slot 1 arbitration-lost/transmit error occurs SSIST1 F/F SSIEN1 F/F b1 b1 Slot 2 arbitration-lost/transmit error occurs SSIST2 F/F SSIEN2 F/F b2 b2 Slot 3 arbitration-lost/transmit error occurs SSIST3 F/F SSIEN3 F/F b3 b3 Slot 4 arbitration-lost/transmit error occurs SSIST4 F/F SSIEN4 F/F b4 b4 Slot 5 arbitration-lost/transmit error occurs SSIST5 F/F SSIEN5 F/F b5 b5 Slot 6 arbitration-lost/transmit error occurs SSIST6 F/F SSIEN6 F/F b6 b6 Slot 7 arbitration-lost/transmit error occurs SSIST7 F/F SSIEN7 F/F b7 b7 To the remaining 8-source inputs in the next page Figure 13.2.6 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (4/5) 13-38 32182 Group User’s Manual (Rev.1.0) 13 CAN0SSIST (H'0080 1044) CAN0SSIEN (H'0080 1048) Slot 8 arbitration-lost/transmit error occurs Data bus b8 b8 SSIST8 F/F SSIEN8 F/F CAN MODULE 13.2 CAN Module Related Registers 8-source inputs (Level) To the preceding page Slot 9 arbitration-lost/transmit error occurs SSIST9 F/F SSIEN9 F/F b9 b9 Slot 10 arbitration-lost/transmit error occurs SSIST10 F/F SSIEN10 F/F b10 b10 Slot 11 arbitration-lost/transmit error occurs SSIST11 F/F SSIEN11 F/F b11 b11 Slot 12 arbitration-lost/transmit error occurs SSIST12 F/F SSIEN12 F/F b12 b12 Slot 13 arbitration-lost/transmit error occurs SSIST13 F/F SSIEN13 F/F b13 b13 Slot 14 arbitration-lost/transmit error occurs SSIST14 F/F SSIEN14 F/F b14 b14 Slot 15 arbitration-lost/transmit error occurs SSIST15 F/F SSIEN15 F/F b15 b15 Figure 13.2.7 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (5/5) 13-39 32182 Group User’s Manual (Rev.1.0) 13 CAN1SLIST (H'0080 140C) CAN1SLIEN (H'0080 1410) Slot 0 transmission/reception completed Data bus b0 b0 SSB0 F/F IRB0 F/F CAN MODULE 13.2 CAN Module Related Registers 35-source inputs (Level) CAN1 transmit/receive & error interrupt request Slot 1 transmission/reception completed SSB1 F/F IRB1 F/F b1 b1 Slot 2 transmission/reception completed SSB2 F/F IRB2 F/F b2 b2 Slot 3 transmission/reception completed SSB3 F/F IRB3 F/F b3 b3 Slot 4 transmission/reception completed b4 b4 SSB4 F/F IRB4 F/F Slot 5 transmission/reception completed b5 b5 SSB5 F/F IRB5 F/F Slot 6 transmission/reception completed b6 b6 SSB6 F/F IRB6 F/F Slot 7 transmission/reception completed b7 b7 SSB7 F/F IRB7 F/F To the remaining 27-source inputs in the next page Figure 13.2.8 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (1/5) 13-40 32182 Group User’s Manual (Rev.1.0) 13 CAN1SLIST (H'0080 140C) CAN1SLIEN (H'0080 1410) Slot 8 transmission/reception completed Data bus b8 b8 SSB8 F/F IRB8 F/F CAN MODULE 13.2 CAN Module Related Registers 27-source inputs (Level) To the preceding page Slot 9 transmission/reception completed SSB9 b9 b9 F/F IRB9 F/F Slot 10 transmission/reception completed SSB10 b10 b10 F/F IRB10 F/F Slot 11 transmission/reception completed SSB11 b11 b11 F/F IRB11 F/F Slot 12 transmission/reception completed b12 b12 SSB12 F/F IRB12 F/F Slot 13 transmission/reception completed SSB13 b13 b13 F/F IRB13 F/F Slot 14 transmission/reception completed b14 b14 SSB14 F/F IRB14 F/F Slot 15 transmission/reception completed b15 b15 SSB15 F/F IRB15 F/F To the remaining 19-source inputs in the next page Figure 13.2.9 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (2/5) 13-41 32182 Group User’s Manual (Rev.1.0) 13 CAN1ERIST (H'0080 1414) CAN1ERIEN (H'0080 1415) CAN bus error occurs Data bus b5 b13 BEIS F/F BEIEN F/F CAN MODULE 13.2 CAN Module Related Registers 19-source inputs (Level) To the preceding page Go to error passive state EPIS F/F EPIEN F/F b6 b14 Go to bus off state b7 b15 EOIS F/F EOIEN F/F To the remaining 16-source inputs in the next page Figure 13.2.10 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (3/5) 13-42 32182 Group User’s Manual (Rev.1.0) 13 CAN1SSIST (H'0080 1444) CAN1SSIEN (H'0080 1488) Slot 0 arbitration-lost/transmit error occurs Data bus b0 b0 SSIST0 F/F SSIEN0 F/F CAN MODULE 13.2 CAN Module Related Registers 16-source inputs To the preceding page (Level) Slot 1 arbitration-lost/transmit error occurs SSIST1 F/F SSIEN1 F/F b1 b1 Slot 2 arbitration-lost/transmit error occurs SSIST2 F/F SSIEN2 F/F b2 b2 Slot 3 arbitration-lost/transmit error occurs SSIST3 F/F SSIEN3 F/F b3 b3 Slot 4 arbitration-lost/transmit error occurs SSIST4 F/F SSIEN4 F/F b4 b4 Slot 5 arbitration-lost/transmit error occurs SSIST5 F/F SSIEN5 F/F b5 b5 Slot 6 arbitration-lost/transmit error occurs SSIST6 F/F SSIEN6 F/F b6 b6 Slot 7 arbitration-lost/transmit error occurs SSIST7 F/F SSIEN7 F/F b7 b7 To the remaining 8-source inputs in the next page Figure 13.2.11 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (4/5) 13-43 32182 Group User’s Manual (Rev.1.0) 13 CAN1SSIST (H'0080 1444) CAN1SSIEN (H'0080 1488) Slot 8 arbitration-lost/transmit error occurs Data bus b8 b8 SSIST8 F/F SSIEN8 F/F CAN MODULE 13.2 CAN Module Related Registers 8-source inputs (Level) To the preceding page Slot 9 arbitration-lost/transmit error occurs SSIST9 F/F SSIEN9 F/F b9 b9 Slot 10 arbitration-lost/transmit error occurs SSIST10 F/F SSIEN10 F/F b10 b10 Slot 11 arbitration-lost/transmit error occurs SSIST11 F/F SSIEN11 F/F b11 b11 Slot 12 arbitration-lost/transmit error occurs SSIST12 F/F SSIEN12 F/F b12 b12 Slot 13 arbitration-lost/transmit error occurs SSIST13 F/F SSIEN13 F/F b13 b13 Slot 14 arbitration-lost/transmit error occurs SSIST14 F/F SSIEN14 F/F b14 b14 Slot 15 arbitration-lost/transmit error occurs SSIST15 F/F SSIEN15 F/F b15 b15 Figure 13.2.12 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (5/5) 13-44 32182 Group User’s Manual (Rev.1.0) 13 13.2.9 CAN Cause of Error Registers CAN0 Cause of Error Register (CAN0EF) CAN1 Cause of Error Register (CAN1EF) b8 0 CAN MODULE 13.2 CAN Module Related Registers 14 0 9 0 10 ETR 0 11 BITE 0 12 0 13 0 b15 ACKE 0 STFE FORME CRCE b 8–9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". ETR Transmit/receive error judgment bit BITE Bit error detection bit STFE Stuff error detection bit FORME Form error detection bit CRCE CRC error detection bit ACKE ACK error detection bit 0: Error detected when sending 1: Error detected when receiving 0: Bit error not detected 1: Bit error detected 0: Stuff error not detected 1: Stuff error detected 0: Form error not detected 1: Form error detected 0: CRC error not detected 1: CRC error detected 0: ACK error not detected 1: ACK error detected R R R – – – Function R 0 R R R W 0 – – – This register indicates error information when a communication error occurred. (1) ETR (Transmit/Receive Error Judgement) bit (Bit 10) This bit is set to "1" if the CAN module was operating as a reception node when a communication error occurred. The bit is cleared to "0" by a read of this register. (2) BITE (Bit Error Detection) bit (Bit 11) This bit is set to "1" when a bit error was detected. The bit is cleared to "0" by a read of this register. (3) STFE (Stuff Error Detection) bit (Bit 12) This bit is set to "1" when a stuff error was detected. The bit is cleared to "0" by a read of this register. (4) FORME (Form Error Detection) bit (Bit 13) This bit is set to "1" when a form error was detected. The bit is cleared to "0" by a read of this register. (5) CRCE (CRC Error Detection) bit (Bit 14) This bit is set to "1" when a CRC error was detected. The bit is cleared to "0" by a read of this register. (6) ACKE (ACK Error Detection) bit (Bit 15) This bit is set to "1" when an ACK error was detected. The bit is cleared to "0" by a read of this register. Note: • Depending on the error status, two or more bits may be set at the same time. 13-45 32182 Group User’s Manual (Rev.1.0) 13 13.2.10 CAN Mode Registers CAN0 Mode Register (CAN0MOD) CAN1 Mode Register (CAN1MOD) b0 0 CAN MODULE 13.2 CAN Module Related Registers 5 0 1 0 2 0 3 0 4 0 6 0 b7 CMOD 0 b 0–5 6–7 Bit Name No function assigned. Fix to "0". CMOD CAN operation mode select bit 00: 01: 10: 11: Normal mode Bus monitor mode Self-diagnostic mode Settings inhibited Function R 0 R W 0 W (1) CMOD (CAN Operation Mode Select) bits (Bit 6, Bit 7) These bits select the CAN operation mode. • Normal operation mode Normal transmit/receive operations can be performed. • Bus monitor mode Only receive operation is performed. During bus monitor mode, the CTX output is fixed high and neither ACK nor an error frame can be returned. Note: • During bus monitor mode, issuing transmit requests is inhibited. The ACK bit is handled as “Don’t care” during bus monitor mode. Therefore, if all bits of data including the CRC delimiter are received normally, it is assumed that data has been received normally no matter whether the ACK bit is high. • Self-diagnostic mode CTX and CRX are connected together internally in the CAN module. When combined with loopback mode, this mode allows communication to be performed within the CAN module alone. During selfdiagnostic mode, the CTX pin output is fixed high even when transmitting. M32R/ECU CAN module Self-diagnostic mode Rx CRX pin Ack signal generating circuit Tx CTX pin Figure 13.2.13 Conceptual Diagram of Self-Diagnostic Mode 13-46 32182 Group User’s Manual (Rev.1.0) 13 CAN0 DMA Transfer Request Select Register (CAN0DMARQ) b8 0 CAN MODULE 13.2 CAN Module Related Registers 13.2.11 CAN DMA Transfer Request Select Register 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 CDMSEL1 CDMSEL0 b 8–13 14 15 Bit Name No function assigned. Fix to "0". CDMSEL1 CAN DMA1 transfer request source select bit CDMSEL0 CAN DMA0 transfer request source select bit 0: Slot 1 transmission failed 1: Slot 14 transmission/reception completed 0: Slot 0 transmission failed 1: Slot 15 transmission/reception completed Function R 0 R R W 0 W W CAN0 can generate DMA transfer requests. This register is used to select the cause or source of that request. (1) CDMSEL1 (CAN DMA1 Transfer Request Source Select) bit (Bit 14) This bit selects one of the following two as the cause or source of a transfer request to DMA2. • Slot 1 transmission failed If the CDMSEL1 bit is set to "0", a transfer request is generated when transmission in slot 1 has failed for reasons of arbitration-lost or transmit error. • Slot 14 transmission/reception completed If the CDMSEL1 bit is set to "1", a transfer request is generated when transmission/reception in slot 14 is completed. Notes: • If slot 14 has been set for remote frame transmission, a DMA transfer request is generated when remote frame transmission is completed as well as when data frame reception is completed. • If slot 14 has been set for remote frame reception (automatic response), a DMA transfer request is generated when remote frame reception is completed as well as when data frame transmission is completed. Note: • CAN1 does not have the DMA transfer request function. (2) CDMSEL0 (CAN DMA0 Transfer Request Source Select) bit (Bit 15) This bit selects one of the following two as the cause or source of a transfer request to DMA0. • Slot 0 transmission failed If the CDMSEL0 bit is set to "0", a transfer request is generated when transmission in slot 0 has failed for reasons of arbitration-lost or transmit error. • Slot 15 transmission/reception completed If the CDMSEL0 bit is set to "1", a transfer request is generated when transmission/reception in slot 15 is completed. Notes: • If slot 15 has been set for remote frame transmission, a DMA transfer request is generated when remote frame transmission is completed as well as when data frame reception is completed. • If slot 15 has been set for remote frame reception (automatic response), a DMA transfer request is generated when remote frame reception is completed as well as when data frame transmission is completed. 13-47 32182 Group User’s Manual (Rev.1.0) 13 13.2.12 CAN Mask Registers CAN0 Global Mask Register Standard ID0 (C0GMSKS0) CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) CAN1 Global Mask Register Standard ID0 (C1GMSKS0) CAN1 Local Mask Register A Standard ID0 (C1LMSKAS0) CAN1 Local Mask Register B Standard ID0 (C1LMSKBS0) b0 0 CAN MODULE 13.2 CAN Module Related Registers 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 SID0M SID1M SID2M SID3M SID4M b 0–2 3–7 Bit Name No function assigned. Fix to "0". SID0M–SID4M (Standard mask ID0–standard mask ID4) 0: ID not checked 1: ID checked Function R 0 R W 0 W CAN0 Global Mask Register Standard ID1 (C0GMSKS1) CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1) CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1) CAN1 Global Mask Register Standard ID1 (C1GMSKS1) CAN1 Local Mask Register A Standard ID1 (C1LMSKAS1) CAN1 Local Mask Register B Standard ID1 (C1LMSKBS1) b8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 SID5M SID6M SID7M SID8M SID9M SID10M b 8–9 10–15 Bit Name No function assigned. Fix to "0". SID5M–SID10M (Standard mask ID5–standard mask ID10) 0: ID not checked 1: ID checked Function R 0 R W 0 W Three mask registers are used in acceptance filtering: global mask register, local mask register A and local mask register B. The global mask register is used for message slots 0-13, while local mask registers A and B are used for message slots 14 and 15, respectively. • If any bit in this register is set to "0", the corresponding ID bit is masked (assumed to have matched) during acceptance filtering. • If any bit in this register is set to "1", the corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set in the message slot, the received data is stored in it. Notes: • SID0M corresponds to the MSB of the standard ID. • The global mask register can only be modified when none of slots 0-13 have receive requests set. • The local mask register A can only be modified when slot 14 does not have a receive request set. • The local mask register B can only be modified when slot 15 does not have a receive request set. 13-48 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Global Mask Register Extended ID0 (C0GMSKE0) CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) CAN1 Global Mask Register Extended ID0 (C1GMSKE0) CAN1 Local Mask Register A Extended ID0 (C1LMSKAE0) CAN1 Local Mask Register B Extended ID0 (C1LMSKBE0) b0 0 CAN MODULE 13.2 CAN Module Related Registers 1 0 2 0 3 0 4 EID0M 0 5 0 6 0 b7 0 EID1M EID2M EID3M b 0–3 4–7 Bit Name No function assigned. Fix to "0". EID0M–EID3M (Extended mask ID0–extended mask ID3) 0: ID not checked 1: ID checked Function R 0 R W 0 W CAN0 Global Mask Register Extended ID1 (C0GMSKE1) CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1) CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1) CAN1 Global Mask Register Extended ID1 (C1GMSKE1) CAN1 Local Mask Register A Extended ID1 (C1LMSKAE1) CAN1 Local Mask Register B Extended ID1 (C1LMSKBE1) b8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 EID4M EID5M EID6M EID7M EID8M EID9M EID10M EID11M b 8–15 Bit Name EID4M–EID11M (Extended mask ID4–extended mask ID11) Function 0: ID not checked 1: ID checked R R W W 13-49 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Global Mask Register Extended ID2 (C0GMSKE2) CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) CAN1 Global Mask Register Extended ID2 (C1GMSKE2) CAN1 Local Mask Register A Extended ID2 (C1LMSKAE2) CAN1 Local Mask Register B Extended ID2 (C1LMSKBE2) b0 0 CAN MODULE 13.2 CAN Module Related Registers 1 0 2 0 3 0 4 0 5 0 6 0 B7 0 EID12M EID13M EID14M EID15M EID16M EID17M b 0,1 2–7 Bit Name No function assigned. Fix to "0". EID12M–EID17M (Extended mask ID12–extended mask ID17) 0: ID not checked 1: ID checked Function R 0 R W 0 W Three mask registers are used in acceptance filtering: global mask register, local mask register A and local mask register B. The global mask register is used for message slots 0-13, while local mask registers A and B are used for message slots 14 and 15, respectively. • If any bit in this register is set to "0", the corresponding ID bit is masked (assumed to have matched) during acceptance filtering. • If any bit in this register is set to "1", the corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set in the message slot, the received data is stored in it. Notes: • EID0M corresponds to the MSB of the extended ID. • The global mask register can only be modified when none of slots 0-13 have receive requests set. • The local mask register A can only be modified when slot 14 does not have a receive request set. • The local mask register B can only be modified when slot 15 does not have a receive request set. 13-50 32182 Group User’s Manual (Rev.1.0) 13 Slot 0 Slot 1 CAN MODULE 13.2 CAN Module Related Registers Slots controlled by the global mask register Slot 2 Slot 13 Slot 14 Slot 15 Slot controlled by local mask register A Slot controlled by local mask register B Figure 13.2.14 Relationship between the Mask Registers and the Controlled Slots Mask bit value ID of received frame ID set in slot Mask register set value 0: The received message and slot IDs are not checked for matching and handled as "Don't care" (masked) 1: The received message and slot IDs are checked for matching Acceptance judgment signal Acceptance judgment signal 0: The received message is ignored (not stored in any slot) 1: The received message is stored in the slot that has the matching ID Figure 13.2.15 Concept of Acceptance Filtering 13-51 32182 Group User’s Manual (Rev.1.0) 13 13.2.13 CAN Single-Shot Mode Control Registers CAN0 Single-Shot Mode Control Register (CAN0SSMODE) CAN1 Single-Shot Mode Control Register (CAN1SSMODE) b0 0 CAN MODULE 13.2 CAN Module Related Registers 8 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 SSCNT0 SSCNT1 SSCNT2 SSCNT3 SSCNT4 SSCNT5 SSCNT6 SSCNT7 SSCNT8 SSCNT9 SSCNT10 SSCNT11 SSCNT12 SSCNT13 SSCNT14 SSCNT15 b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name SSCNT0 (Slot 0 single-shot mode bit) SSCNT1 (Slot 1 single-shot mode bit) SSCNT2 (Slot 2 single-shot mode bit) SSCNT3 (Slot 3 single-shot mode bit) SSCNT4 (Slot 4 single-shot mode bit) SSCNT5 (Slot 5 single-shot mode bit) SSCNT6 (Slot 6 single-shot mode bit) SSCNT7 (Slot 7 single-shot mode bit) SSCNT8 (Slot 8 single-shot mode bit) SSCNT9 (Slot 9 single-shot mode bit) SSCNT10 (Slot 10 single-shot mode bit) SSCNT11 (Slot 11 single-shot mode bit) SSCNT12 (Slot 12 single-shot mode bit) SSCNT13 (Slot 13 single-shot mode bit) SSCNT14 (Slot 14 single-shot mode bit) SSCNT15 (Slot 15 single-shot mode bit) Function 0: Normal mode 1: Single-shot mode R R W W Normally in CAN, if transmission has failed for reasons of arbitration-lost or transmit error, the transmit operation is continued until successfully transmitted. This register is used to specify for each slot whether or not to retry a transmit operation in such a case. In single-shot mode, if transmission fails for reasons of arbitration-lost or transmit error, the transmit operation is not retried. If any bit in this register is set to "1", the corresponding slot operates in single-shot mode. Note: • Settings of this register can only be changed when the message slot control register for the slot whose corresponding bit is to be modified is in the H’00 state. 13-52 32182 Group User’s Manual (Rev.1.0) 13 13.2.14 CAN Message Slot Control Registers CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Slot 0 Control Register (C0MSL0CNT) Slot 1 Control Register (C0MSL1CNT) Slot 2 Control Register (C0MSL2CNT) Slot 3 Control Register (C0MSL3CNT) Slot 4 Control Register (C0MSL4CNT) Slot 5 Control Register (C0MSL5CNT) Slot 6 Control Register (C0MSL6CNT) Slot 7 Control Register (C0MSL7CNT) Slot 8 Control Register (C0MSL8CNT) Slot 9 Control Register (C0MSL9CNT) Slot 10 Control Register (C0MSL10CNT) Slot 11 Control Register (C0MSL11CNT) Slot12 Control Register (C0MSL12CNT) Slot 13 Control Register (C0MSL13CNT) Slot 14 Control Register (C0MSL14CNT) Slot 15 Control Register (C0MSL15CNT) Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot 0 Control Register (C1MSL0CNT) 1 Control Register (C1MSL1CNT) 2 Control Register (C1MSL2CNT) 3 Control Register (C1MSL3CNT) 4 Control Register (C1MSL4CNT) 5 Control Register (C1MSL5CNT) 6 Control Register (C1MSL6CNT) 7 Control Register (C1MSL7CNT) 8 Control Register (C1MSL8CNT) 9 Control Register (C1MSL9CNT) 10 Control Register (C1MSL10CNT) 11 Control Register (C1MSL11CNT) 12 Control Register (C1MSL12CNT) 13 Control Register (C1MSL13CNT) 14 Control Register (C1MSL14CNT) 15 Control Register (C1MSL15CNT) CAN MODULE 13.2 CAN Module Related Registers 13-53 32182 Group User’s Manual (Rev.1.0) 13 b0(b8) TR 0 1 RR 0 2 RM 0 3 RL 0 4 RA 0 5 ML 0 6 0 b7(b15) 0 TRSTAT TRFIN CAN MODULE 13.2 CAN Module Related Registers b 0 1 2 3 4 Bit Name TR Transmit request bit RR Receive request bit RM Remote bit RL Automatic response inhibit bit RA Remote active bit Function 0: Do not use the message slot as transmit slot 1: Use the message slot as transmit slot 0: Do not use the message slot as receive slot 1: Use the message slot as receive slot 0: Transmit/receive data frame 1: Transmit/receive remote frame 0: Enable automatic response for remote frame 1: Disable automatic response for remote frame During BasicCAN mode 0: Receive data frame (status) 1: Receive remote frame (status) During normal mode 0: Data frame 1: Remote frame 0: No message was lost 1: Message was lost During a transmit slot 0: Transmission idle 1: Transmit request accepted During a receive slot 0: Reception idle 1: Storing received data During a transmit slot 0: Not transmitted yet 1: Finished transmitting During a receive slot 0: Not received yet 1: Finished receiving R R W – R R R R W W W W 5 6 ML Message lost bit TRSTAT Transmit/receive status bit R(Note 1) R – 7 TRFIN Transmission/reception finished bit R(Note 1) Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. Notes: • If a transmit request is written to this register while the CAN module is reset (CANnCNT FRST or RST bit = "1"), it starts sending upon detecting 11 consecutive recessive bits on the CAN bus after exiting the reset state. • If data/remote frame transmit requests are issued for two or more slots, the slot with the smallest slot number sends a frame. If data/remote frame receive requests are issued for two or more slots, the slot with the smallest slot number among the slots satisfying the receive condition receives a frame. • If transmission failed when single-shot mode is selected, this register is cleared to H’00. (1) TR (Transmit Request) bit (Bit 0) To use the message slot as a transmit slot, set this bit to "1". To use the message slot as a data frame or remote frame receive slot, set this bit to "0". 13-54 32182 Group User’s Manual (Rev.1.0) 13 (2) RR (Receive Request) bit (Bit 1) CAN MODULE 13.2 CAN Module Related Registers To use the message slot as a receive slot, set this bit to "1". To use the message slot as a data frame or remote frame transmit slot, set this bit to "0". If TR (Transmit Request) bit and RR (Receive Request) bit both are set to "1", device operation is undefined. (3) RM (Remote) bit (Bit 2) To handle remote frames in the message slot, set this bit to "1". There are following two methods of settings to handle remote frames: • Set for remote frame transmission The data set in the message slot is transmitted as a remote frame. When the CAN module finished sending, the slot automatically changes to a data frame receive slot. However, if a data frame is received before the CAN module finished sending a remote frame, the received data is stored in the message slot and the remote frame is not transmitted. • Set for remote frame reception Remote frames are received. The processing to be performed after receiving a remote frame is selected by RL (automatic response inhibit) bit. (4) RL (Automatic Response Inhibit) bit (Bit 3) This bit is effective when the message slot has been set as a remote frame receive slot. It selects the processing to be performed after receiving a remote frame. If this bit is set to "0", the message slot automatically changes to a transmit slot after receiving a remote frame and transmits the data set in it as a data frame. If this bit is set to "1", the message slot stops operating after receiving a remote frame. Note: • Always set this bit to "0" unless the message slot is set for remote frame reception. (5) RA (Remote Active) bit (Bit 4) This bit functions differently for slots 0-13 and slots 14 and 15. • Slots 0–13 This bit is set to "1" when the message slot is set for remote frame transmission (reception). Then, when remote frame transmission (reception) is completed, the bit is cleared to "0". • Slots 14 and 15 The function of this bit differs depending on how the CAN Control Register BCM (BasicCAN Mode) bit is set. If BCM = "0" (normal operation), this bit is set to "1" when the message slot is set for remote frame transmission (reception). If BCM = "1" (BasicCAN), this bit indicates which type of frame is received. During BasicCAN mode, the received data is stored in slots 14 and 15 for both data and remote frames. If RA = "0", it means that the frame stored in the slot is a data frame. If RA = "1", it means that the frame stored in the slot is a remote frame. (6) ML (Message Lost) bit (Bit 5) This bit is effective for receive slots. It is set to "1" when unread received data contained in the message slot is overwritten by reception. This bit is cleared by writing "0" in software. 13-55 32182 Group User’s Manual (Rev.1.0) 13 (7) TRSTAT (Transmit/Receive Status) bit (Bit 6) CAN MODULE 13.2 CAN Module Related Registers This bit indicates that the CAN module is sending or receiving and is accessing the message slot. This bit is set to "1" when the CAN module is accessing, and set to "0" when not accessing. • During a transmit slot This bit is set to "1" when a transmit request for the message slot is accepted. It is cleared to "0" when the CAN module lost in bus arbitration, when a CAN bus error occurs, or when transmission is completed. • During a receive slot This bit is set to "1" while the CAN module is receiving data, with the received data being stored in the message slot. Note that the value read from the message slot while the TRSTAT bit remains set is undefined. (8) TRFIN (Transmit/Receive Finished) bit (Bit 7) This bit indicates that the CAN module finished sending or receiving. • When set for a transmit slot This bit is set to "1" when the CAN module finished sending the data stored in the message slot. This bit is cleared by writing "0" in software. However, it cannot be cleared when the TRSTAT (Transmit/ Receive Status) bit = "1". • When set for a receive slot This bit is set to "1" when the CAN module finished receiving normally the data to be stored in the message slot. This bit is cleared by writing "0" in software. However, it cannot be cleared when the TRSTAT (Transmit/Receive Status) bit = "1". Notes: • Before reading the received data out of the message slot, be sure to clear the TRFIN (Transmit/Receive Finished) bit to "0". If the TRFIN (Transmit/Receive Finished) bit happens to be set to "1" after a read, it means that new received data was stored while reading and the read data contains an undefined value. In that case, discard the read data, clear the TRFIN bit to "0" and read out data again. • When sending/receiving remote frames, the TRFIN bit is automatically cleared to "0" by hardware. Therefore, the TRFIN bit cannot be used as a transmission/reception-finished flag. 13-56 32182 Group User’s Manual (Rev.1.0) 13 13.2.15 CAN Message Slots CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 1 ? CAN MODULE 13.2 CAN Module Related Registers Slot 0 Standard ID0 (C0MSL0SID0) Slot 1 Standard ID0 (C0MSL1SID0) Slot 2 Standard ID0 (C0MSL2SID0) Slot 3 Standard ID0 (C0MSL3SID0) Slot 4 Standard ID0 (C0MSL4SID0) Slot 5 Standard ID0 (C0MSL5SID0) Slot 6 Standard ID0 (C0MSL6SID0) Slot 7 Standard ID0 (C0MSL7SID0) Slot 8 Standard ID0 (C0MSL8SID0) Slot 9 Standard ID0 (C0MSL9SID0) Slot 10 Standard ID0 (C0MSL10SID0) Slot 11 Standard ID0 (C0MSL11SID0) Slot 12 Standard ID0 (C0MSL12SID0) Slot 13 Standard ID0 (C0MSL13SID0) Slot 14 Standard ID0 (C0MSL14SID0) Slot 15 Standard ID0 (C0MSL15SID0) Slot 0 Standard ID0 (C1MSL0SID0) Slot 1 Standard ID0 (C1MSL1SID0) Slot 2 Standard ID0 (C1MSL2SID0) Slot 3 Standard ID0 (C1MSL3SID0) Slot 4 Standard ID0 (C1MSL4SID0) Slot 5 Standard ID0 (C1MSL5SID0) Slot 6 Standard ID0 (C1MSL6SID0) Slot 7 Standard ID0 (C1MSL7SID0) Slot 8 Standard ID0 (C1MSL8SID0) Slot 9 Standard ID0 (C1MSL9SID0) Slot 10 Standard ID0 (C1MSL10SID0) Slot 11 Standard ID0 (C1MSL11SID0) Slot 12 Standard ID0 (C1MSL12SID0) Slot 13 Standard ID0 (C1MSL13SID0) Slot 14 Standard ID0 (C1MSL14SID0) Slot 15 Standard ID0 (C1MSL15SID0) 2 ? b0 ? 3 SID0 ? 4 SID1 ? 5 SID2 ? 6 SID3 ? b7 SID4 ? b 0–2 3–7 Bit Name No function assigned. Fix to "0". SID0–SID4 (Standard ID0–standard ID4) Standard ID0–standard ID4 Function R 0 R W 0 W These registers are the memory space for transmit and receive frames. 13-57 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 9 ? CAN MODULE 13.2 CAN Module Related Registers Slot 0 Standard ID1 (C0MSL0SID1) Slot 1 Standard ID1 (C0MSL1SID1) Slot 2 Standard ID1 (C0MSL2SID1) Slot 3 Standard ID1 (C0MSL3SID1) Slot 4 Standard ID1 (C0MSL4SID1) Slot 5 Standard ID1 (C0MSL5SID1) Slot 6 Standard ID1 (C0MSL6SID1) Slot 7 Standard ID1 (C0MSL7SID1) Slot 8 Standard ID1 (C0MSL8SID1) Slot 9 Standard ID1 (C0MSL9SID1) Slot 10 Standard ID1 (C0MSL10SID1) Slot 11 Standard ID1 (C0MSL11SID1) Slot 12 Standard ID1 (C0MSL12SID1) Slot 13 Standard ID1 (C0MSL13SID1) Slot 14 Standard ID1 (C0MSL14SID1) Slot 15 Standard ID1 (C0MSL15SID1) Slot 0 Standard ID1 (C1MSL0SID1) Slot 1 Standard ID1 (C1MSL1SID1) Slot 2 Standard ID1 (C1MSL2SID1) Slot 3 Standard ID1 (C1MSL3SID1) Slot 4 Standard ID1 (C1MSL4SID1) Slot 5 Standard ID1 (C1MSL5SID1) Slot 6 Standard ID1 (C1MSL6SID1) Slot 7 Standard ID1 (C1MSL7SID1) Slot 8 Standard ID1 (C1MSL8SID1) Slot 9 Standard ID1 (C1MSL9SID1) Slot 10 Standard ID1 (C1MSL10SID1) Slot 11 Standard ID1 (C1MSL11SID1) Slot 12 Standard ID1 (C1MSL12SID1) Slot 13 Standard ID1 (C1MSL13SID1) Slot 14 Standard ID1 (C1MSL14SID1) Slot 15 Standard ID1 (C1MSL15SID1) 10 SID5 ? ? b8 11 SID6 ? 12 SID7 ? 13 SID8 ? 14 SID9 ? b15 SID10 ? b 8, 9 10–15 Bit Name No function assigned. Fix to "0". SID5–SID10 (Standard ID5–standard ID10) Standard ID5–standard ID10 Function R 0 R W 0 W These registers are the memory space for transmit and receive frames. 13-58 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 1 ? CAN MODULE 13.2 CAN Module Related Registers Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot 2 ? 0 Extended ID0 (C0MSL0EID0) 1 Extended ID0 (C0MSL1EID0) 2 Extended ID0 (C0MSL2EID0) 3 Extended ID0 (C0MSL3EID0) 4 Extended ID0 (C0MSL4EID0) 5 Extended ID0 (C0MSL5EID0) 6 Extended ID0 (C0MSL6EID0) 7 Extended ID0 (C0MSL7EID0) 8 Extended ID0 (C0MSL8EID0) 9 Extended ID0 (C0MSL9EID0) 10 Extended ID0 (C0MSL10EID0) 11 Extended ID0 (C0MSL11EID0) 12 Extended ID0 (C0MSL12EID0) 13 Extended ID0 (C0MSL13EID0) 14 Extended ID0 (C0MSL14EID0) 15 Extended ID0 (C0MSL15EID0) 0 Extended ID0 (C1MSL0EID0) 1 Extended ID0 (C1MSL1EID0) 2 Extended ID0 (C1MSL2EID0) 3 Extended ID0 (C1MSL3EID0) 4 Extended ID0 (C1MSL4EID0) 5 Extended ID0 (C1MSL5EID0) 6 Extended ID0 (C1MSL6EID0) 7 Extended ID0 (C1MSL7EID0) 8 Extended ID0 (C1MSL8EID0) 9 Extended ID0 (C1MSL9EID0) 10 Extended ID0 (C1MSL10EID0) 11 Extended ID0 (C1MSL11EID0) 12 Extended ID0 (C1MSL12EID0) 13 Extended ID0 (C1MSL13EID0) 14 Extended ID0 (C1MSL14EID0) 15 Extended ID0 (C1MSL15EID0) 3 ? b0 ? 4 EID0 ? 5 EID1 ? 6 EID2 ? b7 EID3 ? b 0–3 4–7 Bit Name No function assigned. Fix to "0". EID0–EID3 (Extended ID0–extended ID3) Extended ID0–extended ID3 Function R 0 R W 0 W These registers are the memory space for transmit and receive frames. Note: • If the message slot is set for the receive slot standard ID format, an undefined value is written to the EID bits when storing received data. 13-59 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 9 EID5 ? CAN MODULE 13.2 CAN Module Related Registers Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot 10 EID6 ? 0 Extended ID1 (C0MSL0EID1) 1 Extended ID1 (C0MSL1EID1) 2 Extended ID1 (C0MSL2EID1) 3 Extended ID1 (C0MSL3EID1) 4 Extended ID1 (C0MSL4EID1) 5 Extended ID1 (C0MSL5EID1) 6 Extended ID1 (C0MSL6EID1) 7 Extended ID1 (C0MSL7EID1) 8 Extended ID1 (C0MSL8EID1) 9 Extended ID1 (C0MSL9EID1) 10 Extended ID1 (C0MSL10EID1) 11 Extended ID1 (C0MSL11EID1) 12 Extended ID1 (C0MSL12EID1) 13 Extended ID1 (C0MSL13EID1) 14 Extended ID1 (C0MSL14EID1) 15 Extended ID1 (C0MSL15EID1) 0 Extended ID1 (C1MSL0EID1) 1 Extended ID1 (C1MSL1EID1) 2 Extended ID1 (C1MSL2EID1) 3 Extended ID1 (C1MSL3EID1) 4 Extended ID1 (C1MSL4EID1) 5 Extended ID1 (C1MSL5EID1) 6 Extended ID1 (C1MSL6EID1) 7 Extended ID1 (C1MSL7EID1) 8 Extended ID1 (C1MSL8EID1) 9 Extended ID1 (C1MSL9EID1) 10 Extended ID1 (C1MSL10EID1) 11 Extended ID1 (C1MSL11EID1) 12 Extended ID1 (C1MSL12EID1) 13 Extended ID1 (C1MSL13EID1) 14 Extended ID1 (C1MSL14EID1) 15 Extended ID1 (C1MSL15EID1) 11 EID7 ? b8 EID4 ? 12 EID8 ? 13 EID9 ? 14 EID10 ? b15 EID11 ? b 8–15 Bit Name EID4–EID11 (Extended ID4–extended ID11) Function Extended ID4–extended ID11 R R W W These registers are the memory space for transmit and receive frames. Note: • If the message slot is set for the receive slot standard ID format, an undefined value is written to the EID bits when storing received data. 13-60 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 1 ? CAN MODULE 13.2 CAN Module Related Registers Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot 2 EID12 ? ? 0 Extended ID2 (C0MSL0EID2) 1 Extended ID2 (C0MSL1EID2) 2 Extended ID2 (C0MSL2EID2) 3 Extended ID2 (C0MSL3EID2) 4 Extended ID2 (C0MSL4EID2) 5 Extended ID2 (C0MSL5EID2) 6 Extended ID2 (C0MSL6EID2) 7 Extended ID2 (C0MSL7EID2) 8 Extended ID2 (C0MSL8EID2) 9 Extended ID2 (C0MSL9EID2) 10 Extended ID2 (C0MSL10EID2) 11 Extended ID2 (C0MSL11EID2) 12 Extended ID2 (C0MSL12EID2) 13 Extended ID2 (C0MSL13EID2) 14 Extended ID2 (C0MSL14EID2) 15 Extended ID2 (C0MSL15EID2) 0 Extended ID2 (C1MSL0EID2) 1 Extended ID2 (C1MSL1EID2) 2 Extended ID2 (C1MSL2EID2) 3 Extended ID2 (C1MSL3EID2) 4 Extended ID2 (C1MSL4EID2) 5 Extended ID2 (C1MSL5EID2) 6 Extended ID2 (C1MSL6EID2) 7 Extended ID2 (C1MSL7EID2) 8 Extended ID2 (C1MSL8EID2) 9 Extended ID2 (C1MSL9EID2) 10 Extended ID2 (C1MSL10EID2) 11 Extended ID2 (C1MSL11EID2) 12 Extended ID2 (C1MSL12EID2) 13 Extended ID2 (C1MSL13EID2) 14 Extended ID2 (C1MSL14EID2) 15 Extended ID2 (C1MSL15EID2) 3 EID13 ? b0 4 EID14 ? 5 EID15 ? 6 EID16 ? b7 EID17 ? b 0, 1 2–7 Bit Name No function assigned. Fix to "0". EID12–EID17 (Extended ID12–extended ID17) Extended ID12–extended ID17 Function R 0 R W 0 W These registers are the memory space for transmit and receive frames. Note: • If the message slot is set for the receive slot standard ID format, an undefined value is written to the EID bits when storing received data. 13-61 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 9 ? CAN MODULE 13.2 CAN Module Related Registers Slot 0 Data Length Register (C0MSL0DLC) Slot 1 Data Length Register (C0MSL1DLC) Slot 2 Data Length Register (C0MSL2DLC) Slot 3 Data Length Register (C0MSL3DLC) Slot 4 Data Length Register (C0MSL4DLC) Slot 5 Data Length Register (C0MSL5DLC) Slot 6 Data Length Register (C0MSL6DLC) Slot 7 Data Length Register (C0MSL7DLC) Slot 8 Data Length Register (C0MSL8DLC) Slot 9 Data Length Register (C0MSL9DLC) Slot 10 Data Length Register (C0MSL10DLC) Slot 11 Data Length Register (C0MSL11DLC) Slot 12 Data Length Register (C0MSL12DLC) Slot 13 Data Length Register (C0MSL13DLC) Slot 14 Data Length Register (C0MSL14DLC) Slot 15 Data Length Register (C0MSL15DLC) Slot 0 Data Length Register (C1MSL0DLC) Slot 1 Data Length Register (C1MSL1DLC) Slot 2 Data Length Register (C1MSL2DLC) Slot 3 Data Length Register (C1MSL3DLC) Slot 4 Data Length Register (C1MSL4DLC) Slot 5 Data Length Register (C1MSL5DLC) Slot 6 Data Length Register (C1MSL6DLC) Slot 7 Data Length Register (C1MSL7DLC) Slot 8 Data Length Register (C1MSL8DLC) Slot 9 Data Length Register (C1MSL9DLC) Slot 10 Data Length Register (C1MSL10DLC) Slot 11 Data Length Register (C1MSL11DLC) Slot 12 Data Length Register (C1MSL12DLC) Slot 13 Data Length Register (C1MSL13DLC) Slot 14 Data Length Register (C1MSL14DLC) Slot 15 Data Length Register (C1MSL15DLC) 10 ? b8 ? 11 ? 12 DLC0 ? 13 DLC1 ? 14 DLC2 ? b15 DLC3 ? b 8–11 12–15 Bit Name No function assigned. Fix to "0". DLC0–DLC3 Data length setting bit 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: | 0 1 2 3 4 5 6 7 8 bytes bytes bytes bytes bytes bytes bytes bytes bytes | Function R 0 R W 0 W 1111: 8 bytes These registers are the memory space for transmit and receive frames. When sending, the register is used to set the transmit data length. When receiving, the register is used to store the receive frame DLC. 13-62 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 1 ? CAN MODULE 13.2 CAN Module Related Registers Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot 2 ? 0 Data 0 (C0MSL0DT0) 1 Data 0 (C0MSL1DT0) 2 Data 0 (C0MSL2DT0) 3 Data 0 (C0MSL3DT0) 4 Data 0 (C0MSL4DT0) 5 Data 0 (C0MSL5DT0) 6 Data 0 (C0MSL6DT0) 7 Data 0 (C0MSL7DT0) 8 Data 0 (C0MSL8DT0) 9 Data 0 (C0MSL9DT0) 10 Data 0 (C0MSL10DT0) 11 Data 0 (C0MSL11DT0) 12 Data 0 (C0MSL12DT0) 13 Data 0 (C0MSL13DT0) 14 Data 0 (C0MSL14DT0) 15 Data 0 (C0MSL15DT0) 0 Data 0 (C1MSL0DT0) 1 Data 0 (C1MSL1DT0) 2 Data 0 (C1MSL2DT0) 3 Data 0 (C1MSL3DT0) 4 Data 0 (C1MSL4DT0) 5 Data 0 (C1MSL5DT0) 6 Data 0 (C1MSL6DT0) 7 Data 0 (C1MSL7DT0) 8 Data 0 (C1MSL8DT0) 9 Data 0 (C1MSL9DT0) 10 Data 0 (C1MSL10DT0) 11 Data 0 (C1MSL11DT0) 12 Data 0 (C1MSL12DT0) 13 Data 0 (C1MSL13DT0) 14 Data 0 (C1MSL14DT0) 15 Data 0 (C1MSL15DT0) 3 ? D7 ? D0 ? 4 ? 5 ? 6 ? C0MSL0DT0–C0MSL15DT0, C1MSL0DT0–C1MSL15DT0 b 0–7 Bit Name C0MSL0DT0–C0MSL15DT0, C1MSL0DT0–C1MSL15DT0 Function Message slot data 0 R R W W These registers are the memory space for transmit and receive frames. Notes: • During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) = "0". • The first byte of the CAN frame data field corresponds to message slot n data 0. Data is transmitted or received beginning with the MSB side of the register. 13-63 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 9 ? CAN MODULE 13.2 CAN Module Related Registers Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot 10 ? 0 Data 1 (C0MSL0DT1) 1 Data 1 (C0MSL1DT1) 2 Data 1 (C0MSL2DT1) 3 Data 1 (C0MSL3DT1) 4 Data 1 (C0MSL4DT1) 5 Data 1 (C0MSL5DT1) 6 Data 1 (C0MSL6DT1) 7 Data 1 (C0MSL7DT1) 8 Data 1 (C0MSL8DT1) 9 Data 1 (C0MSL9DT1) 10 Data 1 (C0MSL10DT1) 11 Data 1 (C0MSL11DT1) 12 Data 1 (C0MSL12DT1) 13 Data 1 (C0MSL13DT1) 14 Data 1 (C0MSL14DT1) 15 Data 1 (C0MSL15DT1) 0 Data 1 (C1MSL0DT1) 1 Data 1 (C1MSL1DT1) 2 Data 1 (C1MSL2DT1) 3 Data 1 (C1MSL3DT1) 4 Data 1 (C1MSL4DT1) 5 Data 1 (C1MSL5DT1) 6 Data 1 (C1MSL6DT1) 7 Data 1 (C1MSL7DT1) 8 Data 1 (C1MSL8DT1) 9 Data 1 (C1MSL9DT1) 10 Data 1 (C1MSL10DT1) 11 Data 1 (C1MSL11DT1) 12 Data 1 (C1MSL12DT1) 13 Data 1 (C1MSL13DT1) 14 Data 1 (C1MSL14DT1) 15 Data 1 (C1MSL15DT1) 11 ? b15 ? b8 ? 12 ? 13 ? 14 ? C0MSL0DT1–C0MSL15DT1, C1MSL0DT1–C1MSL15DT1 b 8–15 Bit Name C0MSL0DT1–C0MSL15DT1, C1MSL0DT1–C1MSL15DT1 Function Message slot data 1 R R W W These registers are the memory space for transmit and receive frames. Note: • During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 1. 13-64 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 1 ? CAN MODULE 13.2 CAN Module Related Registers Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot 2 ? 0 Data 2 (C0MSL0DT2) 1 Data 2 (C0MSL1DT2) 2 Data 2 (C0MSL2DT2) 3 Data 2 (C0MSL3DT2) 4 Data 2 (C0MSL4DT2) 5 Data 2 (C0MSL5DT2) 6 Data 2 (C0MSL6DT2) 7 Data 2 (C0MSL7DT2) 8 Data 2 (C0MSL8DT2) 9 Data 2 (C0MSL9DT2) 10 Data 2 (C0MSL10DT2) 11 Data 2 (C0MSL11DT2) 12 Data 2 (C0MSL12DT2) 13 Data 2 (C0MSL13DT2) 14 Data 2 (C0MSL14DT2) 15 Data 2 (C0MSL15DT2) 0 Data 2 (C1MSL0DT2) 1 Data 2 (C1MSL1DT2) 2 Data 2 (C1MSL2DT2) 3 Data 2 (C1MSL3DT2) 4 Data 2 (C1MSL4DT2) 5 Data 2 (C1MSL5DT2) 6 Data 2 (C1MSL6DT2) 7 Data 2 (C1MSL7DT2) 8 Data 2 (C1MSL8DT2) 9 Data 2 (C1MSL9DT2) 10 Data 2 (C1MSL10DT2) 11 Data 2 (C1MSL11DT2) 12 Data 2 (C1MSL12DT2) 13 Data 2 (C1MSL13DT2) 14 Data 2 (C1MSL14DT2) 15 Data 2 (C1MSL15DT2) 3 ? b7 ? b0 ? 4 ? 5 ? 6 ? C0MSL0DT2–C0MSL15DT2, C1MSL0DT2–C1MSL15DT2 b 0–7 Bit Name C0MSL0DT2–C0MSL15DT2, C1MSL0DT2–C1MSL15DT2 Function Message slot data 2 R R W W These registers are the memory space for transmit and receive frames. Note: • During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 2. 13-65 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 9 ? CAN MODULE 13.2 CAN Module Related Registers Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot Slot 10 ? 0 Data 3 (C0MSL0DT3) 1 Data 3 (C0MSL1DT3) 2 Data 3 (C0MSL2DT3) 3 Data 3 (C0MSL3DT3) 4 Data 3 (C0MSL4DT3) 5 Data 3 (C0MSL5DT3) 6 Data 3 (C0MSL6DT3) 7 Data 3 (C0MSL7DT3) 8 Data 3 (C0MSL8DT3) 9 Data 3 (C0MSL9DT3) 10 Data 3 (C0MSL10DT3) 11 Data 3 (C0MSL11DT3) 12 Data 3 (C0MSL12DT3) 13 Data 3 (C0MSL13DT3) 14 Data 3 (C0MSL14DT3) 15 Data 3 (C0MSL15DT3) 0 Data 3 (C1MSL0DT3) 1 Data 3 (C1MSL1DT3) 2 Data 3 (C1MSL2DT3) 3 Data 3 (C1MSL3DT3) 4 Data 3 (C1MSL4DT3) 5 Data 3 (C1MSL5DT3) 6 Data 3 (C1MSL6DT3) 7 Data 3 (C1MSL7DT3) 8 Data 3 (C1MSL8DT3) 9 Data 3 (C1MSL9DT3) 10 Data 3 (C1MSL10DT3) 11 Data 3 (C1MSL11DT3) 12 Data 3 (C1MSL12DT3) 13 Data 3 (C1MSL13DT3) 14 Data 3 (C1MSL14DT3) 15 Data 3 (C1MSL15DT3) 11 ? b15 ? b8 ? 12 ? 13 ? 14 ? C0MSL0DT3–C0MSL15DT3, C1MSL0DT3–C1MSL15DT3 b 8–15 Bit Name C0MSL0DT3–C0MSL15DT3, C1MSL0DT3–C1MSL15DT3 Function Message slot data 3 R R W W These registers are the memory space for transmit and receive frames. Note: • During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 3. 13-66 32182 Group User’s Manual (Rev.1.0) 13 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message Message 1 ? CAN MODULE 13.2 CAN Module Related Registers Slot 0 Data 4 (C0MSL0DT4) Slot 1 Data 4 (C0MSL1DT4) Slot 2 Data 4 (C0MSL2DT4) Slot 3 Data 4 (C0MSL3DT4) Slot 4 Data 4 (C0MSL4DT4) Slot 5 Data 4 (C0MSL5DT4) Slot 6 Data 4 (C0MSL6DT4) Slot 7 Data 4 (C0MSL7DT4) Slot 8 Data 4 (C0MSL8DT4) Slot 9 Data 4 (C0MSL9DT4) Slot 10 Data 4 (C0MSL10DT4) Slot 11 Data 4 (C0MSL11DT4) Slot 12 Data 4 (C0MSL12DT4) Slot 13 Data 4 (C0MSL13DT4) Slot 14 Data 4 (C0MSL14DT4) Slot 15 Data 4 (C0MSL15DT4) Slot 0 Data 4 (C1MSL0DT4) Slot 1 Data 4 (C1MSL1DT4) Slot 2 Data 4 (C1MSL2DT4) Slot 3 Data 4 (C1MSL3DT4) Slot 4 Data 4 (C1MSL4DT4) Slot 5 Data 4 (C1MSL5DT4) Slot 6 Data 4 (C1MSL6DT4) Slot 7 Data 4 (C1MSL7DT4) Slot 8 Data 4 (C1MSL8DT4) Slot 9 Data 4 (C1MSL9DT4) Slot 10 Data 4 (C1MSL10DT4) Slot 11 Data 4 (C1MSL11DT4) Slot 12 Data 4 (C1MSL12DT4) Slot 13 Data 4 (C1MSL13DT4) Slot 14 Data 4 (C1MSL14DT4) Slot 15 Data 4 (C1MSL15DT4) 2 ? b7 ? b0 ? 3 ? 4 ? 5 ? 6 ? C0MSL0DT4–C0MSL15DT4, C1MSL0DT4–C1MSL15DT4 b 0–7 Bit Name C0MSL0DT4–C0MSL15DT4, C1MSL0DT4–C1MSL15DT4 Function Message slot data 4 R R W W These registers are the memory space for transmit and receive frames. Note: • During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 4. 13-67 32182 Group User’s Manual (Rev.1.0) 13 CAN0 Message Slot 0 Data 5 (C0MSL0DT5) CAN0 Message Slot 1 Data 5 (C0MSL1DT5) CAN0 Message Slot 2 Data 5 (C0MSL2DT5) CAN0 Message Slot 3 Data 5 (C0MSL3DT5) CAN0 Message Slot 4 Data 5 (C0MSL4DT5) CAN0 Message Slot 5 Data 5 (C0MSL5DT5) CAN0 Message Slot 6 Data 5 (C0MSL6DT5) CAN0 Message Slot 7 Data 5 (C0MSL7DT5) CAN0 Message Slot 8 Data 5 (C0MSL8DT5) CAN0 Message Slot 9 Data 5 (C0MSL9DT5) CAN0 Message Slot 10 Data 5 (C0MSL10DT5) CAN0 Message Slot 11 Data 5 (C0MSL11DT5) CAN0 Message Slot 12 Data 5 (C0MSL12DT5) CAN0 Message Slot 13 Data 5 (C0MSL13DT5) CAN0 Message Slot 14 Data 5 (C0MSL14DT5) CAN0 Message Slot 15 Data 5 (C0MSL15DT5) CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 Message Slot 0 Data 5 (C1MSL0DT5) Message Slot 1 Data 5 (C1MSL1DT5) Message Slot 2 Data 5 (C1MSL2DT5) Message Slot 3 Data 5 (C1MSL3DT5) Message Slot 4 Data 5 (C1MSL4DT5) Message Slot 5 Data 5 (C1MSL5DT5) Message Slot 6 Data 5 (C1MSL6DT5) Message Slot 7 Data 5 (C1MSL7DT5) Message Slot 8 Data 5 (C1MSL8DT5) Message Slot 9 Data 5 (C1MSL9DT5) Message Slot 10 Data 5 (C1MSL10DT5) Message Slot 11 Data 5 (C1MSL11DT5) Message Slot 12 Data 5 (C1MSL12DT5) Message Slot 13 Data 5 (C1MSL13DT5) Message Slot 14 Data 5 (C1MSL14DT5) Message Slot 15 Data 5 (C1MSL15DT5) 9 ? CAN MODULE 13.2 CAN Module Related Registers Cin × R1 + C2(R1 + R2) --- Eq. B2 Thus, the maximum value of R1 can be obtained as a criterion from the equation below. Note, however, that for single mode (when sample-and-hold is disabled), the sampling time for the second and subsequent bits (C2 charging time) must be applied. C2 charging time - C2 × R 2 Cin + C2 R1 < Appendix 4-14 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.10 Precautions about Serial I/O Appendix 4.10 Precautions about Serial I/O Appendix 4.10.1 Precautions on Using CSIO Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set before the serial I/O starts operating. If these settings need to be changed after a transmit or receive operation has started, first check to see that transmit and receive operations have finished and then clear the transmit and receive enable bits before making changes. • Settings of BRG (Baud Rate Register) If f(BCLK) is selected with the BRG clock source select bit, use caution when setting the BRG register so that the transfer rate will not exceed 2 Mbps. • About successive transmission To transmit data successively, make sure the next transmit data is set in the SIO Transmit Buffer Register before the current data transmission finishes. • About reception Because the receive shift clock in CSIO mode is derived by an operation of the transmit circuit, transmit operation must always be executed (by sending dummy data) even when the serial I/O is used for only receiving data. In this case, be aware that if the port function is set for the TXD pin (by setting the operation mode register to "1"), dummy data may actually be output from the pin. • About successive reception To receive data successively, make sure that data (dummy data) is set in the SIO Transmit Buffer Register before a transmit operation on the transmitter side starts. • Transmission/reception using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before serial communication starts. • About reception finished bit If a receive error (overrun error) occurs, the reception finished bit can only be cleared by clearing the receive enable bit, and cannot be cleared by reading out the receive buffer register. • About overrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer register, with the previous received data retained in it. Although a receive operation continues thereafter, the subsequent received data is not stored in the receive buffer register (receive status bit = "1"). Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared to "0". And this is the only way that the overrun error flag can be cleared. • About DMA transfer request generation during SIO transmission If the transmit buffer register becomes empty (transmit buffer empty flag = "1") while the transmit enable bit remains set to "1" (transmission enabled), an SIO transmit buffer empty DMA transfer request is generated. • About DMA transfer request generation during SIO reception If the reception finished bit is set to "1" (receive buffer register full), a reception finished DMA transfer request is generated. Be aware, however, that if an overrun error occurred during reception, this DMA transfer request is not generated. Appendix 4-15 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.10 Precautions about Serial I/O Appendix 4.10.2 Precautions on Using UART Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set before the serial I/O starts operating. If these settings need to be changed after a transmit or receive operation has started, first check to see that transmit and receive operations have finished and then clear the transmit and receive enable bits before making changes. • Settings of BRG (Baud Rate Register) If f(BCLK) is selected with the BRG clock source select bit, make sure the value set in the BRG register is equal to or greater than 7. Writes to the SIO Baud Rate Register take effect in the next cycle after the BRG counter has finished counting. However, if the register is accessed for write while transmission and reception are disabled, the written value takes effect at the same time it is written. • Transmission/reception using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before serial communication starts. • About overrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer register, with the previous received data retained in it. Once an overrun error occurs, although a receive operation continues, the subsequent received data is not stored in the receive buffer register. Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared. And this is the only way that the overrun error flag can be cleared. • Flags showing the status of UART receive operation There are following flags that indicate the status of receive operation during UART mode: • SIO Receive Control Register receive status bit • SIO Receive Control Register reception finished bit • SIO Receive Control Register receive error sum bit • SIO Receive Control Register overrun error bit • SIO Receive Control Register parity error bit • SIO Receive Control Register framing error bit The manner in which the reception finished bit and various error flags are cleared differs depending on whether an overrun error occurred, as described below. [When an overrun error did not occur] Cleared by reading out the lower byte of the receive buffer register or by clearing the receive enable bit. [When an overrun error occurred] Cleared by only clearing the receive enable bit. Appendix 4-16 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.11 Precautions about RAM Backup Mode Appendix 4.11 Precautions about RAM Backup Mode Appendix 4.11.1 Precautions to Be Observed at Power-On When changing port X from input mode to output mode after power-on, pay attention to the following. If port X is set for output mode while no data is set in the Port X Data Register, the port’s initial output level is instable. Therefore, before changing port X for output mode, make sure the Port X Data Register is set to output a high. Unless this precaution is followed, port output may go low at the same time the port is set for output after the oscillation has stabilized, causing the microcomputer to enter RAM backup mode. Appendix 4-17 32182 Group User's Manual (Rev.1.0) Appendix 4 Appendix 4.12 Precautions about JTAG SUMMARY OF PRECAUTIONS Appendix 4.12 Precautions about JTAG Appendix 4.12.1 Notes on Board Design when Connecting JTAG To materialize fast and highly reliable communication with JTAG tools, make sure wiring lengths of JTAG pins are matched during board design. VCCE(5V) M32R/ECU 10KΩ (Note 1) RESET# 10KΩ 33Ω JTDO 10KΩ 33Ω JTDI 10KΩ 33Ω JTMS 10KΩ 33Ω JTCK 33Ω JTRST 2KΩ 0.1µF VSS User board 33Ω SDI connector (JTAG connector) Power JTAG tool RESET (Note 2) TDO TDI TMS TCK TRST GND Make sure wiring lengths are the same, and avoid bending wires as much as possible. Be careful not to use through-holes within the wiring. Note 1: The RESET# related circuit and resistance-capacitance values must be determined depending on the user board's system design conditions and the microcomputer's operating conditions. Note 2: N-channel open-drain output is recommended for the RESET output of JTAG tools. For details, see JTAG tool specifications. Notes: • Only if the JTRST pin is firmly tied to ground, the JTDO, JTDI, JTMS and JTCLK pins can be processed by either pullup or pulldown. • Each of these pins must always be processed even when not using JTAG tools. The same pullup/pulldown resistance values as when using JTAG tools may be used. Figure 4.12.1 Notes on Board Design when Connecting JTAG Tools Appendix 4-18 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.12 Precautions about JTAG Appendix 4.12.2 Processing Pins when Not Using JTAG The following shows how the pins on the chip should be processed when not using JTAG tools. VCCE(5V) M32R/ECU 0–100KΩ JTDO 0–100KΩ JTDI 0–100KΩ JTMS 0–100KΩ JTCK JTRST 0–100KΩ User board Note: • Only if the JTRST pin is firmly tied to ground, the JTDO, JTDI, JTMS and JTCLK pins can be processed by either pullup or pulldown. Figure 4.12.2 Processing Pins when Not Using JTAG Appendix 4-19 32182 Group User's Manual (Rev.1.0) Appendix 4 Appendix 4.13 Precautions about Noise SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise The following describes precautions to be taken about noise and corrective measures against noise. The corrective measures described here are theoretically effective for noise, but require that the application system incorporating those measures be fully evaluated before it can actually be put to use. Appendix 4.13.1 Reduction of Wiring Length Wiring on the board may serve as an antenna to draw noise into the microcomputer. Shorter the total wiring length, the smaller the possibility of drawing noise into the microcomputer. (1) Wiring of the RESET# pin Reduce the length of wiring connecting to the RESET# pin. Especially when connecting a capacitor between the RESET# and VSS pins, make sure it is wired to each pin in the shortest distance possible (within 20 mm). Reset is a function to initialize the internal logic of the microcomputer. The width of a pulse applied to the RESET# pin is important and is therefore specified as part of timing requirements. If a pulse in width shorter than the specified duration (i.e., noise) is applied to the RESET# pin, the microcomputer will not be reset for a sufficient duration of time and come out of reset before its internal logic is fully initialized, causing the program to malfunction. Noise Reset circuit VSS Reset circuit VSS RESET# VSS RESET# VSS Long wiring Short wiring Figure 4.13.1 Example Wiring of the RESET# Pin Appendix 4-20 32182 Group User's Manual (Rev.1.0) Appendix 4 (2) Wiring of clock input/output pins SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Use as much thick and short wiring as possible for connections to the clock input/output pins. When connecting a capacitor to the oscillator, make sure its grounding lead wire and the OSC-VSS pin on the microcomputer are connected in the shortest distance possible (within 20 mm). Also, make sure the VSS pattern used for clock oscillation is a large ground plane and is connected to GND. The microcomputer operates synchronously with the clock generated by an oscillator circuit. Inclusion of noise on the clock input/output pins causes the clock waveform to become distorted, which may result in the microcomputer operating erratically or getting out of control. Furthermore, if a noise-induced potential difference exists between the microcomputer’s VSS level and that of the oscillator, the clock fed into the microcomputer may not be an exact clock. Noise OSC-VSS XIN XOUT VSS OSC-VSS XIN XOUT VSS Thin and long wiring Thick and short wiring Figure 4.13.2 Example Wiring of Clock Input/Output Pins Appendix 4-21 32182 Group User's Manual (Rev.1.0) Appendix 4 (3) Wiring of the VCNT pin SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Use as much thick and short wiring as possible for connections to the VCNT pin. When connecting a capacitor to VCNT, make sure its grounding lead wire and the OSC-VSS pin on the microcomputer are connected in the shortest distance possible. Also, make sure the VSS pattern used for VCNT is a large ground plane and is connected to GND. The external circuit inserted for the VCNT pin plays the role of a low-pass filter that stabilizes the PLL’s internal voltage and eliminates noise. If noise exceeding the limit of the low-pass filter penetrates into the wiring, the internal circuit may be disturbed by that noise and become unable to produce a precise clock, causing the microcomputer to operate erratically or get out of control. Noise OSC-VSS VCNT VSS OSC-VSS VCNT VSS Thin and long wiring Thick and short wiring Figure 4.13.3 Example Wiring of the VCNT Pin (4) Wiring of the operation mode setup pins When connecting the operation mode setup pins and the VCC or VSS pin, make sure they are wired in the shortest distance possible. The levels of the operation mode setup pins affect the microcomputer’s operation mode. When connecting the operation mode setup pins and the VCC or VSS pin, be careful that no noise-induced potential difference will exist between the operation mode setup pins and the VCC or VSS pin. This is because the presence of such a potential difference makes operation mode instable, which may result in the microcomputer operating erratically or getting out of control. Noise Operation mode setup pins Operation mode setup pins VSS VSS Long wiring Figure 4.13.4 Example Wiring of the MOD0 and MOD1 Pins Short wiring Appendix 4-22 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines Insert a bypass capacitor of about 0.1 µF between the VSS and VCC lines. At this time, make sure the requirements described below are met. • The wiring length between the VSS pin and bypass capacitor and that between the VCC pin and bypass capacitor are the same. • The wiring length between the VSS pin and bypass capacitor and that between the VCC pin and bypass capacitor are the shortest distance possible. • The VSS and VCC lines have a greater wiring width than that of all other signal lines. VCC Chip VCC VSS Chip VSS VCC VSS Figure 4.13.5 Example of a Bypass Capacitor Inserted between VSS and VCC Lines Appendix 4.13.3 Processing Analog Input Pin Wiring Insert a resistor of about 100 to 500Ω in series to the analog signal line connecting to the analog input pin at a position as close to the microcomputer as possible. Also, insert a capacitor of about 100 pF between the analog input pin and AVSS pin at a position as close to the AVSS pin as possible. The signal fed into the analog input pin (e.g., A-D converter input pin) normally is an output signal from a sensor. In many cases, a sensor to detect changes of event is located apart from the board on which the microcomputer is mounted, so that wiring to the analog input pin is inevitably long. Because a long wiring serves as an antenna which draws noise into the microcomputer, the signal fed into the analog input pin tends to be noise-ridden. Furthermore, if the capacitor connected between the analog input pin and AVSS pin is grounded at a position apart from the AVSS pin, noise riding on the ground line may penetrate into the microcomputer via the capacitor. Noise Sensor Microcomputer Analog input pin AVSS Figure 4.13.6 Example of a Resistor and Capacitor Inserted for the Analog Signal Line Appendix 4-23 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin The oscillator that generates the fundamental clock for microcomputer operation requires consideration to make it unsusceptible to influences from other signals. (1) Avoidance from large-current signal lines Signal lines that conduct a large current exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer (especially the oscillator and VCNT pin) as possible. Also, make sure the circuit is protected with a GND pattern. Systems using a microcomputer have signal lines to control a motor, LED or thermal head, for example. When a large current flows in these signal lines, it generates noise due to mutual inductance (M). Noise is generated by mutual inductance between the microcomputer and an adjacent signal line M OSC-VSS XIN Large current XOUT VCNT GND A signal line that conducts a large current exists near the microcomputer. M OSC-VSS XIN XOUT Large current VCNT GND Locate a signal line that conducts a large current apart from the microcomputer. Figure 4.13.7 Example Wiring of a Large-Current Signal Line Appendix 4-24 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise (2) Avoiding effects of rapidly level-changing signal lines Locate signal lines whose levels change rapidly as far away from the oscillator as possible. Also, make sure the rapidly level-changing signal lines will not intersect the clock-related signal lines and other noise-sensitive signal lines. Rapidly level-changing signal lines tend to affect other signal lines as their voltage level frequently rises and falls. Especially if these signal lines intersect the clock-related signal lines, they will cause the clock waveform to become distorted, which may result in the microcomputer operating erratically or getting out of control. High-speed serial I/O High-speed timer input/output, etc. XIN XOUT VCNT Signal line intersecting the clock-related and other signal lines High-speed serial I/O High-speed timer input/output, etc. XIN XOUT VCNT Locate the signal line away from the clock-related and other signal lines Figure 4.13.8 Example Wiring of a Rapidly Level-Changing Signal Line Appendix 4-25 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise (3) Protection against signal lines that are the source of strong noise Do not use any pin that will probably be subject to strong noise for an adjacent port near the oscillator and VCNT pins. If the pin can be left unused, set it for input and connect to GND via a resistor, or fix it to output and leave open. If the pin needs to be used, it is recommended that it be used for input-only. For protection against a still stronger noise source, set the adjacent port for input and connect to GND via a resistor, and use those that belong to the same port group as much for input-only as possible. If greater stability is required, do not use those that belong to the same port group and set them for input and connect to GND via a resistor. If they need to be used, insert a limiting resistor for protection against noise. If the ports or pins adjacent to the oscillator and VCNT pins operate at high speed or are exposed to strong noise from an external source, noise may affect the oscillator circuit, causing its oscillation to become instable. XIN XOUT Oscillator External noise or switching noise Noise VCNT Adjacent pin/peripheral pin (set for output) Fast switching Switching noise from an output pin applied directly to the port Adjacent pin/peripheral pin (set for input) Noise External noise from an input pin applied directly to the port Figure 4.13.9 Example Processing of a Noise-Laden Pin Appendix 4-26 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for output) Method for limiting the effect of noise in output mode Adjacent pin/peripheral pin (set for input) Noise Method for limiting noise with a resistor Noise Adjacent pin/peripheral pin (set for output) Fast switching Method for limiting switching noise with a resistor Figure 4.13.10 Example Processing of Pins Adjacent to the Oscillator and VCNT Pins Appendix 4-27 32182 Group User's Manual (Rev.1.0) Appendix 4 SUMMARY OF PRECAUTIONS Appendix 4.13 Precautions about Noise Appendix 4.13.5 Processing Input/Output Ports For input/output ports, take the appropriate measures in both hardware and software following the procedure described below. Hardware measures • Insert resistors of 100Ω or more in series to the input/output ports. Software measures • For input ports, read out data in a program two or more times to verify that the levels coincide. • For output ports, rewrite the data register at certain intervals because there is a possibility of the output data being inverted by noise. • Rewrite the direction register at certain intervals. Noise Data bus Direction register Noise Data register Input/output port Figure 4.13.11 Example Processing of Input/Output Ports Appendix 4-28 32182 Group User's Manual (Rev.1.0) R ENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER USER’S MANUAL 32182 Group Rev.1.00 Editioned by Committee of editing of RENESAS Semiconductor User’s Manual This book, or parts thereof, may not be reproduced in any form without permission of Renesas Technology Corporation. Copyright © 2 003. Renesas Technology Corporation, All rights reserved. 32182 Group User's Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan