M38047F3HHP

REJ09B0212-0100Z 8 3804 Group (Spec. H) User’s Manual RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 1.00 Revision date: Jan 14, 2005 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. 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Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. REVISION HISTORY Rev. Date Page 1.00 Jan 14, 2005 – First edition issued 3804 Group (Spec. H) User’s Manual Description Summary (1/1) B EFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization q C HAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q C HAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. q C HAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the notes, and the list of registers. 2. Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: (Note 2) Bits b7 b6 b5 b4 b3 b2 b1 b0 0 Bit attributes (Note 1) Contents immediately after reset release CPU mode register (CPUM) [Address : 003B16] b 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits b1 b0 Functions 0 0 : Single-chip mode 01: 1 0 : Not available 11: 0 : 0 page 1 : 1 page At reset RW 0 0 0 0 0 0 ✕ ✕ Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are “0.” Fix this bit to “0. ” Main clock division ratio selection bits 0 0 : φ = XIN/2 (High-speed mode) 0 1 : φ = XIN/8 (Middle-speed mode) 1 0 : φ = XIN/8 (Middle-speed mode) 1 1 : φ = XIN (Double-speed mode) b7 b6 1 0 : Bit in which nothing is arranged : Bit that is not used for control of the corresponding function Notes 1: Contents immediately after reset release 0 •••••• “0” at reset release 1 •••••• “1” at reset release Undefined •••••• Undefined or reset release ✻ ••••••Contents determined by option at reset release 2: Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R••••••Read ••••••Read enabled ✕••••••Read disabled W••••••Write ••••••Write enabled ✕ ••••••Write disabled 3. Supplementary For details of related development tools and documents, refer to web page “ 3804 Group ” o n our website (http://www.renesas.com/eng/products/mpumcu/8bit/38000/index.html). Table of contents 3804 Group (Spec.H) Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES ...................................................................................................................................... 1-2 PIN CONFIGURATION .................................................................................................................. 1-3 FUNCTIONAL BLOCK .................................................................................................................. 1-4 PIN DESCRIPTION ........................................................................................................................ 1-5 PART NUMBERING ....................................................................................................................... 1-6 GROUP EXPANSION .................................................................................................................... 1-7 Memory Size ............................................................................................................................. 1-7 Packages ................................................................................................................................... 1-7 FUNCTIONAL DESCRIPTION ...................................................................................................... 1-8 CENTRAL PROCESSING UNIT (CPU) ................................................................................. 1-8 MEMORY ................................................................................................................................. 1-13 I/O PORTS .............................................................................................................................. 1-15 INTERRUPTS .......................................................................................................................... 1-23 TIMERS ................................................................................................................................... 1-27 SERIAL INTERFACE ............................................................................................................. 1-40 PULSE WIDTH MODULATION (PWM) ................................................................................ 1-54 A/D CONVERTER .................................................................................................................. 1-56 D/A CONVERTER .................................................................................................................. 1-58 WATCHDOG TIMER .............................................................................................................. 1-59 MULTI-MASTER I2C-BUS INTERFACE ............................................................................... 1-60 RESET CIRCUIT .................................................................................................................... 1-74 CLOCK GENERATING CIRCUIT ......................................................................................... 1-76 FLASH MEMORY MODE ...................................................................................................... 1-80 NOTES ON PROGRAMMING ..................................................................................................... 1-99 NOTES ON USAGE ................................................................................................................... 1-100 FUNCTIONAL DESCRIPTION SUPPLEMENT ....................................................................... 1-101 Interrupt ................................................................................................................................. 1-101 Timing After Interrupt ........................................................................................................... 1-102 A/D Converter ....................................................................................................................... 1-103 CHAPTER 2 APPLICATION 2.1 I/O port ..................................................................................................................................... 2-2 2.1.1 Memory map ................................................................................................................... 2-2 2.1.2 Relevant registers .......................................................................................................... 2-3 2.1.3 Port Pi pull-up control register ..................................................................................... 2-5 2.1.4 Terminate unused pins .................................................................................................. 2-5 2.1.5 Notes on I/O port ........................................................................................................... 2-6 2.1.6 Termination of unused pins .......................................................................................... 2-7 2.2 Interrupt ................................................................................................................................... 2-8 2.2.1 Memory map ................................................................................................................... 2-8 2.2.2 Relevant registers .......................................................................................................... 2-8 2.2.3 Interrupt source ............................................................................................................ 2-12 2.2.4 Interrupt operation ........................................................................................................ 2-13 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z i Table of contents 3804 Group (Spec.H) 2.2.5 Interrupt control ............................................................................................................ 2-16 2.2.6 INT interrupt .................................................................................................................. 2-19 2.2.7 Notes on interrupts ...................................................................................................... 2-20 2.3 Timer ....................................................................................................................................... 2-22 2.3.1 Memory map ................................................................................................................. 2-22 2.3.2 Relevant registers ........................................................................................................ 2-23 2.3.3 Timer application examples ........................................................................................ 2-32 2.3.4 Notes on timer .............................................................................................................. 2-45 2.4 Serial interface ..................................................................................................................... 2-47 2.4.1 Memory map ................................................................................................................. 2-47 2.4.2 Relevant registers ........................................................................................................ 2-48 2.4.3 Serial I/O connection examples ................................................................................. 2-56 2.4.4 Setting of serial I/O transfer data format ................................................................. 2-58 2.4.5 Serial I/O1, serial I/O3 operation: stop and initialize .............................................. 2-59 2.4.6 Serial I/O pin function and selection method ........................................................... 2-60 2.4.7 Serial I/O application examples ................................................................................. 2-61 2.4.8 Notes on serial interface ............................................................................................. 2-81 2.5 Multi-master I 2C-BUS interface ......................................................................................... 2-84 2.5.1 Memory map ................................................................................................................. 2-84 2.5.2 Relevant registers ........................................................................................................ 2-85 2.5.3 I 2C-BUS overview ......................................................................................................... 2-94 2.5.4 Communication format ................................................................................................. 2-95 2.5.5 Synchronization and arbitration lost .......................................................................... 2-96 2.5.6 SMBUS communication usage example ................................................................... 2-98 2.5.7 Notes on multi-master I 2C-BUS interface ............................................................... 2-114 2.5.8 Notes on programming for SMBUS interface ......................................................... 2-117 2.6 PWM ...................................................................................................................................... 2-118 2.6.1 Memory map ............................................................................................................... 2-118 2.6.2 Relevant registers ...................................................................................................... 2-118 2.6.3 PWM output circuit application example ................................................................. 2-120 2.6.4 Notes on PWM ........................................................................................................... 2-122 2.7 A/D converter ..................................................................................................................... 2-123 2.7.1 Memory map ............................................................................................................... 2-123 2.7.2 Relevant registers ...................................................................................................... 2-123 2.7.3 A/D converter application examples ........................................................................ 2-127 2.7.4 Notes on A/D converter ............................................................................................ 2-131 2.8 D/A Converter ..................................................................................................................... 2-132 2.8.1 Memory map ............................................................................................................... 2-132 2.8.2 Relevant registers ...................................................................................................... 2-133 2.8.3 D/A converter application example .......................................................................... 2-135 2.8.4 Notes on D/A converter ............................................................................................ 2-138 2.9 Watchdog timer .................................................................................................................. 2-139 2.9.1 Memory map ............................................................................................................... 2-139 2.9.2 Relevant registers ...................................................................................................... 2-139 2.9.3 Watchdog timer application examples ..................................................................... 2-141 2.9.4 Notes on watchdog timer .......................................................................................... 2-142 2.10 Reset .................................................................................................................................. 2-143 2.10.1 Connection example of reset IC ............................................................................ 2-143 ____________ 2.10.2 Notes on RESET pin ............................................................................................... 2-144 2.11 Clock generating circuit ................................................................................................ 2-145 2.11.1 Relevant registers .................................................................................................... 2-145 2.11.2 Clock generating circuit application example ....................................................... 2-146 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z ii Table of contents 3804 Group (Spec.H) 2.12 Standby function ............................................................................................................. 2-149 2.12.1 Stop mode ................................................................................................................. 2-149 2.12.2 Wait mode ................................................................................................................. 2-153 2.13 Flash memory mode ....................................................................................................... 2-156 2.13.1 Overview .................................................................................................................... 2-156 2.13.2 Memory map ............................................................................................................. 2-156 2.13.3 Relevant registers .................................................................................................... 2-157 2.13.4 Parallel I/O mode ..................................................................................................... 2-159 2.13.5 Standard serial I/O mode ........................................................................................ 2-159 2.13.6 CPU rewrite mode ................................................................................................... 2-160 2.13.7 Flash memory mode application examples .......................................................... 2-162 2.13.8 Notes on CPU rewrite mode .................................................................................. 2-166 CHAPTER 3 APPENDIX 3.1 ELECTRICAL CHARACTERISTICS ...................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics ................................................................................................ 3-6 3.1.4 A/D converter characteristics ........................................................................................ 3-8 3.1.5 D/A converter characteristics ........................................................................................ 3-8 3.1.6 Power source circuit timing characteristics ................................................................ 3-8 3.1.7 Timing requirements and switching characteristics ................................................... 3-9 3.1.8 Multi-master I 2C-BUS bus line characteristics .......................................................... 3-14 3.2 Standard characteristics .................................................................................................... 3-15 3.2.1 Power source current standard characteristics ........................................................ 3-15 3.2.2 Port standard characteristics ...................................................................................... 3-19 3.2.3 A/D conversion standard characteristics ................................................................... 3-22 3.2.4 D/A conversion standard characteristics ................................................................... 3-26 3.3 Notes on use ........................................................................................................................ 3-27 3.3.1 Notes on input and output ports ................................................................................ 3-27 3.3.2 Termination of unused pins ........................................................................................ 3-28 3.3.3 Notes on interrupts ...................................................................................................... 3-29 3.3.4 Notes on 8-bit timer (timer 1, 2, X, Y) ..................................................................... 3-30 3.3.5 Notes on 16-bit timer (timer Z) .................................................................................. 3-30 3.3.6 Notes on serial interface ............................................................................................. 3-32 3.3.7 Notes on multi-master I 2C-BUS interface ................................................................. 3-34 3.3.8 Notes on programming for SMBUS interface ........................................................... 3-36 3.3.9 Notes on PWM ............................................................................................................. 3-37 3.3.10 Notes on A/D converter ............................................................................................ 3-37 3.3.11 Notes on D/A converter ............................................................................................ 3-38 3.3.12 Notes on watchdog timer .......................................................................................... 3-38 ____________ 3.3.13 Notes on RESET pin ................................................................................................. 3-38 3.3.14 Notes on low-speed operation mode ...................................................................... 3-38 3.3.15 Quartz-crystal oscillator ............................................................................................. 3-39 3.3.16 Notes on restarting oscillation .................................................................................. 3-39 3.3.17 Notes on using stop mode ....................................................................................... 3-39 3.3.18 Notes on wait mode .................................................................................................. 3-40 3.3.19 Notes on CPU rewrite mode .................................................................................... 3-40 3.3.20 Notes on programming .............................................................................................. 3-40 3.3.21 Notes on flash memory version ............................................................................... 3-42 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z iii Table of contents 3804 Group (Spec.H) 3.3.22 Notes on electric characteristic differences between mask ROM and flash nemory version MCUs ............................................................................................................. 3-42 3.3.23 Notes on handling of power source pins ............................................................... 3-42 3.3.24 Power Source Voltage ............................................................................................... 3-42 3.4 Countermeasures against noise ...................................................................................... 3-43 3.4.1 Shortest wiring length .................................................................................................. 3-43 3.4.2 Connection of bypass capacitor across V SS l ine and V CC l ine ............................... 3-45 3.4.3 Wiring to analog input pins ........................................................................................ 3-46 3.4.4 Oscillator concerns ....................................................................................................... 3-47 3.4.5 Setup for I/O ports ....................................................................................................... 3-48 3.4.6 Providing of watchdog timer function by software .................................................. 3-49 3.5 Control registers .................................................................................................................. 3-50 3.6 Package outline ................................................................................................................... 3-80 3.7 Machine instructions .......................................................................................................... 3-82 3.8 List of instruction code ..................................................................................................... 3-93 3.9 SFR memory map ................................................................................................................ 3-94 3.10 Pin configurations ............................................................................................................. 3-95 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z iv List of figures 3804 Group (Spec.H) List of figures CHAPTER 1 HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 3804 group (Spec. H) pin configuration ........................................................................ 1-3 2 3804 group (Spec. H) pin configuration ........................................................................ 1-3 3 Functional block diagram ................................................................................................. 1-4 4 Part numbering .................................................................................................................. 1-6 5 Memory expansion plan ................................................................................................... 1-7 6 740 Family CPU register structure ................................................................................. 1-8 7 Register push and pop at interrupt generation and subroutine call .......................... 1-9 8 Structure of CPU mode register ................................................................................... 1-11 9 Structure of MISRG ........................................................................................................ 1-12 10 Memory map diagram ................................................................................................... 1-13 11 Memory map of special function register (SFR) ...................................................... 1-14 12 Port block diagram (1) ................................................................................................. 1-16 13 Port block diagram (2) ................................................................................................. 1-17 14 Port block diagram (3) ................................................................................................. 1-18 15 Structure of port pull-up control register (1) ............................................................. 1-19 16 Structure of port pull-up control register (2) ............................................................. 1-20 17 Structure of port pull-up control register (3) ............................................................. 1-21 18 Structure of port pull-up control register (4) ............................................................. 1-22 19 Interrupt control ............................................................................................................. 1-25 20 Structure of interrupt-related registers ....................................................................... 1-26 21 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-29 22 Structure of timer XY mode register .......................................................................... 1-30 23 Structure of timer 12, X and timer Y, Z count source selection registers ........... 1-31 24 Block diagram of timer Z ............................................................................................. 1-35 25 Structure of timer Z mode register ............................................................................. 1-36 26 Timing chart of timer/event counter mode ................................................................ 1-37 27 Timing chart of pulse output mode ............................................................................ 1-37 28 Timing chart of pulse period measurement mode (Measuring term between two rising edges) .. 1-38 29 Timing chart of pulse width measurement mode (Measuring “L” term) ................ 1-38 30 Timing chart of programmable waveform generating mode ................................... 1-39 31 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating) ... 1-39 32 Block diagram of clock synchronous serial I/O1 ...................................................... 1-40 33 Operation of clock synchronous serial I/O1 .............................................................. 1-40 34 Block diagram of UART serial I/O1 ............................................................................ 1-41 35 Operation of UART serial I/O1 ................................................................................... 1-41 36 Structure of serial I/O1 control registers ................................................................... 1-43 37 Structure of serial I/O2 control register ..................................................................... 1-46 38 Block diagram of serial I/O2 ....................................................................................... 1-46 39 Timing of serial I/O2 ..................................................................................................... 1-47 40 Block diagram of clock synchronous serial I/O3 ...................................................... 1-48 41 Operation of clock synchronous serial I/O3 .............................................................. 1-48 42 Block diagram of UART serial I/O3 ............................................................................ 1-49 43 Operation of UART serial I/O3 ................................................................................... 1-49 44 Structure of serial I/O3 control registers ................................................................... 1-51 45 Timing of PWM period ................................................................................................. 1-54 46 Block diagram of PWM function ................................................................................. 1-54 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z v List of figures 3804 Group (Spec.H) Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Structure of PWM control register .............................................................................. 1-55 PWM output timing when PWM register or PWM prescaler is changed .............. 1-55 Structure of AD/DA control register ........................................................................... 1-56 Structure of 10-bit A/D mode reading ........................................................................ 1-56 Block diagram of A/D converter .................................................................................. 1-57 Block diagram of D/A converter .................................................................................. 1-58 Equivalent connection circuit of D/A converter (DA1) ............................................. 1-58 Block diagram of Watchdog timer .............................................................................. 1-59 Structure of Watchdog timer control register ............................................................ 1-59 Block diagram of multi-master I 2C-BUS interface .................................................... 1-60 Structure of I 2C slave address registers 0 to 2 ....................................................... 1-61 Structure of I 2C clock control register ........................................................................ 1-62 Structure of I 2C control register .................................................................................. 1-63 Structure of I2C status register ................................................................................... 1-65 Interrupt request signal generating timing ................................................................. 1-65 START condition generating timing diagram ............................................................ 1-66 STOP condition generating timing diagram ............................................................... 1-66 START/STOP condition detecting timing diagram .................................................... 1-67 STOP condition detecting timing diagram ................................................................. 1-67 Structure of I2C START/STOP condition control register ........................................ 1-68 Structure of I 2C special mode status register ........................................................... 1-69 Structure of I 2C special mode control register ......................................................... 1-70 Address data communication format .......................................................................... 1-71 Reset circuit example ................................................................................................... 1-74 Reset sequence ............................................................................................................ 1-74 Internal status at reset ................................................................................................. 1-75 Ceramic resonator circuit ............................................................................................. 1-77 External clock input circuit .......................................................................................... 1-77 System clock generating circuit block diagram ........................................................ 1-78 State transitions of system clock ................................................................................ 1-79 Block diagram of built-in flash memory ..................................................................... 1-81 Structure of flash memory control register 0 ............................................................ 1-82 Structure of flash memory control register 1 ............................................................ 1-82 Structure of flash memory control register 2 ............................................................ 1-83 CPU rewrite mode set/release flowchart ................................................................... 1-83 Program flowchart ......................................................................................................... 1-85 Erase flowchart .............................................................................................................. 1-86 Full status check flowchart and remedial procedure for errors ............................. 1-88 Structure of ROM code protect control address ...................................................... 1-89 ID code store addresses .............................................................................................. 1-90 Connection for standard serial I/O mode 1 (M38049FFHFP/HP/KP) .................... 1-94 Connection for standard serial I/O mode 2 (M38049FFHFP/HP/KP) .................... 1-95 Connection for standard serial I/O mode 1 (M38049FFHSP) ................................ 1-96 Connection for standard serial I/O mode 2 (M38049FFHSP) ................................ 1-97 Operating waveform for standard serial I/O mode 1 ............................................... 1-98 Operating waveform for standard serial I/O mode 2 ............................................... 1-98 Timing chart after an interrupt occurs ..................................................................... 1-102 Time up to execution of the interrupt processing routine ..................................... 1-102 A/D conversion equivalent circuit ............................................................................. 1-104 A/D conversion timing chart ...................................................................................... 1-105 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z vi List of figures 3804 Group (Spec.H) CHAPTER 2 APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2 2.1.2 Structure of Port Pi (i = 0 to 6) ................................................................................. 2-3 2.1.3 Structure of Port Pi direction register (i = 0 to 6) .................................................. 2-3 2.1.4 Structure of Port Pi pull-up control register (i = 0, 1, 2, 4, 5, 6) ......................... 2-4 2.1.5 Structure of Port P3 pull-up control register ............................................................ 2-4 2.2.1 Memory map of registers relevant to interrupt ........................................................ 2-8 2.2.2 Structure of Interrupt source selection register ....................................................... 2-8 2.2.3 Structure of Interrupt edge selection register .......................................................... 2-9 2.2.4 Structure of Interrupt request register 1 ................................................................... 2-9 2.2.5 Structure of Interrupt request register 2 ................................................................. 2-10 2.2.6 Structure of Interrupt control register 1 .................................................................. 2-10 2.2.7 Structure of Interrupt control register 2 .................................................................. 2-11 2.2.8 Interrupt operation diagram ....................................................................................... 2-13 2.2.9 Changes of stack pointer and program counter upon acceptance of interrupt request .... 2-14 2.2.10 Time up to execution of interrupt processing routine ......................................... 2-15 2.2.11 Timing chart after acceptance of interrupt request ............................................. 2-15 2.2.12 Interrupt control diagram ......................................................................................... 2-16 2.2.13 Example of multiple interrupts ................................................................................ 2-18 2.2.14 Sequence of changing relevant register ............................................................... 2-20 2.2.15 Sequence of check of interrupt request bit .......................................................... 2-21 2.3.1 Memory map of registers relevant to timers .......................................................... 2-22 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y ............................................ 2-23 2.3.3 Structure of Timer 1 .................................................................................................. 2-23 2.3.4 Structure of Timer 2, Timer X, Timer Y ................................................................. 2-24 2.3.5 Structure of Timer Z (low-order, high-order) .......................................................... 2-24 2.3.6 Structure of Timer XY mode register ...................................................................... 2-25 2.3.7 Structure of Timer Z mode register ......................................................................... 2-26 2.3.8 Structure of Timer 12, X count source selection register .................................... 2-28 2.3.9 Structure of Timer Y, Z count source selection register ...................................... 2-28 2.3.10 Structure of Interrupt source selection register ................................................... 2-29 2.3.11 Structure of Interrupt request register 1 ............................................................... 2-30 2.3.12 Structure of Interrupt request register 2 ............................................................... 2-30 2.3.13 Structure of Interrupt control register 1 ................................................................ 2-31 2.3.14 Structure of Interrupt control register 2 ................................................................ 2-31 2.3.15 Timers connection and setting of division ratios ................................................. 2-33 2.3.16 Relevant registers setting ....................................................................................... 2-33 2.3.17 Control procedure ..................................................................................................... 2-34 2.3.18 Peripheral circuit example ....................................................................................... 2-35 2.3.19 Timers connection and setting of division ratios ................................................. 2-35 2.3.20 Relevant registers setting ....................................................................................... 2-36 2.3.21 Control procedure ..................................................................................................... 2-37 2.3.22 Judgment method of valid/invalid of input pulses ............................................... 2-38 2.3.23 Relevant registers setting ....................................................................................... 2-39 2.3.24 Control procedure ..................................................................................................... 2-40 2.3.25 Timers connection and setting of division ratios ................................................. 2-41 2.3.26 Relevant registers setting ....................................................................................... 2-42 2.3.27 Control procedure (1) .............................................................................................. 2-43 2.3.28 Control procedure (2) .............................................................................................. 2-44 2.4.1 Memory map of registers relevant to Serial I/O .................................................... 2-47 2.4.2 Structure of Transmit/Receive buffer register 1 and Transmit/Receive buffer register 3 .. 2-48 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z vii List of figures 3804 Group (Spec.H) Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.4.3 Structure of Serial I/O1 status register and Serial I/O3 status register ............. 2-48 2.4.4 Structure of Serial I/O1 control register .................................................................. 2-49 2.4.5 Structure of Serial I/O3 control register .................................................................. 2-50 2.4.6 Structure of UART1 control register ........................................................................ 2-51 2.4.7 Structure of UART3 control register ........................................................................ 2-51 2.4.8 Structure of Baud rate generator 1 and Baud rate generator 3 ......................... 2-52 2.4.9 Structure of Serial I/O2 control register .................................................................. 2-52 2.4.10 Structure of Serial I/O2 register ............................................................................. 2-53 2.4.11 Structure of Interrupt source selection register ................................................... 2-53 2.4.12 Structure of Interrupt request register 1 ............................................................... 2-54 2.4.13 Structure of Interrupt request register 2 ............................................................... 2-54 2.4.14 Structure of Interrupt control register 1 ................................................................ 2-55 2.4.15 Structure of Interrupt control register 2 ................................................................ 2-55 2.4.16 Serial I/O connection examples (1) ....................................................................... 2-56 2.4.17 Serial I/O connection examples (2) ....................................................................... 2-57 2.4.18 Serial I/O transfer data format ............................................................................... 2-58 2.4.19 Connection diagram ................................................................................................. 2-61 2.4.20 Timing chart (using clock synchronous serial I/O) .............................................. 2-61 2.4.21 Registers setting relevant to transmitting side ..................................................... 2-62 2.4.22 Registers setting relevant to receiving side ......................................................... 2-63 2.4.23 Control procedure of transmitting side .................................................................. 2-64 2.4.24 Control procedure of receiving side ...................................................................... 2-65 2.4.25 Connection diagrams ............................................................................................... 2-66 2.4.26 Timing chart (serial I/O1) ........................................................................................ 2-66 2.4.27 Registers setting relevant to serial I/O1 ............................................................... 2-67 2.4.28 Setting of serial I/O1 transmission data ............................................................... 2-67 2.4.29 Control procedure of serial I/O1 ............................................................................ 2-68 2.4.30 Registers setting relevant to serial I/O2 ............................................................... 2-69 2.4.31 Setting of serial I/O2 transmission data ............................................................... 2-69 2.4.32 Control procedure of serial I/O2 ............................................................................ 2-70 2.4.33 Connection diagram ................................................................................................. 2-71 2.4.34 Timing chart .............................................................................................................. 2-72 2.4.35 Relevant registers setting ....................................................................................... 2-72 2.4.36 Control procedure of master unit ........................................................................... 2-73 2.4.37 Control procedure of slave unit ............................................................................. 2-74 2.4.38 Connection diagram (Communication using UART) ............................................ 2-75 2.4.39 Timing chart (using UART) ..................................................................................... 2-75 2.4.40 Registers setting relevant to transmitting side ..................................................... 2-77 2.4.41 Registers setting relevant to receiving side ......................................................... 2-78 2.4.42 Control procedure of transmitting side .................................................................. 2-79 2.4.43 Control procedure of receiving side ...................................................................... 2-80 2.4.44 Sequence of setting serial I/Oi (i = 1, 3) control register again ....................... 2-82 2.5.1 Memory map of registers relevant to I2C-BUS interface ...................................... 2-84 2.5.2 Structure of MISRG ................................................................................................... 2-85 2.5.3 Structure of I2C data shift register ........................................................................... 2-85 2.5.4 Structure of I 2C special mode status register ........................................................ 2-86 2.5.5 Structure of I 2C status register ................................................................................. 2-87 2.5.6 Structure of I2C control register ............................................................................... 2-88 2.5.7 Structure of I2C clock control register ..................................................................... 2-89 2.5.8 Structure of I2C START/STOP condition control register ..................................... 2-90 2.5.9 Structure of I 2C special mode control register ....................................................... 2-90 2.5.10 Structure of I2C slave address register i (i = 0 to 2) ......................................... 2-91 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z viii List of figures 3804 Group (Spec.H) Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.5.11 Structure of Interrupt source selection register ................................................... 2-91 2.5.12 Structure of Interrupt request register 1 ............................................................... 2-92 2.5.13 Structure of Interrupt request register 2 ............................................................... 2-92 2.5.14 Structure of Interrupt control register 1 ................................................................ 2-93 2.5.15 Structure of Interrupt control register 2 ................................................................ 2-93 2.5.16 I2C-BUS connection structure ................................................................................. 2-94 2.5.17 I2C-BUS communication format example .............................................................. 2-95 2.5.18 RESTART condition of master reception .............................................................. 2-96 2.5.19 SCL waveforms when synchronizing clocks ......................................................... 2-97 2.5.20 Initial setting example for SMBUS communication .............................................. 2-99 2.5.21 Read Word protocol communication as SMBUS master device ..................... 2-100 2.5.22 Generating of START condition and transmission process of slave address + write bit ... 2-101 2.5.23 Transmission process of command ..................................................................... 2-102 2.5.24 T ransmission process of RESTART condition and slave address + read bit ... 2-103 2.5.25 Reception process of lower data ......................................................................... 2-104 2.5.26 Reception process of upper data ........................................................................ 2-105 2.5.27 Generating of STOP condition ............................................................................. 2-106 2.5.28 Communication example as SMBUS slave device ............................................ 2-107 2.5.29 Reception process of START condition and slave address ............................ 2-108 2.5.30 Reception process of command ........................................................................... 2-109 2.5.31 Reception process of RESTART condition and slave address ....................... 2-110 2.5.32 Transmission process of lower data .................................................................... 2-111 2.5.33 Transmission process of upper data ................................................................... 2-112 2.5.34 Reception of STOP condition ............................................................................... 2-113 2.6.1 Memory map of registers relevant to PWM ......................................................... 2-118 2.6.2 Structure of PWM control register ......................................................................... 2-118 2.6.3 Structure of PWM prescaler ................................................................................... 2-119 2.6.4 Structure of PWM register ...................................................................................... 2-119 2.6.5 Connection diagram ................................................................................................. 2-120 2.6.6 PWM output timing ................................................................................................... 2-120 2.6.7 Setting of relevant registers ................................................................................... 2-121 2.6.8 PWM output .............................................................................................................. 2-121 2.6.9 Control procedure ..................................................................................................... 2-122 2.7.1 Memory map of registers relevant to A/D converter ........................................... 2-123 2.7.2 Structure of AD/DA control register ....................................................................... 2-123 2.7.3 Structure of AD conversion register 1 .................................................................. 2-124 2.7.4 Structure of AD conversion register 2 .................................................................. 2-124 2.7.5 Structure of Interrupt source selection register ................................................... 2-125 2.7.6 Structure of Interrupt request register 2 ............................................................... 2-126 2.7.7 Structure of Interrupt control register 2 ................................................................ 2-126 2.7.8 Connection diagram ................................................................................................. 2-127 2.7.9 Relevant registers setting ....................................................................................... 2-127 2.7.10 Control procedure (10-bit A/D mode) .................................................................. 2-128 2.7.11 Connection diagram ............................................................................................... 2-129 2.7.12 Relevant registers setting ..................................................................................... 2-129 2.7.13 Control procedure (8-bit A/D mode) .................................................................... 2-130 2.8.1 Memory map of registers relevant to D/A converter ........................................... 2-132 2.8.2 Structure of Port P5 direction register .................................................................. 2-133 2.8.3 Structure of AD/DA control register ....................................................................... 2-133 2.8.4 Structure of DAi converter register ........................................................................ 2-134 2.8.5 Peripheral circuit example ....................................................................................... 2-135 2.8.6 Speaker output example ......................................................................................... 2-135 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z ix List of figures 3804 Group (Spec.H) Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.8.7 Relevant registers setting ....................................................................................... 2-136 2.8.8 Control procedure ..................................................................................................... 2-137 2.9.1 Memory map of registers relevant to watchdog timer ........................................ 2-139 2.9.2 Structure of Watchdog timer control register ....................................................... 2-139 2.9.3 Structure of CPU mode register ............................................................................ 2-140 2.9.4 Watchdog timer connection and division ratio setting ........................................ 2-141 2.9.5 Relevant registers setting ....................................................................................... 2-142 2.9.6 Control procedure ..................................................................................................... 2-142 2.10.1 Example of poweron reset circuit ........................................................................ 2-143 2.10.2 RAM backup system .............................................................................................. 2-143 2.11.1 Structure of CPU mode register .......................................................................... 2-145 2.11.2 Connection diagram ............................................................................................... 2-146 2.11.3 Status transition diagram during power failure .................................................. 2-146 2.11.4 Setting of relevant registers ................................................................................. 2-147 2.11.5 Control procedure ................................................................................................... 2-148 2.12.1 Oscillation stabilizing time at restoration by reset input .................................. 2-150 2.12.2 Execution sequence example at restoration by occurrence of INT0 interrupt request ... 2-152 2.12.3 Reset input time ..................................................................................................... 2-154 2.13.1 Memory map of M38049FFHSP/FP/HP/KP ........................................................ 2-156 2.13.2 Memory map of registers relevant to flash memory ......................................... 2-157 2.13.3 Structure of Flash memory control register 0 .................................................... 2-157 2.13.4 Structure of Flash memory control register 1 .................................................... 2-158 2.13.5 Structure of Flash memory control register 2 .................................................... 2-158 2.13.6 Rewrite example of built-in flash memory in standard serial I/O mode ......... 2-162 2.13.7 Connection example in standard serial I/O mode (1) ....................................... 2-163 2.13.8 Connection example in standard serial I/O mode (2) ....................................... 2-163 2.13.9 Connection example in standard serial I/O mode (3) ....................................... 2-164 2.13.10 Example of rewrite system for built-in flash memory in CPU rewrite mode (singlechip mode) ............................................................................................................ 2-165 CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Circuit for measuring output switching characteristics (1) ................................... 3-12 Circuit for measuring output switching characteristics (2) ................................... 3-12 Timing diagram (in single-chip mode) ..................................................................... 3-13 Timing diagram of multi-master I 2C-BUS ................................................................ 3-14 Power source current standard characteristics (in high-speed mode) ............... 3-15 Power source current standard characteristics (in middle-speed mode) ........... 3-15 Power source current standard characteristics (in low-speed mode) ................. 3-16 Power source current standard characteristics (in high-speed mode, f(X IN) = 16.8 MHz, WAIT state) ....................................................................................................... 3-16 3.2.5 Power source current standard characteristics (in middle-speed mode, f(X IN) = 16.8 MHz, WAIT state) ....................................................................................................... 3-17 3.2.6 Power source current standard characteristics (in low-speed mode, WAIT state) ...... 3-17 3.2.7 Power source current standard characteristics (in high-speed mode, f(X IN) = 16.8 MHz, A/D converter operating) ................................................................................. 3-18 3.2.8 Power source current standard characteristics (at oscillation stopping) ............ 3-18 3.2.9 CMOS output port P-channel side characteristics (Ta = 25 °C) ......................... 3-19 3.2.10 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-19 3.2.11 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C) .... 3-20 3.2.12 C MOS large current output port N-channel side characteristics (Ta = 25 °C) .... 3-20 3.2.13 CMOS input port at pull-up characteristics (Ta = 25 °C) .................................. 3-21 3.1.1 3.1.2 3.1.3 3.1.4 3.2.1 3.2.2 3.2.3 3.2.4 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z x List of figures 3804 Group (Spec.H) Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.2.14 A/D conversion standard characteristics (f(X IN) = 8 MHz) ................................. 3-23 3.2.15 A/D conversion standard characteristics (f(XIN) = 12 MHz) ............................... 3-24 3.2.16 A/D conversion standard characteristics (f(XIN) = 16 MHz) ............................... 3-25 3.2.17 D/A conversion standard characteristics ............................................................... 3-26 3.3.1 Sequence of changing relevant register ................................................................. 3-29 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-30 3.3.3 Sequence of setting serial I/Oi (i = 1, 3) control register again ......................... 3-33 3.3.4 Ceramic resonator circuit .......................................................................................... 3-38 3.3.5 Initialization of processor status register ................................................................ 3-40 3.3.6 Sequence of PLP instruction execution .................................................................. 3-41 3.3.7 Stack memory contents after PHP instruction execution ..................................... 3-41 3.3.8 Status flag at decimal calculations .......................................................................... 3-41 _____________ 3.4.1 Wiring for the RESET pin ......................................................................................... 3-43 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-44 3.4.3 Wiring for CNV SS p in .................................................................................................. 3-44 3.4.4 Bypass capacitor across the V SS l ine and the V CC l ine ........................................ 3-45 3.4.5 Analog signal line and a resistor and a capacitor ................................................ 3-46 3.4.6 Wiring for a large current signal line ...................................................................... 3-47 3.4.7 Wiring of signal lines where potential levels change frequently ......................... 3-47 3.4.8 V SS p attern on the underside of an oscillator ........................................................ 3-48 3.4.9 Setup for I/O ports ..................................................................................................... 3-48 3.4.10 Watchdog timer by software ................................................................................... 3-49 3.5.1 Structure of Port Pi .................................................................................................... 3-50 3.5.2 Structure of Port Pi direction register ..................................................................... 3-50 3.5.3 Structure of Timer 12, X count source selection register .................................... 3-51 3.5.4 Structure of Timer Y, Z count source selection register ...................................... 3-52 3.5.5 Structure of MISRG ................................................................................................... 3-53 3.5.6 Structure of I2C data shift register ........................................................................... 3-53 3.5.7 Structure of I2C special mode status register ........................................................ 3-54 3.5.8 Structure of I2C status register................................................................................. 3-55 3.5.9 Structure of I2C control register ............................................................................... 3-56 3.5.10 Structure of I2C clock control register ................................................................... 3-57 3.5.11 Structure of I2C START/STOP condition control register ................................... 3-58 3.5.12 Structure of I2C special mode control register ..................................................... 3-58 3.5.13 Structure of Transmit/Receive buffer register 1, Transmit/Receive buffer register 3 .... 3-59 3.5.14 Structure of Serial I/O1 status register, Serial I/O3 status register ................. 3-59 3.5.15 Structure of Serial I/O1 control register ................................................................ 3-60 3.5.16 Structure of UART1 control register ...................................................................... 3-61 3.5.17 Structure of Baud rate generator i ........................................................................ 3-61 3.5.18 Structure of Serial I/O2 control register ................................................................ 3-62 3.5.19 Structure of Watchdog timer control register ....................................................... 3-62 3.5.20 Structure of Serial I/O2 register ............................................................................. 3-63 3.5.21 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-63 3.5.22 Structure of Timer 1 ................................................................................................ 3-64 3.5.23 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-64 3.5.24 Structure of Timer XY mode register .................................................................... 3-65 3.5.25 Structure of Timer Z low-order, Timer Z high-order ........................................... 3-66 3.5.26 Structure of Timer Z mode register ....................................................................... 3-66 3.5.27 Structure of PWM control register ......................................................................... 3-68 3.5.28 Structure of PWM prescaler ................................................................................... 3-68 3.5.29 Structure of PWM register ...................................................................................... 3-68 3.5.30 Structure of Serial I/O3 control register ................................................................ 3-69 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z xi List of figures 3804 Group (Spec.H) Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.5.31 3.5.32 3.5.33 3.5.34 3.5.35 3.5.36 3.5.37 3.5.38 3.5.39 3.5.40 3.5.41 3.5.42 3.5.43 3.5.44 3.5.45 3.5.46 3.5.47 3.5.48 Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure of of of of of of of of of of of of of of of of of of UART3 control register ...................................................................... 3-70 AD/DA control register ....................................................................... 3-70 AD conversion register 1 .................................................................. 3-71 DAi conversion register (i = 1, 2) .................................................... 3-71 AD conversion register 2 .................................................................. 3-71 Interrupt source selection register ................................................... 3-72 Interrupt edge selection register ...................................................... 3-73 CPU mode register ............................................................................ 3-73 Interrupt request register 1 ............................................................... 3-74 Interrupt request register 2 ............................................................... 3-74 Interrupt control register 1 ................................................................ 3-75 Interrupt control register 2 ................................................................ 3-75 Flash memory control register 0 ...................................................... 3-76 Flash memory control register 1 ...................................................... 3-77 Flash memory control register 2 ...................................................... 3-77 Port Pi pull-up control register (i = 0 to 2, 4 to 6) ....................... 3-78 Port P3 pull-up control register ........................................................ 3-78 I2C slave address register i (i = 0 to 2) ......................................... 3-79 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z xii List of tables 3804 Group (Spec.H) List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 Support products ............................................................................................................ 1-2 2 Pin description ................................................................................................................ 1-5 3 Push and pop instructions of accumulator or processor status register ............... 1-9 4 Set and clear instructions of each bit of processor status register ..................... 1-10 5 I/O port function ........................................................................................................... 1-15 6 Interrupt vector addresses and priority ..................................................................... 1-24 7 Multi-master I2C-BUS interface functions .................................................................. 1-60 8 Set values of I 2C clock control register and SCL frequency ................................. 1-62 9 START condition generating timing table ................................................................. 1-66 10 STOP condition generating timing table ................................................................. 1-66 11 START condition/STOP condition detecting conditions ........................................ 1-67 12 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency .................................................................................................. 1-68 13 Summary of 3804 group (spec. H) ......................................................................... 1-80 14 State of E/W inhibition function ............................................................................... 1-83 15 List of software commands (CPU rewrite mode) .................................................. 1-85 16 Definition of each bit in status register .................................................................. 1-87 17 Description of pin function (Flash Memory Serial I/O Mode 1) .......................... 1-93 18 Description of pin function (Flash Memory Serial I/O Mode 2) .......................... 1-93 19 Interrupt sources, vector addresses and priority ................................................. 1-101 20 Relative formula for a reference voltage VREF o f A/D converter and Vref ( at 10-bit A/ D mode) .................................................................................................................... 1-103 21 Relative formula for a reference voltage V REF o f A/D converter and V ref ( at 8-bit A/ D mode) .................................................................................................................... 1-103 22 C hange of AD conversion register during A/D conversion (at 10-bit A/D mode) . 1-103 23 C hange of AD conversion register during A/D conversion (at 8-bit A/D mode) ... 1-104 CHAPTER 2 APPLICATION Table Table Table Table Table Table Table Table Table Table Table Table 2.1.1 Termination of unused pins (in single-chip mode) ............................................... 2-5 2.2.1 Interrupt sources, vector addresses and priority .............................................. 2-12 2.2.2 List of interrupt bits according to interrupt source ............................................. 2-17 2.3.1 CNTR 0/CNTR 1 a ctive edge switch bit function .................................................... 2-25 2.3.2 CNTR 2 a ctive edge switch bit function ................................................................ 2-27 2.4.1 Pin function in clock synchronous serial I/O mode ............................................ 2-60 2.4.2 Pin function in UART mode ................................................................................... 2-60 2.4.3 Pin function in clock synchronous serial I/O mode ............................................ 2-60 2.4.4 Setting examples of Baud rate generator (BRG) values and transfer bit rate values ... 2-76 2.12.1 State in stop mode ............................................................................................. 2-149 2.12.2 State in wait mode .............................................................................................. 2-153 2.13.1 Parallel unit when parallel programming (when using EFP-I provided by Suisei Electronics System Co., Ltd.) ............................................................................ 2-159 Table 2.13.2 Connection example to programmer when serial programming (4 wires) .. 2-159 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z xiii List of tables 3804 Group (Spec.H) CHAPTER 3 APPENDIX Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2 3.1.2 Recommended operating conditions (1) ................................................................ 3-3 3.1.3 Recommended operating conditions (2) ................................................................ 3-4 3.1.4 Recommended operating conditions (3) ............................................................... .3-5 3.1.5 Electrical characteristics (1) ..................................................................................... 3-6 3.1.6 Electrical characteristics (2) ..................................................................................... 3-7 3.1.7 A/D converter recommended operating conditions ............................................... 3-8 3.1.8 A/D converter characteristics ................................................................................... 3-8 3.1.9 D/A converter characteristics ................................................................................... 3-8 3.1.10 Power source circuit timing characteristics ......................................................... 3-8 3.1.11 Timing requirements (1) ......................................................................................... 3-9 3.1.12 Timing requirements (2) ....................................................................................... 3-10 3.1.13 Switching characteristics ...................................................................................... 3-11 3.1.14 Multi-master I 2C-BUS bus line characteristics .................................................. 3-14 3.5.1 CNTR 0/CNTR 1 a ctive edge switch bit function .................................................... 3-65 3.5.2 CNTR 2 a ctive edge switch bit function ................................................................ 3-67 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z xiv CHAPTER 1 HARDWARE DESCRIPTION FEATURES PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USAGE DATA REQUIRED FOR MASK ORDERS FUNCTIONAL DESCRIPTION SUPPLEMENT HARDWARE 3804 Group (Spec.H) DESCRIPTION/FEATURES DESCRIPTION The 3804 group (Spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3804 group (Spec. H) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the A/D converter and D/A converters. FEATURES q Basic machine-language instructions ...................................... 71 q Minimum instruction execution time ................................ 0.24 µs (at 16.8 MHz oscillation frequency) q Memory size Flash memory .............................................................. 60 K bytes RAM ............................................................................ 2048 bytes q Programmable input/output ports ............................................ 56 q Software pull-up resistors ................................................. Built-in q Interrupts 21 sources, 16 vectors ................................................................. (external 8, internal 12, software 1) q Timers ........................................................................... 16-bit ✕ 1 8-bit ✕ 4 (with 8-bit prescaler) q Watchdog timer ............................................................ 16-bit ✕ 1 q Serial interface Serial I/O1, 3 ............... 8-bit ✕ 2 (UART or Clock-synchronized) Serial I/O2 ................................... 8-bit ✕ 1 (Clock-synchronized) q PWM ............................................ 8-bit ✕ 1 (with 8-bit prescaler) q Multi-master I2C-BUS interface ................................... 1 channel q A/D converter ............................................. 10-bit ✕ 16 channels (8-bit reading enabled) q D/A converter .................................................. 8-bit ✕ 2 channels q LED direct drive port .................................................................. 8 q Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) q Power source voltage In high-speed mode At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V At 12.5 MHz oscillation frequency ............................ 4.0 to 5.5 V At 8.4 MHz oscillation frequency) ............................. 2.7 to 5.5 V In middle-speed mode At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V At 12.5 MHz oscillation frequency ............................ 2.7 to 5.5 V In low-speed mode At 32 kHz oscillation frequency ................................. 2.7 to 5.5 V q Power dissipation In high-speed mode ............................................. 27.5 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................... 1200 µW (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) q Operating temperature range .................................... –20 to 85°C q Packages SP .................................................. 64P4B (64-pin 750 mil SDIP) FP ....................................... 64P6N-A (64-pin 14 ✕ 14 mm QFP) HP ..................................... 64P6Q-A (64-pin 10 ✕ 10 mm LQFP) KP ..................................... 64P6U-A (64-pin 14 ✕ 14 mm LQFP) q Power source voltage ...................................... Vcc = 2.7 to 5.5 V qProgram/Erase voltage .................................... Vcc = 2.7 to 5.5 V qProgramming method ...................... Programming in unit of byte qErasing method ...................................................... Block erasing qProgram/Erase control by software command qNumber of times for programming/erasing ............................ 100 sNotes Cannot be used for application embedded in the MCU card. Currently support products are listed below. Table 1 Support products Product name M38049FFHSP M38049FFHFP M38049FFHHP M38049FFHKP Flash memory size (bytes) RAM size (bytes) Package 64P4B 64P6N-A 64P6Q-A 64P6U-A Remarks 61440 2048 Vcc = 2.7 to 5.5 V Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-2 HARDWARE 3804 Group (Spec.H) PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW) P01/AN9 P02/AN10 P07/AN15 P10/INT41 P11/INT01 P03/AN11 P04/AN12 P00/AN8 P05/AN13 P06/AN14 P13 P14 P15 35 P16 34 P12 P17 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 44 40 41 45 48 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33/SCL P32/SDA P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 47 46 43 42 39 38 37 36 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 M38049FFHFP/HP/KP 13 12 P62/AN2 P60/AN0 P56/PWM P54/CNTR0 P51/SOUT2 10 11 P55/CNTR1 P53/SRDY2 P52/SCLK2 P45/TXD1 P57/INT3 P61/AN1 P50/SIN2 14 15 P44/RXD1 P47/SRDY1/CNTR2 Package type : 64P6N-A/64P6Q-A/64P6U-A Fig. 1 3804 group (Spec. H) pin configuration PIN CONFIGURATION (TOP VIEW) VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) Package type : 64P4B Fig. 2 3804 group (Spec. H) pin configuration P46/SCLK1 P43/INT2 16 5 4 1 3 2 6 7 8 9 M38049FFHSP Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-3 FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B) Clock Clock Sub-clock Sub-clock input output input output Reset input X IN X OUT X CIN X COUT V SS V CC RESET CNVSS 26 27 1 32 3804 Group (Spec.H) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z Data bus CPU Timer 1 (8) A X Y Prescaler X (8) Prescaler 12 (8) FUNCTIONAL BLOCK Fig. 3 Functional block diagram 30 31 28 29 Clock generating circuit RAM ROM Timer 2 (8) Timer X (8) S CNTR0 PC H PS PC L CNTR1 Prescaler Y (8) Timer Y (8) Timer Z (16) CNTR2 A/D converter (10) PWM(8) SI/O2(8) SI/O1(8) D/A D/A converter converter 2 (8) 1 (8) SI/O3(8) IC 2 INT3 INT00 INT1 INT2 INT40 INT01 INT41 P6(8) P5(8) P4(8) P3(8) P2(8) P1(8) P0(8) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VREF AVSS FUNCTIONAL BLOCK HARDWARE I/O port P6 I/O port P5 I/O port P4 I/O port P3 I/O port P2 (LED drive) I/O port P1 I/O port P0 1-4 HARDWARE 3804 Group (Spec.H) PIN DESCRIPTION PIN DESCRIPTION Table 2 Pin description Pin VCC, VSS CNVSS VREF AVSS RESET XIN XOUT Name Power source CNVSS input Reference voltage Analog power source Reset input Clock input Clock output Functions •Apply voltage of 2.7 V–5.5 V to Vcc, and 0 V to Vss. •This pin controls the operation mode of the chip. •Normally connected to VSS. •Reference voltage input pin for A/D and D/A converters. •Analog power source input pin for A/D and D/A converters. •Connect to VSS. •Reset input pin for active “L”. •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. P00/AN8– P07/AN15 P10/INT41 P11/INT01 P12–P17 P20–P27 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 I/O port P0 I/O port P1 •8-bit CMOS I/O port. •A/D converter input pin •I/O direction register allows each pin to be individually programmed as either input or output. •Interrupt input pin •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •P20–P27 are enabled to output large current for LED drive. I/O port P3 •8-bit CMOS I/O port. •D/A converter input pin •I/O direction register allows each pin to be individually programmed as either input or output. •I2C-BUS interface function pins •CMOS compatible input level. •P32 to P33 can be switched between CMOS compat- •Serial I/O3 function pin ible input level or SMBUS input level in the I2C-BUS interface function. •P30, P31, P34–P37 are CMOS 3-state output structure. •P32, P33 are N-channel open-drain output structure. •Pull-up control of P30, P31, P34–P37 is enabled in a bit unit. P40/INT40/ XCOUT P41/INT00/ XCIN P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1 /CNTR2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0– P67/AN7 I/O port P6 I/O port P4 •8-bit CMOS I/O port. •Interrupt input pin •I/O direction register allows each pin to be individually •Sub-clock generating I/O pin programmed as either input or output. (resonator connected) •CMOS compatible input level. •Interrupt input pin •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •Serial I/O1 function pin Function except a port function I/O port P2 •Serial I/O1, timer Z function pin I/O port P5 •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •Timer X function pin •Timer Y function pin •PWM output pin •Interrupt input pin •A/D converter input pin •Serial I/O2 function pin Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-5 HARDWARE 3804 Group (Spec.H) PART NUMBERING PART NUMBERING Product name M3804 9 F F H SP Package type SP : 64P4B FP : 64P6N-A HP : 64P6Q-A KP : 64P6U-A : standard H : Minner spec. change product ROM/PROM size 9 : 36864 bytes 1 : 4096 bytes A: 40960 bytes 2 : 8192 bytes B: 45056 bytes 3 : 12288 bytes C: 49152 bytes 4 : 16384 bytes D: 53248 bytes 5 : 20480 bytes E: 57344 bytes 6 : 24576 bytes F : 61440 bytes 7 : 28672 bytes 8 : 32768 bytes Memory type F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 4 Part numbering Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-6 HARDWARE 3804 Group (Spec.H) GROUP EXPANSION GROUP EXPANSION Renesas plans to expand the 3804 group (Spec. H) as follows. Packages 64P4B ......................................... 64-pin shrink plastic-molded DIP 64P6N-A .................................... 0.8 mm-pitch plastic molded QFP 64P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP 64P6U-A .................................. 0.8 mm-pitch plastic molded LQFP Memory Size Flash memory size ......................................................... 60 K bytes RAM size ....................................................................... 2048 bytes Memory Expansion Plan ROM size (bytes) : Under development : Mass production As of Dec. 2004 60K M38049FFH M38049FF 48K 32K 28K 24K 20K 16K 12K 8K 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size (bytes) Fig. 5 Memory expansion plan Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-7 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3804 group (Spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls (see Table 3). [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag NVTBD I ZC Fig. 6 740 Family CPU register structure Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-8 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION On-going Routine Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) – 1 (PCL) (S)– 1 M (S) (S) M (S) (S) M (S) (S) (PCH) (S) – 1 (PCL) (S) – 1 (PS) (S) – 1 Push contents of processor status register on stack Push return address on stack Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S) I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack POP return address from stack Note: Condition for acceptance of an interrupt Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 7 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-9 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “ 0 ” , arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic. Table 4 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag – – I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-10 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. b7 1 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig. 8 Structure of CPU mode register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-11 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION qMiddle-speed mode automatic switch by SCL/SDA Interrupt The SCL/SDA interrupt source enables an automatic switch when the middle-speed mode automatic switch set bit (bit 1) of MISRG (address 001016) is set to “1”. The conditions for an automatic switch execution depend on the settings of bits 5 and 6 of the I2C START/STOP condition control register (address 001616). Bit 5 is the SCL/SDA interrupt pin polarity selection bit and bit 6 is the SCL/SDA interrupt pin selection bit. The main clock oscillation stabilizing time can also be selected by middle-speed mode automatic switch wait time set bit (bit 2) of the MISRG. qMiddle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to “1” in the condition that the middle-speed mode automatic switch set bit is “1” while operating in low-speed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016). MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting “1” to bit 0 of MISRG (address 001016). However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure 9 shows the structure of MISRG. (2) Bits 1, 2, 3 of address 0010 16: Middle-speed Mode Automatic Switch Function In order to switch the clock mode of an MCU which has a subclock, the following procedure is necessary: set CPU mode register (003B16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). However, the 3804 group (Spec. H) has the built-in function which automatically switches from low to middle-speed mode either by the SCL/SDA interrupt or by program. b7 b0 MISRG (MISRG : address 001016) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set “0116” to Timer 1, “FF16” to Prescaler 12 1: Automatically set disabled Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enabled (Note1, 2) Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start (Note1) Not used (return “0” when read) (Do not write “1” to this bit) Note 1: During operation in low-speed mode, it is possible automatically to switch to middle-speed mode owing to SCL/SDA interrupt. 2: When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (003B16) change. Fig. 9 Structure of MISRG Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-12 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM The RAM is used for data storage and for stack area of subroutine calls and interrupts. Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The ROM area can program/erase. RAM area RAM size (bytes) Address XXXX16 000016 SFR area 004016 010016 RAM Zero page 192 256 384 512 640 768 896 1024 1536 2048 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 XXXX16 Not used 0FF016 0FFF16 SFR area Not used ROM area ROM size (bytes) Address YYYY16 YYYY16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page Fig. 10 Memory map diagram Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-13 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Timer 12, X count source selection register (T12XCSS) Timer Y, Z count source selection register (TYZCSS) MISRG I2C data shift register (S0) I2C special mode status register (S3) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) I2C START/STOP condition control register (S2D) I2C special mode control register (S3D) Transmit/Receive buffer register 1 (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator 1 (BRG1) Serial I/O2 control register (SIO2CON) Watchdog timer control register (WDTCON) Serial I/O2 register (SIO2) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer Z low-order (TZL) Timer Z high-order (TZH) Timer Z mode register (TZM) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) Baud rate generator 3 (BRG3) Transmit/Receive buffer register 3 (TB3/RB3) Serial I/O3 status register (SIO3STS) Serial I/O3 control register (SIO3CON) UART3 control register (UART3CON) AD/DA control register (ADCON) AD conversion register 1 (AD1) DA1 conversion register (DA1) DA2 conversion register (DA2) AD conversion register 2 (AD2) Interrupt source selection register (INTSEL) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0FE016 0FE116 0FE216 0FE316 0FE416 0FE516 0FE616 0FE716 0FE816 0FE916 0FEA16 0FEB16 0FEC16 0FED16 0FEE16 0FEF16 Flash memory control register 0 (FMCR0) Flash memory control register 1 (FMCR1) Flash memory control register 2 (FMCR2) Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Port P2 pull-up control register (PULL2) Port P3 pull-up control register (PULL3) Port P4 pull-up control register (PULL4) Port P5 pull-up control register (PULL5) Port P6 pull-up control register (PULL6) I2C slave address register 0 (S0D0) I2C slave address register 1 (S0D1) I2C slave address register 2 (S0D2) ✽ Reserved area: Do not write any data to these addresses, because these areas are reserved. Fig. 11 Memory map of special function register (SFR) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-14 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION comes an input pin. When “ 1 ” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin beTable 5 I/O port function Pin P00/AN8–P07/AN15 P10/INT41 P11/INT01 P12–P17 P20/LED0– P27/LED7 P30/DA1 P31/DA2 P32/SDA P33/SCL Name Port P0 Port P1 I/O Structure CMOS compatible input level CMOS 3-state output Non-Port Function A/D converter input External interrupt input Related SFRs AD/DA control register Interrupt edge selection register Ref.No. (1) (2) (3) Port P2 Port P3 CMOS compatible input level CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS/SMBUS input level (when selecting I2C-BUS interface function) CMOS compatible input level CMOS 3-state output D/A converter output I2C-BUS interface function I/O AD/DA control register I2C control register (4) (5) P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCIN P41/INT00/XCOUT P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1/CNTR2 Serial I/O3 function I/O Serial I/O3 control register UART3 control register Interrupt edge selection register CPU mode register Interrupt edge selection register Serial I/O1 control register UART1 control register Serial I/O1 control register Timer Z mode register Serial I/O2 control register (6) (7) (8) (9) (10) (11) (2) (6) (7) (8) (12) Port P4 CMOS compatible input level CMOS 3-state output External interrupt input Sub-clock generating circuit External interrupt input Serial I/O1 function I/O Serial I/O1 function I/O Timer Z function I/O Port P5 CMOS compatible input level CMOS 3-state output Serial I/O2 function I/O P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0–P67/AN7 Timer X, Y function I/O PWM output External interrupt input Port P6 CMOS compatible input level CMOS 3-state output A/D converter input Timer XY mode register PWM control register Interrupt edge selection register AD/DA control register (13) (14) (15) (16) (17) (18) (2) (1) Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-15 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION (1) Ports P0, P6 Pull-up control bit (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch A/D converter input Analog input pin selection bit Interrupt input (3) Ports P12 to P17, P2 Pull-up control bit Direction register (4) Ports P30, P31 Pull-up control bit Direction register Data bus Port latch Data bus Port latch D/A converter output DA1 output enable (P30) DA2 output enable (P31) (5) Ports P32, P33 I2C-BUS interface enable bit Direction register (6) Ports P34, P44 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Port latch Data bus Port latch Data bus SDA output SCL output SDA input SCL input Serial I/O input (7) Ports P35, P45 Pull-up control bit Serial I/O enable bit Transmit enable bit Direction register P-channel output disable bit (8) Ports P36, P46 Serial I/O synchronous clock selection bit Pull-up control bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Data bus Port latch Serial I/O output Serial I/O clock output Serial I/O external clock input Fig. 12 Port block diagram (1) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-16 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION (9) Port P37 Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Direction register (10) Port P40 Pull-up control bit Port XC switch bit Direction register Data bus Port latch Data bus Port latch INT40 interrupt input Serial I/O3 ready output Port P41 Port XC switch bit Oscillator (11) Port P41 Pull-up control bit (12) Port P47 Timer Z operating mode bits Bit 2 Bit 1 Bit 0 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Pull-up control bit Port XC switch bit Direction register Data bus Port latch Data bus Port latch INT00 interrupt input Sub-clock generating circuit input Timer output Serial I/O1 ready output CNTR2 interrupt input (13) Port P50 Pull-up control bit (14) Port P51 Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Direction register Data bus Port latch P-channel output disable bit Data bus Port latch Serial I/O2 input Serial I/O2 output Fig. 13 Port block diagram (2) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-17 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION (15) Port P52 Pull-up control bit Serial I/O2 synchronous clock selection bit (16) Port P53 Pull-up control bit Serial I/O2 port selection bit SRDY2 enable bit Direction register Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 (18) Port P56 Pull-up control bit Pull-up control bit PWM output enable bit Direction register Direction register Data bus Port latch Data bus Port latch Pulse output mode Timer output PWM output CNTR interrupt input Fig. 14 Port block diagram (3) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-18 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Port P0 pull-up control register (PULL0: address 0FF016) P00 pull-up control bit 0: No pull-up 1: Pull-up P01 pull-up control bit 0: No pull-up 1: Pull-up P02 pull-up control bit 0: No pull-up 1: Pull-up P03 pull-up control bit 0: No pull-up 1: Pull-up P04 pull-up control bit 0: No pull-up 1: Pull-up P05 pull-up control bit 0: No pull-up 1: Pull-up P06 pull-up control bit 0: No pull-up 1: Pull-up P07 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P1 pull-up control register (PULL1: address 0FF116) P10 pull-up control bit 0: No pull-up 1: Pull-up P11 pull-up control bit 0: No pull-up 1: Pull-up P12 pull-up control bit 0: No pull-up 1: Pull-up P13 pull-up control bit 0: No pull-up 1: Pull-up P14 pull-up control bit 0: No pull-up 1: Pull-up P15 pull-up control bit 0: No pull-up 1: Pull-up P16 pull-up control bit 0: No pull-up 1: Pull-up P17 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 15 Structure of port pull-up control register (1) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-19 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Port P2 pull-up control register (PULL2: address 0FF216) P20 pull-up control bit 0: No pull-up 1: Pull-up P21 pull-up control bit 0: No pull-up 1: Pull-up P22 pull-up control bit 0: No pull-up 1: Pull-up P23 pull-up control bit 0: No pull-up 1: Pull-up P24 pull-up control bit 0: No pull-up 1: Pull-up P25 pull-up control bit 0: No pull-up 1: Pull-up P26 pull-up control bit 0: No pull-up 1: Pull-up P27 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P3 pull-up control register (PULL3: address 0FF316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up Not used (return “0” when read) P34 pull-up control bit 0: No pull-up 1: Pull-up P35 pull-up control bit 0: No pull-up 1: Pull-up P36 pull-up control bit 0: No pull-up 1: Pull-up P37 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 16 Structure of port pull-up control register (2) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-20 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Port P4 pull-up control register (PULL4: address 0FF416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up P45 pull-up control bit 0: No pull-up 1: Pull-up P46 pull-up control bit 0: No pull-up 1: Pull-up P47 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P5 pull-up control register (PULL5: address 0FF516) P50 pull-up control bit 0: No pull-up 1: Pull-up P51 pull-up control bit 0: No pull-up 1: Pull-up P52 pull-up control bit 0: No pull-up 1: Pull-up P53 pull-up control bit 0: No pull-up 1: Pull-up P54 pull-up control bit 0: No pull-up 1: Pull-up P55 pull-up control bit 0: No pull-up 1: Pull-up P56 pull-up control bit 0: No pull-up 1: Pull-up P57 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 17 Structure of port pull-up control register (3) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-21 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Port P6 pull-up control register (PULL6: address 0FF616) P60 pull-up control bit 0: No pull-up 1: Pull-up P61 pull-up control bit 0: No pull-up 1: Pull-up P62 pull-up control bit 0: No pull-up 1: Pull-up P63 pull-up control bit 0: No pull-up 1: Pull-up P64 pull-up control bit 0: No pull-up 1: Pull-up P65 pull-up control bit 0: No pull-up 1: Pull-up P66 pull-up control bit 0: No pull-up 1: Pull-up P67 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 18 Structure of port pull-up control register (4) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-22 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION INTERRUPTS The 3804 group (Spaec. H)’s interrupts are a type of vector and occur by 16 sources among 23 sources: nine external, thirteen internal, and one software. s Notes When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) Timer Z mode register (address 002A16) I2C START/STOP condition control register (address 001616) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection register (address 003916) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ➀Set the corresponding interrupt enable bit to “0” (disabled). ➁Set the interrupt edge select bit or the interrupt source select bit to “1”. ➂Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. {Set the corresponding interrupt enable bit to “1” (enabled). Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt. When several interrupt requests occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Interrupt Source Selection Which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 003916). 1. INT0 or Timer Z 2. Serial I/O1 transmission or SCL, SDA 3. CNTR0 or SCL, SDA 4. CNTR1 or Serial I/O3 reception 5. Serial I/O2 or Timer Z 6. INT2 or I2C 7. INT4 or CNTR2 8. A/D converter or serial I/O3 transmission External Interrupt Pin Selection The occurrence sources of the external interrupt INT0 and INT4 can be selected from either input from INT00 and INT40 pin, or input from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003A16). Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-23 HARDWARE 3804 Group (Spec.H) Table 6 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission SCL, SDA Timer X Timer Y Timer 1 Timer 2 CNTR0 SCL, SDA CNTR1 Serial I/O3 reception Serial I/O2 Timer Z INT2 I 2C INT3 INT4 CNTR2 A/D converter Serial I/O3 transmission BRK instruction 16 FFDF16 FFDE16 11 FFE916 FFE816 6 7 8 9 10 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 Priority 1 2 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFFA16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At detection of either rising or falling edge of SCL or SDA At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of SCL or SDA At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow 13 FFE516 FFE416 At detection of either rising or falling edge of INT2 input At completion of data transfer At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A/D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty 17 FFDD16 FFDC16 At BRK instruction execution Valid when serial I/O3 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected STP release timer underflow Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected FUNCTIONAL DESCRIPTION 3 4 5 FFF916 FFF716 FFF516 FFF816 FFF616 FFF416 External interrupt (active edge selectable) 12 FFE716 FFE616 14 15 FFE316 FFE116 FFE216 FFE016 Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-24 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 19 Interrupt control Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-25 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns “0” when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns “0” when read) 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit/SCL, SDA interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0/SCL, SDA interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2/I2C interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0/SCL, SDA interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2/I2C interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns “0” when read) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit/SCL, SDA interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit b7 b0 Interrupt source selection register (INTSEL: address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt (Do not write “1” to these bits simultaneously.) Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Serial I/O1 transmit/SCL, SDA interrupt source selection bit 0 : Serial I/O1 transmit interrupt 1 : SCL, SDA interrupt (Do not write “1” to these bits simultaneously.) CNTR0/SCL, SDA interrupt source selection bit 0 : CNTR0 interrupt 1 : SCL, SDA interrupt INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt INT2/I2C interrupt source selection bit 0 : INT2 interrupt 1 : I2C interrupt CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A/D converter interrupt 1 : Serial I/O3 transmit interrupt Fig. 20 Structure of interrupt-related registers Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-26 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION TIMERS q8-bit Timers The 3804 group (Spec. H) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”. qTimer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B 16). When these bits are “ 00 ” ( high-speed mode) or “ 01 ” (middle-speed mode), X IN is selected. When these bits are“10” (low-speed mode), XCIN is selected. qPrescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN). Timer X and Timer Y The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316). (1) Timer mode qMode selection This mode can be selected by setting “00” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The timer count operation is started by setting “0” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). When the timer reaches “0016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse output mode qMode selection This mode can be selected by setting “01” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The operation is the same as the timer mode ’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. Regardless of the timer counting or not the output of CNTR0/CNTR1 pin is initialized to the level of specified by their active edge switch bits when writing to the timer. When the CNTR0 active edge switch bit (bit 2) and the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is “0”, the output starts with “H” level. When it is “1”, the output starts with “L” level. Switching the CNTR0 or CNTR1 active edge switch bit will reverse the output level of the corresponding CNTR0 or CNTR1 pin. sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P5 4/ P55 to output in this mode. Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit. qPrescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(XCIN). The count source is selected by the timer 12, X count source selection register (address 000E16) and the timer Y, Z count source selection register (address 000F16 ) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN) or f(XCIN); and f(XCIN). Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-27 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION (3) Event counter mode qMode selection This mode can be selected by setting “10” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation The operation is the same as the timer mode’s except that the timer counts signals input from the CNTR 0 o r CNTR 1 p in. The valid edge for the count operation depends on the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to input in this mode. (4) Pulse width measurement mode qMode selection This mode can be selected by setting “11” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). qExplanation of operation When the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is “1”, the timer counts during the term of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input (“L” term). When it is “0”, the timer counts during the term of one rising edge input until the next falling edge input (“H” term). sPrecautions Set the double-function port of CNTR0/CNTR1 pin and port P54/ P55 to input in this mode. The count operation can be stopped by setting “1” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). The interrupt request bit is set to “1” each time the timer underflows. •Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-28 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION XIN “00” “01” (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider Count source selection bit Data bus XCIN Clock for timer 12 Clock for timer Y Main clock division ratio selection bits Clock for timer X “10” Prescaler X latch (8) f(XCIN) Pulse width measurement mode Timer mode Pulse output mode Prescaler X (8) CNTR0 active edge switch bit “0” “1 ” CNTR0 active edge switch bit “1” Q Q Event counter mode Timer X count stop bit Timer X latch (8) Timer X (8) To timer X interrupt request bit P54/CNTR0 To CNTR0 interrupt request bit Toggle flip-flop T R Timer X latch write pulse Pulse output mode Port P54 direction register Port P54 latch “0” Pulse output mode Data bus Count source selection bit Clock for timer Y f(XCIN) Pulse width measurement mode Prescaler Y latch (8) Timer mode Pulse output mode Prescaler Y (8) Timer Y latch (8) Timer Y (8) P55/CNTR1 CNTR1 active edge switch bit “0” “1” To timer Y interrupt request bit Event counter mode Timer Y count stop bit To CNTR1 interrupt request bit CNTR1 active edge switch bit “1” Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode Port P55 direction register Port P55 latch “0” Pulse output mode Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) Clock for timer 12 Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 21 Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-29 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0 : Count start 1 : Count stop Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR1 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0 : Count start 1 : Count stop Fig. 22 Structure of timer XY mode register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-30 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Timer 12, X count source selection register (T12XCSS : address 000E16) Timer 12 count source selection bits b3b2b1b0 1010 : 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 Timer X count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) b7 b0 Not used 1011 : 1100 : 1101 : 1110 : 1111 : Not used Timer Y, Z count source selection register (TYZCSS : address 000F16) Timer Y count source selection bits b3b2b1b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Timer Z count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Not used 1011 : 1100 : 1101 : 1110 : 1111 : Not used Fig. 23 Structure of timer 12, X and timer Y, Z count source selection registers Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-31 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION q16-bit Timer The timer Z is a 16-bit timer. When the timer reaches “000016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to the timer Z is set to “1”. When reading/writing to the timer Z, perform reading/writing to both the high-order byte and the low-order byte. When reading the timer Z, read from the high-order byte first, followed by the low-order byte. Do not perform the writing to the timer Z between read operation of the high-order byte and read operation of the low-order byte. When writing to the timer Z, write to the low-order byte first, followed by the high-order byte. Do not perform the reading to the timer Z between write operation of the low-order byte and write operation of the high-order byte. The timer Z can select the count source by the timer Z count source selection bits of timer Y, Z count source selection register (bits 7 to 4 at address 000F16). Timer Z can select one of seven operating modes by setting the timer Z mode register (address 002A16). (2) Event counter mode qMode selection This mode can be selected by setting “000” to the timer Z operating mode bits (bits 2 to 0) and setting “1” to the timer/event counter mode switch bit (bit 7) of the timer Z mode register (address 002A16). The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. qInterrupt The interrupt at an underflow is the same as the timer mode’s. qExplanation of operation The operation is the same as the timer mode’s. Set the double-function port of CNTR2 pin and port P47 to input in this mode. Figure 26 shows the timing chart of the timer/event counter mode. (3) Pulse output mode qMode selection This mode can be selected by setting “001” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode’s. qExplanation of operation The operation is the same as the timer mode’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the output starts with “H” level. When it is “1”, the output starts with “L” level. sPrecautions The double-function port of CNTR2 pin and port P47 is automatically set to the timer pulse output port in this mode. The output from CNTR2 pin is initialized to the level depending on CNTR2 active edge switch bit by writing to the timer. When the value of the CNTR2 active edge switch bit is changed, the output level of CNTR2 pin is inverted. Figure 27 shows the timing chart of the pulse output mode. (1) Timer mode qMode selection This mode can be selected by setting “000” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt When an underflow occurs, the INT0/timer Z interrupt request bit (bit 0) of the interrupt request register 1 (address 003C16) is set to “1”. qExplanation of operation During timer stop, usually write data to a latch and a timer at the same time to set the timer value. The timer count operation is started by setting “0” to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16). When the timer reaches “000016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. When writing data to the timer during operation, the data is written only into the latch. Then the new latch value is reloaded into the timer at the next underflow. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-32 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION (4) Pulse period measurement mode qMode selection This mode can be selected by setting “010” to the timer Z operating mode bits (bits 2 to 0) and setting “ 0 ” t o the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode’s. When the pulse period measurement is completed, the INT 4 / CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to “1”. qExplanation of operation The cycle of the pulse which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the timer counts during the term from one falling edge of CNTR2 pin input to the next falling edge. When it is “1”, the timer counts during the term from one rising edge input to the next rising edge input. When the valid edge of measurement completion/start is detected, the 1’s complement of the timer value is written to the timer latch and “FFFF16” is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and “FFFF 16” is set to the timer. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. sPrecautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. Figure 28 shows the timing chart of the pulse period measurement mode. (5) Pulse width measurement mode qMode selection This mode can be selected by setting “011” to the timer Z operating mode bits (bits 2 to 0) and setting “ 0 ” t o the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode’s. When the pulse widths measurement is completed, the INT 4 / CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to “1”. qExplanation of operation The pulse width which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the timer counts during the term from one rising edge input to the next falling edge input (“H” term). When it is “1”, the timer counts during the term from one falling edge of CNTR2 pin input to the next rising edge of input (“L” term). When the valid edge of measurement completion is detected, the 1’s complement of the timer value is written to the timer latch. When the valid edge of measurement completion/start is detected, “FFFF16” is set to the timer. When the timer Z underflows, the timer Z interrupt occurs and “FFFF16” is set to the timer Z. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. sPrecautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. Figure 29 shows the timing chart of the pulse width measurement mode. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-33 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION •“L” one-shot pulse; Bit 5 of timer Z mode register = “1” The output level of the CNTR2 pin is initialized to “H” at mode selection. When trigger generation (input signal to INT 1 p in) is detected, “L” is output from the CNTR2 pin. When an underflow occurs, “H” is output. The “L” one-shot pulse width is set by the setting value to the timer Z low-order and high-order. When trigger generating is detected during timer count stop, although “L” is output from the CNTR2 pin, “L” output state continues because an underflow does not occur. sPrecautions Set the double-function port of INT1 pin and port P42 to input in this mode. Set the double-function port of CNTR2 pin and port P2 2 is automatically set to the programmable one-shot generating port in this mode. This mode cannot be used in low-speed mode. If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. Figure 31 shows the timing chart of the programmable one-shot generating mode. (6) Programmable waveform generating mode qMode selection This mode can be selected by setting “100” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode’s. qExplanation of operation The operation is the same as the timer mode’s. Moreover the timer outputs the data set in the output level latch (bit 4) of the timer Z mode register (address 002A16) from the CNTR2 pin each time the timer underflows. Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform from the CNTR2 pin. sPrecautions The double-function port of CNTR2 pin and port P47 is automatically set to the programmable waveform generating port in this mode. Figure 30 shows the timing chart of the programmable waveform generating mode. sNotes regarding all modes qTimer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. qTimer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. qSwitch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR2 active edge switch bit and the INT1 active edge selection bit. qSwitch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. qUsage of CNTR2 pin as normal I/O port To use the CNTR2 pin as normal I/O port P47, set timer Z operating mode bits (b2, b1, b0) of timer Z mode register (address 002A16) to “000”. (7) Programmable one-shot generating mode qMode selection This mode can be selected by setting “101” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). qCount source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. qInterrupt The interrupt at an underflow is the same as the timer mode’s. The trigger to generate one-shot pulse can be selected by the INT1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003A16). When it is “0”, the falling edge active is selected; when it is “1”, the rising edge active is selected. When the valid edge of the INT1 pin is detected, the INT1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003C16) is set to “1”. qExplanation of operation •“H” one-shot pulse; Bit 5 of timer Z mode register = “0” The output level of the CNTR2 pin is initialized to “L” at mode selection. When trigger generation (input signal to INT 1 p in) is detected, “H” is output from the CNTR2 pin. When an underflow occurs, “L” is output. The “H” one-shot pulse width is set by the setting value to the timer Z register low-order and high-order. When trigger generating is detected during timer count stop, although “H” is output from the CNTR 2 p in, “H” output state continues because an underflow does not occur. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-34 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION P42/INT1 Programmable one-shot generating mode Programmable one-shot generating circuit CNTR2 active edge Data bus Programmable one-shot switch bit “1” generating mode “0” Programmable waveform generating mode Output level latch D T Q To INT1 interrupt request bit Pulse output mode CNTR2 active edge switch bit S Q T “001” “100” “101” Q “0” “1” Pulse output mode Timer Z operating mode bits Port P47 direction register Timer Z low-order latch Port P47 latch Timer Z low-order Timer Z high-order latch Timer Z high-order To timer Z interrupt request bit Pulse period measurement mode Pulse width measurement mode Edge detection circuit “1” “1” To CNTR2 interrupt request bit Clock for timer Z P47/CNTR2 “0” f(XCIN) “0” CNTR2 active edge switch bit XIN Timer/Event counter mode switch bit Timer Z count stop bit XCIN Count source Divider selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Fig. 24 Block diagram of timer Z Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-35 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Timer Z mode register (TZM : address 002A16) Timer Z operating mode bits b2b1b0 0 0 0 : Timer/Event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : Not available 1 1 1 : Not available Timer Z write control bit 0 : Writing data to both latch and timer simultaneously 1 : Writing data only to latch Output level latch 0 : “L” output 1 : “H” output CNTR2 active edge switch bit 0 : •Event counter mode: Count at rising edge •Pulse output mode: Start outputting “H” •Pulse period measurement mode: Measurement between two falling edges •Pulse width measurement mode: Measurement of “H” term •Programmable one-shot generating mode: After start outputting “L”, “H” one-shot pulse generated •Interrupt at falling edge 1 : •Event counter mode: Count at falling edge •Pulse output mode: Start outputting “L” •Pulse period measurement mode: Measurement between two rising edges •Pulse width measurement mode: Measurement of “L” term •Programmable one-shot generating mode: After start outputting “H”, “L” one-shot pulse generated •Interrupt at rising edge Timer Z count stop bit 0 : Count start 1 : Count stop Timer/Event counter mode switch bit (Note) 0 : Timer mode 1 : Event counter mode Note: When selecting the modes except the timer/event counter mode, set “0” to this bit. Fig. 25 Structure of timer Z mode register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-36 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION FFFF16 TL 000016 TR TR TR TL : Value set to timer latch TR : Timer interrupt request Fig. 26 Timing chart of timer/event counter mode FFFF16 TL 000016 TR TR TR TR Waveform output from CNTR2 pin CNTR2 CNTR2 TL : Value set to timer latch TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 27 Timing chart of pulse output mode Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-37 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION 000016 T3 T2 T1 FFFF16 TR FFFF16 + T1 Signal input from CNTR2 pin CNTR2 CNTR2 CNTR2 of rising edge active TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 28 Timing chart of pulse period measurement mode (Measuring term between two rising edges) TR T2 T3 FFFF16 CNTR2 CNTR2 000016 T3 T2 T1 FFFF16 TR Signal input from CNTR2 pin FFFF16 + T2 T3 T1 CNTR2 CNTR2 CNTR2 CNTR2 interrupt of rising edge active; Measurement of “L” width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 29 Timing chart of pulse width measurement mode (Measuring “L” term) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-38 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION FFFF16 T3 L T2 T1 000016 Signal output from CNTR2 pin L TR T1 T3 T2 TR TR TR CNTR2 CNTR2 L : Timer initial value TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 30 Timing chart of programmable waveform generating mode FFFF16 L Signal input from INT1 pin Signal output from CNTR2 pin TR TR TR L CNTR2 L CNTR2 L L : One-shot pulse width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 31 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-39 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION SERIAL INTERFACE Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O1. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O1 control register Address 001A16 Address 001816 Receive buffer register 1 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P44/RXD1 Receive shift register 1 Shift clock P46/SCLK1 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY1 F/F Falling-edge detector Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 Address 001C16 1/4 Clock control circuit Shift clock Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 P45/TXD1 Transmit shift register 1 Transmit buffer register 1 Address 001816 Data bus Fig. 32 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD1 Serial input RxD1 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 33 Operation of clock synchronous serial I/O1 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-40 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the Data bus Address 001816 OE Receive buffer register 1 Character length selection bit ST detector 7 bits Receive shift register 1 8 bits PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator (f(XCIN) in low-speed mode) Address 001C16 1/4 ST/SP/PA generator 1/16 P45/TXD1 Character length selection bit Transmit buffer register 1 Transmit shift register 1 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 UART1 control register Address 001B16 P44/RXD1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Address 001816 Data bus Fig. 34 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD1 ST TBE=0 TBE=1 TSC=1✽ D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 ✽ SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD1 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 35 Operation of UART serial I/O1 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-41 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD1 pin. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Baud Rate Generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-42 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O pins) b7 b0 UART1 control register (UART1CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 36 Structure of serial I/O1 control registers Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-43 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation q Note Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to “0”. q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. 2.2 Stop of receive operation q Note Clear the receive enable bit to “0” (receive disabled). 2.3 Stop of transmit/receive operation q Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to “0”. q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, S CLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. q Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). s Notes concerning serial I/O1 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation q Note Clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, S CLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. 1.2 Stop of receive operation q Note Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0” (serial I/O disabled). 1.3 Stop of transmit/receive operation q Note Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) q Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O disabled) (refer to 1.1). Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-44 HARDWARE 3804 Group (Spec.H) 3. SRDY1 output of reception side q Note When signals are output from the SRDY1 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY1 output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O1 control register again q Note Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” FUNCTIONAL DESCRIPTION 7. Transmit interrupt request when transmit enable bit is set q Note When using the transmit interrupt, take the following sequence. ➀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instruction has executed. ➃ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). q Reason When the transmit enable bit is set to “ 1 ” , the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. ↓ Set the bits 0 to 3 and bit 6 of the serial I/O control register ↓ Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time 5. Data transmission control with referring to transmit shift register completion flag q Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected q Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLK1 input level. Also, write data to the transmit buffer register at “H” of the SCLK1 input level. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-45 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O2. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits b2 b1 b0 [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight bits which control various serial I/O2 functions. 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Fig. 37 Structure of serial I/O2 control register 1/8 1/16 Divider Internal synchronous clock selection bits f(XIN) (f(XCIN) in low-speed mode) 1/32 1/64 1/128 1/256 Data bus P53 latch “0” P53/SRDY2 Serial I/O2 synchronous clock selection bit “1” Synchronization circuit SCLK2 SRDY2 “1” SRDY2 output enable bit “0” External clock P52 latch “0” P52/SCLK2 “1” Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O2 interrupt request P51 latch “0” P51/SOUT2 “1” Serial I/O2 port selection bit P50/SIN2 Serial I/O2 register (8) Address 001F16 Fig. 38 Block diagram of serial I/O2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-46 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or f(XCIN) in low-speed mode, can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Fig. 39 Timing of serial I/O2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-47 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Serial I/O3 Serial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O3. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O3 mode can be selected by setting the serial I/O3 mode selection bit of the serial I/O3 control register (bit 6 of address 003216) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O3 control register Address 003216 Address 003016 Receive buffer register 3 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P34/RXD3 Receive shift register 3 Shift clock P36/SCLK3 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P37/SRDY3 F/F Falling-edge detector Serial I/O3 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 3 Address 002F16 1/4 Clock control circuit Shift clock Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 P35/TXD3 Transmit shift register 3 Transmit buffer register 3 Address 003016 Data bus Fig. 40 Block diagram of clock synchronous serial I/O3 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD3 Serial input RxD3 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY3 Write pulse to receive/transmit buffer register (address 003016) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 41 Operation of clock synchronous serial I/O3 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-48 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit of the serial I/O3 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the Data bus Address 003016 Receive buffer register 3 OE Character length selection bit ST detector 7 bits Receive shift register 3 Serial I/O3 control register Address 003216 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P34/RXD3 8 bits PE FE SP detector Clock control circuit Serial I/O3 synchronous clock selection bit P36/SCLK3 BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator 3 (f(XCIN) in low-speed mode) Address 002F16 1/4 ST/SP/PA generator 1/16 P35/TXD3 Character length selection bit Transmit buffer register 3 Transmit shift register 3 UART3 control register Address 003316 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 Address 003016 Data bus Fig. 42 Block diagram of UART serial I/O3 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD3 ST TBE=0 TBE=1 TSC=1✽ D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 ✽ SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD3 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 43 Operation of UART serial I/O3 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-49 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [Serial I/O3 Control Register (SIO3CON)] 003216 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 003316 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P35/TXD3 pin. [Serial I/O3 Status Register (SIO3STS)] 003116 The read-only serial I/O3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O3 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O3 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O3 enable bit SIOE (bit 7 of the serial I/O3 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O3 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 003016 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Baud Rate Generator 3 (BRG3)] 002F16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-50 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Serial I/O3 status register (SIO3STS : address 003116) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 Serial I/O3 control register (SIO3CON : address 003216) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O3 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY3 output enable bit (SRDY) 0: P37 pin operates as normal I/O pin 1: P37 pin operates as SRDY3 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O3 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O3 enable bit (SIOE) 0: Serial I/O disabled (pins P34 to P37 operate as normal I/O pins) 1: Serial I/O enabled (pins P34 to P37 operate as serial I/O pins) b7 b0 UART3 control register (UART3CON : address 003316) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P35/TXD3 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 44 Structure of serial I/O3 control registers Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-51 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation q Note Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to “0”. q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD3, RxD3, S CLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. 2.2 Stop of receive operation q Note Clear the receive enable bit to “0” (receive disabled). 2.3 Stop of transmit/receive operation q Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to “0”. q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD3, RxD3, S CLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. q Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). s Notes concerning serial I/O3 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation q Note Clear the serial I/O3 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD 3, RxD3, S CLK3, and SRDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD3 pin and an operation failure occurs. 1.2 Stop of receive operation q Note Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O3 enable bit to “0” (serial I/O disabled). 1.3 Stop of transmit/receive operation q Note Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) q Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O3 enable bit to “0” (serial I/O disabled) (refer to 1.1). Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-52 HARDWARE 3804 Group (Spec.H) 3. SRDY3 output of reception side q Note When signals are output from the SRDY3 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY3 output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O3 control register again q Note Set the serial I/O3 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” FUNCTIONAL DESCRIPTION 7. Transmit interrupt request when transmit enable bit is set q Note When using the transmit interrupt, take the following sequence. ➀ Set the serial I/O3 transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O3 transmit interrupt request bit to “0” after 1 or more instruction has executed. ➃ Set the serial I/O3 transmit interrupt enable bit to “1” (enabled). q Reason When the transmit enable bit is set to “ 1 ” , the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. ↓ Set the bits 0 to 3 and bit 6 of the serial I/O3 control register ↓ Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time 5. Data transmission control with referring to transmit shift register completion flag q Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected q Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLK3 input level. Also, write data to the transmit buffer register at “H” of the SCLK input level. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-53 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION PULSE WIDTH MODULATION (PWM) The 3804 group (Spec. H) has PWM functions with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2 or the clock input XCIN or that clock input divided by 2 in low-speed mode. PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “ 1 ” , operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as port P56. Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(XIN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz) Output pulse “H” term = PWM period ✕ m / 255 = 0.125 ✕ (n+1) ✕ m µs (when f(XIN) = 8 MHz) 31.875 ✕ m ✕(n+1) µs 255 PWM output T = [31.875 ✕ (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz Fig. 45 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch Count source selection bit XIN or PWM register latch “0” “1” Port P56 PWM register PWM prescaler XCIN 1/2 Port P56 latch PWM enable bit Fig. 46 Block diagram of PWM function Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-54 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 PWM control register (PWMCON : address 002B16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 Not used (return “0” when read) Fig. 47 Structure of PWM control register A B C B= C T2 T PWM output T PWM register write signal T T2 (Changes “H” term from “A” to “B”.) PWM prescaler write signal (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 48 PWM output timing when PWM register or PWM prescaler is changed Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-55 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION A/D CONVERTER [AD Conversion Register 1, 2 (AD1, AD2)] 003516, 003816 The AD conversion register is a read-only register that stores the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read. Bit 7 of the AD conversion register 2 is the conversion mode selection bit. When this bit is set to “0,” the A/D converter becomes the 10-bit A/D mode. When this bit is set to “1,” that becomes the 8-bit A/D mode. The conversion result of the 8-bit A/D mode is stored in the AD conversion register 1. As for 10-bit A/D mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the AD conversion registers 1, 2 after A/D conversion is completed (in Figure 50). As for 10-bit A/D mode, the 8-bit reading inclined to MSB is performed when reading the AD converter register 1 after A/D conversion is started; and when the AD converter register 1 is read after reading the AD converter register 2, the 8-bit reading inclined to LSB is performed. Channel Selector The channel selector selects one of ports P67/AN7 to P60/AN0 or P07/AN15 to P00/AN8, and inputs the voltage to the comparator. Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the AD conversion registers 1, 2. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A/D conversion. b7 b0 AD/DA control register (ADCON : address 003416) Analog input pin selection bits 1 b2 b1 b0 [AD/DA Control Register (ADCON)] 003416 The AD/DA control register controls the A/D conversion process. Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at “0” during an A/D conversion, and changes to “1” when an A/D conversion ends. Writing “0” to this bit starts the A/D conversion. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: P60/AN0 or P00/AN8 1: P61/AN1 or P01/AN9 0: P62/AN2 or P02/AN10 1: P63/AN3 or P03/AN11 0: P64/AN4 or P04/AN12 1: P65/AN5 or P05/AN13 0: P66/AN6 or P06/AN14 1: P67/AN7 or P07/AN15 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Analog input pin selection bit 2 0: AN0 to AN7 side 1: AN8 to AN15 side Not used (returns “0” when read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled Comparison Voltage Generator The comparison voltage generator divides the voltage between VREF and AVSS into 1024, and that outputs the comparison voltage in the 10-bit A/D mode (256 division in 8-bit A/D mode). The A/D converter successively compares the comparison voltage Vref in each mode, dividing the VREF voltage (see below), with the input voltage. • 10-bit A/D mode (10-bit reading) Vref = VREF ✕ n (n = 0–1023) 1024 • 10-bit A/D mode (8-bit reading) Vref = VREF ✕ n (n = 0–255) 256 • 8-bit A/D mode Vref = VREF ✕ (n–0.5) (n = 1–255) 256 =0 (n = 0) Fig. 49 Structure of AD/DA control register 10-bit reading (Read address 003816 before 003516) b0 b7 AD conversion register 2 0 b9 b8 (AD2: address 003816) b7 b0 AD conversion register 1 b7 b6 b5 b4 b3 b2 b1 b0 (AD1: address 003516) Note : Bits 2 to 6 of address 003816 become “0” at reading. 8-bit reading (Read only address 003516) b7 b0 AD conversion register 1 b9 b8 b7 b6 b5 b4 b3 b2 (AD1: address 003516) Fig. 50 Structure of 10-bit A/D mode reading Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-56 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Data bus AD/DA control register (Address 003416) b7 b0 4 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 A/D control circuit AD conversion register 2 AD conversion register 1 10 Resistor ladder AD converter interrupt request Comparator (Address 003816) (Address 003516) Channel selector VREF AVSS Fig. 51 Block diagram of A/D converter Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-57 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION D/A CONVERTER The 3804 group (Spec. H) has two internal D/A converters (DA1 and DA2) with 8-bit resolution. The D/A conversion is performed by setting the value in each DA conversion register. The result of D/A conversion is output from the DA1 or DA2 pin by setting the DA output enable bit to “1”. When using the D/A converter, the corresponding port direction register bit (P30/DA1 or P31/DA2) must be set to “0” (input status). The output analog voltage V is determined by the value n (decimal notation) in the DA conversion register as follows: V = VREF ✕ n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the DA conversion registers are cleared to “00 16”, and the DA output enable bits are cleared to “0”, and the P30/DA1 and P31/DA2 pins become high impedance. The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load. DA1 conversion register (8) DA1 output enable bit P30/DA1 Data bus R-2R resistor ladder DA2 conversion register (8) DA2 output enable bit P31/DA2 R-2R resistor ladder Fig. 52 Block diagram of D/A converter “0” DA1 output enable bit R P30/DA1 “1” MSB DA1 conversion register “0” “1” 2R R R R R R R 2R 2R 2R 2R 2R 2R 2R 2R LSB AVSS VREF Fig. 53 Equivalent connection circuit of D/A converter (DA1) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-58 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION When bit 6 of the watchdog timer control register is kept at “0”, the STP instruction is enabled. When that is executed, both the clock and the watchdog timer stop. Count re-starts at the same time as the release of stop mode (Note) . The watchdog timer does not stop while a WIT instruction is executed. In addition, the STP instruction is disabled by writing “1” to this bit again. When the STP instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. Once a “1” is written to this bit, it cannot be programmed to “0” again. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is “0”: when XCIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is “1”: when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 µs Note: The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not underflow during this period. WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Watchdog Timer Initial Value Watchdog timer L is set to “FF16” and watchdog timer H is set to “FF16” by writing to the watchdog timer control register (address 001E16) or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. Watchdog Timer Operations The watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. An internal reset occurs when watchdog timer H underflows. The reset is released after its release time. After the release, the program is restarted from the reset vector address. Usually, write to the watchdog timer control register by software before an underflow of the watchdog timer H. The watchdog timer does not function if the watchdog timer control register is not written to at least once. XCIN “10” Main clock division ratio selection bits (Note) XIN “FF16” is set when watchdog timer control register is written to. Watchdog timer L (8) 1/16 Data bus “FF16” is set when watchdog timer control register is written to. Watchdog timer H (8) “0” “1” “00” “01” Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit Reset release time waiting Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Internal reset RESET Fig. 54 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001E16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 55 Structure of Watchdog timer control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-59 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION MULTI-MASTER I2C-BUS INTERFACE The 3804 group (Spec. H) has the multi-master interface. The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 56 shows a block diagram of the multi-master I2C-BUS interface and Table 7 lists the multi-master I 2 C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C slave address registers 0 to 2, the I2C data shift register, the I 2C clock control register, the I2C control register, the I2C status register, the I2C START/STOP condition control register, the I2C special mode control register, the I2C special mode status register, and other control circuits. When using the multi-master I2 C-BUS interface, set 1 MHz or more to the internal clock φ. I2C-BUS Table 7 Multi-master I2C-BUS interface functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ= 4 MHz) Format Communication mode SCL clock frequency System clock φ = f(XIN)/2 (high-speed mode) φ = f(XIN)/8 (middle-speed mode) Interrupt generating circuit Interrupt request signal (SCL, SDA, IRQ) b7 I2C slave address registers 0 to 2 b0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB S0D0–2 Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I2C data shift register S0 Interrupt generating circuit Interrupt request signal (I2CIRQ) b0 b7 MST TRX BB PIN b0 AL AAS AD0 LRB SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 S2D I2C START/STOP condition control register AL circuit S1 Internal data bus I2C status register BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE b7 S PCF PIN2 b0 A AS2 A AS1 A AS0 S2 I2C clock control register Clock division System clock (φ) S3 I2C special mode status register b7 b7 TISS TSEL 10BIT AL S SAD b0 PIN2 HD PIN2 IN HSLAD ACK I CON b0 ES0 BC2 BC1 BC0 SPCFL S1D I2C control register Bit counter S3D I2 C special mode control register Fig. 56 Block diagram of multi-master I2C-BUS interface ✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-60 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [I2C Data Shift Register (S0)] 001116 The I2C data shift register (S0: address 001116) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The minimum 2 cycles of the internal clock φ a re required from the rising of the SCL until input to this register. The I2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit) of the I2C control register (S1D: address 001416) is “1”. The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (S1: address 001316) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value. b7 b0 I2C slave address register 0 (S0D0: address 0FF716) I2C slave address register 1 (S0D1: address 0FF816) I2C slave address register 2 (S0D2: address 0FF916) Read/write bit Slave address SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB Fig. 57 Structure of I2C slave address registers 0 to 2 [I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)] 0FF716 to 0FF916 The I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to 0FF916) consists of a 7-bit slave address and a read/ write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected. •Bit 0: Read/write bit (RWB) This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, set RWB to “0” because the first address data to be received is compared with the contents (SAD6 to SAD0 + RWB) of the I2C slave address registers 0 to 2. When 2-byte address data match slave address, a 7-bit slave address which is received after restart condition has detected and R/W data can be matched by setting “1” to RWB with software. The RWB is cleared to “0” automatically when the stop condition is detected. •Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bits’ contents. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-61 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [I2C Clock Control Register (S2)] 001516 The I2C clock control register (S2: address 001516) is used to set ACK control, SCL mode and SCL frequency. •Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 8. •Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is selected. When the bit is set to “1,” the high-speed clock mode is selected. When connecting the bus of the high-speed mode I2C bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) in the high-speed mode (2 division clock). •Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock ✽ is generated. When this bit is set to “0,” the ACK return mode is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is selected. The SDA is held in the “H” status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is automatically made “H” (ACK is not returned). ✽ACK clock: Clock for acknowledgment b7 ACK ACK BIT b0 FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 I2C clock control register (S2 : address 001516) SCL frequency control bits Refer to Table 8. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock Fig. 58 Structure of I2C clock control register Table 8 Set values of I 2 C clock control register and SCL frequency SCL frequency Setting value of (at φ = 4 MHz, unit : kHz) (Note 1) CCR4–CCR0 Standard clock High-speed clock CCR4 CCR3 CCR2 CCR1 CCR0 mode mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Setting disabled Setting disabled Setting disabled – (Note 2) – (Note 2) 100 83.3 500/CCR value (Note 3) 17.2 16.6 16.1 Setting disabled Setting disabled Setting disabled 333 250 400 (Note 3) 166 1000/CCR value (Note 3) 34.5 33.3 32.3 •Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to “0,” the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA “H”) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transfer. If data is written during transfer, the I 2C clock generator is reset, so that data cannot be transferred normally. … … … … 0 1 1 1 1 1 1 1 1 1 1 1 Notes 1: Duty of SCL output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration reduction. These are values when SCL synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of 4 MHz or less. 3: The data formula of SCL frequency is described below: φ/(8 ✕ CCR value) Standard clock mode φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5) φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of φ frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. … 1 0 1 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-62 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [I2C Control Register (S1D)] 001416 The I2C control register (S1D: address 001416) controls data communication format. •Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK clock bit (bit 7 of S2, address 001516) have been transferred, and BC0 to BC2 are returned to “0002”. Also when a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. •Bit 3: I2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to “0,” the use disable status is provided, so that the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ES0 = “0,” the following is performed. • PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C status register, S1, at address 001316 ). • Writing data to the I2C data shift register (S0: address 001116) is disabled. •Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “I 2 C Status Register,” bit 1) is received, transfer processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recognized. •Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C slave address registers 0 to 2 are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, and all the bits of the I2C slave address registers 0 to 2 are compared with address data. •Bit 7: I2C-BUS interface pin input level selection bit (TISS) This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. b7 TISS 10 B IT S AD b0 ALS ES0 BC2 BC1 BC0 I2C control register (S1D : address 001416) Bit counter (Number of transmit/receive bits) b2 b 1 b0 0 0 0:8 0 0 1:7 0 1 0:6 0 1 1:5 1 0 0:4 1 0 1:3 1 1 0:2 1 1 1:1 I2C-BUS interface enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format Not used (return “0” when read) I2C-BUS interface pin input level selection bit 0 : SMBUS input 1 : CMOS input Fig. 59 Structure of I2C control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-63 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [I2C Status Register (S1)] 001316 The I2C status register (S1: address 001316) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set “00002” to the low-order 4 bits, because these bits become the reserved bits at writing. •Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (S0: address 001116). •Bit 1: General call detecting flag (AD0) When the ALS bit is “0”, this bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “ 0 ” b y detecting the STOP condition or START condition, or reset. ✽General call: The master transmits the general call address “00 16” to all slaves. •Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is “0”. ➀ In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions: • The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2C slave address register. • A general call is received. ➁ In the slave receive mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition: • When the address data is compared with the I 2C slave address register (8 bits consisting of slave address and RWB bit), the first bytes agree. ➂ This bit is set to “0” by executing a write instruction to the I2C data shift register (S0: address 001116) when ES0 is set to “1” or reset. •Bit 3: Arbitration lost✽ detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” The arbitration lost can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the agreement of its own slave address and address data transmitted by another master device. The AL bit is set to “0” in one of the following conditions: •Executing a write instruction to the I2C data shift register (S0: address 001116) •When the ES0 bit is “0” •At reset ✽Arbitration lost :The status in which communication as a master is disabled. •Bit 4: SCL pin low hold bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the PIN bit changes from “ 1 ” t o “ 0. ” A t the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 61 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions: • Executing a write instruction to the I 2C data shift register (S0: address 001116). (This is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.) • When the ES0 bit is “0” • At reset • When writing “1” to the PIN bit by software The PIN bit is set to “0” in one of the following conditions: • Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) • Immediately after completion of 1-byte data reception • In the slave reception mode, with ALS = “0” and immediately after completion of slave address agreement or general call address reception • In the slave reception mode, with ALS = “1” and immediately after completion of address data reception •Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to “1” by detecting the START condition, and is set to “0” by detecting the STOP condition. The condition of these detecting is set by the START/STOP condition setting bits (SSC4 – SSC0) of the I 2 C START/STOP condition control register (S2D: address 001616). When the ES0 bit of the I2C control register (bit 3 of S1D, address 001416) is “0” or reset, the BB flag is set to “0.” For the writing function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition Generating Method” described later. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-64 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION •Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. This bit is set/reset by software and hardware. About set/reset by hardware is described below. This bit is set to “1” by hardware when all the following conditions are satisfied: • When ALS is “0” • In the slave reception mode or the slave transmission mode • When the R/W bit reception is “1” This bit is set to “0” in one of the following conditions: • When arbitration lost is detected. • When a STOP condition is detected. • When writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note). • With MST = “0” and when a START condition is detected. • With MST = “0” and when ACK non-return is detected. • At reset •Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communication are generated on the SCL. This bit is set to “0” in one of the following conditions. • Immediately after completion of the byte which has lost arbitration when arbitration lost is detected • When a STOP condition is detected. • Writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note). • At reset Note: START condition duplication preventing function The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition occurrence. However, when a START condition by another master device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. b7 b0 I2C status register (S1 : address 001316) Last receive bit (Note) 0 : Last bit = “0” 1 : Last bit = “1” General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected SCL pin low hold bit 0 : SCL pin low hold 1 : SCL pin low release Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode MST TRX BB PIN AL AAS AD0 LRB Note: These bits and flags can be read out, but cannot be written. Write “0” to these bits at writing. Fig. 60 Structure of I2C status register SCL PIN I2CIRQ Fig. 61 Interrupt request signal generating timing Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-65 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION START Condition Generating Method When writing “1” to the MST, TRX, and BB bits of the I2C status register (S1: address 001316) at the same time after writing the slave address to the I2C data shift register (S0: address 001116) with the condition in which the ES0 bit of the I2C control register (S1D: address 001416) is “1” and the BB flag is “0”, a START condition occurs. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 62, the START condition generating timing diagram, and Table 9, the START condition generating timing table. STOP Condition Generating Method When the ES0 bit of the I 2 C control register (S1D: address 001416) is “1,” write “1” to the MST and TRX bits, and write “0” to the BB bit of the I2C status register (S1: address 001316) simultaneously. Then a STOP condition occurs. The STOP condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 63, the STOP condition generating timing diagram, and Table 10, the STOP condition generating timing table. I2C status register write signal SCL Setup time Hold time I 2C status register write signal Setup time Hold time SDA SCL SDA Fig. 63 STOP condition generating timing diagram Table 10 STOP condition generating timing table High-speed clock mode Standard clock mode Item 3.0 µs (12 cycles) 5.0 µs (20 cycles) Setup time 2.5 µs (10 cycles) 4.5 µs (18 cycles) Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Fig. 62 START condition generating timing diagram Table 9 START condition generating timing table Standard clock mode High-speed clock mode Item 2.5 µs (10 cycles) 5.0 µs (20 cycles) Setup time 2.5 µs (10 cycles) 5.0 µs (20 cycles) Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-66 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 64, 65, and Table 11. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL release time, setup time, and hold time (see Table 11). The BB flag is set to “1” by detecting the START condition and is reset to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 11, the BB flag set/ reset time. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “I2CIRQ” occurs to the CPU. SCL release time SCL SDA BB flag Setup time Hold time BB flag set time Fig. 64 START/STOP condition detecting timing diagram SCL release time SCL SDA BB flag Setup time Hold time BB flag reset time Table 11 START condition/STOP condition detecting conditions Standard clock mode High-speed clock mode SCL release time Setup time Hold time BB flag set/ reset time SSC value + 1 cycle (6.25 µs) 4 cycles (1.0 µs) SSC value + 1 cycle < 4.0 µs (3.125 µs) 2 cycles (0.5 µs) 2 SSC value + 1 cycle < 4.0 µs (3.125 µs) 2 cycles (0.5 µs) 2 SSC value –1 + 2 cycles (3.375 µs) 3.5 cycles (0.875 µs) 2 Fig. 65 STOP condition detecting timing diagram Note: Unit : Cycle number of internal clock φ SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the I2C START/ STOP condition control register is set to “1816” at φ = 4 MHz. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-67 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [I2C START/STOP Condition Control Register (S2D)] 001616 The I2C START/STOP condition control register (S2D: address 001616) controls START/STOP condition detection. •Bits 0 to 4: START/STOP condition set bits (SSC4–SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(XIN) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 11. Do not set “000002” or an odd number to the START/STOP condition set bits (SSC4 to SSC0). Refer to Table 12, the recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency. •Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin. •Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin. Note: When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/ SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt. b7 b0 SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 I2C START/STOP condition control register (S2D : address 001616) START/STOP condition set bits SCL/SDA interrupt pin polarity selection bit 0 : Falling edge active 1 : Rising edge active SCL/SDA interrupt pin selection bit 0 : SDA valid 1 : SCL valid Not used (Fix this bit to “0”.) Fig. 66 Structure of I2C START/STOP condition control register Table 12 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency Oscillation frequency f(XIN) (MHz) 8 8 4 2 Main clock divide ratio 2 8 2 2 Internal clock φ (MHz) 4 1 2 1 START/STOP condition control register XXX11010 XXX11000 XXX00100 XXX01100 XXX01010 XXX00100 SCL release time (µs) 6.75 µs (27 cycles) 6.25 µs (25 cycles) 5.0 µs (5 cycles) 6.5 µs (13 cycles) 5.5 µs (11 cycles) 5.0 µs (5 cycles) Setup time (µs) 3.5 µs (14 cycles) 3.25 µs (13 cycles) 3.0 µs (3 cycles) 3.5 µs (7 cycles) 3.0 µs (6 cycles) 3.0 µs (3 cycles) Hold time (µs) 3.25 µs (13 cycles) 3.0 µs (12 cycles) 2.0 µs (2 cycles) 3.0 µs (6 cycles) 2.5 µs (5 cycles) 2.0 µs (2 cycles) Note: Do not set an odd number to the START/STOP condition set bits (SSC4 to SSC0) and “000002”. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-68 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [I 2 C Special Mode Status Register (S3)] 001216 The I2 C special mode status register (S3: address 001216) consists of the flags indicating I2C operating state in the I2C special mode, which is set by the I2C special mode control register (S3D: address 001716). The stop condition flag is valid in all operating modes. •Bit 0: Slave address 0 comparison flag (AAS0) Bit 1: Slave address 1 comparison flag (AAS1) Bit 2: Slave address 2 comparison flag (AAS2) These flags indicate a comparison result of address data. These flags are valid only when the slave address control bit (MSLAD) is “1”. In the 7-bit addressing format of the slave reception mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I2C slave address registers 0 to 2 are set to “1” when an address data immediately after an occurrence of a START condition agrees with the high-order 7-bit slave address stored in the I2C slave address registers 0 to 2 (addresses 0FF716 to 0FF916). In the 10-bit addressing format of the slave mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I2C slave address registers are set to “1” when an address data is compared with the 8 bits consisting of the slave address stored in the I2C slave address registers 0 to 2 and the RWB bit, and the first byte agrees. These flags are initialized to “0” at reset, when the slave address control bit (MSLAD) is “0”, or when writing data to the I2C data shift register (S0: address 001116). •Bit 5: SCL pin low hold 2 flag (PIN2) When the ACK interrupt control bit (ACKICON) and the ACK clock bit (ACK) are “1”, this flag is set to “0” in synchronization with the falling of the data’s last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs. This flag is initialized to “1” at reset, when the ACK interrupt control bit (ACKICON) is “0”, or when writing “1” to the SCL pin low hold 2 flag set bit (PIN2IN). The SCL pin is held low when either the SCL pin low hold bit (PIN) or the SCL pin low hold 2 flag (PIN2) becomes “0”. The low hold state of the SCL pin is released when both the SCL pin low hold bit (PIN) and the SCL pin low hold 2 flag (PIN2) are “1”. •Bit 7: Stop condition flag (SPCF) This flag is set to “1” when a STOP condition occurs. This flag is initialized to “0” at reset, when the I2C-BUS interface enable bit (ES0) is “0”, or when writing “1” to the STOP condition flag clear bit (SPFCL). b7 SP CF PIN2 b0 AAS2 AA S1 AAS0 I2C special mode status register (S3 : address 001216) Slave address 0 comparison flag 0 : Address disagreement 1 : Address agreement Slave address 1 comparison flag 0 : Address disagreement 1 : Address agreement Slave address 2 comparison flag 0 : Address disagreement 1 : Address agreement Not used (return “0” when read) Not used (return “0” when read) SCL pin low hold 2 flag 0 : SCL pin low hold 1 : SCL pin low release (Note) Not used (return “0” when read) STOP condition flag 0 : No detection 1 : Detection Note: In order that the low hold state of the SCL pin may release, it is necessary that the SCL pin low hold 2 flag and the SCL pin low hold bit (PIN) are “1” simultaneously. Fig. 67 Structure of I2C special mode status register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-69 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION [I 2 C Special Mode Control Register (S3D)] 001716 The I2C special mode control register (S3D: address 001716) controls special functions such as occurrence timing of reception interrupt request and extending slave address comparison to 3 bytes. •Bit 1: ACK interrupt control bit (ACKICON) This bit controls the timing of I2C interrupt request occurrence at completion of data receiving due to master reception or slave reception. When this bit is “0”, the SCL pin low hold bit (PIN) is set to “0” in synchronization with the falling of the last SCL clock, including the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs. When this bit is “1” and the ACK clock bit (ACK) is “1”, the SCL pin low hold 2 flag (PIN2) is set to “0” in synchronization with the falling of the data’s last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs again. The ACK bit can be changed after the contents of data are confirmed by using this function. •Bit 2: I2C slave address control bit (MSLAD) This bit controls a slave address. When this bit is “0”, only the I2C slave address register 0 (address 0FF716 ) becomes valid as a slave address and a read/write bit. When this bit is “1”, all of the I2C slave address registers 0 to 2 (addresses 0FF7 16 to 0FF916) become valid as a slave address and a read/write bit. In this case, when an address data agrees with any one of the I2C slave address registers 0 to 2, the slave address comparison flag (AAS) is set to “1” and the I2C slave address comparison flag corresponding to the agreed I 2C slave address registers 0 to 2 is also set to “1”. •Bit 5: SCL pin low hold 2 flag set bit (PIN2IN) Writing “1” to this bit initializes the SCL pin low hold 2 flag (PIN2) to “1”. When writing “0”, nothing is generated. •Bit 6: SCL pin low hold set bit (PIN2HD) When the SCL pin low hold bit (PIN) becomes “0”, the SCL pin is held low. However, the SCL pin low hold bit (PIN) cannot be set to “0” by software. The SCL pin low hold set bit (PIN2HD) is used to , hold the SCL pin in the low state by software. When writing “1” to this bit, the SCL pin low hold 2 flag (PIN2) becomes “0”, and the SCL pin is held low. When writing “0”, nothing occurs. •Bit 7: STOP condition flag clear bit (SPFCL) Writing “1” to this bit initializes the STOP condition flag (SPCF) to “0”. When writing “0”, nothing is generated. b7 SPFCL b0 PIN2- PIN2IN HD MSLAD ACKI CON I2C special mode control register (S3D : address 001716) Not used (Fix this bit to “0”.) ACK interrupt control bit 0 : At communication completion 1 : At falling of ACK clock and communication completion Slave address control bit 0 : One-byte slave address compare mode 1 : Three-byte slave address compare mode Not used (return “0” when read) Not used (Fix this bit to “0”.) SCL pin low hold 2 flag set bit (Notes 1, 2) Writing “1” to this bit initializes the SCL pin low hold 2 flag to “1”. SCL pin low hold set bit (Notes 1, 2) When writing “1” to this bit, the SCL pin low hold 2 flag becomes “0” and the SCL pin is held low. STOP condition flag clear bit (Note 2) Writing “1” to this bit initializes the STOP condition flag to “0”. Notes 1: Do not write “1” to these bits simultaneously. 2: return “0” when read Fig. 68 Structure of I2C special mode control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-70 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. ➀ 7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (S1D: address 001416) to “0”. The first 7bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I 2C slave address register. At the time of this comparison, address comparison of the RWB bit of the I2C slave address register is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 69, (1) and (2). ➁ 10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (S1D: address 0014 16) to “1.” An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I2C slave address register. At the time of this com- parison, an address comparison between the RWB bit of the I2C slave address register and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RWB bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I2C status register (S1: address 001316) is set to “1.” After the second-byte address data is stored into the I2C data shift register (S0: address 001116 ), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RWB bit of the I2C slave address register to “1” by software. This processing can make the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of the I2C slave address register. For the data transmission format when the 10-bit addressing format is selected, refer to Figure 69, (3) and (4). (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W 7 bits “0” A Data 1 to 8 bits A Data 1 to 8 bits A/A P (2) A master-receiver receives data from a slave-transmitter S Slave address R/W 7 bits “1” A Data 1 to 8 bits A Data 1 to 8 bits A P (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address S Slave address R/W 1st 7 bits 7 bits “0” A Slave address 2nd bytes 8 bits A Data 1 to 8 bits A Data 1 to 8 bits A/A P (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S Slave address R/W 1st 7 bits 7 bits “0” A Slave address 2nd bytes 8 bits A Sr Slave address R/W 1st 7 bits 7 bits “1” A Data 1 to 8 bits A Data 1 to 8 bits A P S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit : Master to slave : Slave to master Fig. 69 Address data communication format Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-71 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C slave address register and “0” into the RWB bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (S2: address 001516). ➂ Set “0016” in the I 2C status register (S1: address 001316 ) so that transmission/reception mode can become initializing condition. ➃ Set a communication enable status by setting “0816” in the I2C control register (S1D: address 001416). ➄ Confirm the bus free condition by the BB flag of the I2C status register (S1: address 001316). ➅ Set the address data of the destination of transmission in the high-order 7 bits of the I 2 C data shift register (S0: address 001116) and set “0” in the least significant bit. ➆ Set “F0 16” in the I 2C status register (S1: address 001316 ) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occur. ➇ S et transmit data in the I 2 C data shift register (S0: address 001116). At this time, an SCL and an ACK clock automatically occur. ➈ When transmitting control data of more than 1 byte, repeat step ➇. ➉ Set “D016” in the I2C status register (S1: address 0013 16) to generate a STOP condition if ACK is not returned from slave reception side or transmission ends. Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C slave address register and “0” in the RWB bit. ➁ S et the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (S2: address 001516). ➂ Set “00 16” in the I2C status register (S1: address 0013 16) so that transmission/reception mode can become initializing condition. ➃ Set a communication enable status by setting “0816” in the I2C control register (S1D: address 001416). ➄ When a START condition is received, an address comparison is performed. ➅ •When all transmitted addresses are “0” (general call): AD0 of the I2C status register (S1: address 001316) is set to “1” and an interrupt request signal occurs. • When the transmitted addresses agree with the address set in ➀: AAS of the I2C status register (S1: address 001316) is set to “1” and an interrupt request signal occurs. • In the cases other than the above AD0 and AAS of the I2C status register (S1: address 001316) are set to “0” and no interrupt request signal occurs. ➆ S et dummy data in the I 2 C data shift register (S0: address 001116). ➇ When receiving control data of more than 1 byte, repeat step ➆. ➈ When a STOP condition is detected, the communication ends. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-72 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION sPrecautions when using multi-master I2CBUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. • I2C data shift register (S0: address 001116) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. • I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to0FF916) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because H/W changes the read/write bit (RWB) at the above timing. • I2C status register (S1: address 001316) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by H/W. • I2C control register (S1D: address 001416) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because H/W changes the bit counter (BC0-BC2) at the above timing. • I2C clock control register (S2: address 001516) The read-modify-write instruction can be executed for this register. • I 2 C START/STOP condition control register (S2D: address 001616) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure using multi-master 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 5. : : LDA — SEI BBS 5, S1, BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI : : BUSBUSY: CLI : : (Taking out of slave address value) (Interrupt disabled) (BB flag confirming and branch process) (Writing of slave address value) (Trigger of START condition generating) (Interrupt enabled) 5. Disable interrupts during the following three process steps: • BB flag confirming • Writing of slave address value • Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. (3) RESTART condition generating procedure 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 4.) Execute the following procedure when the PIN bit is “0.” : : LDM #$00, S1 LDA — SEI STA S0 LDM #$F0, S1 CLI : : (Select slave receive mode) (Taking out of slave address value) (Interrupt disabled) (Writing of slave address value) (Trigger of RESTART condition generating) (Interrupt enabled) 2. Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. 3. The SCL pin is released by writing the slave address value to the I2C data shift register. 4. Disable interrupts during the following two process steps: • Writing of slave address value • Trigger of RESTART condition generating (4) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become the same as above. (5) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “ 0 ” a fter generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers does not have the problem. (Interrupt enabled) 2. Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirming and branch process. 3. Use “ STA $12, STX $12 ” o r “ STY $12 ” o f the zero page addressing instruction for writing the slave address value to the I2C data shift register. 4. Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown the above procedure example. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-73 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Then the RESET pin is returned to an “H” level (the power source voltage should be between 2.7 V to 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 ( high-order byte) and address FFFC16 (low-order byte). Input to the RESET pin in the following procedure. qWhen power source is stabilized (1) Input “L” level to RESET pin. (2) Input “L” level for 16 cycles or more to XIN pin. (3) Input “H” level to RESET pin. qAt power-on (1) Input “L” level to RESET pin. (2) Increase the power source voltage to 2.7 V. (3) Wait for td(P-R) until internal power source has stabilized. (4) Input “L” level for 16 cycles or more to XIN pin. (5) Input “H” level to RESET pin. VCC RESET VCC 0V 2.7 V RESET 0V 0.2VCC or less td(P-R)+XIN 16 cycles or more 5V RESET VCC Power source voltage detection circuit VCC 0V 5V 2.7 V RESET 0V td(P-R)+XIN 16 cycles or more Example at VCC = 5V Fig. 70 Reset circuit example XIN φ RESET Internal reset Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 71 Reset sequence Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-74 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0 0110011 0 0110011 0016 (41) Timer Z (low-order) (TZL) (42) Timer Z (high-order) (TZH) (43) Timer Z mode register (TZM) (44) PWM control register (PWMCON) (45) PWM prescaler (PREPWM) (46) PWM register (PWM) (47) Baud rate generator 3 (BRG3) (48) Transmit/Receive buffer register 3 (TB3/RB3) (49) Serial I/O3 status register (SIO3STS) (50) Serial I/O3 control register (SIO3CON) (51) UART3 control register (UART3CON) (52) AD/DA control register (ADCON) (53) AD conversion register 1 (AD1) (54) DA1 conversion register (DA1) (55) DA2 conversion register (DA2) (56) AD conversion register 2 (AD2) (57) Interrupt source selection register (INTSEL) (58) Interrupt edge selection register (INTEDGE) (59) CPU mode register (CPUM) (60) Interrupt request register 1 (IREQ1) (61) Interrupt request register 2 (IREQ2) (62) Interrupt control register 1 (ICON1) (63) Interrupt control register 2 (ICON2) (64) Flash memory control register 0 (FMCR0) (65) Flash memory control register 1 (FMCR1) (66) Flash memory control register 2 (FMCR2) (67) Port P0 pull-up control register (PULL0) (68) Port P1 pull-up control register (PULL1) (69) Port P2 pull-up control register (PULL2) (70) Port P3 pull-up control register (PULL3) (71) Port P4 pull-up control register (PULL4) (72) Port P5 pull-up control register (PULL5) (73) Port P6 pull-up control register (PULL6) (74) I2C (75) I2C (76) I2C slave address register 0 (S0D0) slave address register 1 (S0D1) slave address register 2 (S0D3) Address Register contents 002816 002916 002A16 002B16 FF16 FF16 0016 0016 002C16 X X X X X X X X 002D16 X X X X X X X X 002F16 X X X X X X X X 003016 X X X X X X X X 003116 1 0 0 0 0 0 0 0 003216 0016 (10) Port P4 direction register (P4D) (11) Port P5 (P5) (12) Port P5 direction register (P5D) (13) Port P6 (P6) (14) Port P6 direction register (P6D) (15) (16) Timer 12, X count source selection register (T12XCSS) Timer Y, Z count source selection register (TYZCSS) 003316 1 1 1 0 0 0 0 0 003416 0 0 0 0 1 0 0 0 003516 X X X X X X X X 003616 003716 003816 003916 003A16 0016 0016 0 00 0 0 0XX 0016 0016 (17) MISRG (18) I2C data shift register (S0) (19) I2C special mode status register (S3) (20) I2C status register (S1) (21) I2C control register (S1D) (22) I2C clock control register (S2) 001116 X X X X X X X X 001216 0 0 1 0 0 0 0 0 001316 0 0 0 1 0 0 0 X 001416 001516 0016 0016 003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0FE016 0FE116 0FE216 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FF816 0FF916 (PS) (PCH) (PCL) 0016 0016 0016 0016 0116 4016 4516 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X XXXX1 XX FFFD16 contents FFFC16 contents (23) I2C START/STOP condition control register (S2D)001616 0 0 0 1 1 0 1 0 (24) I2C special mode control register (S3D) (25) Transmit/Receive buffer register 1 (TB1/RB1) (26) Serial I/O1 status register (SIO1STS) (27) Serial I/O1 control register (SIO1CON) (28) UART1 control register (UART1CON) (29) Baud rate generator 1 (BRG1) (30) Serial I/O2 control register (SIO2CON) (31) Watchdog timer control register (WDTCON) (32) Serial I/O2 register (SIO2) (33) Prescaler 12 (PRE12) (34) Timer 1 (T1) (35) Timer 2 (T2) (36) Timer XY mode register (TM) (37) Prescaler X (PREX) (38) Timer X (TX) (39) Prescaler Y (PREY) (40) Timer Y (TY) 001716 0016 001816 X X X X X X X X 001916 1 0 0 0 0 0 0 0 001A16 0016 001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016 001E16 0 0 1 1 1 1 1 1 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 (77) Processor status register (78) Program counter Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 72 Internal status at reset Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-75 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION CLOCK GENERATING CIRCUIT The 3804 group (Spec. H) has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer ’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip.(An external feed-back resistor may be needed depending on conditions.) However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and X CIN oscillators stop. When the oscillation stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the oscillation stabilizing time set after STP instruction released bit is “1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. Therefore make sure not to set the timer 1 interrupt request bit to “1” before the STP instruction stops the oscillator. When the oscillator is restarted by reset, apply “ L ” l evel to the RESET pin until the oscillation is stable since a wait time will not be generated. The internal power supply circuit is changed to low power consumption mode for consumption current reduction at the time of STP instruction execution. Although an internal power supply circuit is usually changed to the normal operation mode at the time of the return from an STP instruction, since a certain time is required to start the power supply to the flash memory and operation of flash memory to be enabled, set wait time 100 µs or more by the oscillation stabilization time set function after release of the STP instruction which used the timer 1. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of XIN. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1.” When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. sNote • If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN). •When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to select a specific oscillator with the specification demanded. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-76 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION XCIN Rf XCOUT Rd CCOUT XIN XOUT Rd (Note) CCIN CI N COUT Notes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig. 73 Ceramic resonator circuit XCIN XCOUT Open XIN XOUT Open External oscillation circuit VCC VSS External oscillation circuit VCC VSS Fig. 74 External clock input circuit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-77 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION XCIN XCOUT “1” “0” Port XC switch bit XIN (Note 4) XOUT Main clock division ratio selection bits (Note 1) Low-speed mode Divider Prescaler 12 (Note 3) 1/2 High-speed or middle-speed mode 1/4 Timer 1 Reset or STP instruction (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode High-speed or low-speed mode Main clock stop bit Timing φ (internal clock) Q S R STP instruction WIT instruction SQ R QS R STP instruction Reset Reset Interrupt disable flag l Interrupt request Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to “1”. 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset. The count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is “1”, set the appropriate value to them in accordance with oscillation stablizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. 4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig. 75 System clock generating circuit block diagram Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-78 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION Reset Middle-speed mode (f(φ)=1 MHz) CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) C M6 “1”←→“0” High-speed mode (f(φ)=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) → CM ”← 0” “1 M6 →“ C ”← “1 4 ” “0 C “0 M4 CM ”← “1 6 →“ 1” ”← → “0 ” C M4 “1”←→“0” Middle-speed mode (f(φ)=1 MHz) CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM6 “1”←→“0” High-speed mode (f(φ)=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) CM7=1 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) C M7 “1”←→“0” Low-speed mode (f(φ)=16 kHz) C “0 M7 CM ”←→ “1 6 “1 ”← ” → “0 ” C M4 “1”←→“0” b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available CM7=1 CM6=0 CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 76 State transitions of system clock C M5 “1”←→“0” Low-speed mode (f(φ)=16 kHz) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-79 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION FLASH MEMORY MODE The 3804 group (spec. H) has the flash memory that can be rewritten with a single power source. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). This flash memory has some blocks on it as shown in Figure 77 and each block can be erased. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user ’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. q Summary Table 13 lists the summary of the 3804 Group (spec. H). Table 13 Summary of 3804 group (spec. H) Item Power source voltage (Vcc) Program/Erase VPP voltage (VPP) Flash memory mode Erase block division User ROM area/Data ROM area Boot ROM area (Note) Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection Specifications VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V 3 modes; Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode Refer to Fig. 77. Not divided (4K bytes) In units of bytes Block erase Program/Erase control by software command 5 commands 100 Available in parallel I/O mode and standard serial I/O mode Note: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be erased and written in only parallel I/O mode. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-80 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION q Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 77 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset and the CNV SS pin high after pulling the P45/TxD1 pin and CNVss pin high, the CPU starts operating (start address of program is stored into addresses FFFC16 and FFFD16 ) using the control program in the Boot ROM area. This mode is called the “Boot mode”. Also, User ROM area can be rewritten using the control program in the Boot ROM area. q CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 77 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area before it can be executed. q Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. 000016 SFR area 004016 RAM 083F16 Internal RAM area (2K bytes) 100016 180016 200016 User ROM area Data block B: 2K bytes Data block A: 2K bytes Block 3: 24K bytes Notes 1: The boot ROM area can be rewritten in a parallel I/O mode. (Access to except boot ROM area is disablrd.) 2: To specify a block, use the maximum address in the block. 0FE016 0FFF16 100016 SFR area 800016 Block 2: 16K bytes C00016 Block 1: 8 K bytes Internal flash memory area (60K bytes) E00016 Block 0: 8 K bytes F00016 Boot ROM area 4K bytes FFFF16 FFFF16 FFFF16 Fig. 77 Block diagram of built-in flash memory Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-81 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Flash memory control register 0 (FMCR0: address : 0FE016: initial value: 0116) RY/BY status flag qOutline Performance CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM area before it can be executed. The MCU enters CPU rewrite mode by setting “1” to the CPU rewrite mode select bit (bit 1 of address 0FE0 16). Then, software commands can be accepted. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 78 shows the flash memory control register 0. Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “ 0 ” (busy). Otherwise, it is “1” (ready). Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. And then, software commands can be accepted. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in the internal RAM for write to bit 1. To set this bit 1 to “1”, it is necessary to write “0” and then write “1” in succession to bit 1. The bit can be set to “0” by only writing “0”. Bit 2 of the flash memory control register 0 is the 8 KB user block E/W enable bit. By setting combination of bit 4 of the flash memory control register 2 and this bit as shown in Table 14, E/W is disabled to user block in the CPU rewriting mode. Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when flash memory access has failed. When the CPU rewrite mode select bit is “1”, setting “1” for this bit resets the control circuit. To release the reset, it is necessary to set this bit to “0”. Bit 5 of the flash memory control register 0 is the User ROM area select bit and is valid only in the boot mode. Setting this bit to “1” in the boot mode switches an accessible area from the boot ROM area to the user ROM area. To use the CPU rewrite mode in the boot mode, set this bit to “1”. To rewrite bit 5, execute the useroriginal reprogramming control software transferred to the internal RAM in advance. Bit 6 of the flash memory control register 0 is the program status flag. This bit is set to “1” when writing to flash memory is failed. When program error occurs, the block cannot be used. Bit 7 of the flash memory control register 0 is the erase status flag. This bit is set to “1” when erasing flash memory is failed. When erase error occurs, the block cannot be used. Figure 79 shows the flash memory control register 1. Bit 0 of the flash memory control register 1 is the Erase suspend enable bit. By setting this bit to “1”, the erase suspend mode to suspend erase processing temporaly when block erase command is executed can be used. In order to set this bit to “1”, writing “0” and “1” in succession to bit 0. In order to set this bit to “0”, write “0” only to bit 0. Bit 1 of the flash memory control register 1 is the erase suspend request bit. By setting this bit to “1” when erase suspend enable bit is “1”, the erase processing is suspended. Bit 6 of the flash memory control register 1 is the erase suspend flag. This bit is cleared to “0” at the flash erasing. 0 : Busy (being written or erased) 1 : Ready CPU rewrite mode select bit (Note 1) 0 : CPU rewrite mode invalid 1 : CPU rewrite mode valid 8KB user block E/W enable bit (Notes 1, 2) 0 : E/W disabled 1 : E/W enabled Flash memory reset bit (Notes 3, 4) 0 : Normal operation 1 : reset Not used (do not write “1” to this bit.) User ROM area select bit (Note 5) 0 : Boot ROM area is accessed 1 : User ROM area is accessed Program status flag 0: Pass 1: Error Erase status flag 0: Pass 1: Error Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: This bit can be written only when CPU rewrite mode select bit is “1”. 3: Effective only when the CPU rewrite mode select bit = “1”. Fix this bit to “0” when the CPU rewrite mode select bit is “0”. 4: When setting this bit to “1” (when the control circuit of flash memory is reset), the flash memory cannot be accessed for 10 µs. 5: Write to this bit in program on RAM Fig. 78 Structure of flash memory control register 0 b7 b0 Flash memory control register 1 (FMCR1: address : 0FE116: initial value: 4016) Erase Suspend enble bit (Notes 1) 0 : Suspend invalid 1 : Suspend valid Erase Suspend request bit (Notes 2) 0 : Erase restart 1 : Suspend request Not used (do not write “1” to this bit.) Erase Suspend flag 0 : Erase active 1 : Erase inactive (Erase Suspend mode) Not used (do not write “1” to this bit.) Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the suspend enable bit = “1”. Fig. 79 Structure of flash memory control register 1 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-82 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION b7 b0 Flash memory control register 2 (FMCR2: address : 0FE216: initial value: 4516) Not used Not used (do not write “1” to this bit.) Not used All user block E/W enable bit (Notes 1, 2) 0 : E/W disabled 1 : E/W enabled Not used Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the CPU rewrite mode select bit = “1”. Fig. 80 Structure of flash memory control register 2 Table 14 State of E/W inhibition function All user block E/W enable bit 0 0 1 1 8 KB user block E/W enable bit 0 1 0 1 8 KB ✕ 2 block 16 KB + 24 KB block Data block Addresses C00016 to FFFF16 Addresses 200016 to BFFF16 Addresses 100016 to 1FFF16 E/W disabled E/W disabled E/W enabled E/W disabled E/W disabled E/W enabled E/W disabled E/W enabled E/W enabled E/W enabled E/W enabled E/W enabled Figure 81 shows a flowchart for setting/releasing CPU rewrite mode. Start Single-chip mode or Boot mode Set CPU mode register (Note 1) Transfer CPU rewrite mode control program to internal RAM Jump to control program transferred to internal RA M (Subsequent operations are executed by control program in this RAM) Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Set all user block E/W enable bit to “1” (by writing “0” and then “1” in succession) Set 8 KB user block E/W enable bit (At E/W disabled; writing “0”, at E/W enabled; writing “0” and then “1” in succession) Using software command executes erase, program, or other operation Execute read array command (Note 2) Set all user block E/W enable bit to “0” Set 8 KB user block E/W enable bit to “0” Write “0” to CPU rewrite mode select bit End Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B16). 2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command. Fig. 81 CPU rewrite mode set/release flowchart Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-83 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION s Notes on CPU Rewrite Mode Take the notes described below when rewriting the flash memory in CPU rewrite mode. qOperation speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using the clock division ratio selection bits (bits 6 and 7 of address 003B16). qInstructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode. qInterrupts The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. qWatchdog timer If the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. qReset Reset is always valid. The MCU is activated using the boot mode at release of reset in the condition of CNVss = “H”, so that the program will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-84 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION The RY/BY status flag of the flash memory control register is “0” during write operation and “1” when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. q Software Commands Table 15 lists the software commands. After setting the CPU rewrite mode select bit to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. • Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained until another command is written. • Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. • Clear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. • Program Command (4016) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by _____ read status register or the RY/BY status flag. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is written. Start Write “4016” Write Write address Write data Read status register SR7 = “1”? or RY/BY = “1” ? YES NO SR4 = “0”? YES Program completed NO Program error Fig. 82 Program flowchart Table 15 List of software commands (CPU rewrite mode) Command Read array Read status register Clear status register Program Block erase Cycle number 1 2 1 2 2 Mode Write Write Write Write Write First bus cycle Data Address (D0 to D7) X (Note 4) Second bus cycle Mode Address Data (D0 to D7) F F1 6 7016 5016 4016 2016 Write Write WA (Note 2) BA (Note 3) X X X X Read X SRD (Note 1) WD (Note 2) D016 Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address to be erased (Input the maximum address of each block.) 4: X denotes a given address in the User ROM area. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-85 HARDWARE 3804 Group (Spec.H) • Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed by read status register or the RY/BY status flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. The RY/BY status flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. FUNCTIONAL DESCRIPTION Start Write “2016” Write “D016” Block address Read status register SR7 = “1”? or RY/BY = “1”? NO YES NO SR5 = “0” ? Erase error YES Erase completed (write read command “FF16”) Fig. 83 Erase flowchart Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-86 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is reset to “0”. •Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”. The program status is reset to “0” when it is cleared. If “1” is written for any of the SR5 and SR4 bits, the read array, program, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. q Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 16 shows the status register. Each bit in this register is explained below. •Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready). Table 16 Definition of each bit in status register Each bit of SRD bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition “1” Ready Terminated in error Terminated in error “0” Busy Terminated normally Terminated normally - Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-87 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION q Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 84 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = “1” and SR5 = “1” ? NO SR5 = “0” ? YES SR4 = “0” ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (block erase, program) Note: When one of SR5 and SR4 is set to “1”, none of the read array, program, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 84 Full status check flowchart and remedial procedure for errors Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-88 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION If one or both of the pair of ROM code protect bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be readout or modified. Once the ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM code protect reset bits. Rewriting of only the ROM code protect control address (address FFDB16) cannot be performed. When rewriting the ROM code protect reset bit, rewrite the whole user ROM area (block 0) containing the ROM code protect control address. q F unctions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. (1) ROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control address (address FFDB16) in parallel I/O mode. Figure 85 shows the ROM code protect control address (address FFDB16). (This address exists in the User ROM area.) b7 b0 1 1 ROMCP (FF16 when shipped) ROM code protect control address (address FFDB16) Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (ROMCR) (Note 3) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 1) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite mode. Fig. 85 Structure of ROM code protect control address Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-89 HARDWARE 3804 Group (Spec.H) (2) ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD4 16 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory. FUNCTIONAL DESCRIPTION Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig. 86 ID code store addresses Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-90 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION q Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 3804 Group (spec. H). For details, refer to the user ’s manual of each writer manufacturer. • User ROM and Boot ROM Areas In parallel I/O mode, the User ROM and Boot ROM areas shown in Figure 77 can be rewritten. Both areas of flash memory can be operated on in the same way. The Boot ROM area is 4 Kbytes in size and located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the fac-tory. Therefore, using the MCU in standard serial I/O mode, do not rewrite to the Boot ROM area. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-91 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION q Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the CNVss pin and “H” to the P45 (BOOTENT) pin, and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. The standard serial I/ O mode has standard serial I/O mode 1 of the clock synchronous serial and standard serial I/O mode 2 of the clock asynchronous serial. Tables 17 and 18 show description of pin function (standard serial I/O mode). Figures 87 to 90 show the pin connections for the standard serial I/O mode. In standard serial I/O mode, only the User ROM area shown in Figure 77 can be rewritten. The Boot ROM area cannot be written. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, this function determines whether the ID code sent from the peripheral unit (programmer) and those written in the flash memory match. The commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-92 HARDWARE 3804 Group (Spec.H) Table 17 Description of pin function (Flash Memory Serial I/O Mode 1) Pin name VCC,VSS CNVSS RESET XIN XOUT AVSS VREF P00–P07,P10–P17, P20–P27,P30–P37, P40–P43,P50–P57, P60–P67 P44 P45 P46 P47 Signal name Power supply CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input I/O port I/O I I I I O I I/O Function Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin. After input of port is set, input “H” level. Reset input pin. To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. Connect AVss to Vss. Apply reference voltage of A/D to this pin. Input “L” or “H” level, or keep open. FUNCTIONAL DESCRIPTION RxD input TxD output SCLK input BUSY output I O I O Serial data input pin. Serial data output pin. Serial clock input pin. BUSY signal output pin. Table 18 Description of pin function (Flash Memory Serial I/O Mode 2) Pin name VCC,VSS CNVSS RESET XIN XOUT AVss VREF P00–P07,P10–P17, P20–P27,P30–P37, P40–P43,P50–P57, P60–P67 P44 P45 P46 P47 Signal name Power supply CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input I/O port I/O I I I I O I I/O Function Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin. After input of port is set, input “H” level. Reset input pin. To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. Connect AVss to Vss. Apply reference voltage of A/D to this pin. Input “L” or “H” level, or keep open. RxD input TxD output SCLK input BUSY output I O I O Serial data input pin. Serial data output pin. Input “L” level. BUSY signal output pin. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-93 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION P02/AN10 P01/AN9 P00/AN8 P05/AN13 P06/AN14 P10/INT41 P04/AN12 P11/INT01 P03/AN11 P07/AN15 P12 P13 P14 P15 35 P16 34 48 46 45 44 41 40 43 42 39 38 47 37 36 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33/SCL P32/SDA P31/DA2 P30/DA1 VCC VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 RESET CNVss VSS ✽ M38049FFHFP/HP/KP 13 12 10 11 P56/PWM P54/CNTR0 P53/SRDY2 P51/SOUT2 P45/TXD1 P44/RXD1 P62/AN2 P60/AN0 P57/INT3 14 15 P55/CNTR1 P52/SCLK2 P47/SRDY1/CNTR2 ✽ Connect oscillation circuit. indicates flash memory pin. P46/SCLK1 P43/INT2 P61/AN1 P50/SIN2 16 2 5 4 1 3 6 7 8 9 RxD TxD SCLK BUSY Package type: 64P6N-A/64P6Q-A/64P6U-A Fig. 87 Connection for standard serial I/O mode 1 (M38049FFHFP/HP/KP) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-94 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION P02/AN10 P01/AN9 P00/AN8 P05/AN13 P06/AN14 P10/INT41 P04/AN12 P11/INT01 P03/AN11 P07/AN15 P12 P13 P14 P15 35 P16 34 48 46 45 47 44 41 40 43 42 39 38 37 36 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33/SCL P32/SDA P31/DA2 P30/DA1 VCC VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 RESET CNVss ✽ VSS M38049FFHFP/HP/KP 13 12 10 11 P56/PWM P54/CNTR0 P53/SRDY2 P51/SOUT2 P45/TXD1 P44/RXD1 P62/AN2 P60/AN0 P57/INT3 14 15 P55/CNTR1 P52/SCLK2 P47/SRDY1/CNTR2 ✽ Connect oscillation circuit. indicates flash memory pin. P46/SCLK1 P43/INT2 P61/AN1 P50/SIN2 16 2 5 6 4 1 3 7 8 9 RxD TxD “L” input BUSY Package type: 64P6N-A/64P6Q-A/64P6U-A Fig. 88 Connection for standard serial I/O mode 2 (M38049FFHFP/HP/KP) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-95 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION V CC BUSY SCLK T XD R XD CNVSS RESET VSS VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN ✽ XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) M38049FFHSP ✽ Connect oscillation circuit. indicates flash memory pin. Package type: 64P4B Fig. 89 Connection for standard serial I/O mode 1 (M38049FFHSP) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-96 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION V CC BUSY “L” input T XD R XD CNVSS RESET VSS VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN ✽ XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) M38049FFHSP ✽ Connect oscillation circuit. indicates flash memory pin. Package type: 64P4B Fig. 90 Connection for standard serial I/O mode 2 (M38049FFHSP) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-97 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION td(CNVSS-RESET) td(P45-RESET) Power source RESET CNVSS P45(TXD) P46(SCLK) P47(BUSY) P44(RXD) Symbol td(CNVss-RESET) td(P45-RESET) Limits Unit Min. Typ. Max. – – ms 0 ms 0 Notes: In the standard serial I/O mode 1, input “H” to the P46 pin. Be sure to set the CNVss pin to “H” before rising RESET. Be sure to set the P45 pin to “H” before rising RESET. Fig. 91 Operating waveform for standard serial I/O mode 1 td(CNVSS-RESET) td(P45-RESET) Power source RESET CNVSS P45(TXD) P46(SCLK) P47(BUSY) P44(RXD) Symbol td(CNVss-RESET) td(P45-RESET) Limits Unit Min. Typ. Max. ms – – 0 ms 0 Notes: In the standard serial I/O mode 2, input “H” to the P46 pin. Be sure to set the CNVss pin to “H” before rising RESET. Be sure to set the P45 pin to “H” before rising RESET. Fig. 92 Operating waveform for standard serial I/O mode 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-98 HARDWARE 3804 Group (Spec.H) NOTES ON PROGRAMMING NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Serial Interface In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1.” Serial I/O continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed. When in serial I/Os 1 and 3 (clock-synchronous mode) or in serial I/O2, an external clock is used as synchronous clock, write transmission data to the transmit buffer register or serial I/O2 register, during transfer clock is “H.” Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. A/D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A/D conversion. Do not execute the STP instruction during an A/D conversion. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. D/A Converter The accuracy of the D/A converter becomes rapidly poor under the VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V is recommended. When a D/A converter is not used, set all values of D/Ai conversion registers (i=1, 2) to “0016.” Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Instruction Execution Time Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. The instruction execution time is obtained by multiplying the period of the internal clock φ b y the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The period of the internal clock φ is double of the XIN period in high-speed mode. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The instruction with the addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-99 HARDWARE 3804 Group (Spec.H) NOTES ON USAGE NOTES ON USAGE Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (V CC pin) and analog power source input pin (AV SS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recommended. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Flash Memory Version The CNVss pin determines the flash memory mode. To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor. Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes, built-in ROM, and layout pattern etc.When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version, please conduct evaluations equivalent to the system evaluations conducted for the flash memory version. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1.Mask ROM Confirmation Form ✽ 2.Mark Specification Form ✽ 3.Data to be written to ROM, in EPROM form (three identical copies) ✽ For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom). Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-100 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL DESCRIPTION SUPPLEMENT Interrupt The 3804 group (Spec. H) permits interrupts on the basis of 16 sources. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to “Table 19”. Table 19 Interrupt sources, vector addresses and priority Interrupt Source Reset (Note 2) INT0 Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission SCL, SDA Timer X Timer Y Timer 1 Timer 2 CNTR0 SCL, SDA CNTR1 Serial I/O3 reception Serial I/O2 Timer Z INT2 I 2C INT3 INT4 CNTR2 A/D converter Serial I/O3 transmission BRK instruction 16 FFDF16 FFDE16 11 FFE916 FFE816 6 7 8 9 10 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 Priority 1 2 Vector Addresses (Note 1) Low High FFFC16 FFFD16 FFFB16 FFFA16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At detection of either rising or falling edge of SCL or SDA At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of SCL or SDA At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception 12 FFE716 FFE616 At completion of serial I/O2 data transmission or reception At timer Z underflow 13 FFE516 FFE416 At detection of either rising or falling edge of INT2 input At completion of data transfer At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A/D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty 17 FFDD16 FFDC16 At BRK instruction execution Valid when serial I/O3 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected STP release timer underflow Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected 3 4 5 FFF916 FFF716 FFF516 FFF816 FFF616 FFF416 External interrupt (active edge selectable) 14 15 FFE316 FFE116 FFE216 FFE016 Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-101 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 93 shows a timing chart after an interrupt occurs, and Figure 94 shows the time up to execution of the interrupt processing routine. φ SYNC RD WR Address bus Data bus PC Not used S, SPS S-1, SPS S-2, SPS BL AL BH AL, AH AH PCH PCL PS SYNC : CPU operation code fetch cycle (This is an internal signal that cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : “0016” or “0116” Fig. 93 Timing chart after an interrupt occurs Interrupt request generated Start of interrupt processing Main routine Waiting time for Stack push and post-processing Vector fetch of pipeline Interrupt processing routine 0 to 16 cycles 2 cycles 5 cycles 7 to 23 cycles (When f(XIN) = 8.4 MHz, 0.83 µs to 2.74 µs) Fig. 94 Time up to execution of the interrupt processing routine Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-102 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION SUPPLEMENT A/D Converter A/D conversion is started by setting AD conversion completion bit to “0”. During A/D conversion, internal operations are performed as follows. 1. After the start of A/D conversion, AD conversion register goes to “ 00 16” . 2. The highest-order bit of AD conversion register is set to “ 1 ” . and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage VIN. 3. As a result of comparison, when Vref < V IN, the highestorder bit of AD conversion register becomes “ 1. ” W hen Vref > VIN, the highest-order bit becomes “ 0. ” By repeating the above operations up to the lowest-order bit of the AD conversion register, an analog value converts into a digital value. In the 10-bit A/D mode, A/D conversion completes at 61 cycles of 2tc(XIN)* (15.25 µs at f(XIN) = 8.0 MHz) after it is started. In the 8bit A/D mode, A/D conversion completes at 50 cycles of 2tc(XIN) (12.5 µs at f(XIN) = 8.0 MHz) after it is started. And the result of the conversion is stored into the AD conversion register. Concurrently with the completion of A/D conversion, the A/D conversion completion bit is set to “1” and an A/D conversion interrupt request occurs, so that the AD conversion interrupt request bit is set to “1”. * tc(XIN) = Main clock input cycle time Table 20 Relative formula for a reference voltage VREF of A/D converter and Vref (at 10-bit A/D mode) When n = 0 When n = 1 to 1023 Vref = 0 Vref = VREF 1024 ✕n n : Value of A/D converter (decimal numeral) Table 21 Relative formula for a reference voltage VREF of A/D converter and Vref (at 8-bit A/D mode) When n = 0 When n = 1 to 255 Vref = 0 Vref = VREF 256 ✕ (n – 0.5) n : Value of A/D converter (decimal numeral) Table 22 Change of AD conversion register during A/D conversion (at 10-bit A/D mode) Change of AD conversion register At start of conversion First comparison Second comparison Third comparison 0 1 ✽1 Value of comparison voltage (Vref) 0 0 0 0 0 0 0 0 VREF 2 VREF 2 VREF 2 ± ± V REF 4 V REF 4 ± VREF 8 0 0 0 1 ✽ 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ✽ 1 2 • • • After completion of tenth comparison ✽ • • • A result of A/D conversion 1 ✽ • • • ✽6 ✽7 ✽8 ✽9 ✽10 2 ✽ 3 ✽4 ✽5 VREF 2 ± V REF 4 ± ••• ± V REF 1024 ✽1–✽10: A result of the first to tenth comparison Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-103 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION SUPPLEMENT Table 23 Change of AD conversion register during A/D conversion (at 8-bit A/D mode) Change of AD conversion register At start of conversion First comparison Second comparison Third comparison 0 1 ✽1 Value of comparison voltage (Vref) 0 0 0 0 V REF 2 VREF 2 VREF 2 – ± ± VREF 512 VREF 4 VREF 4 – ± VREF 512 V REF 8 – VREF 512 0 0 0 1 ✽ 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ✽ 1 2 • • • After completion of eighth comparison ✽ • • • A result of A/D conversion 1 ✽ • • • ✽6 ✽7 ✽8 2 ✽ 3 ✽4 ✽5 VREF 2 ± VREF 4 ± ••• ± VREF 256 – VREF 512 ✽1–✽8: A result of the first to eighth comparison Figure 95 shows A/D conversion equivalent circuit, and Figure 96 shows A/D conversion timing chart. VCC About 2 kΩ AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 VSS V IN Sampling clock VCC AVSS C Chopper amplifier AD conversion register 1 AD conversion register 2 AD conversion interrupt request b4 b2 b1 b0 AD/DA control register VREF Built-in D/A converter Vref Reference clock AVSS Fig. 95 A/D conversion equivalent circuit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-104 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION SUPPLEMENT XI N 2 Write signal for AD control register AD conversion completion bit At 10-bit A/D mode : 61 cycles At 8-bit A/D mode : 50 cycles Sampling clock Fig. 96 A/D conversion timing chart Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-105 HARDWARE 3804 Group (Spec.H) FUNCTIONAL DESCRIPTION SUPPLEMENT Memo Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 1-106 CHAPTER 2 APPLICATION 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 I/O port Interrupt Timer Serial interface Multi-master I2C-BUS interface PWM A/D converter D/A converter Watchdog timer Reset Clock generating circuit Standby function Flash memory mode APPLICATION 3804 Group (Spec.H) 2.1 I/O port 2.1 I/O port This paragraph describes the setting method of I/O port relevant registers, notes etc. 2.1.1 Memory map Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Port P2 pull-up control register (PULL2) Port P3 pull-up control register (PULL3) Port P4 pull-up control register (PULL4) Port P5 pull-up control register (PULL5) 0FF616 Port P6 pull-up control register (PULL6) Fig. 2.1.1 Memory map of I/O port relevant registers Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-2 APPLICATION 3804 Group (Spec.H) 2.1 I/O port 2.1.2 Relevant registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (i = 0, 1, 2, 3, 4, 5, 6) (Pi: addresses 000016, 000216, 000416, 000616, 000816, 000A16, 000C16) b 0 1 2 3 4 5 6 7 Name Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7 Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 0 0 0 Fig. 2.1.2 Structure of Port Pi (i = 0 to 6) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6) (PiD: addresses 000116, 000316, 000516, 000716, 000916, 000B16, 000D16) b Name Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset R W 0 0 0 0 0 0 0 0 0 Port Pi direction register 1 2 3 4 5 6 7 Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-3 APPLICATION 3804 Group (Spec.H) 2.1 I/O port Port Pi pull-up control register (i = 0 to 2, 4 to 6) b7 b6 b5 b4 b3 b2 b1 b0 Port Pi pull-up control register (i = 0 to 2, 4 to 6) (PULLi: addresses 0FF016, 0FF116, 0FF216, 0FF416, 0FF516, 0FF616) b Name Functions 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up 0: No pull-up 1: Pull-up At reset R W 0 0 0 0 0 0 0 0 0 Port Pi0 pull-up control bit 1 Port Pi1 pull-up control bit 2 Port Pi2 pull-up control bit 3 Port Pi3 pull-up control bit 4 Port Pi4 pull-up control bit 5 Port Pi5 pull-up control bit 6 Port Pi6 pull-up control bit 7 Port Pi7 pull-up control bit Fig. 2.1.4 Structure of Port Pi pull-up control register (i = 0, 1, 2, 4, 5, 6) Port P3 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 pull-up control register (PULL3: address 0FF316) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 0: No pull-up 0 Port P30 pull-up control bit 1: Pull-up Port P31 pull-up 0: No pull-up 1 control bit 1: Pull-up 2 Nothing is arranged for these bits. These are write disabled bits. When these bits are read 3 out, the contents are “0”. 0: No pull-up 4 Port P34 pull-up control bit 1: Pull-up 5 Port P35 pull-up 0: No pull-up control bit 1: Pull-up 0: No pull-up 6 Port P36 pull-up control bit 1: Pull-up Port P37 pull-up 7 0: No pull-up control bit 1: Pull-up Fig. 2.1.5 Structure of Port P3 pull-up control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-4 APPLICATION 3804 Group (Spec.H) 2.1 I/O port 2.1.3 Port Pi pull-up control register Valid/Invalid of pull-up resistor can be set by the pull-up control register by a bit unit. Pull-up control is valid only when each direction register is set to the input mode. Note: P orts P3 2 a nd P3 3 d o not have pull-up control bit because they are N-channel open-drain output. 2.1.4 Terminate unused pins Table 2.1.1 Termination of unused pins (in single-chip mode) Pins Termination P0, P1, P2, P3, • S et to the input mode and connect each to V CC o r V SS t hrough a resistor of 1 k Ω t o P4, P5, P6 10 k Ω . • S et to the output mode and open at “ L ” o r “ H ” o utput state. VREF AVSS XOUT Connect to Vss (GND). Connect to Vss (GND). Open (only when using external clock) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-5 APPLICATION 3804 Group (Spec.H) 2.1 I/O port 2.1.5 Notes on I/O port (1) Notes in standby state In standby state ✽1 f or low-power dissipation, do not make input levels of an I/O port “ undefined ” , especially for I/O ports of the N-channel open-drain. Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a resistor. When determining a resistance value, note the following points: • E xternal circuit • V ariation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: • W hen setting as an input port : Fix its input level • When setting as an output port : Prevent current from flowing out to external q Reason Even when setting as an output port with its direction register, when the content of the port latch is “ 1 ” , the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes “ undefined ” d epending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an I/O port are “ undefined ” . This may cause power source current. ✽ 1 standby state: stop mode by executing S TP i nstruction wait mode by executing W IT i nstruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the unspecified bit may be changed. q R eason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. • As for bit which is set for input port: The pin state is read in the CPU, and is written to this bit after bit managing. • As for bit which is set for output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: •Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. • As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. ✽ 2 Bit managing instructions: S EB a nd C LB i nstructions Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-6 APPLICATION 3804 Group (Spec.H) 2.1 I/O port 2.1.6 Termination of unused pins (1) Terminate unused pins ➀ I /O ports : • Set the I/O ports for the input mode and connect them to V CC o r V SS t hrough each resistor of 1 k Ω t o 10 k Ω . Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. ➁ T he AVss pin when not using the A/D converter : • When not using the A/D converter, handle a power source pin for the A/D converter, AVss pin as follows: AVss: Connect to the Vss pin. (2) Termination remarks ➀ I /O ports : Do not open in the input mode. q R eason • The power source current may increase depending on the first-stage circuit. • An effect due to noise may be easily produced as compared with proper termination ➀ a nd shown on the above. ➁ I /O ports : When setting for the input mode, do not connect to V CC o r V SS d irectly. q R eason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and V CC ( or V SS). ➂ I /O ports : When setting for the input mode, do not connect multiple ports in a lump to V CC o r VSS t hrough a resistor. q R eason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. • At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-7 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt 2.2 Interrupt This paragraph explains the registers setting method and the notes relevant to the interrupt. 2.2.1 Memory map 003916 003A16 003C16 003D16 003E16 003F16 Interrupt source selection register (INTSEL) Interrupt edge selection register (INTEDGE) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.2.1 Memory map of registers relevant to interrupt 2.2.2 Relevant registers Interrupt source selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt source selection register (INTSEL: address 003916) b Name Functions 0: INT0 interrupt 1: Timer Z interrupt 0: Serial I/O2 interrupt 1: Timer Z interrupt 0: Serial I/O1 transmit interrupt 1: SCL, SDA interrupt 0: CNTR0 interrupt 1: SCL, SDA interrupt 0: INT4 interrupt 1: CNTR2 interrupt 0: INT2 interrupt 1: I2C interrupt 0: CNTR1 interrupt 1: Serial I/O3 receive interrupt 0: A/D converter interrupt 1: Serial I/O3 transmit interrupt At reset R W 0 0 INT0/Timer Z interrupt source selection bit (*1) 1 Serial I/O2/Timer Z interrupt source selection bit (*1) 2 Serial I/O1 transmit/ SCL, SDA interrupt source selection bit (*2) 3 CNTR0/SCL, SDA interrupt source selection bit (*2) 4 INT4/CNTR2 interrupt source selection bit 5 INT2/I2C interrupt source selection bit 6 CNTR1/Serial I/O3 receive interrupt source selection bit 7 AD converter/Serial I/O3 transmit interrupt source selection bit 0 0 0 0 0 0 0 *1: Do not write 1 to these bits simultaneously. *2: Do not write 1 to these bits simultaneously. Fig. 2.2.2 Structure of Interrupt source selection register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-8 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE: address 003A16) b Name Functions At reset R W 0 0 0 0: Falling edge active 0 INT0 active edge 1: Rising edge active selection bit 0: Falling edge active 1 INT1 active edge 1: Rising edge active selection bit 2 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are “0”. 3 INT2 active edge 0: Falling edge active selection bit 1: Rising edge active 4 INT3 active edge 0: Falling edge active selection bit 1: Rising edge active 0: Falling edge active 5 INT4 active edge selection bit 1: Rising edge active 6 INT0, INT4 interrupt 0: INT00, INT40 interrupt switch bit 1: INT01, INT41 interrupt 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are “0”. 0 0 0 0 0 Fig. 2.2.3 Structure of Interrupt edge selection register Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1 : address 003C16) b Name Functions At reset R W 0 0 0 0 ✽ ✽ ✽ ✽ 0 INT0/Timer Z 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 1 INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 2 Serial I/O1 receive 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 0 : No interrupt request issued 3 Serial I/O1 transmit/SCL, SDA 1 : Interrupt request issued interrupt request bit 4 Timer X interrupt request bit 5 Timer Y interrupt request bit 6 Timer 1 interrupt request bit 0 : No interrupt request issued 0 0 0 0 ✽ ✽ ✽ ✽ 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 7 Timer 2 interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: 0 can be set by software, but 1 cannot be set. Fig. 2.2.4 Structure of Interrupt request register 1 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-9 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2 : address 003D16) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 ✽ ✽ 0 CNTR0/SCL, SDA interrupt request bit 1 CNTR1/Serial I/O3 receive interrupt request bit 2 Serial I/O2/Timer Z interrupt request bit 3 INT2/I2C interrupt request bit 4 INT3 interrupt request bit 5 INT4/CNTR2 interrupt request bit 6 AD converter/Serial I/O3 transmit interrupt request bit 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . ✽: 0 can be set by software, but 1 cannot be set. 0 Fig. 2.2.5 Structure of Interrupt request register 2 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1 : address 003E16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 INT0/Timer Z interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O1 receive interrupt enable bit 3 Serial I/O1 transmit/SCL, SDA interrupt enable bit 4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit 0 0 0 0 Fig. 2.2.6 Structure of Interrupt control register 1 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-10 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2 : address 003F16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 CNTR0/SCL, SDA interrupt enable bit 1 CNTR1/ Serial I/O3 receive interrupt enable bit 2 Serial I/O2/ Timer Z interrupt enable bit 3 INT2/I2C interrupt enable bit 4 INT3 interrupt enable bit 5 INT4/CNTR2 interrupt enable bit 6 AD converter/Serial I/O3 transmit interrupt enable bit 7 Fix this bit to “0”. 0 0 0 0 0 0 Fig. 2.2.7 Structure of Interrupt control register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-11 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt 2.2.3 Interrupt source The 3804 group (Spec. H) ’s interrupts are a type of vector and occur by 16 sources among 23 sources: nine external, thirteen internal, and one software. These are vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to Tables 2.2.1. Table 2.2.1 Interrupt sources, vector addresses and priority Interrupt Source Reset (Note 2) INT0 Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission SCL, SDA Timer X Timer Y Timer 1 Timer 2 CNTR0 SCL, SDA CNTR1 Serial I/O3 reception Serial I/O2 Timer Z INT2 I 2C INT3 INT4 CNTR2 A/D converter Serial I/O3 transmission BRK instruction 16 FFDF16 FFDE16 11 FFE916 FFE816 6 7 8 9 10 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 Priority 1 2 Vector Addresses (Note 1) Low High FFFC16 FFFD16 FFFB16 FFFA16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At detection of either rising or falling edge of SCL or SDA At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of SCL or SDA At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow 13 FFE516 FFE416 At detection of either rising or falling edge of INT2 input At completion of data transfer 14 15 FFE316 FFE116 FFE216 FFE016 At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A/D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty 17 FFDD16 FFDC16 At BRK instruction execution Valid when serial I/O3 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected STP release timer underflow Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected 3 4 5 FFF916 FFF716 FFF516 FFF816 FFF616 FFF416 External interrupt (active edge selectable) 12 FFE716 FFE616 Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-12 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt 2.2.4 Interrupt operation When an interrupt request is accepted, the contents of the following registers just before acceptance of the interrupt requests are automatically pushed onto the stack area in the order of ➀ , ➁ a nd ➂. ➀High-order contents of program counter (PC H) ➁Low-order contents of program counter (PC L) ➂Contents of processor status register (PS) After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector address enters the program counter and consequently the interrupt processing routine is executed. When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the above registers pushed onto the stack area are restored to the respective registers in the order of ➂, ➁ and ➀; and the microcomputer resumes the processing executed just before acceptance of the interrupts. Figure 2.2.8 shows an interrupt operation diagram. Executing routine ······· Interrupt occurs (Accepting interrupt request) Suspended operation Contents of program counter (high-order) are pushed onto stack Contents of program counter (low-order) are pushed onto stack Contents of processor status register are pushed onto stack Interrupt processing routine RTI instruction Contents of processor status register are popped from stack Contents of program counter (low-order) are popped from stack Contents of program counter (high-order) are popped from stack Resume processing ······· : Operation commanded by software : Internal operation performed automatically Fig. 2.2.8 Interrupt operation diagram Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-13 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt (1) Processing upon acceptance of interrupt request Upon acceptance of an interrupt request, the following operations are automatically performed. ➀The processing being executed is stopped. ➁The contents of the program counter and the processor status register are pushed onto the stack area. Figure 2.2.9 shows the changes of the stack pointer and the program counter upon acceptance of an interrupt request. ➂Concurrently with the push operation, the jump destination address (the beginning address of the interrupt processing routine) of the occurring interrupt stored in the vector address is set in the program counter, then the interrupt processing routine is executed. ➃After the interrupt processing routine is started, the corresponding interrupt request bit is automatically cleared to “ 0 ” . The interrupt disable flag is set to “ 1 ” s o that multiple interrupts are disabled. Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination address in the vector area corresponding to each interrupt. Program counter PCL Program counter (low-order) PCH Program counter (high-order) Stack pointer S (S) Interrupt request is accepted Program counter PCL PCH Vector address (from Interrupt vector area) Stack pointer S (S) – 3 Interrupt disable flag = “1” (s) – 3 Interrupt disable flag = “0” (S) Stack area Stack area Processor status register Program counter (low-order) (S) Program counter (high-order) Fig. 2.2.9 Changes of stack pointer and program counter upon acceptance of interrupt request Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-14 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt (2) Timing after acceptance of interrupt request The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently being executed. Figure 2.2.10 shows the time up to execution of interrupt processing routine and Figure 2.2.11 shows the timing chart after acceptance of interrupt request. Interrupt request generated Start of interrupt processing Main routine Waiting time for Stack push and post-processing Vector fetch of pipeline Interrupt processing routine ✽ 0 to 16 cycles 2 cycles 5 cycles 7 to 23 cycles (When f(XIN) = 8 MHz, 1.75 µs to 5.75 µs) ✽ When executing DIV instruction Fig. 2.2.10 Time up to execution of interrupt processing routine Waiting time for pipeline post-processing Push onto stack Vector fetch Interrupt operation starts φ SYNC RD WR Address bus Data bus PC Not used S, SPS S-1, SPS S-2, SPS BL AL BH AL, AH AH PCH P CL PS SYNC : CPU operation code fetch cycle (This is an internal signal that cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : “0016” or “0116” Fig. 2.2.11 Timing chart after acceptance of interrupt request Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-15 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt 2.2.5 Interrupt control The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.12 shows an interrupt control diagram. Interrupt request bit Interrupt enable bit Interrupt request Interrupt disable flag BRK instruction Reset Fig. 2.2.12 Interrupt control diagram The interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not affect each other. An interrupt is accepted when all the following conditions are satisfied. q Interrupt request bit .......... “1” q Interrupt enable bit ........... “1” q Interrupt disable flag ........ “0” Though the interrupt priority is determined by hardware, a variety of priority processing can be performed by software using the above bits and flag. Tables 2.2.2 shows list of interrupt control bits according to the interrupt source. (1) Interrupt request bits The interrupt request bits are allocated to the interrupt request register 1 (address 003C 16) and interrupt request register 2 (address 003D 16). The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to “1”. The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt is accepted, this bit is automatically cleared to “ 0 ” . Each interrupt request bit can be set to “ 0 ” , but cannot be set to “ 1 ” , by software. (2) Interrupt enable bits The interrupt enable bits are allocated to the interrupt control register 1 (address 003E 16) and the interrupt control register 2 (address 003F 16). The interrupt enable bits control the acceptance of the corresponding interrupt request. When an interrupt enable bit is “ 0 ” , the corresponding interrupt request is disabled. If an interrupt request occurs when this bit is “ 0 ” , the corresponding interrupt request bit is set to “ 1 ” b ut the interrupt is not accepted. In this case, unless the interrupt request bit is set to “ 0 ” b y software, the interrupt request bit remains in the “ 1 ” s tate. When an interrupt enable bit is “ 1 ” , the corresponding interrupt is enabled. If an interrupt request occurs when this bit is “ 1 ” , the interrupt is accepted (when interrupt disable flag = “ 0 ” ). Each interrupt enable bit can be set to “ 0 ” o r “ 1 ” b y software. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-16 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt (3) Interrupt disable flag The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable flag controls the acceptance of interrupt request except BRK instruction. When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set to “0” with the CLI instruction. When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”, so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine. Figure 2.2.13 shows an example of multiple interrupts. Table 2.2.2 List of interrupt bits according to interrupt source Interrupt source INT 0/Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission/SCL, SDA Timer X Timer Y Timer 1 Timer 2 CNTR 0/SCL, SDA CNTR 1/Serial I/O3 reception Serial I/O2/Timer Z INT 2/I2C INT3 INT 4/CNTR2 A/D converter/Serial I/O3 transmission Interrupt enable bit Address 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003F16 003F16 003F16 003F16 003F16 003F16 003F16 Bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 Interrupt request bit Address 003C16 003C16 003C16 003C16 003C16 003C16 003C16 003C16 003D16 003D16 003D16 003D16 003D16 003D16 003D16 Bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-17 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt Interrupt request Nesting Reset Time Main routine I=1 C1 = 0, C2 = 0 Interrupt request 1 C1 = 1 I=0 Interrupt 1 Interrupt request 2 I=1 C2 = 1 I=0 Interrupt 2 I=1 RTI I=0 Multiple interrupt RTI I=0 I : Interrupt disable flag C1 : Interrupt enable bit of interrupt 1 C2 : Interrupt enable bit of interrupt 2 : Set automatically. : Set by software. Fig. 2.2.13 Example of multiple interrupts Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-18 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt 2.2.6 INT interrupt The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin (INT 0–INT 4). (1) Active edge selection INT 0–INT4 c an be selected from either a falling edge or rising edge detection as an active edge by the interrupt edge selection register. In the “0” state, the falling edge of the corresponding pin is detected. In the “1” state, the rising edge of the corresponding pin is detected. (2) INT0, INT 2, INT 4 i nterrupt source selection When using the following interrupt source, select which of the interrupt source by the interrupt source selection register (address 0039 16). (Set these bits to “0” when using INT.) •INT 0 o r timer Z (bit 0) •INT 4 o r CNTR 2 ( bit 4) •INT 2 o r I 2C (bit 5) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-19 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt 2.2.7 Notes on interrupts (1) Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. •Interrupt edge selection register (address 003A 16) •Timer XY mode register (address 0023 16) •Timer Z mode register (address 002A 16) •I2C START/STOP condition control register (address 001616) Set the above listed registers or bits as the following sequence. Set the corresponding interrupt enable bit to “0” (disabled) . ↓ Set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select bit to “1”. ↓ NOP (One or more instructions) ↓ Set the corresponding interrupt request bit to “0” (no interrupt request issued). ↓ Set the corresponding interrupt enable bit to “1” (enabled). Fig. 2.2.14 Sequence of changing relevant register s Reason When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Concerned register: Interrupt edge selection register (address 003A 16) Timer XY mode register (address 0023 16) Timer Z mode register (address 002A 16) I 2C START/STOP condition control register (address 0016 16) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated. Concerned register: Interrupt source selection register (address 0039 16) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-20 APPLICATION 3804 Group (Spec.H) 2.2 Interrupt (2) Check of interrupt request bit q W hen executing the B BC o r B BS i nstruction to an interrupt request bit of an interrupt request register immediately after this bit is set to “0”, execute one or more instructions before executing the B BC o r B BS i nstruction. Clear the interrupt request bit to “0” (no interrupt issued) ↓ NOP (one or more instructions) ↓ Execute the BBC or BBS instruction Fig. 2.2.15 Sequence of check of interrupt request bit s Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-21 APPLICATION 3804 Group (Spec.H) 2.3 Timer 2.3 Timer This paragraph explains the registers setting method and the notes relevant to the timers. 2.3.1 Memory map Address 000E16 000F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 Timer 12, X count source selection register (T12XCSS) Timer Y, Z count source selection register (TYZCSS) Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer Z low-order (TZL) Timer Z high-order (TZH) Timer Z mode register (TZM) 003916 003C16 003D16 003E16 003F16 Interrupt source selection register (INTSEL) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.3.1 Memory map of registers relevant to timers Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-22 APPLICATION 3804 Group (Spec.H) 2.3 Timer 2.3.2 Relevant registers Prescaler 12, Prescaler X, Prescaler Y b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) (addresses 002016, 002416, 002616) b Functions At reset R W 1 1 1 1 1 1 1 1 0 • Set a count value of each prescaler. 1 • The value set in this register is written to both 2 each prescaler and the corresponding 3 prescaler latch at the same time. • When this register is read out, the count value 4 of the corresponding prescaler is read out. 5 6 7 Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1: address 002116) b Functions At reset R W 1 0 0 0 0 0 0 0 0 • Set timer 1 count value. 1 • The value set in this register is written to both 2 the timer 1 and the timer 1 latch at the same 3 time. • When the timer 1 is read out, the count value 4 of the timer 1 is read out. 5 6 7 Fig. 2.3.3 Structure of Timer 1 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-23 APPLICATION 3804 Group (Spec.H) 2.3 Timer Timer 2, Timer X, Timer Y b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2), Timer X (TX), Timer Y (TY) (addresses 002216, 002516, 002716) b Functions At reset R W 1 1 1 1 1 1 1 1 0 • Set each timer count value. 1 • The value set in this register is written to both 2 each timer and the corresponding timer latch 3 at the same time. • When each timer is read out, the count value 4 of the corresponding timer is read out. 5 6 7 Fig. 2.3.4 Structure of Timer 2, Timer X, Timer Y Timer Z low-order, Timer Z high-order b7 b6 b5 b4 b3 b2 b1 b0 Timer Z low-order (TZL), Timer Z high-order (TZH) (addresses 002816, 002916) b 0 1 2 3 4 5 6 7 Functions • Set each timer count value. [At write] • Depending on the write control bit (bit 3 of TZM), the value set to this register is written to each timer and the corresponding timer latch at the same time, or is written only to the latch. [At read] • The corresponding timer count value is read out by reading this register. • Read both registers in order of TZH and TZL following. • Write both registers in order of TZL and TZH following. At reset R W 1 1 1 1 1 1 1 1 Fig. 2.3.5 Structure of Timer Z (low-order, high-order) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-24 APPLICATION 3804 Group (Spec.H) 2.3 Timer Timer XY mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer XY mode register (TM: address 002316) b Name b1 b0 Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer X operating mode bits 1 2 3 4 5 6 7 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge Refer to Table 2.3.1 switch bit Timer X count stop 0: Count start 1: Count stop bit Timer Y operating b5 b4 0 0: Timer mode mode bits 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge Refer to Table 2.3.1 switch bit Timer Y count stop 0: Count start 1: Count stop bit Fig. 2.3.6 Structure of Timer XY mode register Table 2.3.1 CNTR 0 / CNTR 1 a ctive edge switch bit function Timer X /Timer Y operation modes Timer mode CNTR 0 / C NTR 1 a ctive edge switch bit (bits 2, 6 of address 0023 16) contents “0” CNTR 0 / C NTR 1 i nterrupt request occurrence: Falling edge ; No influence to timer count “1” CNTR 0 / C NTR 1 i nterrupt request occurrence: Rising edge Pulse output mode ; No influence to timer count “0” Pulse output start: Beginning at “ H ” l evel CNTR 0 / C NTR 1 i nterrupt request occurrence: Falling edge “1” Pulse output start: Beginning at “ L ” l evel CNTR 0 / C NTR 1 i nterrupt request occurrence: Rising edge Event counter mode “0” Timer X / Timer Y: Rising edge count CNTR 0 / C NTR 1 i nterrupt request occurrence: Falling edge “1” Timer X / Timer Y: Falling edge count CNTR 0 / C NTR 1 i nterrupt request occurrence: Rising edge Pulse width measurement mode “0” Timer X / Timer Y: “ H ” l evel width measurement CNTR 0 / C NTR 1 i nterrupt request occurrence: Falling edge “1” Timer X / Timer Y: “ L ” l evel width measurement CNTR 0 / C NTR 1 i nterrupt request occurrence: Rising edge Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-25 APPLICATION 3804 Group (Spec.H) 2.3 Timer Timer Z mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Z mode register (TZM: address 002A16) b Name b2b1b0 Functions 0 0 0: Timer/Event counter mode 0 0 1: Pulse output mode 0 1 0: Pulse period measurement mode 0 1 1: Pulse width measurement mode 1 0 0: Programmable waveform generating mode 1 0 1: Programmable one-shot generating mode 1 1 0: Not available 1 1 1: Not available At reset R W 0 0 Timer Z operating mode bits 1 0 2 0 3 Timer Z write control 0: Writing data to both latch and timer simultaneousuly bit 1: Writing data only to latch 0: “L” output 4 Output level latch 1: “H” output CNTR2 active edge Refer to Table 2.3.2. 5 switch bit 6 Timer Z count stop 0: Count start 1: Count stop bit 7 Timer/Event counter 0: Timer mode mode switch bit (Note) 1: Event counter mode 0 0 0 0 0 Note: When selecting the modes except the timer/event counter mode, set “0” to this bit. Fig. 2.3.7 Structure of Timer Z mode register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-26 APPLICATION 3804 Group (Spec.H) 2.3 Timer Table 2.3.2 CNTR 2 a ctive edge switch bit function Timer Z operation modes Timer mode CNTR2 a ctive edge switch bit (bit 5 of address 002A 16) contents “0” CNTR 2 i nterrupt request occurrence: Falling edge ; No influence to timer count “1” CNTR 2 i nterrupt request occurrence: Rising edge ; No influence to timer count Event counter mode “0” Timer Z: Rising edge count CNTR 2 i nterrupt request occurrence: Falling edge “1” Timer Z: Falling edge count CNTR 2 i nterrupt request occurrence: Rising edge Pulse output mode “0” Pulse output start: Beginning at “ H ” l evel CNTR 2 i nterrupt request occurrence: Falling edge “1” Pulse output start: Beginning at “ L ” l evel CNTR 2 i nterrupt request occurrence: Rising edge Pulse period measurement mode “0” Timer Z : Term from one falling edge to next falling edge measurement CNTR 2 i nterrupt request occurrence: Falling edge “1” Timer Z : Term from one rising edge to next rising edge measurement CNTR 2 i nterrupt request occurrence: Rising edge Pulse width measurement mode “0” Timer Z: “ H ” l evel width measurement CNTR 2 i nterrupt request occurrence: Falling edge “1” Timer Z: “ L ” l evel width measurement CNTR 2 i nterrupt request occurrence: Rising edge Programmable one-shot generating “0” Timer Z : Pulse output start from “ L ” l evel, and “ H ” l evel one-shot mode pulse is output. CNTR 2 i nterrupt request occurrence: Falling edge “1” Timer Z : Pulse output start from “ H ” l evel, and “ L ” l evel one-shot pulse is output. CNTR 2 i nterrupt request occurrence: Rising edge Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-27 APPLICATION 3804 Group (Spec.H) 2.3 Timer Timer 12, X count source selection register b7 b6 b5 b4 b3 b2 b1 b0 Timer 12, X count source selection register (T12XCSS: address 000E16) b Name b3b2b1b0 Functions 0 0 0 0: f(XIN)/2 or f(XCIN)/2 0 0 0 1: f(XIN)/4 or f(XCIN)/4 0 0 1 0: f(XIN)/8 or f(XCIN)/8 0 0 1 1: f(XIN)/16 or f(XCIN)/16 0 1 0 0: f(XIN)/32 or f(XCIN)/32 0 1 0 1: f(XIN)/64 or f(XCIN)/64 0 1 1 0: f(XIN)/128 or f(XCIN)/128 0 1 1 1: f(XIN)/256 or f(XCIN)/256 1 0 0 0: f(XIN)/512 or f(XCIN)/512 1 0 0 1: f(XIN)/1024 or f(XCIN)/1024 1010 to 1111: Not available b7b6b5b4 At reset R W 1 1 0 0 1 1 0 0 0 Timer 12 count source selection bits 1 2 3 4 Timer X count source selection bits 5 6 7 0 0 0 0: f(XIN)/2 or f(XCIN)/2 0 0 0 1: f(XIN)/4 or f(XCIN)/4 0 0 1 0: f(XIN)/8 or f(XCIN)/8 0 0 1 1: f(XIN)/16 or f(XCIN)/16 0 1 0 0: f(XIN)/32 or f(XCIN)/32 0 1 0 1: f(XIN)/64 or f(XCIN)/64 0 1 1 0: f(XIN)/128 or f(XCIN)/128 0 1 1 1: f(XIN)/256 or f(XCIN)/256 1 0 0 0: f(XIN)/512 or f(XCIN)/512 1 0 0 1: f(XIN)/1024 or f(XCIN)/1024 1 0 1 0: f(XCIN) 1011 to 1111: Not available Fig. 2.3.8 Structure of Timer 12, X count source selection register Timer Y, Z count source selection register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z count source selection register (TYZCSS: address 000F16) b Name b3b2b1b0 Functions 0 0 0 0: f(XIN)/2 or f(XCIN)/2 0 0 0 1: f(XIN)/4 or f(XCIN)/4 0 0 1 0: f(XIN)/8 or f(XCIN)/8 0 0 1 1: f(XIN)/16 or f(XCIN)/16 0 1 0 0: f(XIN)/32 or f(XCIN)/32 0 1 0 1: f(XIN)/64 or f(XCIN)/64 0 1 1 0: f(XIN)/128 or f(XCIN)/128 0 1 1 1: f(XIN)/256 or f(XCIN)/256 1 0 0 0: f(XIN)/512 or f(XCIN)/512 1 0 0 1: f(XIN)/1024 or f(XCIN)/1024 1 0 1 0: f(XCIN) 1011 to 1111: Not available b7b6b5b4 At reset R W 1 0 Timer Y count source selection bits 1 1 0 2 3 0 4 Timer Z count source selection bits 5 6 7 0 0 0 0: f(XIN)/2 or f(XCIN)/2 0 0 0 1: f(XIN)/4 or f(XCIN)/4 0 0 1 0: f(XIN)/8 or f(XCIN)/8 0 0 1 1: f(XIN)/16 or f(XCIN)/16 0 1 0 0: f(XIN)/32 or f(XCIN)/32 0 1 0 1: f(XIN)/64 or f(XCIN)/64 0 1 1 0: f(XIN)/128 or f(XCIN)/128 0 1 1 1: f(XIN)/256 or f(XCIN)/256 1 0 0 0: f(XIN)/512 or f(XCIN)/512 1 0 0 1: f(XIN)/1024 or f(XCIN)/1024 1 0 1 0: f(XCIN) 1011 to 1111: Not available 1 1 0 0 Fig. 2.3.9 Structure of Timer Y, Z count source selection register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-28 APPLICATION 3804 Group (Spec.H) 2.3 Timer Interrupt source selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt source selection register (INTSEL: address 003916) b Name Functions 0: INT0 interrupt 1: Timer Z interrupt 0: Serial I/O2 interrupt 1: Timer Z interrupt 0: Serial I/O1 transmit interrupt 1: SCL, SDA interrupt 0: CNTR0 interrupt 1: SCL, SDA interrupt 0: INT4 interrupt 1: CNTR2 interrupt 0: INT2 interrupt 1: I2C interrupt 0: CNTR1 interrupt 1: Serial I/O3 receive interrupt 0: A/D converter interrupt 1: Serial I/O3 transmit interrupt At reset R W 0 0 INT0/Timer Z interrupt source selection bit (*1) 1 Serial I/O2/Timer Z interrupt source selection bit (*1) 2 Serial I/O1 transmit/ SCL, SDA interrupt source selection bit (*2) 3 CNTR0/SCL, SDA interrupt source selection bit (*2) 4 INT4/CNTR2 interrupt source selection bit 5 INT2/I2C interrupt source selection bit 6 CNTR1/Serial I/O3 receive interrupt source selection bit 7 AD converter/Serial I/O3 transmit interrupt source selection bit 0 0 0 0 0 0 0 *1: Do not write 1 to these bits simultaneously. *2: Do not write 1 to these bits simultaneously. Fig. 2.3.10 Structure of Interrupt source selection register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-29 APPLICATION 3804 Group (Spec.H) 2.3 Timer Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1 : address 003C16) b Name Functions At reset R W 0 0 0 0 ✽ ✽ ✽ ✽ 0 INT0/Timer Z 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 1 INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 2 Serial I/O1 receive 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 0 : No interrupt request issued 3 Serial I/O1 transmit/SCL, SDA 1 : Interrupt request issued interrupt request bit 4 Timer X interrupt request bit 5 Timer Y interrupt request bit 6 Timer 1 interrupt request bit 0 : No interrupt request issued 0 0 0 0 ✽ ✽ ✽ ✽ 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 7 Timer 2 interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: 0 can be set by software, but 1 cannot be set. Fig. 2.3.11 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2 : address 003D16) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 ✽ ✽ 0 CNTR0/SCL, SDA interrupt request bit 1 CNTR1/Serial I/O3 receive interrupt request bit 2 Serial I/O2/Timer Z interrupt request bit 3 INT2/I2C interrupt request bit 4 INT3 interrupt request bit 5 INT4/CNTR2 interrupt request bit 6 AD converter/Serial I/O3 transmit interrupt request bit 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . ✽: 0 can be set by software, but 1 cannot be set. 0 Fig. 2.3.12 Structure of Interrupt request register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-30 APPLICATION 3804 Group (Spec.H) 2.3 Timer Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1 : address 003E16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 INT0/Timer Z interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O1 receive interrupt enable bit 3 Serial I/O1 transmit/SCL, SDA interrupt enable bit 4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit Timer 2 interrupt 7 enable bit 0 0 0 0 Fig. 2.3.13 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2 : address 003F16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 CNTR0/SCL, SDA interrupt enable bit 1 CNTR1/ Serial I/O3 receive interrupt enable bit 2 Serial I/O2/ Timer Z interrupt enable bit 3 INT2/I2C interrupt enable bit 4 INT3 interrupt enable bit 5 INT4/CNTR2 interrupt enable bit 6 AD converter/Serial I/O3 transmit interrupt enable bit 7 Fix this bit to “0”. 0 0 0 0 0 0 Fig. 2.3.14 Structure of Interrupt control register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-31 APPLICATION 3804 Group (Spec.H) 2.3 Timer 2.3.3 Timer application examples (1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer Y, Timer Z, Timer 1, Timer 2) When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. • Generation of an output signal timing • Generation of a wait time [Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer Z, Timer 1, Timer 2) The value of the timer latch is automatically written to the corresponding timer each time the timer underflows, and each timer interrupt request occurs in cycles. • Generation of cyclic interrupts • Clock function (measurement of 250 ms); see Application example 1 • Control of a main routine cycle [Function 3] Output of Rectangular waveform (Timer X, Timer Y, Timer Z) The output level of the CNTR pin is inverted each time the timer underflows (in the pulse output mode). • Piezoelectric buzzer output; see Application example 2 • Generation of the remote control carrier waveforms [Function 4] Count of External pulses (Timer X, Timer Y, Timer Z) External pulses input to the CNTR pin are counted as the timer count source (in the event counter mode). • Frequency measurement; see Application example 3 • Division of external pulses • Generation of interrupts due to a cycle using external pulses as the count source; count of a reel pulse [Function 5] Measurement of External pulse width (Timer X, Timer Y, Timer Z) The “ H ” o r “ L ” l evel width of external pulses input to CNTR pin is measured (in the pulse width measurement mode). • Measurement of external pulse frequency (measurement of pulse width of FG pulse ✽ f or a motor); see Application example 4 • Measurement of external pulse duty (when the frequency is fixed) FG pulse ✽: Pulse used for detecting the motor speed to control the motor speed. [Function 6] Output of Arbitrary waveform (Timer Z) The value which is set to the output level latch is output from the CNTR pin each time the timer underflows. (programmable waveform generating mode) [Function 7] One-shot pulse output by external trigger (Timer Z) The value of timer latch is set to timer by trigger signal which is input from the INT pin, and timer is counted down. When trigger signal is input, “H” or “L” is output from the CNTR pin at the same time, and “ L ” o r “ H ” i s output by underflow of timer. (programmable one-shot generating mode) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-32 APPLICATION 3804 Group (Spec.H) 2.3 Timer (2) Timer application example 1: Clock function (measurement of 250 ms) Outline: The input clock is divided by the timer so that the clock can count up at 250 ms intervals. Specifications: • The clock f(X IN) = 4.19 MHz (2 22 H z) is divided by the timer. •The clock is counted up in the process routine of the timer X interrupt which occurs at 250 ms intervals. Figure 2.3.15 shows the timers connection and setting of division ratios; Figure 2.3.16 shows the relevant registers setting; Figure 2.3.17 shows the control procedure. Timer X count source selection bit f(XIN) = 4.19 MHz 1/16 Prescaler X 1/256 Timer X 1/256 Timer X interrupt request bit 0 or 1 250 ms Dividing by 4 with software 1/4 1 second 0 : No interrupt request issued 1 : Interrupt request issued Fig. 2.3.15 Timers connection and setting of division ratios Timer 12, X count source selection register (address 000E16) b7 b0 T12XCSS 0011 Timer X count source : f(XIN)/16 Timer XY mode register (address 002316) b7 b0 TM 1 00 Timer X operating mode: Timer mode Timer X count: Stop Clear to “0” when starting count. Prescaler X (address 002416) b7 b0 PREX 256 – 1 Timer X (address 002516) b7 b0 Set “division ratio – 1” TX 256 – 1 Interrupt control register 1 (address 003E16) b7 b0 ICON1 1 Timer X interrupt: Enabled Interrupt request register 1 (address 003C16) b7 b0 IREQ1 0 Timer X interrupt request (becomes “1” at 250 ms intervals) Fig. 2.3.16 Relevant registers setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-33 APPLICATION 3804 Group (Spec.H) 2.3 Timer RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SEI TM XXXX1X002 (address 002316) IREQ1 (address 003C16), bit4 0 ICON1 (address 003E16), bit4 1 ..... ..... •All interrupts disabled •Timer X : Timer mode •Clear Timer X interrupt request bit •Timer X interrupt enabled T12XCSS (address 000E16) (address 002416) PREX (address 002516) TX TM CLI ..... ..... 0011XXXX2 256 – 1 256 – 1 0 •Timer X count source : f(XIN)/16 •Set “division ratio – 1” to Prescaler X and Timer X (address 002316), bit3 •Timer X count start •Interrupts enabled Main processing (Note 1) PREX (address 002416) 256 – 1 TX (address 002516) 256 – 1 IREQ1 (address 003C16), bit4 0 ..... •Reset Timer to restart count from 0 second after completion of clock set Note 1: Perform procedure for completion of clock set only when completing clock set. Timer X interrupt process routine CLT (Note 2) CLD (Note 3) Push registers to stack Note 2: When using Index X mode flag (T) Note 3: When using Decimal mode flag (D) •Push registers used in interrupt process routine Clock stop ? N Clock count up (1/4 second to year) Y •Judge whether clock stops •Clock count up Pop registers •Pop registers pushed to stack RTI Fig. 2.3.17 Control procedure Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-34 APPLICATION 3804 Group (Spec.H) 2.3 Timer (3) Timer application example 2: Piezoelectric buzzer output Outline : The rectangular waveform output function of the timer is applied for a piezoelectric buzzer output. Specifications: •The rectangular waveform, dividing the clock f(XIN) = 8 MHz into about 2 kHz (2049 Hz), is output from the P4 7/CNTR 2 p in. • The level of the P47/CNTR 2 p in is fixed to “ H ” w hile a piezoelectric buzzer output stops. Figure 2.3.18 shows a peripheral circuit example, and Figure 2.3.19 shows the timers connection and setting of division ratios. Figure 2.3.20 shows the relevant registers setting, and Figure 2.3.21 shows the control procedure. The “H” level is output while a piezoelectric buzzer output stops. CNTR2 output P47/CNTR2 244 µs 244 µs PiPiPi..... Set a division ratio so that the underflow output period of the timer Z 3804 Group (Spec. H) can be 244 µs. Fig. 2.3.18 Peripheral circuit example Timer Z count source selection bit Timer Z f(XIN) = 8 MHz 1/16 1/122 CNTR2 Fig. 2.3.19 Timers connection and setting of division ratios Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-35 APPLICATION 3804 Group (Spec.H) 2.3 Timer Timer Y, Z count source selection register (address 000F16) b7 b0 TYZCSS 0011 Timer Z count source: f(XIN)/16 Timer Z mode register (address 002A16) b7 b0 TM 10 0001 Timer Z operating mode : Pulse output mode Write value in latch and timer at the same time CNTR2 active edge switch : Output starting at “H” level Timer Z count : Stop Clear to “0” when starting count Timer Z high-order (address 002916) b7 b0 TZH 0 Timer Z low-order (address 002816) b7 b0 Set “division ratio – 1” TZL 122–1 Port P4 direction register (address 000916) b7 b0 P4D 1 P47/CNTR2 : Output mode Port P4 (address 000816) b7 b0 P4 1 “H” output at stopping buzzer output Fig. 2.3.20 Relevant registers setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-36 APPLICATION 3804 Group (Spec.H) 2.3 Timer RESET q X: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization P4 (address 000816), bit7 P4D (address 000916) ICON1 (address 003E16), bit0 0 X10X00012 (address 002A16) TZM TYZCSS (address 000F16) (address 002816) TZL (address 002916) TZH 0011XXXX2 122–1 0 Main processing Output unit Buzzer request ? Yes Stop of piezoelectric buzzer output Fig. 2.3.21 Control procedure Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z ..... 1 1XXXXXXX2 •Timer Z interrupt disabled •Timer Z count stopped; Buzzer output stopped •Timer Z: Pulse output mode •Timer Z count source: f(XIN)/16 •Set (division ratio – 1) to timer Z TZM ..... ..... ..... •Processing buzzer request, generated during main processing, in output unit No (address 002A16), bit6 1 TZM (address 002A16), bit6 0 Start of piezoelectric buzzer output 2-37 APPLICATION 3804 Group (Spec.H) 2.3 Timer (4) Timer application example 3: Frequency measurement Outline : The following two values are compared to judge whether the frequency is within a valid range. • A value by counting pulses input to P5 5/CNTR 1 p in with the timer. • A reference value Specifications: • The pulse is input to the P5 5/CNTR 1 p in and counted by the timer Y. •The clock f(XIN) = 8 MHz is dividing by the timer 1, and the interrupt request occurs at about 2 ms intervals. • A count value is read out at about 2 ms intervals, the timer 1 interrupt interval. When the count value is 28 to 40, it is judged that the input pulse is valid. •Because the timer is a down-counter, the count value is compared with 227 to 215 (Note). Note: 227 to 215 = {255 (initial value of counter) – 2 8} to {255 – 4 0}; 28 to 40 means the number of valid count value. Figure 2.3.22 shows the judgment method of valid/invalid of input pulses; Figure 2.3.23 shows the relevant registers setting; Figure 2.3.24 shows the control procedure. Input pulse ••••• ••••• ••••• 71.4 µs or more (less than 14 kHz) 71.4 µs (14 kHz) 50 µs (20 kHz) 50 µs or less (20 kHz or more) Invalid 2 ms = 28 counts 71.4 µs Valid 2 ms 50 µs Invalid = 40 counts Fig. 2.3.22 Judgment method of valid/invalid of input pulses Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-38 APPLICATION 3804 Group (Spec.H) 2.3 Timer Timer XY mode register (address 002316) b7 b0 TM 1 110 Timer Y operating mode: Event counter mode CNTR1 active edge switch: Falling edge count Timer Y count: Stop Clear to “0” when starting count Timer 12, X count source selection register (address 000E16) b7 b0 T12XCSS 0100 f(XIN)/32: select Prescaler 12 (address 002016) b7 b0 PRE12 64 – 1 Timer 1 (address 002116) b7 b0 T1 8–1 Set “division ratio – 1” Prescaler Y (address 002616) b7 b0 PREY 1–1 Timer Y (address 002716) b7 b0 TY 255 Set 255 just before counting pulses (After a certain time has passed, the number of input pulses is decreased from this value.) Interrupt control register 1 (address 003E16) b7 b0 ICON1 10 Timer Y interrupt: Disabled Timer 1 interrupt: Enabled Interrupt request register 1 (address 003C16) b7 b0 IREQ1 0 Judgment of Timer Y interrupt request bit ( “1” of this bit when reading the count value indicates the 256 or more pulses input in the condition of Timer Y = 255) Fig. 2.3.23 Relevant registers setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-39 APPLICATION 3804 Group (Spec.H) 2.3 Timer RESET Initialization SEI 1110XXXX2 (address 002316) TM T12XCSS(address 000E16) XXXX01002 PRE12 (address 002016) 64 – 1 (address 002116) T1 8–1 (address 002616) PREY 1–1 (address 002716) TY 255 IREQ1 (address 003C16) X00XXXXX2 1 ICON1 (address 003E16), bit6 TM CLI ... .. ... .. ... .. q x: This bit is not used here. Set it to “0” or “1” arbitrary. •All interrupts disabled •Timer Y operating mode : Event counter mode (Count a falling edge of pulses input from CNTR1 pin.) •Set division ratio so that Timer 1 interrupt will occur at 2 ms intervals. •Timer 1, Y interrupt request bit cleared •Timer 1 interrupt: Enabled •Timer Y count start •Interrupts enabled (address 002316), bit7 0 Timer 1 interrupt process routine CLT (Note 1) CLD (Note 2) Push registers to stack Note 1: When using Index X mode flag (T) Note 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine 1 IREQ1(address 003C16), bit5 ? 0 (A) TY (address 002716) •Read the count value •Store the count value into Accumulator (A) •Process as out of range when the count value is 256 or more In range 214 < (A) < 228 Out of range Fpulse 0 Fpulse •Compare the read value with reference value •Store the comparison result to flag Fpulse 1 TY (address 002716) IREQ1 (address 003C16), bit5 256 – 1 0 •Initialize the counter value •Clear Timer Y interrupt request bit Process judgment result Pop registers •Pop registers pushed to stack RTI Fig. 2.3.24 Control procedure Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-40 APPLICATION 3804 Group (Spec.H) 2.3 Timer (5) Timer application example 4: Measurement of FG pulse width for motor Outline: The timer Z counts the “H” level width of the pulses input to the P47/CNTR2 pin. An underflow is detected by the timer Z interrupt and an end of the input pulse “H” level is detected by the P4 7/CNTR2 i nterrupt. Specifications : •The timer Z counts the “H” level width of the FG pulse input to the P4 7/CNTR 2 pin. When the clock frequency is 8 MHz, the count source is 2 µs, which is obtained by dividing the clock frequency by 16. Measurement can be made up to 131.072 ms in the range of FFFF 16 t o 0000 16. Figure 2.3.25 shows the timers connection and setting of division ratio; Figure 2.3.26 shows the relevant registers setting; Figure 2.3.27 and Figure 2.3.28 show the control procedure. Timer Z count source selection bit f(XIN) = 8 MHz 1/16 Timer Z 1/65536 Timer Z interrupt request bit 0 or 1 131.072 ms 0 : No interrupt request issued 1 : Interrupt request issued Fig. 2.3.25 Timers connection and setting of division ratios Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-41 APPLICATION 3804 Group (Spec.H) 2.3 Timer Port P4 direction register (address 000916) b7 b0 P4D 0 P47/CNTR2: Input mode Timer Z mode register (address 002A16) b7 b0 TZM 10 0011 Timer Z operating mode: Pulse width measurement mode Write in latch and timer at the same time CNTR2 active edge switch: “H” level width measurement Timer Z count: Stop Clear to “0” when starting count Timer Y, Z count source selection register (address 000F16) b7 b0 TYZCSS 0011 Timer Z count source: f(XIN)/16 Timer Z high-order (address 002916) b7 b0 TZH FF16 Set initial value “FFFF16” before starting pulse width measurement. (When not setting the initial value, count is started from the timer value before measurement start.) Timer Z low-order (address 002816) b7 b0 TZL FF16 Interrupt source selection register (address 003916) b7 b0 INTSEL 1 1 INT0/timer Z interrupt source: Timer Z interrupt INT4/CNTR2 interrupt source: CNTR2 interrupt Interrupt request register 1 (address 003C16) b7 b0 IREQ1 0 Timer Z interrupt request (Set to “1” automatically when Timer Z underflows) Interrupt control register 1 (address 003E16) b7 b0 ICON1 1 Timer Z interrupt: Enabled Interrupt request register 2 (address 003D16) b7 b0 IREQ2 0 CNTR2 interrupt request (Set to “1” automatically when “H” level input came to the end) Interrupt control register 2 (address 003F16) b7 b0 ICON2 1 CNTR2 interrupt: Enabled Fig. 2.3.26 Relevant registers setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-42 APPLICATION 3804 Group (Spec.H) 2.3 Timer RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SEI 0XXXXXXX2 (address 000916) P4D X10X00112 (address 002A16) TZM 0011XXXX2 TYZCSS (address 000F16) FF16 (address 002816) TZL FF16 (address 002916) TZH XXX1XXX12 INTSEL (address 003916) IREQ1 (address 003C16), bit0 0 ICON1 (address 003E16), bit0 1 IREQ2 (address 003D16), bit5 0 ICON2 (address 003F16), bit5 1 TZM CLI .... .... ..... •All interrupts disabled •Set P47/CNTR2 pin to input mode •Timer Z: Pulse width measurement mode (Measure “H” level of pulses input from CNTR2 pin.) •Set timer Z initial value •Timer Z interrupt enabled •CNTR2 interrupt enabled •Timer Z count start •Interrupts enabled (address 002A16), bit6 0 Timer Z interrupt process routine CLT (Note 1) CLD (Note 2) Push registers to stack Note 1: When using Index X mode flag (T) Note 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine Error processing Pop registers •Pop registers pushed to stack RTI Note: Timer Z interrupt also occurs owing to factors other than measurement level. (CNTR2 input =“L” in this application) Process it by software as error processing is performed for measurement level as necessary. (CNTR2 input level can be checked by reading the contents of sharing port P47 register.) Fig. 2.3.27 Control procedure (1) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-43 APPLICATION 3804 Group (Spec.H) 2.3 Timer CNTR2 interrupt process routine (Note 1) Notes 2: When using Index X mode flag (T) 3: When using Decimal mode flag (D) •Pushing registers used in interrupt process routine CLT (Note 2) CLD (Note 3) Push registers to stack (A) Measurement result (high-order 8 bits) (A) Measurement result (low-order 8 bits) TZH (A) TZL (A) •Count value read and storing it to RAM Pop registers •Popping registers pushed to stack RTI Note 1: The first value becomes invalid depending on start timing of Timer Z count shown by the following figure. Process it by software as necessary. [ Example 1] • Start Timer Z count when CNTR2 input level is “L”. (CNTR2 input level can be checked by reading the contents of sharing port P47 register.) FFFF16 T1 T2 000016 T1 value: Valid CNTR2 Count start of Timer Z T2 value: Valid CNTR2 interrupt CNTR2 interrupt [ Example 2] • Start Timer Z count when CNTR2 input level is “H”. Invalidate the first CNTR2 interrupt after start of Timer Z count. FFFF16 T1 T2 000016 CNTR2 T1 value: Invalid T2 value: Valid Count start of CNTR2 interrupt Timer z CNTR2 interrupt Fig. 2.3.28 Control procedure (2) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-44 APPLICATION 3804 Group (Spec.H) 2.3 Timer 2.3.4 Notes on timer Notes on 8-bit timer (timer 1, 2, X, Y) q If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). q When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. q Set the double-function port of the CNTR0/CNTR1 pin and port P54/P55 to output in the pulse output mode. q S et the double-function port of CNTR 0/CNTR 1 p in and port P54/P5 5 t o input in the event counter mode and the pulse width measurement mode. Notes on 16-bit timer (timer Z) (1) Pulse output mode q S et the double-function port of the CNTR 2 p in and port P4 7 t o output. (2) Pulse period measurement mode q S et the double-function port of the CNTR 2 p in and port P4 7 t o input. q A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). q S ince the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. q “ FFFF 16 ” i s set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. (3) Pulse width measurement mode q S et the double-function port of the CNTR 2 p in and port P4 7 t o input. q A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). q S ince the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. q “ FFFF 16 ” i s set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. (4) Programmable waveform generating mode q S et the double-function port of the CNTR 2 p in and port P4 7 t o output. (5) Programmable one-shot generating mode q Set the double-function port of CNTR 2 pin and port P4 7 to output, and of INT1 pin and port P42 to input in this mode. q T his mode cannot be used in low-speed mode. q I f the value of the CNTR2 a ctive edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 p in changes. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-45 APPLICATION 3804 Group (Spec.H) 2.3 Timer (6) All modes qTimer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A 16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “ writing data only to the latch ” i s selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation “ writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. qTimer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. qSwitch of interrupt active edge of CNTR 2 a nd INT 1 Each interrupt active edge depends on setting of the CNTR 2 a ctive edge switch bit and the INT1 active edge selection bit. qSwitch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-46 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface 2.4 Serial interface This paragraph explains the registers setting method and the notes relevant to Serial I/O. 2.4.1 Memory map Address 001816 001916 001A16 001B16 001C16 001D16 001F16 Transmit/Receive buffer register 1 (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator 1 (BRG1) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) 002F16 003016 003116 003216 003316 Baud rate generator 3 (BRG3) Transmit/Receive buffer register 3 (TB3/RB3) Serial I/O3 status register (SIO3STS) Serial I/O3 control register (SIO3CON) UART3 control register (UART3CON) 003916 003C16 003D16 003E16 003F16 Interrupt source selection register (INTSEL) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.4.1 Memory map of registers relevant to Serial I/O Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-47 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface 2.4.2 Relevant registers Transmit/Receive buffer register 1, Transmit/Receive buffer register 3 b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register 1 (TB1/RB1: address 001816) Transmit/Receive buffer register 3 (TB3/RB3: address 003016) b 0 1 2 3 4 5 6 7 Functions The transmission data is written to or the receive data is read out from this buffer register. • At write: A data is written to the transmit buffer register. • At read: The contents of the receive buffer register are read out. At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Note: The contents of transmit buffer register cannot be read out. The data cannot be written to the receive buffer register. Fig. 2.4.2 Structure of Transmit/Receive buffer register 1 and Transmit/Receive buffer register 3 Serial I/O1 status register, Serial I/O3 status register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 status register (SIO1STS: address 001916) Serial I/O3 status register (SIO3STS: address 003116) b Name Functions 0: Buffer full 1: Buffer empty 0: Buffer empty 1: Buffer full 0: Transmit shift in progress 1: Transmit shift completed 0 Transmit buffer empty flag (TBE) 1 Receive buffer full flag (RBF) 2 Transmit shift register shift completion flag (TSC) At reset R W ✕ 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ 3 Overrun error flag 0: No error (OE) 1: Overrun error 4 Parity error flag 0: No error (PE) 1: Parity error 5 Framing error flag 0: No error (FE) 1: Framing error 6 Summing error flag 0: (OE) U (PE) U (FE) = 0 (SE) 1: (OE) U (PE) U (FE) = 1 7 Nothing is arranged for this bit. This bit is a write disabled bit. When this bit is read out, the contents are “1”. 0 0 0 0 1 Fig. 2.4.3 Structure of Serial I/O1 status register and Serial I/O3 status register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-48 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Serial I/O1 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON: address 001A16) b Name Functions At reset R W 0 0 0 BRG count source 0: f(XIN) selection bit (CSS) 1: f(XIN)/4 When clock synchronous 1 Serial I/O1 synchronous clock serial I/O is selected, selection bit (SCS) 0: BRG output divided by 4 1: External clock input When UART is selected, 0: BRG output divided by 16 1: External clock input divided by16 2 SRDY1 output enable bit (SRDY) 3 Transmit interrupt source selection bit (TIC) 4 Transmit enable bit (TE) 5 Receive enable bit (RE) 6 Serial I/O1 mode selection bit (SIOM) 7 Serial I/O1 enable bit (SIOE) 0: I/O port (P47) 1: SRDY1 output pin 0: Transmit buffer empty 1: Transmit shift operation completion 0: Transmit disabled 1: Transmit enabled 0: Receive disabled 1: Receive enabled 0: UART 1: Clock synchronous serial I/O 0: Serial I/O1 disabled (P44 to P47: normal I/O pins) 1: Serial I/O1 enabled (P44 to P47: Serial I/O pins) 0 0 0 0 0 0 Fig. 2.4.4 Structure of Serial I/O1 control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-49 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Serial I/O3 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O3 control register (SIO3CON: address 003216) b Name Functions At reset R W 0 0 0 BRG count source 0: f(XIN) selection bit (CSS) 1: f(XIN)/4 When clock synchronous 1 Serial I/O3 synchronous clock serial I/O is selected, selection bit (SCS) 0: BRG output divided by 4 1: External clock input When UART is selected, 0: BRG output divided by 16 1: External clock input divided by16 2 SRDY3 output enable bit (SRDY) 3 Transmit interrupt source selection bit (TIC) 4 Transmit enable bit (TE) 5 Receive enable bit (RE) 6 Serial I/O3 mode selection bit (SIOM) 7 Serial I/O3 enable bit (SIOE) 0: I/O port (P37) 1: SRDY3 output pin 0: Transmit buffer empty 1: Transmit shift operation completion 0: Transmit disabled 1: Transmit enabled 0: Receive disabled 1: Receive enabled 0: UART 1: Clock synchronous serial I/O 0: Serial I/O3 disabled (P34 to P37: normal I/O pins) 1: Serial I/O3 enabled (P34 to P37: Serial I/O pins) 0 0 0 0 0 0 Fig. 2.4.5 Structure of Serial I/O3 control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-50 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface UART1 control register b7 b6 b5 b4 b3 b2 b1 b0 UART1 control register (UART1CON: address 001B16) b Name Functions At reset R W 0 0 0 0 0 0 Character length 0: 8 bits selection bit (CHAS) 1: 7 bits 1 Parity enable bit (PARE) 2 Parity selection bit (PARS) 0: Parity checking disabled 1: Parity checking enabled 0: Even parity 1: Odd parity 3 Stop bit length 0: 1 stop bit selection bit (STPS) 1: 2 stop bits 4 P45/TxD1 P-channel 0: CMOS output output disable bit (in output mode) (POFF) 1: N-channel open-drain output (in output mode) 5 Nothing is arranged for these bits. These are 6 write disabled bits. When these bits are read out, the contents are “1”. 7 1 1 1 ✕ ✕ ✕ Fig. 2.4.6 Structure of UART1 control register UART3 control register b7 b6 b5 b4 b3 b2 b1 b0 UART3 control register (UART3CON: address 003316) b Name Functions At reset R W 0 0 0 0 0 0 Character length 0: 8 bits selection bit (CHAS) 1: 7 bits 1 Parity enable bit (PARE) 2 Parity selection bit (PARS) 0: Parity checking disabled 1: Parity checking enabled 0: Even parity 1: Odd parity 3 Stop bit length 0: 1 stop bit selection bit (STPS) 1: 2 stop bits 4 P35/TxD3 P-channel 0: CMOS output output disable bit (in output mode) (POFF) 1: N-channel open-drain output (in output mode) 5 Nothing is arranged for these bits. These are 6 write disabled bits. When these bits are read out, the contents are “1”. 7 1 1 1 ✕ ✕ ✕ Fig. 2.4.7 Structure of UART3 control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-51 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Baud rate generator i (i = 1, 3) b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator i (BRGi (i=1, 3): address 001C16, 002F16) b Functions At reset R W 0 Set a count value of baud rate generator. Undefined 1 Undefined 2 Undefined 3 Undefined 4 Undefined 5 Undefined 6 Undefined 7 Undefined Note: Write to this register while transmit/receive operation is stopped. Fig. 2.4.8 Structure of Baud rate generator 1 and Baud rate generator 3 Serial I/O2 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register (SIO2CON: address 001D16) b Name b2b1b0 Functions 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 0: I/O port (P51, P52) 1: SOUT2, SCLK2 signal output 0: I/O port (P53) 1: SRDY2 signal output 0: LSB first 1: MSB first 0: External clock 1: Internal clock 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) At reset R W 0 0 0 0 0 0 0 0 Internal synchronous clock 1 selection bits 2 3 Serial I/O2 port selection bit 4 SRDY2 output enable bit 5 Transfer direction selection bit 6 Serial I/O2 synchronous clock selection bit 7 P51/SOUT2 P-channel output disable bit 0 Fig. 2.4.9 Structure of Serial I/O2 control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-52 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Serial I/O2 register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 register (SIO2: address 001F16) b 0 1 2 3 4 5 6 7 Name Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined This register becomes shift register. At transmit: Set transmit data to this register. At receive: Received data is stored to this register. Fig. 2.4.10 Structure of Serial I/O2 register Interrupt source selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt source selection register (INTSEL: address 003916) b Name Functions 0: INT0 interrupt 1: Timer Z interrupt 0: Serial I/O2 interrupt 1: Timer Z interrupt 0: Serial I/O1 transmit interrupt 1: SCL, SDA interrupt 0: CNTR0 interrupt 1: SCL, SDA interrupt 0: INT4 interrupt 1: CNTR2 interrupt 0: INT2 interrupt 1: I2C interrupt 0: CNTR1 interrupt 1: Serial I/O3 receive interrupt 0: A/D converter interrupt 1: Serial I/O3 transmit interrupt At reset R W 0 0 INT0/Timer Z interrupt source selection bit (*1) 1 Serial I/O2/Timer Z interrupt source selection bit (*1) 2 Serial I/O1 transmit/ SCL, SDA interrupt source selection bit (*2) 3 CNTR0/SCL, SDA interrupt source selection bit (*2) 4 INT4/CNTR2 interrupt source selection bit 5 INT2/I2C interrupt source selection bit 6 CNTR1/Serial I/O3 receive interrupt source selection bit 7 AD converter/Serial I/O3 transmit interrupt source selection bit 0 0 0 0 0 0 0 *1: Do not write 1 to these bits simultaneously. *2: Do not write 1 to these bits simultaneously. Fig. 2.4.11 Structure of Interrupt source selection register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-53 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1 : address 003C16) b Name Functions At reset R W 0 0 0 0 ✽ ✽ ✽ ✽ 0 INT0/Timer Z 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 1 INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 2 Serial I/O1 receive 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 0 : No interrupt request issued 3 Serial I/O1 transmit/SCL, SDA 1 : Interrupt request issued interrupt request bit 4 Timer X interrupt request bit 5 Timer Y interrupt request bit 6 Timer 1 interrupt request bit 0 : No interrupt request issued 0 0 0 0 ✽ ✽ ✽ ✽ 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 7 Timer 2 interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: 0 can be set by software, but 1 cannot be set. Fig. 2.4.12 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2 : address 003D16) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 ✽ ✽ 0 CNTR0/SCL, SDA interrupt request bit 1 CNTR1/Serial I/O3 receive interrupt request bit 2 Serial I/O2/Timer Z interrupt request bit 3 INT2/I2C interrupt request bit 4 INT3 interrupt request bit 5 INT4/CNTR2 interrupt request bit 6 AD converter/Serial I/O3 transmit interrupt request bit 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . ✽: 0 can be set by software, but 1 cannot be set. 0 Fig. 2.4.13 Structure of Interrupt request register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-54 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1 : address 003E16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 INT0/Timer Z interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O1 receive interrupt enable bit 3 Serial I/O1 transmit/SCL, SDA interrupt enable bit 4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit 0 0 0 0 Fig. 2.4.14 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2 : address 003F16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 CNTR0/SCL, SDA interrupt enable bit 1 CNTR1/ Serial I/O3 receive interrupt enable bit 2 Serial I/O2/ Timer Z interrupt enable bit 3 INT2/I2C interrupt enable bit 4 INT3 interrupt enable bit 5 INT4/CNTR2 interrupt enable bit 6 AD converter/Serial I/O3 transmit interrupt enable bit 7 Fix this bit to “0”. 0 0 0 0 0 0 Fig. 2.4.15 Structure of Interrupt control register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-55 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface 2.4.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.4.16 shows connection examples of a peripheral IC equipped with the CS pin. There are connection examples using a clock synchronous serial I/O mode. (1) Only transmission (Using the RXDi pin as an I/O port) Port SCLKi TXDi CS CLK DATA (2) Transmission and reception Port SCLKi TXDi RXDi 3804 group (Spec. H) CS CLK IN OUT Peripheral IC 2 (E PROM etc.) 3804 group Peripheral IC (Spec. H) (OSD controller etc.) (3) Transmission and reception (When connecting RXDi with TXDi) (When connecting IN with OUT in peripheral IC) Port SCLKi TXDi RXDi CS CLK IN (4) Connection of plural IC Port SCLKi TXDi R XD i Port 3804 group (Spec. H) CS CLK IN OUT Peripheral IC 1 OUT 3804 group ✽1 Peripheral IC ✽2 2 (Spec. H) (E PROM etc.) CS CLK IN OUT Peripheral IC 2 ✽1: Select an N-channel open-drain output for TXDi pin output control. ✽2: Use the OUT pin of peripheral IC which is an N-channel opendrain output and becomes high impedance during receiving data. Notes 1: “Port” means an output port controlled by software. 2: Use SOUT2 and SIN2 instead of TxDi and RxDi for the serial I/O2. (i = 1, 3) Fig. 2.4.16 Serial I/O connection examples (1) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-56 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface (2) Connection with microcomputer Figure 2.4.17 shows connection examples with another microcomputer. (1) Selecting internal clock SCLKi TXDi RXDi 3804 group (Spec. H) CLK IN OUT Microcomputer (2) Selecting external clock SCLKi TXDi R XD i 3804 group (Spec. H) CLK IN OUT Microcomputer (3) Using SRDYi signal output function (Selecting an external clock) SRDYi (4) In UART ✽ RDY CLK IN OUT Microcomputer TXDi R XD i 3804 group (Spec. H) R XD TXD Microcomputer SCLKi TXDi RXDi 3804 group (Spec. H) ✽ UART cannot be used for serial I/O2. Note: Use SOUT2 and SIN2 instead of TxDi and RxDi for the serial I/O2. (i = 1, 3) Fig. 2.4.17 Serial I/O connection examples (2) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-57 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface 2.4.4 Setting of serial I/O transfer data format A clock synchronous or clock asynchronous (UART) can be selected as a data format of serial I/O1 and serial I/O3. Serial I/O2 operates in a clock synchronous. Figure 2.4.18 shows the serial I/O transfer data format. 1ST-8DATA-1SP ST LSB MSB SP 1ST-7DATA-1SP ST LSB MSB SP 1ST-8DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-7DATA-1PAR-1SP ST LSB MSB PAR SP UART 1ST-8DATA-2SP ST LSB MSB 2SP 1ST-7DATA-2SP ST LSB MSB 2SP Serial I/O1 Serial I/O3 1ST-8DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-7DATA-1PAR-2SP ST LSB MSB PAR 2SP Clock synchronous Serial I/O LSB first Serial I/O2 Clock synchronous Serial I/O LSB first MSB first ST : Start bit SP : Stop bit PAR : Parity bit Fig. 2.4.18 Serial I/O transfer data format Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-58 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface 2.4.5 Serial I/O1, serial I/O3 operation: stop and initialize Serial I/O1 and serial I/O3 perform the same operation. In the following explanations when names of serial I/O1 and serial I/O3 are different, serial I/O1s' are showed first and then serial I/O3s' in the marked ( ). (1) Clock synchronous serial I/O mode s Stop/initialize transmit operation when only transmitting When using an internal clock, set the transmit enable bit and serial I/O1 enable bit (serial I/O3 enable bit) to “ 0 ” . When using an external clock, set the transmit enable bit to “ 0 ” . By setting the transmit enable bit to “ 0 ” , the transmit operations listed below will be stopped or initialized. However, when using an internal clock, the clock is output in 8 pulses, even if the transmit enable bit is set to “ 0 ” d uring transmit operations. • Stop supply of shift clock to transmit shift register • Initialize clock control circuit for transmit • Transmit buffer empty flag = “ 0 ” • Transmit shift register shift complete flag = “ 0 ” • P4 5/TxD 1 p in: input/output port P4 5 ( P35/TxD3 p in: input/output port P35) By setting the serial I/O1 enable bit (serial I/O3 enable bit) to “ 0 ” , pins P4 4/RxD1, P4 5/TxD1, P46/ S CLK1, and P4 7/S RDY1 ( P3 4/RxD 3, P3 5/TxD 3, P3 6/S CLK3 , P3 7/S RDY3 p ins) all become I/O ports. As a result, the internal clock cannot be output externally. s Stop/initialize receive operation when only receiving When using an internal clock, set the receive enable bit and serial I/O1 enable bit (serial I/O3 enable bit) to “ 0 ” . When using an external clock, set the receive enable bit or serial I/O1 enable bit (serial I/O3 enable bit) to “ 0 ” . By setting the receive enable bit to “ 0 ” , the receive operations listed below will be stopped or initialized. However, when using an internal clock, the clock is output in 8 pulses, even if the receive enable bit is set to “ 0 ” d uring receive operations. • Stop supply of shift clock to receive shift register • Initialize clock control circuit for receive • Error flags (over-run, parity, framing, and summing error flags) = “ 0 ” • Receive buffer full flag = “ 0 ” • P4 4/RxD 1 p in: input/output port P4 4 ( P3 4/RxD 3 p in: input/output port P34) By setting the serial I/O1 enable bit (serial I/O3 enable bit) to “ 0 ” , the receive operations listed below will be stopped or initialized. As a result, the internal clock cannot be output externally. • Stop supply of shift clock to receive shift register • Initialize clock control circuit for receive • Error flags (over-run, parity, framing, and summing error flags) = “ 0 ” • Receive buffer full flag = “ 0 ” • P44/RxD1, P4 5/TxD 1, P4 6/S CLK1, P4 7/S RDY1 p ins: I/O ports P44, P4 5, P4 6, P4 7 ( P34/RxD 3, P3 5/TxD3, P3 6/S CLK3, P3 7/SRDY3 p ins: I/O ports P3 4, P3 5, P36, P3 7) s Stop/initialize receive/transmit operation when both receiving and transmitting Set the transmit enable bit and receive enable bit to “ 0 ” s imultaneously. When using an internal clock, also set the serial I/O1 enable bit (serial I/O3 enable bit) to “ 0 ” . (2) UART Mode s Stop/initialize transmit operation Set the transmit enable bit to “ 0 ” . s Stop/initialize receive operation Set the receive enable bit to “ 0 ” . Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-59 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface 2.4.6 Serial I/O pin function and selection method (1) Serial I/O1, serial I/O3 Table 2.4.1 shows the pin function in the clock synchronous serial I/O mode, Table 2.4.2 shows the pin function in the UART mode. Table 2.4.1 Pin function in clock synchronous serial I/O mode Serial I/O1 control register (address 001A16) Serial I/O3 control register (address 003216) Pin name (Serial I/O1) Pin name (Serial I/O3) Function (No te 1) b7 b6 b5 RE 1 0 ✕ ✕ ✕ ✕ 1 ✕ b4 TE 1 ✕ 1 0 1 1 1 ✕ b3 T IC ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ b2 SRDY ✕ ✕ ✕ ✕ ✕ ✕ 1 0 b1 SCS ✕ ✕ ✕ ✕ 1 0 ✕ ✕ SIOE SIOM RxD1, RxD3 P44/RxD1 P34/RxD3 P44, P34 TxD1, TxD3 P45, P35 SCLK1 (External clock input) P46/SCLK1 (Note 2) Corresponding direction CSS register b0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0/1 ✕ 0/1 ✕ ✕ ✕ 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P45/TxD1 P35/TxD3 P36/SCLK3 SCLK1 (Internal clock output) SRDY1, SRDY3 P47/SRDY1 /CNTR2 P37/SRDY3 P47, P37 Note 1: When SIOE is set to “0”, all pins become I/O ports regardless of set value of b6–b0. Note 2: In the pulse output mode, the programmable waveform generating mode, or the programmable one-shot generating mode of the timer Z, this pin functions as the timer Z function output pin regardless of b7-b0 setting. ✕: This is not used for the pin’s function setting. Table 2.4.2 Pin function in UART mode Serial I/O1 control register (address 001A16) Pin name (Serial I/O1) Pin name (Serial I/O3) RxD P44/RxD1 P34/RxD3 P44 TxD P45/TxD1 P35/TxD3 P45 SCLK1 (External clock input) P46/SCLK1 (Note 2) Function (No te 1) b7 b6 SIOM 0 0 0 0 0 0 0 b5 RE 1 0 ✕ ✕ ✕ ✕ ✕ b4 TE ✕ ✕ 1 0 ✕ ✕ ✕ b3 TIC ✕ ✕ ✕ ✕ ✕ ✕ ✕ b2 SRDY ✕ ✕ ✕ ✕ ✕ ✕ ✕ b1 SCS ✕ ✕ ✕ ✕ 1 0 ✕ SIOE 1 1 1 1 1 1 1 Corresponding direction CSS register b0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0/1 ✕ 0/1 ✕ 0/1 0/1 P36/SCLK3 P46 P47 P47/SRDY1 /CNTR2 P37/SRDY3 Note 1: When SIOE is set to “0”, all pins become I/O ports regardless of set value of b6–b0. Note 2: In the pulse output mode, the programmable waveform generating mode, or the programmable one-shot generating mode of the timer Z, this pin functions as the timer Z function output pin regardless of b7-b0 setting. ✕: This is not used for the pin’s function setting. (2) Serial I/O2 Table 2.4.3 shows the pin function in the clock synchronous serial I/O mode. Table 2.4.3 Pin function in clock synchronous serial I/O mode Serial I/O2 control register (address 001D16) Pin name SIN2 P50 SOUT2 P51 SCLK2 (External clock input) P52/SCLK2 SCLK2 (Internal clock output) P52 P53/SRDY2 SRDY2 P53 (Note 2) C orrespo nding d irection register Function (Note 1) b7 ✕ ✕ b6 ✕ ✕ ✕ ✕ ✕ 0 1 ✕ ✕ ✕ b5 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ b4 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 1 0 b3 1 ✕ 1 1 0 1 1 0 ✕ ✕ b2 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ b1 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ b0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ P50/SIN2 0 0/1 ✕ ✕ 0/1 ✕ ✕ 0/1 ✕ 0/1 CMOS output N-channel open-drain output 0 1 (No te 3) P51/SOUT2 ✕ ✕ ✕ ✕ ✕ Notes 1: Although this pin functions as SIN2 when b3 is set to “0”, set “1” to b3. Notes 2: Although this pin functions as SCLK2 when b3 and the corresponding direction register are set to “0”, set “1” to b3. Notes 3: When the corresponding direction register bit is "1", the b7 setting is valid. ✕: This is not used for the pin’s function setting. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-60 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface 2.4.7 Serial I/O application examples (1) Communication using clock synchronous serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O. The SRDY1 s ignal is used for communication control. Figure 2.4.19 shows a connection diagram, and Figure 2.4.20 shows a timing chart. Figure 2.4.21 shows a registers setting relevant to the transmitting side, and Figure 2.4.22 shows registers setting relevant to the receiving side. Transmitting side Receiving side P42/INT1 SRDY1 SCLK1 TXD1 3804 group (Spec. H) SCLK1 R XD 1 3804 group (Spec. H) Note: Use SOUT2 and SIN2 instead of TxDi and RxDi for the serial I/O2. (i = 1, 3) Fig. 2.4.19 Connection diagram Specifications : • • • • Serial I/O is used (clock synchronous serial I/O is selected.) Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32) SRDY1 ( receivable signal) is used. The receiving side outputs SRDY1 signal at intervals of 2 ms (generated by timer), and 2-byte data is transferred from the transmitting side to the receiving side. SRDY1 SCLK1 .... .... TXD D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 .... 2 ms Fig. 2.4.20 Timing chart (using clock synchronous serial I/O) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-61 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Transmitting side Port P4 direction register (Address : 000916) b7 b0 P4D 0 Port P42/INT1: Input mode Serial I/O1 status register (Address : 001916) b7 b0 SIO1STS Transmit buffer empty flag • Confirm that the data has been transferred from Transmit buffer register to Transmit shift register. • When this flag is “1”, it is possible to write the next transmission data in to Transmit buffer register. Transmit shift register shift completion flag Confirm completion of transmitting 1-byte data with this flag. “1” : Transmit shift completed Serial I/O1 control register (Address : 001A16) b7 b0 SIO1CON 1101 00 BRG count source : f(XIN) Serial I/O1 synchronous clock : BRG/4 Transmit enabled Receive disabled Clock synchronous serial I/O Serial I/O1 enabled Baud rate generator 1 (Address : 001C16) b7 b0 BRG1 8–1 Set “division ratio – 1” Interrupt edge selection register (Address : 003A16) b7 b0 INTEDGE 0 INT1 falling edge active Fig. 2.4.21 Registers setting relevant to transmitting side Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-62 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Receiving side Serial I/O1 status register (Address : 001916) b7 b0 SIO1STS Receive buffer full flag Confirm completion of receiving 1-byte data with this flag. “1” : at completing reception “0” : at reading out contents of Receive buffer register Overrun error flag “1” : When data is ready in Receive shift register while Receive buffer register contains the data. Parity error flag “1” : When a parity error occurs in enabled parity. Framing error flag “1” : When stop bits cannot be detected at the specified timing Summing error flag “1” : when any one of the following errors occurs. • Overrun error • Parity error • Framing error Serial I/O1 control register (Address : 001A16) b7 b0 SIO1CON 1111 11 Serial I/O1 synchronous clock : External clock SRDY1 output enabled Transmit enabled Set this bit to “1”, using SRDY1 output. Receive enabled Clock synchronous serial I/O Serial I/O1 enabled Fig. 2.4.22 Registers setting relevant to receiving side Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-63 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Figure 2.4.23 shows a control procedure of the transmitting side, and Figure 2.4.24 shows a control procedure of the receiving side. RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SIO1CON (Address : 001A16) 1101xx002 (Address : 001C16) 8–1 BRG1 0 INTEDGE (Address : 003A16), bit1 ... .. IREQ1 (Address: 003C16), bit1? 1 IREQ1 (Address : 003C16), bit1 0 0 • Detection of INT1 falling edge TB1/RB1 (Address : 001816) The first byte of a transmission data • Transmission data write Transmit buffer empty flag is set to “0” by this writing. SIO1STS (Address : 001916), bit0? 1 TB1/RB1 (Address : 001816) 0 • Judgment of transferring from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) • Transmission data write Transmit buffer empty flag is set to “0” by this writing. The second byte of a transmission data SIO1STS (Address : 001916), bit0? 1 0 • Judgment of transferring from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) SIO1STS (Address : 001916), bit2? 1 0 • Judgment of shift completion of Transmit shift register (Transmit shift register shift completion flag) Fig. 2.4.23 Control procedure of transmitting side Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-64 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SIO1CON (Address : 001A16) ... .. 1111x11x2 N Pass 2 ms? Y TB1/RB1 (Address : 001816) Dummy data • SRDY1 output SRDY1 signal is outpu t by writing data to the TB1/RB1. Using the SRDY1, set Transmit enable bit (bit 4) of the SIO1CON to “1”. • Judgment of completion of receiving (Receive buffer full flag) • An interval of 2 ms generated by Timer. 0 SIO1STS (Address : 001916), bit1? 1 Read out reception data from TB1/RB1 (Address : 001816) • Reception of the first byte data. Receive buffer full flag is set to “0” by reading data. 0 SIO1STS (Address : 001916), bit1? 1 Read out reception data from TB1/RB1 (Address : 001816) • Reception of the second byte data. Receive buffer full flag is set to “0” by reading data. • Judegment of completion of receiving (Receive buffer full flag) Fig. 2.4.24 Control procedure of receiving side Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-65 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface (2) Output of serial data (control of peripheral IC) Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O. The CS signal is output to a peripheral IC through port P6 3. Figure 2.4.25 shows connection diagrams of example for using serial I/O1 and example for using serial I/O2 with the same specification, and Figure 2.4.26 shows a timing chart. P63 SCLK1 TXD1 CS CLK DATA CS CLK DATA P63 SCLK2 SOUT2 CS CLK DATA CS CLK DATA 3804 group (Spec. H) Peripheral IC 3804 group (Spec. H) Peripheral IC (1) Example for using Serial I/O1 (2) Example for using Serial I/O2 Fig. 2.4.25 Connection diagrams Specifications : • Serial I/O is used (clock synchronous serial I/O is selected.) • Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32) • Transfer direction : LSB first • The Serial I/O interrupt is not used. • Port P63 is connected to the CS pin (“L” active) of the peripheral IC for transmission control; the output level of port P63 i s controlled by software. CS CLK DATA DO0 DO1 DO2 DO3 Note: When using serial I/O2, the SOUT2 pin becomes the high-impedance state after transfer is completed. Fig. 2.4.26 Timing chart (serial I/O1) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-66 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Figure 2.4.27 shows registers setting relevant to serial I/O1, and Figure 2.4.28 shows a setting of serial I/O1 transmission data. Serial I/O1 control register (Address : 001A16) b7 b0 SIO1CON 11011000 BRG count source : f(XIN) Serial I/O1 synchronous clock : BRG/4 SRDY1 output disabled Transmit interrupt source : Transmit shift operating completion Transmit enabled Receive disabled Clock synchronous serial I/O Serial I/O1 enabled UART1 control register (Address : 001B16) b7 b0 UART1CON 0 P45/TXD1 pin : CMOS output Baud rate generator 1 (Address : 001C16) b7 b0 BRG1 8 –1 b7 b0 Set “division ratio – 1” Interrupt control register 1 (Address : 003E16) ICON1 0 Serial I/O1 transmit interrupt : Disabled Interrupt request register 1 (Address : 003C16) b7 b0 IREQ1 0 Serial I/O1 transmit interrupt request Confirm completion of transmitting 1-byte data by one unit. “1” : Transmit shift completion Port P6 (Address : 000C16) b7 b0 P6 1 Port P63: CS signal to peripheral ICs "L" active Port P6 direction register (Address : 000D16) b7 b0 P6D 1 Port P63: Output mode Fig. 2.4.27 Registers setting relevant to serial I/O1 Transmit/Receive buffer register 1 (Address : 001816) b7 b0 TB1/RB1 Set a transmission data. Confirm that transmission of the previous data is completed (bit 3 of the Interrupt request register 1 is “1”) before writing data. Fig. 2.4.28 Setting of serial I/O1 transmission data Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-67 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface When the registers are set as shown in Fig. 2.4.27, serial I/O1 can transmit 1-byte data by writing data to the transmit buffer register. Thus, after setting the CS signal to “L”, write the transmission data to the transmit buffer register by each 1 byte, and return the CS signal to “H” when the target number of bytes has been transmitted. Figure 2.4.29 shows a control procedure of serial I/O1. RESET q X: This bi t is not used here. Set it to “0” or “1” arbitrarily. q Initialization SIO1CON (Address : 001A16) 110110002 0 UART1CON(Address : 001B16), bit4 8–1 BRG1 (Address : 001C16) 0 ICON1 (Address : 003E16), bit3 1 P6 (Address : 000C16), bit3 P6D (Address : 000D16) XXXX1XXX2 .... .... • Serial I/O1 setting • Serial I/O1 transmit interrupt : Disabled • CS signal output port setting (“H” level output) P6 (Address : 000C16), bit3 0 • CS signal output level to “L” setting IREQ1 (Address : 003C16), bit3 0 • Serial I/O1 transmit interrupt request bit to “0” setting TB1/RB1 (Address : 001816) a transmission data • Transmission data write (Start of transmit 1-byte data) IREQ1 (Address : 003C16), bit3? 1 0 • Judgment of completion of transmitting 1-byte data N Complete to transmit data? Y • Use any of RAM area as a counter for counting the number of transmitted bytes • Judgment of completion of transmitting the target number of bytes P6 (Address : 000C16), bit3 1 • Returning CS signal output level to “H” when transmission of the target number of bytes is completed Fig. 2.4.29 Control procedure of serial I/O1 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-68 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Figure 2.4.30 shows registers setting relevant to serial I/O2, and Figure 2.4.31 shows a setting of serial I/O2 transmission data. Serial I/O2 control register (Address : 001D16) b7 b0 SIO2CON 1001010 Synchronous clock : f(XIN)/32 Serial I/O2 used SRDY2 output disabled LSB first Internal clock Interrupt source selection register (Address : 003916) b7 b0 INTSEL 0 Serial I/O2/timer Z interrupt source selection : Serial I/O2 interrupt Interrupt control register 2 (Address : 003F16) b7 b0 ICON2 0 Serial I/O2 interrupt : Interrupt disabled Interrupt request register 2 (Address : 003D16) b7 b0 IREQ2 0 Serial I/O2 interrupt request Confirm completion of transmitting 1-byte data by one unit. “1” : Transmit shift completion Port P6 (Address : 000C16) b7 b0 P6 1 Port P63: CS signal to peripheral ICs "L" active Port P6 direction register (Address : 000D16) b7 b0 P6D 1 Port P63: Output mode Fig. 2.4.30 Registers setting relevant to serial I/O2 Serial I/O2 register (Address : 001F16) b7 b0 SIO2 Set a transmission data. Confirm that transmission of the previous data is completed (bit 2 of the Interrupt request register 2 is “1”) before writing data. Fig. 2.4.31 Setting of serial I/O2 transmission data Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-69 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface When the registers are set as shown in Fig. 2.4.30, serial I/O2 can transmit 1-byte data by writing data to the serial I/O2 register. Thus, after setting the CS signal to “L”, write the transmission data to the serial I/O2 register by each 1 byte, and return the CS signal to “H” when the target number of bytes has been transmitted. Figure 2.4.32 shows a control procedure of serial I/O2. RESET q X: This bi t is not used here. Set it to “0” or “1” arbitrarily. q Initialization SIO2CON (Address : 001D16) 010010102 INTSEL (Address : 003916) XXXXXX0X2 ICON2 (Address : 003F16), bit2 0 P6 (Address : 000C16), bit3 1 P6D (Address : 000D16) XXXX1XXX2 .... .... • Serial I/O2 control register setting • Serial I/O2 interrupt : Disabled • CS signal output port setting (“H” level output) P6 (Address : 000C16), bit3 0 • CS signal output level to “L” setting IREQ2 (Address : 003D16), bit2 0 • Serial I/O2 interrupt request bit to “0” setting SIO2 (Address : 001F16) a transmission data • Transmission data write (Start of transmit 1-byte data) IREQ2 (Address : 003D16), bit2? 1 0 • Judgment of completion of transmitting 1-byte data N Complete to transmit data? Y • Use any of RAM area as a counter for counting the number of transmitted bytes. • Judgment of completion of transmitting the target number of bytes P6 (Address : 000C16), bit3 1 • Returning CS signal output level to “H” when transmission of the target number of bytes is completed Fig. 2.4.32 Control procedure of serial I/O2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-70 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface (3) Cyclic transmission or reception of block data (data of specified number of bytes) between two microcomputers Outline : When the clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronous clock. It is necessary to correct that constantly, using “heading adjustment”. This “ heading adjustment ” i s carried out by using the interval between blocks in this example. This example is described for serial I/O1, but this example also can apply serial I/O3. Figure 2.4.33 shows connection diagram. SCLK1 RXD1 TXD1 Master unit SCLK1 TXD1 RXD1 Slave unit Note: Use SOUT2 and SIN2 instead of TxD1 and RxD1 for serial I/O2. Fig. 2.4.33 Connection diagram Specifications : • • • • • • • • S erial I/O is used (clock synchronous serial I/O is selected). S ynchronous clock frequency : 131 kHz (f(X IN) = 4.19 MHz is divided by 32) B yte cycle: 488 µ s N umber of bytes for transmission or reception : 8 byte/block B lock transfer cycle : 16 ms B lock transfer term : 3.5 ms I nterval between blocks : 12.5 ms H eading adjustment time : 8 ms Limitations of the specifications : • Reading of the reception data and setting of the next transmission data must be completed within the time obtained from “byte cycle – time for transferring 1-byte data ” ( in this example, the time taken from generating of the serial I/O1 receive interrupt request to input of the next synchronous clock is 431 µs). • “ Heading adjustment time < interval between blocks ” m ust be satisfied. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-71 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface The communication is performed according to the timing shown in Figure 2.4.34. In the slave unit, when a synchronous clock is not input within a certain time (heading adjustment time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 byte) is received, the clock is ignored. Figure 2.4.35 shows relevant registers setting. D0 D1 D2 D7 D0 Byte cycle Block transfer term Block transfer cycle Heading adjustment time Interval between blocks Processing for heading adjustment Fig. 2.4.34 Timing chart Master unit Serial I/O1 control register (Address : 001A16) b7 b0 SIO1CON 1 1 1 1 1 0 0 0 BRG count source : f(XIN) Synchronous clock : BRG/4 SRDY1 output disabled Transmit interrupt source : Transmit shift operating completion Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O1 enabled Slave unit Serial I/O1 control register (Address : 001A16) b7 b0 SIO1CON 1 1 1 1 01 Not be affected by external clock Synchronous clock : External clock SRDY1 output disabled Not use the serial I/O1 transmit interrupt Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O1 enabled Both of units UART1 control register (Address : 001B16) b7 b0 UART1CON 0 P45/TXD1 pin : CMOS output Baud rate generator 1 (Address : 001C16) b7 b0 BRG1 8–1 Set “division ratio – 1” Fig. 2.4.35 Relevant registers setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-72 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Control procedure : q Control in the master unit After setting the relevant registers shown in Figure 2.4.35, the master unit starts transmission or reception of 1-byte data by writing transmission data to the transmit buffer register. To perform the communication in the timing shown in Figure 2.4.34, take the timing into account and write transmission data. Additionally, read out the reception data when the serial I/O1 transmit interrupt request bit is set to “ 1, ” o r before the next transmission data is written to the transmit buffer register. Figure 2.4.36 shows a control procedure of the master unit using timer interrupts. Interrupt processing routine executed every 488µs CLT (Note 1) CLD (Note 2) Push register to stack q Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack. Within a block transfer period? Y Read a reception data N q Generate a certain block interval by using a timer or other functions. q Count a block interval counter Check the block interval counter and determine to start a block transfer. Complete to transfer a block? N Write a transmission data Y Start a block transfer? Y Write the first transmission data (first byte) in a block N Pop registers q Pop registers which is pushed to stack. RTI Fig. 2.4.36 Control procedure of master unit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-73 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface q Control in the slave unit After setting the relevant registers as shown in Figure 2.4.35, the slave unit becomes the state where a synchronous clock can be received at any time, and the serial I/O1 receive interrupt occurs each time an 8-bit synchronous clock is received. In the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to the transmit buffer register after the received data is read out. However, if no serial I/O1 receive interrupt occurs for a certain time (heading adjustment time or more), the following processing will be performed. 1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register. 2. The data to be received next is processed as the first 1 byte of the received data in the block. Figure 2.4.37 shows a control procedure of the slave unit using the serial I/O1 receive interrupt and any timer interrupt (for heading adjustment). Serial I/O1 receive interrupt processing routine Timer interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack Within a block transfer term? Y Read a reception data • Push the register used in the interrupt processing routine into the stack. • Confirm the received byte counter to judge N the block transfer term. CLT (Note 1) CLD (Note 2) Push register to stack • Push the register used in the interrupt processing routine into the stack. Heading adjustment counter – 1 Heading adjustment counter = 0? Y N A received byte counter +1 Write the first transmission data (first byte) in a block A received byte counter ≥ 8? N Y A received byte counter 0 Pop registers Write a transmission data Write dummy data (FF16) RTI Heading adjustment counter Initial value (Note 3) • Pop registers which is pushed to stack. • Pop registers which is pushed to stack. Pop registers RTI Notes 1: When using the Index X mode flag (T). 2: When using the Decimal mode flag (D). 3: In this example, set the value which is equal to the heading adjustment time divided by the timer interrupt cycle as the initial value of the heading adjustment counter. For example: When the heading adjustment time is 8 ms and the timer interrupt cycle is 1 ms, set 8 as the initial value. Fig. 2.4.37 Control procedure of slave unit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-74 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface (4) Communication (transmit/receive) using asynchronous serial I/O (UART) Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O. Port P4 0 i s used for communication control. Figure 2.4.38 shows a connection diagram, and Figure 2.4.39 shows a timing chart. Transmitting side P40 Receiving side P40 TXD RXD 3804 group (Spec. H) 3804 group (Spec. H) Fig. 2.4.38 Connection diagram (Communication using UART) Specifications : • Serial I/O1 is used (UART is selected). • Transfer bit rate : 9600 bps (f(X IN) = 4.9152 MHz is divided by 512) • Communication control using port P40 (The output level of port P40 i s controlled by software.) • 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms generated by the timer. P40 •••• TXD1 ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 •••• 10 ms Fig. 2.4.39 Timing chart (using UART) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-75 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Table 2.4.4 shows setting examples of the baud rate generator (BRG) values and transfer bit rate values; Figure 2.4.40 shows registers setting relevant to the transmitting side; Figure 2.4.41 shows registers setting relevant to the receiving side. Table 2.4.4 Setting examples of Baud rate generator (BRG) values and transfer bit rate values BRG count source (Note 1) f(X IN)/4 f(X IN)/4 f(X IN)/4 f(X IN)/4 f(X IN)/4 f(X IN)/4 f(X IN)/4 f(X IN)/4 f(X IN) f(X IN) f(X IN) BRG setting value 255(FF16) 127(7F 16) 63(3F16) 31(1F16) 15(0F16) 7(0716) 3(0316) 1(0116) 3(0316) 1(0116) 0(0016) Transfer bit rate (bps) ( Note 2) at f(X IN) = 4.9152 MH Z at f(X IN ) = 16 MH Z 300 600 1200 2400 4800 9600 19200 38400 76800 153600 307200 976.5625 1953.125 3906.25 7812.5 15625 31250 62500 125000 250000 500000 1000000 Notes 1: S elect the BRG count source with bit 0 of the serial I/O1 control register (Address : 001A 16). 2: E quation of transfer bit rate: Transfer bit rate (bps) = f(XIN) (BRG setting value + 1) ✕ 16 ✕ m ✽ ✽ m: When bit 0 of the serial I/O1 control register (Address : 001A 16) is set to “ 0, ” a v alue of m is 1. When bit 0 of the serial I/O1 control register (Address : 001A 16) is set to “ 1, ” a v alue of m is 4. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-76 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Transmitting side Serial I/O1 status register (Address : 001916) b7 b0 SIO1STS Transmit buffer empty flag • Confirm that the data has been transferred from Transmit buffer register to Transmit shift register. • When this flag is “1”, it is possible to write the next transmission data in to Transmit buffer register. Transmit shift register shift completion flag Confirm completion of transmitting 1-byte data with this flag. “1” : Transmit shift completed Serial I/O1 control register (Address : 001A16) b7 b0 SIO1CON 1 0 0 1 001 BRG count source : f(XIN)/4 Synchronous clock : BRG/16 SRDY1 output disabled Transmit enabled Receive disabled Asynchronous serial I/O(UART) Serial I/O1 enabled UART1 control register (Address : 001B16) b7 b0 UART1CON 01 00 Character length : 8 bits Parity checking disabled Stop bit length : 2 stop bits P45/TXD1 pin : CMOS output Baud rate generator 1 (Address : 001C16) b7 b0 BRG1 8–1 Set f(XIN) Transfer bit rate ✕ 16 ✕ m ✽ –1 ✽ When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “0,” a value of m is 1. When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “1,” a value of m is 4. Port P4 (Address : 000816) b7 b0 P4 0 Port P40: Communication control: “H” active Port P4 direction register (Address : 000916) b7 b0 P4D 1 Port P40: Communication control: Output mode Fig. 2.4.40 Registers setting relevant to transmitting side Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-77 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Receiving side Serial I/O1 status register (Address : 001916) b7 b0 SIO1STS Receive buffer full flag Confirm completion of receiving 1-byte data with this flag. “1” : at completing reception “0” : at reading out contents of Receive buffer register Overrun error flag “1” : When data is ready in Receive shift register while Receive buffer register contains the data. Parity error flag “1” : When a parity error occurs in enabled parity. Framing error flag “1” : When stop bits cannot be detected at the specified timing Summing error flag “1” : when any one of the following errors occurs. • Overrun error • Parity error • Framing error Serial I/O1 control register (Address : 001A16) b7 b0 SIO1CON 1010 001 BRG count source : f(XIN)/4 Synchronous clock : BRG/16 SRDY1 output disabled Transmit disabled Receive enabled Asynchronous serial I/O(UART) Serial I/O1 enabled UART1 control register (Address : 001B16) b7 b0 UART1CON 1 0 0 Character length : 8 bits Parity checking disabled Stop bit length : 2 stop bits Baud rate generator 1 (Address : 001C16) b7 b0 BRG1 8–1 Set f(XIN) Transfer bit rate ✕ 16 ✕ m ✽ –1 ✽ When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “0,” a value of m is 1. When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “1,” a value of m is 4. Port P4 direction register (Address : 000916) b7 b0 P4D 0 Port P40: Communication control: Input mode Fig. 2.4.41 Registers setting relevant to receiving side Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-78 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface Figure 2.4.42 shows a control procedure of the transmitting side, and Figure 2.4.43 shows a control procedure of the receiving side. RESET q X: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SIO1CON (Address : 001A16) 1001X0012 UART1CON (Address : 001B16) 000010002 BRG1 (Address : 001C16) 8–1 0 P4 (Address : 000816), bit0 P4D (Address : 000916) XXXXXXX12 ... .. • Port P40 set for communication control Pass 10 ms? Y P4 (Address : 000816), bit0 TB1/RB1 (Address : 001816) 1 N • An interval of 10 ms generated by Timer • Communication start • Transmission data write Transmit buffer empty flag is set to “0” by this writing. • Judgment of transferring data from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) The first byte of a transmission data SIO1STS (Address : 001916), bit0? 1 TB1/RB1 (Address : 001816) The second byte of a transmission data 0 • Transmission data write Transmit buffer empty flag is set to “0” by this writing. • Judgment of transferring data from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) SIO1STS (Address : 001916), bit0? 1 0 SIO1STS (Address : 001916), bit2? 1 0 • Judgment of shift completion of Transmit shift register (Transmit shift register shift completion flag) P4 (Address : 000816), bit0 0 • Communication completion Fig. 2.4.42 Control procedure of transmitting side Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-79 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface RESET Initialization SIO1CON (Address : 001A16) UART1CON (Address : 001B16) BRG1 (Address : 001C16) P4D (Address : 000916) ... .. q X: This bit is not used here. Set it to “0” or “1” arbitrarily. 1010X0012 000010002 8–1 XXXXXXX02 SIO1STS (Address : 001916), bit1? 1 0 • Judgment of completion of receiving (Receive buffer full flag) • Reception of the first byte data Receive buffer full flag is set to “0” by reading data. Read out a reception data from RB1 (Address : 001816) SIO1STS (Address : 001916), bit6? 0 1 • Judgment of an error flag SIO1STS (Address : 001916), bit1? 1 0 • Judgment of completion of receiving (Receive buffer full flag) • Reception of the second byte data Receive buffer full flag is set to “0” by reading data. Read out a reception data from RB1 (Address : 001816) SIO1STS (Address : 001916), bit6? 0 1 • Judgment of an error flag Processing for error 1 P4 (Address : 000816), bit0? 0 SIO1CON (Address : 001A16) SIO1CON (Address : 001A16) 0000X0012 1010X0012 • Countermeasure for a bit slippage Fig. 2.4.43 Control procedure of receiving side Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-80 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface 2.4.8 Notes on serial interface (1) Notes when selecting clock synchronous serial I/O ➀ Stop of transmission operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and transmit disabled). q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled), the internal transmission is running (in this case, since pins TxDi, RxDi, S CLKi, and S RDYi function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/Oi enable bit is set to “ 1 ” a t this time, the data during internally shifting is output to the TxDi pin and an operation failure occurs. ➁ Stop of receive operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the receive enable bit to “ 0 ” ( receive disabled), or clear the serial I/Oi enable bit to “ 0 ” ( serial I/Oi disabled). ➂ Stop of transmit/receive operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear both the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive disabled) in the clock synchronous serial I/O mode. (When data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) q Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “ 0 ” ( transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/Oi enable bit to “0” (serial I/Oi disabled) (refer to ➀ i n (1) ). (2) Notes when selecting clock asynchronous serial I/O ➀ Stop of transmission operation Clear the transmit enable bit to “ 0 ” ( transmit disabled). Transmission operation does not stop by setting the serial I/Oi enable bit (i = 1, 3) to “ 0 ” . q Reason This is the same as ➀ i n (1). ➁ Stop of receive operation Clear the receive enable bit to “ 0 ” ( receive disabled). Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-81 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface ➂ Stop of transmit/receive operation Only transmission operation is stopped. Clear the transmit enable bit to “ 0 ” ( transmit disabled). Transmission operation does not stop by setting the serial I/Oi enable bit (i = 1, 3) to “ 0 ” . q Reason This is the same as ➀ i n (1). Only receive operation is stopped. Clear the receive enable bit to “ 0 ” ( receive disabled). (3) S RDYi ( i = 1, 3) output of reception side When signals are output from the SRDYi pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDYi output enable bit, and the transmit enable bit to “ 1 ” ( transmit enabled). (4) Setting serial I/Oi (i = 1, 3) control register again Set the serial I/Oi control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “ 0. ” Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” ↓ Set the bits 0 to 3 and bit 6 of the serial I/Oi control register ↓ Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time Fig. 2.4.44 Sequence of setting serial I/Oi (i = 1, 3) control register again (5) Data transmission control with referring to transmit shift register completion flag After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “ 1 ” t o “ 0 ” w ith a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (6) Transmission control when external clock is selected When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLKi (i = 1, 3) input level. Also, write the transmit data to the transmit buffer register at “ H ” o f the S CLKi i nput level. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-82 APPLICATION 3804 Group (Spec.H) 2.4 Serial interface (7) Transmit interrupt request when transmit enable bit is set When the transmit interrupt is used, take the following sequence. ➀ S et the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “ 0 ” ( disabled). ➁ S et the tranasmit enable bit to “ 1 ” . ➂ S et the serial I/Oi transmit interrupt request bit (i = 1, 3) to “ 0 ” a fter 1 or more instruction has executed. ➃ S et the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “ 1 ” ( enabled). q Reason When the transmission enable bit is set to “ 1 ” , the transmit buffer empty flag and transmit shift register shift completion flag are also set to “ 1 ” . Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. (8) Writing to baud rate generator i (BRGi) (i = 1, 3) Write data to the baud rate generator i (BRGi) (i = 1, 3) while the transmission/reception operation is stopped. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-83 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface 2.5 Multi-master I2C-BUS interface The only 3804 group has functions of the multi-master I 2C-BUS interface. The multi-master I2C-BUS interface is a serial communication circuit, conforming to the Philips I2C-BUS data transfer format. This paragraph explains the I 2C-BUS overview and communication examples. 2.5.1 Memory map 001016 MISRG 001116 I2C data shift register (S0) 001216 I2C special mode status register (S3) 001316 I2C status register (S1) 001416 I2C control register (S1D) 001516 I2C clock control register (S2) 001616 I2C START/STOP condition control register (S2D) 001716 I2C special mode control register (S3D) 003916 Interrupt source selection register (INTSEL) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) 0FF716 0FF816 I2C slave address register 0 (S0D0) I2C slave address register 1 (S0D1) 0FF916 I2C slave address register 2 (S0D2) Fig. 2.5.1 Memory map of registers relevant to I 2C-BUS interface Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-84 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface 2.5.2 Relevant registers MISRG b7 b6 b5 b4 b3 b2 b1 b0 MISRG (MISRG: address 001016) b Name Functions At reset R W 0 0 Oscillation stabilizing 0: Automatically set (Note 1) time set after STP 1: Autimatically set disabled instruction released bit 1 Middle-speed mode 0: Not set automatically automatic switch set 1: Automatic switching enabled (Notes 2, 3) bit 2 Middle-speed mode 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles automatic switch wait time set bit 3 Middle-speed mode 0: Invalid 1: Automatic switch start automatic switch (Note 3) start bit (Depending on program) 4 Nothing is arranged for these bits. These are write disabled bits. When these bits are read 5 out, the contents are 0 . 6 7 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ Notes 1: 0116 is set to Timer 1, FF16 is set to Prescaler 12. 2: During operation in low-speed mode, it is possible automatically to switch to middle-speed mode owing to the rising of SCL/SDA. 3: When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (003B16) change. Fig. 2.5.2 Structure of MISRG I2C data shift register b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register (S0: address 001116) b Functions At reset R W 0 • 8-bit shift register to store receive data and 1 write transmit data. 2 3 4 5 6 7 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Note: When data is written to I2C data shift register after the MST bit is set to “0” (slave mode), keep the interval for 8 machine cycles or more. Also, when the read-modify-write instructions (SEB, CLB) are used during data transfer, the values may be undefined. Fig. 2.5.3 Structure of I 2C data shift register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-85 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface I2C special mode status register b7 b6 b5 b4 b3 b2 b1 b0 I2C special mode status register (S3: address 001216) b Name Functions 0: Address disagreement 1: Address agreement (Notes 1, 2) 0: Address disagreement 1: Address agreement (Notes 1, 2) 0: Address disagreement 1: Address agreement (Notes 1, 2) 0 Slave address 0 comparison flag (AAS0) 1 Slave address 1 comparison flag (AAS1) 2 Slave address 2 comparison flag (AAS2) At reset R W ✕ 0 0 ✕ 0 ✕ 3 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . 4 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are undefined. 5 SCL pin low hold 2 0: SCL pin low hold 1: SCL pin low release flag (PIN2) (Notes 1, 3) 6 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . 7 STOP condition flag (SPCF) 0: No detection 1: Detection (Notes 1, 4) 0 ✕ ✕ ✕ 0 1 0 ✕ ✕ 0 Notes 1: These bits and flags can be read out, but cannot be written. 2: These bits can be detected only when the data format selection bit (ALS) of I2C control register is set to 0 . 3: This bit is initialized to 1 at reset, when the ACK interrupt control bit is 0 , or when writing 1 to the SCL pin low hold 2 flag set bit. 4: This bit is initialized to 0 at reset, when the I2C-BUS interface enable bit (ES0) is 0 , or when writing 1 to the STOP condition flag clear bit. Fig. 2.5.4 Structure of I 2C special mode status register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-86 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface I2C status register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1: address 001316) b Name Functions At reset R W 0 Last receive bit (LRB) 1 General call detection flag (AD0) 2 Slave address comparison flag (AAS) 3 Arbitration lost detection flag (AL) 4 SCL pin low hold bit (PIN) 5 Bus busy flag (BB) 6 Communication mode specification bits (TRX, MST) 7 Undefined 0: Last bit = 0 1: Last bit = 1 (Note 1) 0 0: No general call detected 1: General call detected (Notes 1, 2) 0 0: Address disagreement 1: Address agreement (Notes 1, 2) 0: Not detected 1: Detected (Note 1) 0: SCL pin low hold (Note 3) 1: SCL pin low release 0: Bus free 1: Bus busy b7 b6 0 1 0 0 0 0 1 1 0: 1: 0: 1: Slave receive mode Slave transmit mode Master receive mode Master transmit mode 0 Notes 1: These flags and bits are exclusive to input. When writing to these bits, write 0 to these bits. 2: These bits can be detected only when the data format selection bit (ALS) of I2C control register is set to 0 . 3: This bit can be set to 1 by program, but cannot be cleared to 0 . 4: All bits are changed by hardware. Do not use the readmodify-write instructions (SEB, CLB). Fig. 2.5.5 Structure of I 2C status register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-87 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface I2C control register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D: address 001416) b Name b2b1b0 Functions 0 0 0: 8 0 0 1: 7 0 1 0: 6 0 1 1: 5 1 0 0: 4 1 0 1: 3 1 1 0: 2 1 1 1: 1 At reset R W 0 0 0 0 0 0 0 Bit counter (Number of transmit/receive 1 bits) (BC0, BC1, BC2) 2 0: Disabled 3 I2C-BUS interface 1: Enabled enable bit (ES0) 0: Addressing format 4 Data format selection bit (ALS) 1: Free data format 5 Addressing format 0: 7-bit addressing format selection bit 1: 10-bit addressing format (10BIT SAD) 6 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . 7 I2C-BUS interface pin 0: SMBUS input input level selection 1: CMOS input bit (TISS) 0 ✕ 0 Note: Do not use the read-modify-write instruction because some bits change by hardware when the start condition is detected and the byte-transfer is completed. Fig. 2.5.6 Structure of I 2C control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-88 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface I2C clock control register b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2: address 001516) b Name Functions Setting value b4b3b2b1b0 00 to 02 03 04 05 06 Standard High-speed clock mode clock mode Disabled Disabled Disabled 333 (Note 2) 250 100 400 (Note 3) 83.3 166 500/CCR value 1000/CCR value (Note 3) (Note 3) 17.2 34.5 1D 1E 16.6 33.3 1F 16.1 32.3 (φ = 4 MHz, Unit: kHz) (Note 1) At reset R W 0 0 0 0 0 0 0 SCL frequency control bits (CCR0, CCR1, 1 CCR2, CCR3, CCR4) 2 3 4 5 SCL mode specification bit (FAST MODE) 6 ACK bit (ACK BIT) 7 ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock 0 0 Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the highspeed clock mode is selected and CCR value = 5 (400 kHz, at φ = 4 MHz). H duration of the clock fluctuates from —4 to +2 machine cycles in the standard clock mode, and fluctuates from —2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because L duration is extended instead of H duration reduction. These are values when SCL clock synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of 4 MHz or less. 3: The data formula of SCL frequency is described below: φ/(8 ✕ CCR value) Standard clock mode φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5) φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of φ frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. Fig. 2.5.7 Structure of I 2C clock control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-89 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface I2C START/STOP condition control register b7 b6 b5 b4 b3 b2 b1 b0 0 I2C START/STOP condition control register (S2D: address 001616) b Name Functions SCL release time = φ (µs) ✕ (SSC+1) Setup time = φ (µs) ✕ (SSC+1)/2 Hold time = φ (µs) ✕ (SSC+1)/2 At reset R W 0 1 0 1 1 0 START/STOP condition set bits 1 (SSC0, SSC1, 2 SSC2, SSC3, SSC4) 3 4 5 SCL/SDA interrupt pin polarity selection bit (SIP) 6 SCL/SDA interrupt pin selection bit (SIS) 7 Fix this bit to 0 . 0: Falling edge active 1: Rising edge active 0: SDA valid 1: SCL valid 0 0 0 Note: Fix SSC0 to 0 . Also, do not set SSC4 to SSC0 to odd values or 000002 . Fig. 2.5.8 Structure of I 2C START/STOP condition control register I2C special mode control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 I2C special mode control register (S3D: address 001716) b Name Functions At reset R W 0 0 0 Fix this bit to 0 . 1 ACK interrupt control 0: At communication completion bit (ACKICON) 1: At falling of ACK clock and communication completion 2 Slave address 0: One-byte slave address control bit (MSLAD) compare mode 1: Three-byte slave address compare mode 3 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . 4 Fix this bit to 0 . 5 SCL pin low hold 2 Writing 1 to this bit initializes flag set bit (PIN2IN) the SCL pin low hold 2 flag to 1 . (Notes 1, 2) Writing 1 to this bit clears 6 SCL pin low hold set bit (PIN2HD) the SCL pin low hold 2 flag to 0 and holds the SCL pin low. (Notes 1, 2) 7 STOP condition flag Writing 1 to this bit initializes clear bit (SPFCL) the STOP condition flag to 0 . (Note 1) 0 0 ✕ 0 0 0 0 Notes 1: When 0 is written to these bits, nothing is happened. 2: Do not write 1 to these bits at the same time. Fig. 2.5.9 Structure of I2C special mode control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-90 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface I2C slave address register i (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 I2C slave address register i (i = 0 to 2) (S0D0, S0D1, S0D2: addresses 0FF716, 0FF816, 0FF916) b Name Functions 0: Write bit 1: Read bit At reset R W 0 0 Read/Write bit (RWB) 1 Slave address 0 The contents of these bits 2 (SAD0, SAD1, SAD2, are compared with the 0 3 SAD3, SAD4, SAD5, address data transmitted 0 from master. 4 SAD6) 0 5 0 6 0 7 0 Note: When the read-modify-write instructions (SEB, CLB) are used at detection of stop condition, the values may be undefined. Fig. 2.5.10 Structure of I 2C slave address register i (i = 0 to 2) Interrupt source selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt source selection register (INTSEL: address 003916) b Name Functions 0: INT0 interrupt 1: Timer Z interrupt 0: Serial I/O2 interrupt 1: Timer Z interrupt 0: Serial I/O1 transmit interrupt 1: SCL, SDA interrupt 0: CNTR0 interrupt 1: SCL, SDA interrupt 0: INT4 interrupt 1: CNTR2 interrupt 0: INT2 interrupt 1: I2C interrupt 0: CNTR1 interrupt 1: Serial I/O3 receive interrupt 0: A/D converter interrupt 1: Serial I/O3 transmit interrupt At reset R W 0 0 INT0/Timer Z interrupt source selection bit (*1) 1 Serial I/O2/Timer Z interrupt source selection bit (*1) 2 Serial I/O1 transmit/ SCL, SDA interrupt source selection bit (*2) 3 CNTR0/SCL, SDA interrupt source selection bit (*2) 4 INT4/CNTR2 interrupt source selection bit 5 INT2/I2C interrupt source selection bit 6 CNTR1/Serial I/O3 receive interrupt source selection bit 7 AD converter/Serial I/O3 transmit interrupt source selection bit 0 0 0 0 0 0 0 *1: Do not write 1 to these bits simultaneously. *2: Do not write 1 to these bits simultaneously. Fig. 2.5.11 Structure of Interrupt source selection register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-91 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1 : address 003C16) b Name Functions At reset R W 0 0 0 0 ✽ ✽ ✽ ✽ 0 INT0/Timer Z 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 1 INT1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 2 Serial I/O1 receive 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 0 : No interrupt request issued 3 Serial I/O1 transmit/SCL, SDA 1 : Interrupt request issued interrupt request bit 4 Timer X interrupt request bit 5 Timer Y interrupt request bit 6 Timer 1 interrupt request bit 0 : No interrupt request issued 0 0 0 0 ✽ ✽ ✽ ✽ 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 7 Timer 2 interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: 0 can be set by software, but 1 cannot be set. Fig. 2.5.12 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2 : address 003D16) b Name Functions At reset R W 0 0 ✽ ✽ 0 CNTR0/SCL, SDA 0 : No interrupt request issued interrupt request bit 1 : Interrupt request issued 1 CNTR1/Serial I/O3 0 : No interrupt request issued 1 : Interrupt request issued receive interrupt request bit 2 Serial I/O2/Timer Z interrupt request bit 3 INT2/I2C interrupt request bit 4 INT3 interrupt request bit 5 INT4/CNTR2 interrupt request bit 6 AD converter/Serial I/O3 transmit interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . ✽: 0 can be set by software, but 1 cannot be set. 0 Fig. 2.5.13 Structure of Interrupt request register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-92 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1 : address 003E16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 INT0/Timer Z interrupt enable bit 1 INT1 interrupt enable bit 2 Serial I/O1 receive interrupt enable bit 3 Serial I/O1 transmit/SCL, SDA interrupt enable bit 4 Timer X interrupt enable bit 5 Timer Y interrupt enable bit 6 Timer 1 interrupt enable bit 7 Timer 2 interrupt enable bit 0 0 0 0 Fig. 2.5.14 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2 : address 003F16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 CNTR0/SCL, SDA interrupt enable bit 1 CNTR1/ Serial I/O3 receive interrupt enable bit 2 Serial I/O2/ Timer Z interrupt enable bit 3 INT2/I2C interrupt enable bit 4 INT3 interrupt enable bit 5 INT4/CNTR2 interrupt enable bit 6 AD converter/Serial I/O3 transmit interrupt enable bit 7 Fix this bit to 0 . 0 0 0 0 0 0 Fig. 2.5.15 Structure of Interrupt control register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-93 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface 2.5.3 I 2C-BUS overview The I 2C-BUS is a both directions serial bus connected with two signal lines; the SCL which transmits a clock and the SDA which transmits data. Each port of the 3804 group has an N-channel open-drain structure for output and a CMOS structure for input. The devices connected with the I 2 C-BUS interface use an open drain, so that external pull-up resistors are required. Accordingly, while any one of devices always outputs “ L ” , other devices cannot output “ H ” . Figure 2.5.16 shows the I 2C-BUS connection structure. SCL output SCL output SCL input SCL input SDA output SDA output SDA input SDA input SCL output SCL input SDA output SDA input Fig. 2.5.16 I 2C-BUS connection structure Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-94 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface 2.5.4 Communication format Figure 2.5.17 shows an I2C-BUS communication format example. The I 2C-BUS consists of the following: • START condition to indicate communication start • Slave address and data to specify each device • ACK to indicate acknowledgment of address and data • STOP condition to indicate communication completion. Bus busy term S Slave address 7 bits R/W A Data 8 bits A Data 8 bits AP SCL SDA Start Addresses 0 to 6 W ACK Data 0 to 7 ACK Data 0 to 7 ACK Stop Fig. 2.5.17 I2C-BUS communication format example (1) START condition When communication starts, the master device outputs the START condition to the slave device. The I2C-BUS defines that data can be changed when a clock line is “L”. Accordingly, data change when a clock line is “ H ” i s treated as STOP or START condition. The data line change from “ H ” t o “ L ” w hen a clock line is “ H ” i s START condition. (2) STOP condition Just as in START condition, the data line change from “ L ” t o “ H ” w hen a clock line is “ H ” i s STOP condition. The term from START condition to STOP condition is called “ Bus busy ” . The master device is inhibited from starting data transfer during that term. The Bus busy status can be judged by using the BB flag of I2C status register (bit 5 of address 001316). (3) Slave address The slave address is transmitted after START condition. This address consists of 7 bits and the 7th bit functions as the read/write (R/W) bit which indicates a data transmission method. The slave devices connected with the same I2C-BUS must have their addresses, individually. It is because that address is defined for the master to specify the transmitted/received slave device. The read/write (R/W) bit indicates a data transmission direction; “L” means write from the master to the slave, and “ H ” m eans read in. (4) Data The data has an 8-bit length. There are two cases depending on the read/write (R/W) bit of a slave address; one is from the master to the slave and the other is from the slave to the master. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-95 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface (5) ACK bit The ACK bit clock is generated by the master. This is used for indication of acknowledgment on the SDA line, the slave ’ s busy and the data end. For example, the slave device makes the SDA line “L” for acknowledgment when confirming the slave address following the START condition. The built-in I2C-BUS interface has the slave address automatic judgment function and the ACK acknowledgment function. “L” is automatically output when the ACK bit of I2C clock control register (bit 6 of address 001516) is “0” and an address data is received. When the slave address and the address data do not correspond, “ H ” ( NACK) is automatically output. In case the slave device cannot receive owing to an interrupt process, performing operation or others, the master can output STOP condition and complete data transfer by making the ACK data of the slave address “ H ” f or acknowledgment. Even in case the slave device cannot receive data during data transferring, the communication can be interrupted by performing NACK acknowledgment to the following data. When the master is receiving the data from the slave, the master can notify the slave of completion of data reception by performing NACK acknowledgment to the last data received from the slave. (6) RESTART condition The master can receive or transmit data without transmission of STOP condition while the master is transmitting or receiving a data. For example, after the master transmitted a data to the slave, transmitting a slave address + R (Read) following RESTART condition can make the following data treat as a reception data. Additionally, transmitting a slave address + W (Write) following RESTART condition can make the following data treat as a transmission data. START condition RESTART condition Master reception 1st-byte Master reception 2nd-byte S Slave address R/W A 7 bits “0” Write Data 8 bits A Sr Slave address R/W A 7 bits “1” Read Lower data 8 bits A Upper data 8 bits AP NACK expression end of master reception data S: START condition P: STOP condition A: ACK bit R/W: Read/Write bit Sr: RESTART condition Master to slave Slave to master Fig. 2.5.18 RESTART condition of master reception 2.5.5 Synchronization and arbitration lost (1) Synchronization When a plural master exists on the I2C-BUS and the masters, which have different speed, are going to simultaneously communicate; there is a rule to unify clocks so that a clock of each bit can be output correctly. Figure 2.5.19 shows a synchronized SCL line example. The SCL (A) and the SCL (B) are the master devices having a different speed. The SCL is synchronized waveforms. As shown by Figure 2.5.19, the SCL lines can be synchronized by the following method; the device which first finishes “H” term makes the SCL line “L” and the device which last remains “L” makes the SCL line “ H ” . Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-96 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➀ SCL(A) ➁ SCL(B) ➂ ➄ ➃ ➅ ➆ SCL Fig. 2.5.19 SCL waveforms when synchronizing clocks ➀ After START condition, the masters, which have different speed, simultaneously start clock transmission. ➁ T he SCL outputs “ L ” b ecause (A) finished counting “ H ” o utput; then (B) ’ s “ H ” o utput counting is interrupted and (B) starts counting “ L ” o utput. ➂ T he (A) outputs “ H ” b ecause (A) finished counting “ L ” t erm; the SCL level does not become “ H ” because (B) outputs “ L ” , and counting “ H ” t erm does not start but stop. ➃ ( B) outputs “ L ” t erm. ➄ T he SCL outputs “ H ” b ecause (B) finished counting “ L ” t erm; then (B) ’ s “ H ” o utput counting is started at the same time as (A). ➅ The SCL outputs “L” because (A) first finished counting “H” output; then (B)’s “H” output counting is interrupted and (B) starts counting “ L ” o utput. ➆ T he above are repeatedly performed. (2) Clock synchronization during communication In the I 2C-BUS, the slave device is permitted to retain the SCL line “ L ” a nd become waiting status for transmission from the master. By byte unit, for the reception preparation of the slave device, the master can become waiting status by making the SCL line “ L ” , which is after completion of byte reception or the ACK. By bit unit, it is possible to slow down a clock speed by retaining the clock line “L” for slave devices having limited hardware. The 3804 group can transmit data correctly without reduction of data bits toward waiting status request from the slave device. It is because the synchronization circuit is included for the case when retaining the SCL line “ L ” a s an internal hardware. After the last bit, including the ACK bit, of a transmission/reception data byte, the SCL line automatically remains “ L ” a nd waiting status is generated until completion of an interrupt process or reception preparation. (3) Arbitration lost A plural master exists on the same bus in the I2C-BUS and there are possibility to start communication simultaneously. Even when the master devices having the same transmission frequency start communication simultaneously, which device must transmit data correctly. Accordingly, there is the definition to detect a communication confliction on the SDA line in the I 2C-BUS. The SDA line is output at the timing synchronized by the SCL, however, the synchronization among the SDA signals is not performed. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-97 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface 2.5.6 SMBUS communication usage example This clause explains a SMBUS communication control example using the I2C-BUS. This is a control example as the master device and the slave device in the Read Word protocol of SMBUS protocol. The following is a communication example of the “Voltage () command” of the Smart battery data. Communication specifications: •Communication frequency = 100 kHz •Slave address of itself, battery, = “0001011X 2” (X means the read/write bit) •Slave address of communication destination, host, = “0001000X 2” (X means the read/write bit) •Voltage () command = “09 16” •Voltage value of acknowledgment = “2EE016” (12000 mV) •The communication process is performed in the interrupt process. However, the main process performs an occurrence of the first START condition and a slave address set. •A communication buffer is established. Data transfer between the main process and the interrupt process is performed through the communication buffer. (1) Initial setting Figure 2.5.20 shows an initial setting example using SMBUS communication. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-98 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface I2C special mode control register (address 001716) b7 b0 S3D 00000000 Fix to “0” ACK interrupt control : At communication completion One-byte slave address compare mode Fix to “0” Fix to “0” SCL pin low hold 2 flag set bit : Not used SCL pin low hold set bit : Not set STOP condition flag clear bit : Not used I2C slave address register 0 (address 0FF716) b7 b0 This setting can be omitted. S0D0 00010110 Set slave address value 001616. I2C clock control register (address 001516) b7 b0 S2 10000101 Set clock 100 kHz (XIN = 8MHz) Standard clock mode ACK is returned ACK clock I2C status register (address 001316) b7 b0 S1 00 1 SCL pin low hold bit: Fix to “1” Slave receive mode I2C START/STOP condition control register (address 001616) b7 b0 S2D 00011010 Set setup time, hold time to 27 cycles (6.75 µs: XIN = 8 MHz). SCL/SDA interrupt: Falling edge active SCL/SDA interrupt: SDA valid Fix to “0” I2C control register (address 001416) b7 b0 S1D 00001000 Set number of transmit/receive bits to “8”. I2C-BUS interface: Enabled Addressing format 7-bit addressing format Fix to “0” Set SMBUS input level. Fig. 2.5.20 Initial setting example for SMBUS communication Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-99 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface (2) Communication example in master device The master device follows the procedures ➀ t o ➅ s hown by Figure 2.5.21. Additionally, the shaded area in the figure is a transmission data from the master device and the white area is a transmission data from the slave device. ➀ ➁ ➂ ➃ ➄ ➅ G enerating of START condition; Transmission of slave address + write bit T ransmission of command G enerating of RESTART condition; Transmission of slave address + read bit R eception of lower data R eception of upper data G enerating of STOP condition Figures 2.5.22 to 2.5.27 show the procedures ➀ t o ➅ . ➀ ➁ ➂ ➃ ➄ ➅ S Slave address R/W A Command A Sr Slave address R/W A 7 bits “0” Write 8 bits 7 bits Interrupt request “1” Read Lower data 8 bits A Upper data 8 bits AP Interrupt request Interrupt request Interrupt request Interrupt request S: START condition P: STOP condition A: ACK bit R/W: Read/Write bit Sr: RESTART condition Master to slave Slave to master Fig. 2.5.21 Read Word protocol communication as SMBUS master device Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-100 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➀ G enerating of START condition; Transmission of slave address + write bit After confirming that other master devices do not use the bus, generate the START condition, because the SMBUS is a multi-master. Write “slave address + write bit ” t o the I2C data shift register (address 0011 16) before performing to make the START condition generate. It is because the SCL of 1-byte unit is output, following occurrence of the START condition. If other master devices start communication until an occurrence of the START condition after confirming the bus use, it cannot communicate correctly. However in this case, that situation does not affect other master devices owing to detection of an arbitration lost or the START condition duplication preventing function. 1 (A)←000100002 SEI (Note 1) • Interrupts disabled 1 (used) BB (address 001316), bit5 ? (Note 2) 0 (not used) S0 (address 001116) ← (A) S1 (address 001316) ←111100002 • Slave address value write • START condition occurrence • Bus use confirmation CLI (Note 1) End • Interrupt enabled Notes 1: In this example, the SEI instruction to disable interrupts need not be executed because this processing is going to be performed in the interrupt processing. When the START condition is generated out of the interrupt processing, execute the SEI instruction to disable interrupts. 2: Use the branch bit instruction to confirm bus busy. Fig. 2.5.22 Generating of START condition and transmission process of slave address + write bit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-101 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➁ T ransmission of command Confirm correct completion of communication at ➀ before command transmission. When receiving the STOP condition, a process not to transmit a command is required, because the internal I2CBUS generates an interrupt request also owing to the STOP condition transmitted to other devices. After confirming correct completion of communication, write a command to the I 2 C data shift register (address 001116). In case the AL bit (bit 3 of address 001316) is “1”, check the slave address comparison flag (AAS bit; bit 2 of address 001316) to judge whether the device given a right of master transmission owing to an arbitration specifies itself as a slave address. When it is “ 1 ” , perform the slave reception; when “0”, wait for a STOP condition occurrence caused by other devices and the communication completion. In case the AL bit is “0”, check the last received bit (LRB bit; bit 0 of address 0013 16). When it is “ 1 ” , make the STOP condition generate and release the bus use, because the specified slave device does not exist on the SMBUS. 2 1(error) PIN (address 001316), bit 4 ? • Judgment of bus hold 0 (slave address transmitted) 1(detected) AL (address 001316), bit 3 ? 0 (not detected) 1(NACK) LRB (address 001316), bit 0 ? 0 (ACK) S0 (address 001116) ← 000010012 • Command data write to I2C data shift register • ACK confirmation • Judgment of arbitration lost detection End STOP condition output 0 (address not corresponded) AAS (address 001316), bit 2 ? • Judgment of slave address comparison 1 (address corresponded) Re-transmission preparation Slave reception Fig. 2.5.23 Transmission process of command Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-102 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➂ G enerating of RESTART condition; Transmission of slave address + read bit Confirm correct completion of communication at ➁ b efore generating the RESTART condition. After confirming correct completion, generate the RESTART condition and perform the transmission process of “ slave address + read bit ” . Note that procedure because that is different from ➀ ’ s process. As the same reason as ➀, write “ slave address + read bit ” t o the I2C data shift register (address 0011 16) before performing to make the START condition generate. However, when writing a slave address to the I 2C data shift register in this condition, a slave address is output at that time. Consequently, the RESTART condition cannot be generated. Therefore, follow the slave reception procedure before those processes. In case the arbitration lost detecting flag (AL bit, bit 3 of address 0013 16) is “ 1 ” , return to the process ➀, because other master devices will have priority to communicate. When the last received bit (LRB bit; bit 0 of address 001316) is “1”, generate the STOP condition and make the bus release, because acknowledgment cannot be done owing to BUSY status of the slave device specified on the SMBUS or other reasons. 3 1 (STOP condition) PIN (address 001316), bit 4 ? • Bus judgment during hold 0 (command transmission) 1 (detected) AL (address 001316), bit 3 ? 0 (not detected) 1 (NACK) LRB (address 001316), bit 0 ? 0 (ACK) S1 (address 001316) ← 000000002 (Note 1) (A) ← 000100012 • Slave receive mode set • ACK confirmation • Judgment of arbitration lost detection • Slave address read out SEI (Note 2) S0 (address 001116) ← (A) S1 (address 001316) ← 111100002 • Interrupt disabled • Slave address value write • RESTART condition occurrence • Interrupt enabled CLI (Note 2) End Re-transmission preparation STOP condition output Notes 1: Set to the receive mode while the PIN bit is “0”. Do not write “1” to the PIN bit. 2: In this example, the SEI instruction to disable interrupts need not be executed because this processing is going to be performed in the interrupt processing. When the START condition is generated out of the interrupt processing, execute the SEI instruction to disable interrupts. Fig. 2.5.24 Transmission process of RESTART condition and slave address + read bit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-103 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➃ R eception of lower data Confirm correct completion of communication at ➂ before receiving the lower data. After confirming correct completion, clear the ACK bit (bit 6 of address 0015 16) to “ 0 ” , in which ACK is returned, and set to the master receive mode. After that, write dummy data to the I 2C data shift register (address 001116). When the MST bit (bit 7 of address 001316) is “0”, perform the error process explained as follows and return to the process ➀. When the last receive bit (LRB bit; bit 0 of address 0013 16) is “ 1 ” , generate the STOP condition and make the bus release, because the slave device specified on the SMBUS does not exist. 4 1 (STOP condition) PIN (address 001316), bit 4 ? • Judgment of bus hold 0 (transmission of RESTART condition) 0 (slave) MST (address 001316), bit 7 ? 1 (master) 1 (NACK) LRB (address 001316), bit 0 ? 0 (ACK) S2 (address 001516) ← 100001012 S1 (address 001316) ←101000002 S0 (address 001116) ← 111111112 • “ACK clock is used” select and “ACK is returned” set • Master receive mode set • Dummy data to I2C data shift register write • ACK confirmation • Judgment of slave mode detection End STOP condition output 1 (detected) AL (address 001316), bit 3 ? 0 (not detected) • Judgment of arbitration lost detection Re-transmission preparation Error processing Fig. 2.5.25 Reception process of lower data Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-104 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➄ T ransmission of upper data Confirm correct completion of communication at ➃ before receiving the upper data. After confirming correct completion, store the received data (lower data). Set the ACK bit (bit 6 of address 0015 16) to “ 1 ” , in which ACK is not returned and write dummy data to the I 2C data shift register (address 0011 16). When the MST bit (bit 7 of address 001316) is “0”, return to the process ➀, because other devices have priority to communicate. 5 1 (STOP condition) PIN (address 001316), bit 4 ? • Judgment of bus hold 0 (lower data transmitted) 0 (slave) MST (address 001316), bit 7 ? 1 (Master) Receive data buffer ← S0 (address 001116) S2 (address 001516) ←110001012 S0 (address 001116) ← 111111112 • Receive data read and save • “NACK is returned” set • Dummy data to I2C data shift register write • Judgment of slave mode detection End 1(detected) AL (address 001316), bit 3 ? 0 (not detected) • Judgment of arbitration lost detection Re-transmission preparation Error processing Fig. 2.5.26 Reception process of upper data Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-105 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➅ G enerating of STOP condition Confirm correct completion of communication at ➄ b efore generating the STOP condition. After confirming correct completion, store the received data (upper data). Clear the ACK bit (bit 6 of address 0015 16) to “ 0 ” , in which ACK is returned, and generate the STOP condition. The communication mode is set to the slave receive mode by the occurrence of STOP condition. When the MST bit (bit 7 of address 001316) is “0”, return to the process ➀, because other devices have priority to communicate. 6 1 (STOP condition) PIN (address 001316), bit 4 ? 0 (upper data transmitted) 1 (detected) AL (address 001316), bit 3 ? 0 (not detected) Receive data buffer ← S0 (address 001116) S2 (address 001516) ← 100001012 S1 (address 001316) ← 110100002 • Receive data read and save • Set “ACK is returned” • STOP condition occurrence • Judgment of arbitration lost detection • Judgment of bus hold 1 (bus busy) BB (address 001316), bit5 ? (Note) 0 (bus free) Re-transmission preparation End Note: Use the branch bit instruction to check bus busy. Also, execute the time out processing separately, if neccessary. • Judgment of bus busy Fig. 2.5.27 Generating of STOP condition Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-106 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface (3) Communication example in slave device The slave device follows the procedures ➀ t o ➅ s hown by Figure 2.5.28. The only difference from the master device ’ s communication is an occurrence of interrupt request after detection of STOP condition. ➀ ➁ ➂ ➃ ➄ ➅ R eception of START condition; Transmission of ACK bit due to slave address correspondence R eception of command R eception of RESTART condition; Reception of slave address + read bit T ransmission of lower data T ransmission of upper data R eception of STOP condition Figures 2.5.29 to 2.5.34 show the procedures ➀ t o ➅. ➀ ➁ ➂ ➃ ➄➅ S Slave address R/W A Command A Sr Slave address R/W A 7 bits “0” Write 8 bits 7 bits Interrupt request “1” Read Lower data 8 bits A Upper data 8 bits AP Interrupt request Interrupt request Master to slave Slave to master Interrupt request Interrupt Interrupt request request S: START condition P: STOP condition A: ACK bit R/W: Read/Write bit Sr: RESTART condition Fig. 2.5.28 Communication example as SMBUS slave device Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-107 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➀ Reception of START condition; Transmission of ACK bit due to slave address correspondence In the case of operation as the slave, all processes are performed in the interrupt after setting of the slave reception in the main process, because an interrupt request does not occur until correspondence of a slave address. In the first interrupt, after confirming correspondence of the slave address, write dummy data to receive a command into the I 2C data shift register. 1 1 (STOP condition) PIN (address 001316), bit 4 ? 0 (slave address received) 0 (not corresponded) AAS (address 001316), bit 2 ? 1 (corresponded) S0 (address 001116) ← 111111112 • Dummy data write to I2C data shift register • Judgment of slave address correspondence • Judgment of bus hold End S1 (address 001316) ← 000100002 • Slave receive mode set Error processing Fig. 2.5.29 Reception process of START condition and slave address Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-108 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➁ R eception of command Confirm correct completion of the command reception in the interrupt after receiving the command. After confirming correct command from the host, write dummy data to the I 2C data shift register to wait for reception of the next slave address. 2 1 (STOP condition) PIN (address 001316), bit 4 ? 0 (command received) Receive data buffer ← S0 (address 001116) Judgment of receive command S2 (address 001516) ← 100001012 S0 (address 001116) ← 111111112 • “ACK clock is used” select and “ACK is returned” set • Dummy data write to I2C data shift register • Receive data read and save • Judgment of bus hold End S1 (address 001316) ← 000100002 • Slave receive mode set Error end Fig. 2.5.30 Reception process of command Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-109 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➂ R eception of RESTART condition and slave address After receiving a slave address, prepare transmission data. Judgment whether receiving data or transmitting is required, because the mode is automatically switched between the receive mode and the transmit mode depending on the R/W bit of the received slave address. Accordingly, judge whether read or write referring the slave address comparison flag (AAS bit; bit 2 of address 0013 16). 3 1 (STOP condition) PIN (address 001316), bit 4 ? 0 (lower data received) 0 (not corresponded) AAS (address 001316), bit 2 ? 1 (corresponded) 0 (received) TRX (address 001316), bit 6 ? 1 (transmitted) S0 (address 001116) ← lower data • Judgment of bus hold • Judgment of transmit/receive mode • Output lower data write to I2C data shift register End Slave receive processing, etc. End S1 (address 001316) ← 000100002 • Slave receive mode set Error end Fig. 2.5.31 Reception process of RESTART condition and slave address Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-110 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➃ T ransmission of lower data Before transmitting the upper data, restart to transmit the data at ➃ and confirm correct completion of transmission of the lower data set in the slave address reception interrupt. After that, transmit the upper data. 4 1 (STOP condition) PIN (address 001316), bit 4 ? • Judgment of bus hold 0 (lower data transmission completed) 1(NACK) LRB (address 001316), bit 0 ? 0 (ACK) S0 (address 001116) ←Upper data • Output upper data write to I2C data shift register • ACK confirmation End S1 (address 001316) ← 000100002 • Slave receive mode set Error end Fig. 2.5.32 Transmission process of lower data Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-111 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➄ T ransmission of upper data Confirm correct completion of the upper data transmission. The master returns the NACK toward the transmitted second-byte data, the upper data. Accordingly, confirm that the last receive bit (LRB bit; bit 0 of address 0013 16) is “ 1 ” . After that, write dummy data to the I 2C data shift register and wait for the interrupt of STOP condition. 5 1 (STOP condition) PIN (address 001316), bit 4 ? • Judgment of bus hold 0 (upper data transmission completed) 0 (ACK) LRB (address 001316), bit 0 ? 1 (NACK) S0 (address 001116) ← 111111112 • Dummy data write to I2C data shift register • ACK confirmation End S1 (address 001316) ← 000100002 • Slave receive mode set Error end Note: Use the branch bit instruction to check bus busy. Fig. 2.5.33 Transmission process of upper data Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-112 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface ➅ R eception of STOP condition Confirm that the STOP condition is correctly output and the bus is released. 6 0 (address or data received) PIN (address 001316), bit 4 ? 1 (STOP condition) End processing S1 (address 001316) ← 000100002 • Slave receive mode set • Judgment of bus hold End S1(address 001316) ← 000100002 • Slave receive mode set Error end Fig. 2.5.34 Reception of STOP condition Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-113 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface 2.5.7 Notes on multi-master I 2C-BUS interface (1) Read-modify-write instruction Each register of the multi-master I2C-BUS interface has bits to change by hardware. The precautions when the read-modify-write instruction such as S EB , C LB e tc. is executed for each register of the multi-master I 2C-BUS interface are described below. ➀ I2C data shift register (S0: address 0011 16) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. ➁ I 2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF7 16 t o 0FF916) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. q Reason It is because hardware changes the read/write bit (RWB) at detecting the STOP condition. ➂ I2C status register (S1: address 0013 16) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ➃ I2C control register (S1D: address 0014 16) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. q Reason Because hardware changes the bit counter (BC0 to BC2). ➄ I2C clock control register (S2: address 001516) The read-modify-write instruction can be executed for this register. ➅ I2C START/STOP condition control register (S2D: address 001616) The read-modify-write instruction can be executed for this register. Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-114 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface (2) START condition generating procedure using multi-master ➀ Procedure example (The necessary conditions of the generating procedure are described as the following ➁ t o ➄ ). LDA #SLADR (Taking out of slave address value) SEI (Interrupt disabled) BBS 5, S1, BUSBUSY (BB flag confirming and branch process) BUSFREE: STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of START condition generating) CLI (Interrupt enabled) : : BUSBUSY: CLI (Interrupt enabled) : : ➁ U se “ Branch on Bit Set ” o f “ BBS 5, S1, – ” f or the BB flag confirming and branch process. ➂ U se “ STA, STX ” o r “ STY ” o f the zero page addressing instruction for writing the slave address value to the I 2C data shift register (S0: address 0011 16). ➃ Execute the branch instruction of above ➁ and the store instruction of above ➂ continuously shown by the above procedure example. ➄ D isable interrupts during the following three process steps: • B B flag confirming • W riting of slave address value • T rigger of START condition generating (3) RESTART condition generating procedure in master ➀ Procedure example (The necessary conditions of the generating procedure are described as the following ➁ t o ➃ ). Execute the following procedure when the PIN bit is “ 0 ” . LDM #$00, S1 (Select slave receive mode) LDA #SLADR (Taking out of slave address value) SEI (Interrupt disabled) STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of RESTART condition generating) CLI (Interrupt enabled) : : ➁ Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. The TRX bit becomes “0” and the SDA pin is released. ➂ T he SCL pin is released by writing the slave address value to the I 2C data shift register. ➃ D isable interrupts during the following two process steps: • W riting of slave address value • T rigger of RESTART condition generating (4) Writing to I 2C status register (S1: address 0013 16) Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “ 0 ” f rom “ 1 ” s imultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” f rom “ 1 ” s imultaneously when the PIN bit is “ 1” . It is because it may become the same as above. Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-115 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface (5) Writing to I 2C clock control register (S2: address 001516) Do not write data into the I2C clock control register during transfer. If data is written during transfer, the I 2C clock generator is reset, so that data cannot be transferred normally. (6) Switching of SCL/SDA interrupt pin polarity selection bit, SCL/SDA interrupt pin selection bit, I 2C-BUS interface enable bit When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I 2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0 is set. Reset the request bit to “ 0 ” a fter setting these bits, and enable the interrupt. (7) Process of after STOP condition generating in master mode Do not write data in the I2C data shift register (S0) and the I2C status register (S1) until the bus busy flag BB becomes “ 0 ” a fter generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers does not have the problem. (8) ES0 bit switch In standard clock mode when SSC = “ 00010 2” o r in high-speed clock mode, flag BB may switch to “ 1 ” i f ES0 bit is set to “ 1 ” w hen SDA is “ L ” . Countermeasure: Set ES0 to “1” w hen SDA is “H”. Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-116 APPLICATION 3804 Group (Spec.H) 2.5 Multi-master I2C-BUS interface 2.5.8 Notes on programming for SMBUS interface (1) Time out process For a smart battery system, the time out process with a program is required so that the communication can be completed even when communication is interrupted. It is because there is possibility of extracting a battery from a PC. The specifications are defined so that communication has been able to be completed within 25 ms from START condition to STOP condition and within 10 ms from the ACK pulse to the ACK pulse of each byte. Accordingly, the following two should be considered as count start conditions. ➀ S DA falling edge caused by SCL/SDA interrupt This is the countermeasure for a communication interrupt in the middle of from START condition to a slave address. However, the detection condition must be considered because a interrupt is also generated by communication from other masters to other slaves. ➁ S MBUS interrupt after receiving slave address This is the countermeasure for when communication is interrupted from receiving a slave address until receiving a command. (2) Low hold of communication line The I2C-BUS interface conforms to the I2C-BUS Standard Specifications. However, because the use condition of SMBUS differs from the I 2C-BUS ’ s, there is possibility of occurrence of the following problem. ➀ L ow hold of SDA line caused by ACK pulse at voltage drop of communication line When the SMBUS voltage slowly drops, that is caused by extracting a battery from equipment or turning off a PC’s power or etc., it might be incorrectly treated as the SCL pulse near the threshold level voltage. When the SDA is judged “L” in that condition, it becomes the general call and the ACK is transmitted. However, when the SCL remains “ L ” a t the ACK pulse, the SDA continuously remains “ L ” u ntil input of the next SCL pulse. Countermeasure: As explained before, start the time out count at the falling of SDA line of START condition and reset ES0 bit of the S1D register when the time out is satisfied ( Note). Note: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit is set to “ 0 ” , it becomes a general-purpose port ; so that the port must be set to input mode or “ H ” . Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 2-117 APPLICATION 3804 Group (Spec.H) 2.6 PWM 2.6 PWM This paragraph explains the registers setting method and the notes relevant to the PWM. 2.6.1 Memory map Address 002B16 002C16 002D16 PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) Fig. 2.6.1 Memory map of registers relevant to PWM 2.6.2 Relevant registers PWM control register b7 b6 b5 b4 b3 b2 b1 b0 PWM control register (PWMCON: address 002B16) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 PWM function 0 : PWM disabled enable bit 1 : PWM enabled 1 Count source 0 : f(XIN) selection bit 1 : f(XIN)/2 2 Nothing is arranged for these bits. These are 3 write disabled bits. When these bits are read 4 out, the contents are “0”. 5 6 7 ✕ ✕ ✕ ✕ ✕ ✕ Fig. 2.6.2 Structure of PWM control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-118 APPLICATION 3804 Group (Spec.H) 2.6 PWM PWM prescaler b7 b6 b5 b4 b3 b2 b1 b0 PWM prescaler (PREPWM: address 002C16) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 •Set the PWM period. 1 •The value set in this register is written to both PWM prescaler pre-latch and PWM prescaler 2 latch at the same time. 3 • When data is written to this register during PWM output, the pulse corresponding to 4 changed value is output at the next period. 5 • When this register is read out, the count value of the PWM prescaler latch is read out. 6 7 Fig. 2.6.3 Structure of PWM prescaler PWM register b7 b6 b5 b4 b3 b2 b1 b0 PWM register (PWM: address 002D16) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 • Set the PWM “H” level output interval. 1 • The value set in this register is written to both PWM register pre-latch and PWM register 2 latch at the same time. 3 • When data is written to this register during PWM output, the pulse corresponding to 4 changed value is output at the next period. 5 • When this register is read out, the contents of the PWM register latch is read out. 6 7 Fig. 2.6.4 Structure of PWM register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-119 APPLICATION 3804 Group (Spec.H) 2.6 PWM 2.6.3 PWM output circuit application example Outline : The rotation speed of the motor is controlled by using PWM (pulse width modulation) output. Figure 2.6.5 shows a connection diagram ; Figures 2.6.6 shows PWM output timing, and Figure 2.6.7 shows a setting of the related registers. P56/PWM D/A converter M Motor driver 3804 group (Spec. H) Fig. 2.6.5 Connection diagram Specifications : • Motor is controlled by using the PWM output function of 8-bit resolution. • Clock f(XIN) = 5 MHz • “T”, PWM cycle : 102 µs • “t”, “H” level width of output pulse : 40 µs (Fixed speed) ✽ A motor speed can be changed by modifying the “H” level width of output pulse. t = 40 µs PWM output T = 102 µs Fig. 2.6.6 PWM output timing Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-120 APPLICATION 3804 Group (Spec.H) 2.6 PWM PWM control register (Address : 002B16) b7 b0 PWMCON 01 PWM output: Enabled (Note) Count source: f(XIN) PWM prescaler (Address : 002C16) b7 b0 PREPWM n Set “T”, PWM cycle n=1 [Equation] 255 ✕ (n + 1) T= f(XIN) PWM register (Address : 002D16) b7 b0 PWM m Set “t”, “H” level width of PWM m = 100 [Equation] t= T✕m 255 Note: The PWM output function has priority even when bit 6 (corresponding bit to P56 pin) of Port P5 direction register is set to “0” (input mode). Fig. 2.6.7 Setting of relevant registers 1. Set the PWM function enable bit to “1” : The P56/PWM pin is used as the PWM pin. The pulse beginning with “H” level pulse is output. 2. Set the PWM function enable bit to “0” : The P56/PWM pin is used as the port P56. Thus, when fixing the output level, take the following procedure: (1) Write an output value to bit 6 of the port P5 register. (2) Write “010000002” to the port P5 direction register. 3. After data is set to the PWM prescaler and the PWM register, the PWM waveforms corresponding to updated data will be output from the next repetitive cycle. PWM output Change PWM output data From the next repetitive cycle, output modified data Fig. 2.6.8 PWM output Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-121 APPLICATION 3804 Group (Spec.H) 2.6 PWM By setting the related registers as shown by Figure 2.6.7, PWM waveforms are output to the externals. This PWM output is integrated through the low pass filter, and that converted into DC signals is used for control of the motor. Figure 2.6.9 shows control procedure. ~ ~ P5 (Address : 000A16), bit6 P5D (Address : 000B16) PREPWM (Address : 002C16) PWM (Address : 002D16) PWMCON (Address : 002B16) 0 X1XXXXXX2 1 100 XXXXXX012 • X : This bit is not used here. Set it to “0” or “1” arbitrarily. • “L” level output from P56/PWM pin • PWM period setting • “H” level width of PWM setting • PWM count source selected, PWM output enabled ~ ~ Fig. 2.6.9 Control procedure 2.6.4 N otes on PWM The PWM starts after the PWM enable bit is set to enable and “ L ” l evel is output from the PWM pin. The length of this “ L “ l evel output is as follows: n+1 2 • f (XIN) n+1 f(XIN) (s) (Count source selection bit = 0, where n is the value set in the prescaler) (s) (Count source selection bit = 1, where n is the value set in the prescaler) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-122 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter 2.7 A/D converter This paragraph explains the registers setting method and the notes relevant to the A/D converter. 2.7.1 Memory map Address 003416 003516 AD/DA control register (ADCON) AD conversion register 1 (AD1) 003816 003916 AD conversion register 2 (AD2) Interrupt source selection register (INTSEL) 003D16 Interrupt request register 2 (IREQ2) 003F16 Interrupt control register 2 (ICON2) Fig. 2.7.1 Memory map of registers relevant to A/D converter 2.7.2 Relevant registers AD/DA control register b7 b6 b5 b4 b3 b2 b1 b0 AD/DA control register (ADCON: address 003416) b Name b2 b1 b0 Functions 0 0 0: P60/AN0 or P00/AN8 0 0 1: P61/AN1 or P01/AN9 0 1 0: P62/AN2 or P02/AN10 0 1 1: P63/AN3 or P03/AN11 1 0 0: P64/AN4 or P04/AN12 1 0 1: P65/AN5 or P05/AN13 1 1 0: P66/AN6 or P06/AN14 1 1 1: P67/AN7 or P07/AN15 At reset R W 0 0 Analog input pin selection bits 1 1 0 2 0 0: Conversion in progress 3 AD conversion 1: Conversion completed completion bit 4 Analog input pin 0: AN0 to AN7 side 1: AN8 to AN15 side selection bit 2 5 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are “0”. 6 DA1 output enable 0: DA1 output disabled 1: DA1 output enabled bit 7 DA2 output enable 0: DA2 output disabled 1: DA2 output enabled bit 1 0 0 0 0 Fig. 2.7.2 Structure of AD/DA control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-123 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter AD conversion register 1 b7 b6 b5 b4 b3 b2 b1 b0 AD conversion register 1 (AD1: address 003516) b Functions At reset R W Undefined Undefined 0 Undefined 0 Undefined 0 Undefined 0 Undefined 0 Undefined 0 Undefined 0 0 This is A/D conversion result stored bits. This is 1 read exclusive register. 2 8-bit read b7 b0 3 b9 b8 b7 b6 b5 b4 b3 b2 4 5 10-bit read b7 b0 6 b7 b6 b5 b4 b3 b2 b1 b0 7 Fig. 2.7.3 Structure of AD conversion register 1 AD conversion register 2 b7 b6 b5 b4 b3 b2 b1 b0 AD conversion register 2 (AD2: address 003816) b Functions At reset R W 0 This is A/D conversion result stored bits. This is Undefined read exclusive register. 10-bit read b0 b7 Undefined 1 0 b9 b8 2 3 4 5 6 7 Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are “0”. 0 0 0 0 0 0 Conversion mode selection bit 0: 10-bit A/D mode 1: 8-bit A/D mode Fig. 2.7.4 Structure of AD conversion register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-124 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter Interrupt source selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt source selection register (INTSEL: address 003916) b Name Functions 0: INT0 interrupt 1: Timer Z interrupt 0: Serial I/O2 interrupt 1: Timer Z interrupt 0: Serial I/O1 transmit interrupt 1: SCL, SDA interrupt 0: CNTR0 interrupt 1: SCL, SDA interrupt 0: INT4 interrupt 1: CNTR2 interrupt 0: INT2 interrupt 1: I2C interrupt 0: CNTR1 interrupt 1: Serial I/O3 receive interrupt 0: A/D converter interrupt 1: Serial I/O3 transmit interrupt At reset R W 0 0 INT0/Timer Z interrupt source selection bit (*1) 1 Serial I/O2/Timer Z interrupt source selection bit (*1) 2 Serial I/O1 transmit/ SCL, SDA interrupt source selection bit (*2) 3 CNTR0/SCL, SDA interrupt source selection bit (*2) 4 INT4/CNTR2 interrupt source selection bit 5 INT2/I2C interrupt source selection bit 6 CNTR1/Serial I/O3 receive interrupt source selection bit 7 AD converter/Serial I/O3 transmit interrupt source selection bit 0 0 0 0 0 0 0 *1: Do not write 1 to these bits simultaneously. *2: Do not write 1 to these bits simultaneously. Fig. 2.7.5 Structure of Interrupt source selection register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-125 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2 : address 003D16) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 ✽ ✽ 0 CNTR0/SCL, SDA interrupt request bit 1 CNTR1/Serial I/O3 receive interrupt request bit 2 Serial I/O2/Timer Z interrupt request bit 3 INT2/I2C interrupt request bit 4 INT3 interrupt request bit 5 INT4/CNTR2 interrupt request bit 6 AD converter/Serial I/O3 transmit interrupt request bit 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ 7 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are 0 . ✽: 0 can be set by software, but 1 cannot be set. 0 Fig. 2.7.6 Structure of Interrupt request register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2 : address 003F16) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 CNTR0/SCL, SDA interrupt enable bit CNTR1/ Serial I/O3 1 receive interrupt enable bit 2 Serial I/O2/ Timer Z interrupt enable bit 3 INT2/I2C interrupt enable bit 4 INT3 interrupt enable bit 5 INT4/CNTR2 interrupt enable bit 6 AD converter/Serial I/O3 transmit interrupt enable bit 7 Fix this bit to “0”. 0 0 0 0 0 0 Fig. 2.7.7 Structure of Interrupt control register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-126 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter 2.7.3 A/D converter application examples (1) Conversion of analog input voltage 1 Outline : T he analog input voltage input from a sensor is converted to digital values. Figure 2.7.8 shows a connection diagram, and Figure 2.7.9 shows the relevant registers setting. P60/AN0 Sensor 3804 Group (Spec. H) Fig. 2.7.8 Connection diagram Specifications : • The analog input voltage input from a sensor is converted to digital values. • P6 0/AN 0 p in is used as an analog input pin. • 10-bit A/D mode AD/DA control register (address 003416) b7 b0 ADCON 0 00 00 Analog input pin : P60/AN0 selected A/D conversion start Analog input pin : AN0–AN7 selected AD conversion register 2 (address 003816) b7 b0 AD2 0 A result of A/D conversion is stored (read-only) (Note). 10-bit A/D mode AD conversion register 1 (address 003516) b7 b0 AD1 (Read-only) A result of A/D conversion is stored (Note). Note: After bit 3 of AD/DA control register (ADCON) is set to “1”, read out that contents. When reading 10-bit data, read address 003816 before address 003516. When reading 10-bit data, bits 2 to 6 of address 003816 become “0”. Fig. 2.7.9 Relevant registers setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-127 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter An analog input signal from a sensor is converted to the digital value according to the relevant registers setting shown by Figure 2.7.9. Figure 2.7.10 shows the control procedure for 10-bit A/D mode. q X: This bit is not used here. Set it to “0” or “1” arbitrarily. AD2 (address 003816) 0XXXXXXX2 •10-bit A/D mode selected ADCON (address 003416) XX0000002 •P60/AN0 pin selected as analog input pin •A/D conversion start ADCON (address 003416), bit3 ? 0 •Judgment of A/D conversion completion 1 Read out AD2 (address 003816) •Read out of high-order digit (b9, b8) of conversion result Read out AD1 (address 003516) •Read out of low-order digit (b7 – b0) of conversion result Fig. 2.7.10 Control procedure (10-bit A/D mode) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-128 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter (2) Conversion of analog input voltage 2 Outline : T he analog input voltage input from a sensor is converted to digital values. Figure 2.7.11 shows a connection diagram, and Figure 2.7.12 shows the relevant registers setting. P60/AN0 Sensor 3804 Group (Spec. H) Fig. 2.7.11 Connection diagram Specifications : • The analog input voltage input from a sensor is converted to digital values. • P6 0/AN 0 p in is used as an analog input pin. • 8-bit A/D mode AD/DA control register (address 003416) b7 b0 ADCON 0 00 00 Analog input pin : P60/AN0 selected A/D conversion start Analog input pin : AN0–AN7 selected AD conversion register 2 (address 003816) b7 b0 AD2 1 8-bit A/D mode AD conversion register 1 (address 003516) b7 b0 AD1 (Read-only) A result of A/D conversion is stored (Note). Note: After bit 3 of AD/DA control register (ADCON) is set to “1”, read out that contents. When reading 8-bit data, read address 003516 only. Fig. 2.7.12 Relevant registers setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-129 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter An analog input signal from a sensor is converted to the digital value according to the relevant registers setting shown by Figure 2.7.12. Figure 2.7.13 shows the control procedure for 8-bit A/D mode. q x: This bit is not used here. Set it to “0” or “1” arbitrarily. AD2 (address 003816) 1XXXXXXX2 •8-bit A/D mode selected ADCON (address 003416) XX0000002 •P60/AN0 pin selected as analog input pin •A/D conversion start ADCON (address 003416), bit3 ? 0 •Judgment of A/D conversion completion 1 Read out AD1 (address 003516) •Read out of conversion result Fig. 2.7.13 Control procedure (8-bit A/D mode) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-130 APPLICATION 3804 Group (Spec.H) 2.7 A/D converter 2.7.4 Notes on A/D converter (1) Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the user side. q Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion precision to be worse. (2) A/D converter power source pin The AVSS pin is A/D converter power source pins. Regardless of using the A/D conversion function or not, connect it as following : • A V SS : C onnect to the V SS l ine q Reason If the AV SS p in is opened, the microcomputer may have a failure because of noise or others. (3) Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A/D conversion. • f (X IN) is 500 kHz or more • D o not execute the S TP i nstruction (4) Difference between at 8-bit reading in 10-bit A/D mode and at 8-bit A/D mode At 8-bit reading in the 10-bit A/D mode, “–1/2 LSB” correction is not performed to the A/D conversion result. In the 8-bit A/D mode, the A/D conversion characteristics is the same as 3802 group’s characteristics because “ – 1/2 LSB ” c orrection is performed. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-131 APPLICATION 3804 Group (Spec.H) 2.8 D/A converter 2.8 D/A Converter This paragraph explains the registers setting method and the notes relevant to the D/A converter. 2.8.1 Memory map 000716 Port P3 direction register (P3D) 003416 003616 003716 AD/DA control register (ADCON) DA1 conversion register (DA1) DA2 conversion register (DA2) Fig. 2.8.1 Memory map of registers relevant to D/A converter Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-132 APPLICATION 3804 Group (Spec.H) 2.8 D/A converter 2.8.2 Relevant registers Port P3 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (P3D: address 000716) b Name Functions 0 : Port P30 input mode 1 : Port P30 output mode 0 : Port P31 input mode 1 : Port P31 output mode 0 : Port P32 input mode 1 : Port P32 output mode 0 : Port P33 input mode 1 : Port P33 output mode 0 : Port P34 input mode 1 : Port P34 output mode 0 : Port P35 input mode 1 : Port P35 output mode 0 : Port P36 input mode 1 : Port P36 output mode 0 : Port P37 input mode 1 : Port P37 output mode At reset R W 0 0 0 0 0 0 0 0 0 Port P3 direction register 1 2 3 4 5 6 7 Fig. 2.8.2 Structure of Port P5 direction register AD/DA control register b7 b6 b5 b4 b3 b2 b1 b0 AD/DA control register (ADCON: address 003416) b Name b2 b1 b0 Functions 0 0 0: P60/AN0 or P00/AN8 0 0 1: P61/AN1 or P01/AN9 0 1 0: P62/AN2 or P02/AN10 0 1 1: P63/AN3 or P03/AN11 1 0 0: P64/AN4 or P04/AN12 1 0 1: P65/AN5 or P05/AN13 1 1 0: P66/AN6 or P06/AN14 1 1 1: P67/AN7 or P07/AN15 At reset R W 0 0 Analog input pin selection bits 1 1 0 2 0 0: Conversion in progress 3 AD conversion 1: Conversion completed completion bit 4 Analog input pin 0: AN0 to AN7 side 1: AN8 to AN15 side selection bit 2 5 Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are “0”. 6 DA1 output enable 0: DA1 output disabled 1: DA1 output enabled bit 7 DA2 output enable 0: DA2 output disabled 1: DA2 output enabled bit 1 0 0 0 0 Fig. 2.8.3 Structure of AD/DA control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-133 APPLICATION 3804 Group (Spec.H) 2.8 D/A converter DAi conversion register b7 b6 b5 b4 b3 b2 b1 b0 DAi conversion register (i = 1, 2) (DAi: addresses 003616, 003716) b Functions At reset R W 0 0 0 0 0 0 0 0 0 This is D/A output value stored bits. This is write 1 exclusive register. 2 3 4 5 6 7 Fig. 2.8.4 Structure of DAi converter register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-134 APPLICATION 3804 Group (Spec.H) 2.8 D/A converter 2.8.3 D/A converter application example (1) Speaker output volume modulation Outline: T he volume of a speaker output is modulated by using D/A converter. Specifications: • Timer X modulates the period of sound for the pitch interval, so that a fixed pitch (“la”: approx. 440 Hz) can be output. Modulating the amplitude with the D/A output value controls the volume. • Use f(XIN) = 6 MHz. • Use DA1 (P3 0/DA 1 p in) as D/A converter. Figure 2.8.5 shows a peripheral circuit example and Figure 2.8.6 shows a speaker output example. Figure 2.8.7 shows the relevant registers setting. 3804 Group (Spec. H) P30/DA1 Amplification circuit Power amplifier + Fig. 2.8.5 Peripheral circuit example Modulation of volume VREF (amplitude is set by D/A1 output) VSS Timer X interrupt Timer X interrupt Timer X interrupt Timer X interrupt Timer X interrupt Timer X interrupt Modulation of pitch interval: 440 Hz (Cycle is set by timer X) Fig. 2.8.6 Speaker output example Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-135 APPLICATION 3804 Group (Spec.H) 2.8 D/A converter b7 b0 0 Port P3 direction register (P3D) (address 000716) P30/DA1: Input mode b7 b0 1 AD/DA control register (ADCON) (address 003416) DA1 output enabled b7 b0 001 Timer XY mode register (TM) (address 002316) Timer X count: Stop Timer mode b7 b0 0011 Timer 12, X count source serection register (T12XCSS) (address 000E16) Timer X count source: f(XIN)/16 b7 b0 2–1 Prescaler X (PREX) (address 002416) Set “division ratio –1” b7 b0 D616 – 1 Timer X (TX) (address 002516) Set “division ratio –1” b7 b0 0 Interrupt request register 1 (IREQ1) (address 003C16) Timer X interrupt request b7 b0 1 Interrupt control register 1 (ICON1) (address 003E16) Timer X interrupt: Enabled b7 b0 DA1 conversion register (DA1) (address 003616) Set conversion value (n) Analog voltage V = b7 b0 VREF × n 256 (n=0 to 255) 000 Timer XY mode register (TM) (address 002316 ) Timer X count: Start Fig. 2.8.7 Relevant registers setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-136 APPLICATION 3804 Group (Spec.H) 2.8 D/A converter When the registers are set as shown in Figure 2.8.7, the speaker output volume is modulated by the D/A output value. Figure 2.8.8 shows the control procedure. RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SEI CLT (Note 1) CLD (Note 2) (address 003E16), bit4 0 ICON1 (address 000716), bit0 0 P3D X1XXXXXX2 (address 003416) ADCON XX001XXX2 (address 002316) TM 0011XXXX2 T12XCSS (address 000E16) 2–1 (address 002416) PREX D616 – 1 (address 002516) TX 1 WORK flag (Note 3) (address 003C16), bit4 0 IREQ1 (address 003E16), bit4 1 ICON1 (address 003616) Set output value (volume) DA1 CLI (address 002316) XX000XXX2 TM •All interrupts disabled Fig. 2.8.8 Control procedure Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z ..... ..... •Timer X interrupt disabled •Set port P30 to input mode •DA1 output enabled •Timer Y: Timer mode, Timer X count: Stop •Timer X count source: f(XIN)/16 •Set “division ratio – 1” to Prescaler X •Set “division ratio – 1” to Timer X •Timer X interrupt request bit cleared •Timer X interrupt: Enabled •D/A converter start •All interrupts enabled •Timer X count start Main processing Notes 1: When using Index X mode flag 2: When using Decimal mode flag 3: The WORK flag is a user flag for work. When this flag is “1 ”, a value other than Vss is output from the DA output pin. When this flag is “0”, Vss is output from the DA output pin. Timer X interrupt process routine Push registers to stack •Push registers used in interrupt process routine Value of WORK flag ? “1” Set value except Vss to DA1 conversion register. Set “0” to WORK flag. “0” Set value of Vss to DA1 conversion register. Set “1” to WORK flag. Pop registers •Pop registers pushed to stack RTI ✻ Decide an D/A value from several times of D/A conversion results. 2-137 APPLICATION 3804 Group (Spec.H) 2.8 D/A converter 2.8.4 Notes on D/A converter (1) Vcc when using D/A converter The D/A converter accuracy when Vcc is 4.0 V or less differs from that of when Vcc is 4.0 V or more. When using the D/A converter, we recommend using a Vcc of 4.0 V or more. (2) DAi conversion register when not using D/A converter When a D/A converter is not used, set all values of the DAi conversion registers (i = 1, 2) to “00 16”. The initial value after reset is “00 16”. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-138 APPLICATION 3804 Group (Spec.H) 2.9 Watchdog timer 2.9 Watchdog timer This paragraph explains the registers setting method and the notes relevant to the watchdog timer. 2.9.1 Memory map Address 001E16 003B16 Watchdog timer control register (WDTCON) CPU mode register (CPUM) Fig. 2.9.1 Memory map of registers relevant to watchdog timer 2.9.2 Relevant registers Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer control register (WDTCON: address 001E16) b Name Functions 0 Watchdog timer H 1 (for read-out of high-order 6 bit) 2 3 4 5 6 STP instruction 0: STP instruction enabled 1: STP instruction disabled disable bit 7 Watchdog timer H 0: Watchdog timer L underflow count source selection 1: f(XIN)/16 or f(XCIN)/16 bit At reset R W 1 ✕ ✕ 1 1 ✕ ✕ 1 1 ✕ ✕ 1 0 0 Fig. 2.9.2 Structure of Watchdog timer control register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-139 APPLICATION 3804 Group (Spec.H) 2.9 Watchdog timer CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register (CPUM: address 003B16) b Name b1 b0 Functions 00 : Single-chip mode 01 : 10 : Not available 11 : 0 : 0 page 1 : 1 page 0: I/O port function (stop oscillating) 1: XCIN-XCOUT oscillation function 0: Oscillating 1: Stopped 0 0: φ=f(XIN)/2 (high-speed mode) 0 1: φ=f(XIN)/8 (middle-speed mode) 1 0: φ=f(XCIN)/2 (low-speed mode) 1 1: Not available b7 b6 At reset R W 0 0 0 1 0 0 Processor mode bits 1 2 Stack page selection bit 3 Fix this bit to “1”. 4 Port Xc switch bit 5 Main clock (XINXOUT) stop bit 6 Main clock division ratio selection bits 0 1 7 0 Fig. 2.9.3 Structure of CPU mode register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-140 APPLICATION 3804 Group (Spec.H) 2.9 Watchdog timer 2.9.3 Watchdog timer application examples (1) Detection of program runaway Outline: If program runaway occurs, let the microcomputer reset, using the internal timer for detection of program runaway. Specifications: • High-speed mode is used as a main clock division ratio. • An underflow signal of the watchdog timer L is supplied as the count source of watchdog timer H. • 1 cycle of main routine is 65.536 ms or less. •Before the watchdog timer H underflows, “0” is set into bit 7 of the watchdog timer control register at every cycle in a main routine. • An underflow of watchdog timer H is judged to be program runaway, and the microcomputer is returned to the reset status. Figure 2.9.4 shows a watchdog timer connection and division ratio setting; Figure 2.9.5 shows the relevant registers setting; Figure 2.9.6 shows the control procedure. Fixed f(XIN) = 16 MHz 1/16 Watchdog timer L Watchdog timer H 1/256 1/256 Reset circuit Internal reset RESET STP instruction disable bit STP instruction Fig. 2.9.4 Watchdog timer connection and division ratio setting Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-141 APPLICATION 3804 Group (Spec.H) 2.9 Watchdog timer CPU mode register (address 003B16) b7 b0 CPUM 000 1 00 Processor mode: Single-chip mode Fix to “1” Main clock (XIN-XOUT): Operating Main clock division ratio: f(XIN)/2 (high-speed mode) Watchdog timer control register (address 001E16) b7 b0 WDTCON 00 Watchdog timer H (for read-out of high-order 6 bits) Enable STP instruction Watchdog timer H count source: Watchdog timer L underflow Fig. 2.9.5 Relevant registers setting RESET Initialization SEI CLT CLD CPUM (address 003B16) : : CLI •All interrupts disabled •Processor mode: Single-chip mode •Main clock f(XIN): Operating •High-speed mode selected as main clock division ratio •Interrupts enabled 000X1X002 WDTCON (address 001E16) 000XXXXX2 •Watchdog timer L underflow selected as Watchdog timer H count source •STP instruction enabled Main processing : : Fig. 2.9.6 Control procedure 2.9.4 Notes on watchdog timer q Make sure that the watchdog timer H does not underflow while waiting Stop release, because the watchdog timer keeps counting during that term. qWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-142 APPLICATION 3804 Group (Spec.H) 2.10 Reset 2.10 Reset 2.10.1 Connection example of reset IC 1 VCC Power source 5 4 GND 3 0.1 µF VSS M62022L Output RESET Delay capacity 3804 Group (Spec. H) Fig. 2.10.1 Example of poweron reset circuit Figure 2.10.2 shows the system example which switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt. System power source voltage +5 V + 7 VCC1 RESET 5 VCC RESET 2 VCC2 INT 3 INT VSS 1 V1 GND 4 Cd 6 3804 Group (Spec. H) M62009L,M62009P,M62009FP Fig. 2.10.2 RAM backup system Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-143 APPLICATION 3804 Group (Spec.H) 2.10 Reset 2.10.2 Notes on RESET pin Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the V SS p in. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • M ake the length of the wiring which is connected to a capacitor as short as possible. • B e sure to verify the operation of application products on the user side. q R eason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-144 APPLICATION 3804 Group (Spec.H) 2.11 C lock generating circuit 2.11 Clock generating circuit This paragraph explains how to set the registers relevant to the clock generating circuit and describes an application example. 2.11.1 Relevant registers CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register (CPUM: address 003B16) b Name b1 b0 Functions 00 : Single-chip mode 01 : Not available 10 : Not available 11 : Not available 0 : 0 page 1 : 1 page 0: I/O port function (oscillation stopped) 1: XCIN-XCOUT oscillation function 0: Oscillating 1: Stopped 0 0: φ=f(XIN)/2 (high-speed mode) 0 1: φ=f(XIN)/8 (middle-speed mode) 1 0: φ=f(XCIN)/2 (low-speed mode) 1 1: Not available b7 b6 At reset R W 0 0 0 1 0 0 Processor mode bits 1 2 Stack page selection bit 3 Fix this bit to “1”. 4 Port Xc switch bit 5 Main clock (XINXOUT) stop bit Main clock division 6 ratio selection bits 0 1 7 0 Fig. 2.11.1 Structure of CPU mode register Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-145 APPLICATION 3804 Group (Spec.H) 2.11 C lock generating circuit 2.11.2 Clock generating circuit application example (1) Status transition during power failure Outline: T he clock counts up every second by using the timer interrupt during a power failure. Input port (Note) Power failure detection signal 3804 Group (Spec. H) Note: A signal is detected when input to input port, interrupt input pin, or analog input pin. Fig. 2.11.2 Connection diagram Specifications: • Reducing power dissipation as low as possible while maintaining clock function • Clock: f(X IN) = 8 MHz, f(X CIN) = 32.768 kHz •Port processing Input port: Fixed to “ H ” o r “ L ” l evel externally. Output port: Fixed to output level that does not cause current flow to the external. (Example) Fix to “ H ” f or an LED circuit that turns on at “ L ” o utput level. I/O port: Input port → F ixed to “ H ” o r “ L ” l evel externally. Output port → O utput of data that does not consume current V REF p in: Terminate A/D conversion operation Stop VREF current dissipation by setting value of DAi conversion register to “ 00 16” . Figure 2.11.3 shows the status transition diagram during power failure and Figure 2.11.4 shows the setting of relevant registers. Reset released Power failure detected XIN XCIN Internal system clock Middle-speed mode High-speed mode Low-speed mode Change internal system clock to high-speed mode After detection, change internal system clock to low-speed mode and stop oscillating XIN-XOUT XCIN-XCOUT oscillation function selected Fig. 2.11.3 Status transition diagram during power failure Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-146 APPLICATION 3804 Group (Spec.H) 2.11 C lock generating circuit b7 b0 CPUM 0 0 0 0 1 00 CPU mode register (CPUM) (address 003B16) Main clock: High-speed mode (f(XIN)/2) (Note 1) b7 b0 CPUM 0 0 0 1 1 (Note 2) 00 CPU mode register (CPUM) (address 003B16) Port XC: XCIN–XCOUT oscillation function b7 b0 CPUM 1 0 0 1 1 00 CPU mode register (CPUM) (address 003B16) Internal system clock: Low-speed mode (f(XCIN)/2) b7 b0 CPUM 1 0 1 1 1 00 CPU mode register (CPUM) (address 003B16) Main clock f(XIN): Stopped Notes 1: This setting is necessary only when selecting the high-speed mode. 2: When selecting the middle-speed mode, bit 6 is “1”. Fig. 2.11.4 Setting of relevant registers Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-147 APPLICATION 3804 Group (Spec.H) 2.11 C lock generating circuit Control procedure: T o prepare for a power failure, set the relevant registers in the order shown below. RESET qX: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization CPUM (address 003B16), bit7, bit 6 CPUM (address 003B16), bit 4 CPUM (address 003B16), bit7, bit 6 CPUM (address 003B16), bit5 Set timer interrupt to occurs every second. Execute WIT instruction. •••• 0, 0 1 When selecting main clock f(XIN)/2 (high-speed mode) Port XC: XCIN-XCOUT oscillation function •••• Detect power failure ? Y 1, 0 (Note) 1 (Note) Internal system clock: f(XCIN)/2 (low-speed mode) Main clock f(XIN) oscillation stopped N At power failure, clock count is performed during timer interrupt processing (every second). N Return condition from power failure completed ? Y Return processing from power failure Note: Do not switch simultaneously. Fig. 2.11.5 Control procedure Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-148 APPLICATION 3804 Group (Spec.H) 2.12 Standby function 2.12 Standby function The 3804 group (Spec. H) is provided with standby functions to stop the CPU by software and put the CPU into the low-power operation. The following two types of standby functions are available. • Stop mode using STP instruction • Wait mode using WIT instruction 2.12.1 Stop mode The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of both clocks (XIN– XOUT, X CIN–X COUT) stop and the internal clock φ s tops at the “ H” level. The CPU stops and peripheral units stop operating. As a result, power dissipation is reduced. (1) State in stop mode Table 2.12.1 shows the state in the stop mode. Table 2.12.1 State in stop mode Item Oscillation CPU Internal clock φ I/O ports P0 – P6 Timer Stopped. Stopped. Stopped at “ H ” l evel. Retains the state at the STP instruction execution. Stopped. (Timers 1, 2, X, Y, Z) However, Timers X, Y, Z can be operated in the event counter mode. Stopped. Stopped. Stopped. However, these can be operated only when an external clock is selected. I 2C-BUS interface A/D converter D/A converter Stopped. Stopped. Retains output voltage. State in stop mode PWM Watchdog timer Serial I/O1, Serial I/O2, Serial I/O3 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-149 APPLICATION 3804 Group (Spec.H) 2.12 Standby function (2) Release of stop mode The stop mode is released by a reset input or by the occurrence of an interrupt request. Note the differences in the restoration process according to reset input or interrupt request, as described below. s Restoration by reset input The stop mode is released by holding the RESET pin to the “ L ” i nput level during the stop mode. Oscillation is started when all ports are in the input state and the stop mode of the main clock (XINXOUT) is released. Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation stabilizing time) is required. The input of the RESET pin should be held at the “L” level until oscillation stabilizes. When the RESET pin is held at the “ L ” l evel for 16 cycles or more of X IN a fter the oscillation has stabilized, the microcomputer will go to the reset state. After the input level of the RESET pin is returned to “ H ” , the reset state is released in approximately 10.5 to 18.5 cycles of the XIN i nput. Figure 2.12.1 shows the oscillation stabilizing time at restoration by reset input. At release of the stop mode by reset input, the internal RAM retains its contents previous to the reset. However, the previous contents of the CPU register and SFR are not retained. For more details concerning reset, refer to “ 2.10 Reset ” . Stop mode Oscillation 16 cycles or stabilizing time more of XIN Operating mode Vcc Time to hold internal reset state = approximately 10.5 to 18.5 cycles of XIN input RESET XIN (Note) Execute Stop instruction Note: Some cases may occur in which no waveform is input to XIN (in low-speed mode). Fig. 2.12.1 Oscillation stabilizing time at restoration by reset input Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-150 APPLICATION 3804 Group (Spec.H) 2.12 Standby function s Restoration by interrupt request The occurrence of an interrupt request in the stop mode releases the stop mode. As a result, oscillation is resumed. The interrupts available for restoration are: •INT 0–INT 4 •CNTR 0, CNTR1, CNTR2 •Serial I/O (1, 2, 3) using an external clock •Timer X, Y, Z using an external event count •SCL/SDA However, when using any of these interrupt requests for restoration from the stop mode, in order to enable the selected interrupt, you must execute the STP instruction after setting the following conditions. [Necessary register setting] ➀ I nterrupt disable flag I = “0” (interrupt enabled) ➁ T imer 1 interrupt enable bit = “0” (interrupt disabled) ➂ I nterrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued) ➃ I nterrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled) For more details concerning interrupts, refer to “2.2 Interrupts”. Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation stabilizing time) is required. For restoration by an interrupt request, waiting time prior to supplying internal clock φ to the CPU is automatically generated✽2 by Prescaler 12 and Timer 1✽1. This waiting time is reserved as the oscillation stabilizing time on the system clock side. The supply of internal clock φ t o the CPU is started at the Timer 1 underflow. Figure 2.12.2 shows an execution sequence example at restoration by the occurrence of an INT 0 interrupt request. ✽1: If the STP instruction is executed when the oscillation stabilizing time set after STP instruction released bit is “0”, “FF 16” and “01 16” are automatically set in the Prescaler 12 counter/latch and Timer 1 counter/latch, respectively. When the oscillation stabilizing time set after STP instruction released bit is “1”, nothing is automatically set to either Prescaler 12 or Timer 1. For this reason, any suitable value can be set to Prescaler 12 and Timer 1 for the oscillation stabilizing time. ✽2: Immediately after the oscillation is started, the count source is supplied to the prescaler 12 so that a count operation is started. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-151 APPLICATION 3804 Group (Spec.H) 2.12 Standby function qWhen restoring microcomputer from stop mode by INT0 interrupt (oscillation stabilizing time set after STP instruction released bit = “0”, rising edge selected) Stop mode XIN or XCIN (System clock) INT0 pin “FF16” Prescaler 12 counter Timer 1 counter “0116” 512 counts Oscillation stabilizing time XIN; “H” XCIN; in high-impedance state INT0 interrupt request bit Peripheral device CPU Stopped Stopped Operating Operating Operating Operating Execute STP instruction INT0 interrupt signal input (INT0 interrupt request occurs) Oscillation start Prescaler 12 count start 512 counts down by prescaler 12 Start supplying internal clock φ to CPU Accept INT0 interrupt request Note: The count source set at STP instruction execution is connected as the prescaler 12 count source. Fig. 2.12.2 Execution sequence example at restoration by occurrence of INT 0 i nterrupt request (3) Notes on using stop mode s Register setting Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP instruction released bit is “ 0 ” ) s Clock restoration After restoration from the stop mode to the normal mode by an interrupt request, the contents of the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both main clock and sub clock were oscillating before execution of the STP instruction, the oscillation of both clocks is resumed at restoration. In the above case, when the main clock side is set as a system clock, the oscillation stabilizing time until the timer 1 underflow is reserved at restoration from the stop mode. When the oscillation stabilizing time set after STP instruction released bit is “0”, the time for 512 counts of the count source become the oscillation stabilizing time. When the oscillation stabilizing time set after STP instruction released bit is “1”, an arbitrarily count value set to the prescaler 12 and the timer 1 become the oscillation stabilizing time. At this time, note that the oscillation on the sub clock side may not be stabilized even after the lapse of the oscillation stabilizing time of the main clock side. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-152 APPLICATION 3804 Group (Spec.H) 2.12 Standby function 2.12.2 Wait mode The wait mode is set by execution of the WIT instruction. In the wait mode, oscillation continues, but the internal clock φ s tops at the “ H ” l evel. The CPU stops, but most of the peripheral units continue operating. (1) State in wait mode The continuation of oscillation permits clock supply to the peripheral units. Table 2.12.2 shows the state in the wait mode. Table 2.12.2 State in wait mode Item Oscillation CPU Internal clock φ I/O ports P0 – P6 Timer PWM Watchdog timer Serial I/O1, Serial I/O2, Serial I/O3 I C-BUS interface A/D converter D/A converter 2 State in wait mode Operating. Stopped. Stopped at “ H ” l evel. Retains the state at the WIT instruction execution. Operating. Operating. Operating. Operating. Stopped. Operating. Retains output voltage. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-153 APPLICATION 3804 Group (Spec.H) 2.12 Standby function (2) Release of wait mode The wait mode is released by reset input or by the occurrence of an interrupt request. Note the differences in the restoration process according to reset input or interrupt request, as described below. In the wait mode, oscillation is continued, so an instruction can be executed immediately after the wait mode is released. s Restoration by reset input The wait mode is released by holding the input level of the RESET pin at “ L ” i n the wait mode. Upon release of the wait mode, all ports are in the input state, and supply of the internal clock φ to the CPU is started. To reset the microcomputer, the RESET pin should be held at an “L” level for 16 cycles or more of XIN. The reset state is released in approximately 10.5 cycles to 18.5 cycles of the XIN i nput after the input of the RESET pin is returned to the “ H ” l evel. At release of wait mode, the internal RAM retains its contents previous to the reset. However, the previous contents of the CPU register and SFR are not retained. Figure 2.12.3 shows the reset input time. For more details concerning reset, refer to “ 2.10 Reset ” . Wait mode Operating mode Vcc 16 cycles of XIN Time to hold internal reset state = approximately 10.5 to 18.5 cycles of XIN input RESET XIN (Note) Execute WIT instruction Note: Some cases may occur in which no waveform is input to XIN (in low-speed mode). Fig. 2.12.3 Reset input time Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-154 APPLICATION 3804 Group (Spec.H) 2.12 Standby function s Restoration by interrupt request In the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the internal clock φ t o the CPU is started. At the same time, the interrupt request used for restoration is accepted, so the interrupt processing routine is executed. However, when using an interrupt request for restoration from the wait mode, in order to enable the selected interrupt, you must execute the STP instruction after setting the following conditions. [Necessary register setting] ➀ I nterrupt disable flag I = “ 0 ” ( interrupt enabled) ➁ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued) ➂ I nterrupt enable bit of interrupt source to be used for restoration = “ 1 ” ( interrupts enabled) For more details concerning interrupts, refer to “ 2.2 Interrupts ” . (3) Notes on wait mode s Clock restoration If the wait mode is released by a reset when X CIN is set as the system clock and X IN oscillation is stopped during execution of the WIT instruction, X CIN oscillation stops, XIN oscillations starts, and X IN i s set as the system clock. In the above case, the RESET pin should be held at “ L ” u ntil the oscillation is stabilized. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-155 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode 2.13 Flash memory mode This paragraph explains the registers setting method and the notes relevant to the flash memory mode of M38049FFHSP/FP/HP/KP. 2.13.1 Overview The functions of the flash memory version are similar to those of the mask ROM version except that the flash memory is built-in and some of the SFR area differ from that of the mask ROM version (refer to “ 2.13.2 Memory map ” ). In the flash memory version, the built-in flash memory can be programmed or erased by using the following three modes. • C PU rewrite mode • P arallel I/O mode • S tandard serial I/O mode 2.13.2 Memory map M38049FFHSP/FP/HP/KP have 60 Kbytes of built-in flash memory. Figure 2.13.1 shows the memory map of the flash memory version. 000016 SFR area 004016 RAM 083F16 Internal RAM area (2 Kbytes) 100016 180016 200016 User ROM area Data block B: 2 Kbytes Data block A: 2 Kbytes Block 3: 24 Kbytes Notes 1: The boot ROM area can be rewritten in a parallel I/O mode. (Access to except boot ROM area is disabled.) 2: To specify a block, use the maximum address in the block. 0FE016 0FFF16 100016 SFR area 800016 Block 2: 16 Kbytes C00016 Block 1: 8 Kbytes Internal flash memory area (60 Kbytes) E00016 Block 0: 8 Kbytes F00016 Boot ROM area 4 Kbytes FFFF16 FFFF16 FFFF16 Fig. 2.13.1 Memory map of M38049FFHSP/FP/HP/KP Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-156 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode 2.13.3 Relevant registers Address 0FE016 Flash memory control register 0 (FMCR0) 0FE116 Flash memory control register 1 (FMCR1) 0FE216 Flash memory control register 2 (FMCR2) Fig. 2.13.2 Memory map of registers relevant to flash memory Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register 0 (FMCR0 : address 0FE016) b Name Functions 0 : Busy (being automatic written or automatic erased) 1 : Ready At reset R W 1 0 RY/BY status flag 1 CPU rewrite mode select bit (Note 1) 2 3 4 5 6 7 0 : CPU rewrite mode invalid (software commandes invalid) 1 : CPU rewrite mode valid (Software commands acceptable) 8 KB user block E/W 0: E/W disabled enable bit (Notes 1, 1: E/W enabled 2) Flash memory reset 0: Normal operation bit (Notes 3, 4) 1: Reset Not used (Do not write “1” to this bit.) User ROM area 0: User ROM area is accessed select bit (Note 5) 1: Boot ROM area is accessed Program status flag 0: Pass 1: Error Erase status flag 0: Pass 1: Error 0 0 0 0 0 0 0 Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: This bit can be written only when the CPU rewrite mode select bit is “1”. 3: Effective only when the CPU rewrite mode select bit = “1”. Fix this bit to “0” when the CPU rewrite mode select bit is “0”. 4: When setting this bit to “1” (when the control circuit of flash memory is reset), the flash memory cannot be accessed for 10 µs. 5: Write to this bit from program on RAM. Fig. 2.13.3 Structure of Flash memory control register 0 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-157 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode Flash memory control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register 1 (FMCR1 : address 0FE116) b Name Functions At reset R W 0 0 0 : Suspend invalid 0 Erase suspend enable bit (Note 1) 1 : Suspend valid 1 Erase suspend 0 : Erase restart (no request issued) request bit (Note 2) 1 : Suspend request (request issued) 2 Nothing is arranged for these bits. If writing to 3 these bits, write “0”. The contents are undefined 4 at reading. 5 0 : Erase active 6 Erase suspend flag 1 : Erase inactive (Erase suspend mode) 7 Nothing is arranged for these bits. If writing to these bits, write “0”. The contents are undefined at reading. 0 0 0 0 1 0 Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. 2: Only when the erase suspend bit is “1”, this bit is valid. Fig. 2.13.4 Structure of Flash memory control register 1 Flash memory control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register 2 (FMCR2 : address 0FE216) b 0 1 2 3 4 Name Functions At reset R W 1 0 1 0 0 Nothing is arranged for these bits. If writing to these bits, write “0”. The contents are undefined at reading. All user block E/W 0 : E/W disabled enable bit (Notes 1, 2) 1 : E/W enabled 0 5 Nothing is arranged for these bits. If writing to 6 these bits, write “0”. The contents are undefined 1 7 at reading. 0 Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. 2: Effective only when the CPU rewrite mode select bit = “1”. Fig. 2.13.5 Structure of Flash memory control register 2 Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-158 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode 2.13.4 Parallel I/O mode In the parallel I/O mode, program/erase to the built-in flash memory can be performed by a flash memory programmer (EFP-I etc.). The memory area of program/erase is from 0F000 16 t o 0FFFF 16 ( boot ROM area) or from 01000 16 t o 0FFFF16 (user ROM area). Be especially careful when erasing; if the memory area is not set correctly, the products will be damaged eternally. Table 2.13.1 shows the parallel unit when programming by EFP-I in the parallel I/O mode. •EFP-I provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm) (product available in Asia and Oceania only) Table 2.13.1 Parallel unit when parallel programming (when using EFP-I provided by Suisei Electronics System Co., Ltd.) Products M38049FFHSP M38049FFHFP M38049FFHHP M38049FFHKP Parallel unit EF3803F-64S EF3803F-64F EF3803F-64H EF3803F-64U Boot ROM area User ROM area 0F000 16 t o 0FFFF16 01000 16 t o 0FFFF16 2.13.5 Standard serial I/O mode Table 2.13.2 shows a pin connection example (4 wires) between the programmer (EFP-I; Serial unit EF1SRP-01U is required additionally) and the microcomputer when programming in the standard serial I/O mode 1. •EFP-I provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm) (product available in Asia and Oceania only) Table 2.13.2 Connection example to programmer when serial programming (4 wires) Function Transfer clock input Serial data input Serial data output Transmit/Receive enable output “ H ” i nput Reset input Target board power source monitor input GND T_VPP T_RESET T_VDD (Note 2) GND ( Note 3) 3 14 4 1, 2, 15, 16 CNVSS RESET ( Note 1) VCC ( Note 2) VSS, AVSS (Note 3) 26 27 1 32, 3 18 19 57 24, 59 EFP-I (EF1SRP-01U) EF1RP-01U side Signal name connector Line number T_SCLK T_TXD T_RXD T_BUSY 9 10 11 12 Flash memory version Pin name P4 6/S CLK1 P4 4/RxD 1 P4 5/TxD1 P4 7/S RDY1/CNTR2 M38049FFHSP M38049FFHSP pin number pin number 13 21 23 22 20 15 14 12 Notes 1: S ince reset release after write verification is not performed, when operating MCU after writing, separate a target connection cable. 2: Supply Vcc of EFP-I side from user side so that the power supply voltage of the output buffer used by the EFP-I side becomes the same as user side power supply voltage (Vcc). 3: Four pins (No. 1, 2, 15, and 16) of the EF1SRP-01U side connector are prepared for GND signal. When connecting with a target board, although connection of only one pin does not have a problem, we recommend connecting with two or more pins. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-159 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode 2.13.6 CPU rewrite mode In the CPU rewrite mode, issuing software commands through the Central Processing Unit (CPU) can rewrite the built-in flash memory. Accordingly, the contents of the built-in flash memory can be rewritten with the microcomputer itself mounted on board, without using the programmer. Store the rewrite control program to the built-in flash memory in advance. The built-in flash memory cannot be read in the CPU rewrite mode. Accordingly, after transferring the rewrite control program to RAM, execute it on the RAM. The following commands can be used in the CPU rewrite mode: read array, read status register, clear status register, program, and block erase. For details concerning each command, refer to “CHAPTER 1 Flash memory mode (CPU rewrite mode)”. (1) CPU rewrite mode beginning/release procedures Operation procedure in the CPU rewrite mode for the built-in flash memory is described below. [Beginning procedure] ➀ A pply “H” to the CNVSS p in and P4 5/TxD 1 p in (at selecting boot ROM area). ➁ R elease reset. ➂ Set bits 6 and 7 (main clock division ratio selection bits) of the CPU mode register. (Make sure that system clock φ i s less than 4.0 MHz.) ➃ A fter CPU rewrite mode control program is transferred to internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program). ➄ S et “1” to the CPU rewrite mode select bit (bit 1 of address 0FFE 16 ). For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. ➅ S et “1” to the all user block E/W enable bit (bit 4 of address 0FE216). Set the 8 KB user block E/W enable bit. (Set to “0” when E/W is disabled, and set to “1” when E/W is enabled.)✽ ✽ For these bits to be set to “1”, the user needs to write “0” and then “1” to those in succession. ➆ F lash memory operations are executed by using software commands. Note 1: T he following procedures are also necessary. • Control for data which is input from the external (serial I/O etc.) and to be programmed to the flash memory. • Initial setting for ports, etc. • Writing to the watchdog timer [Release procedure] ➀ E xecute the read array command. ➁ In order to disable E/W to the user ROM area (except for data block), set “0” to the all user block E/ W enable bit (bit 4 of 0FE216) and the 8 KB user block E/W enable bit (bit 2 of 0FE016) (Note 2). ➂ S et the CPU rewrite mode select bit (bit 1 of address 0FFE 16) to “0”. ➃ Jump from the CPU rewriting control program on RAM to the user program on the flash memory. Note 2: Although E/W inhibition is not indispensable, the safety of system improves by disabling E/W except the time of E/W execution. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-160 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode Also, execute the following processing before the CPU reprogramming mode is selected so that interrupts will not occur during the CPU reprogramming mode. • S et the interrupt disable flag (I) to “ 1 ” When the watchdog timer has already started, write to the watchdog timer control register (address 001E16) periodically during the CPU reprogramming mode in order not to generate the reset by the underflow of the watchdog timer H. During the program or erase execution, watchdog timer is automatically cleared. Accordingly, the inernal reset by underflow does not occur. When the interrupt request or reset occurs in the CPU reprogramming mode, the microcomputer enters the following state; • I nterrupt occurs This may cause a program runaway because the read from the flash memory which has the interrupt vector area cannot be performed. • U nderflow of watchdog timer H, reset This may cause a microcomputer reset; the built-in flash memory control circuit and the flash memory control register are reset. When reset state is released with CNVss = “H” and P4 5/TxD1 = “H”, CPU starts in the boot mode. Also, when the above interrupt and reset occur during program/erase, error data may still exist after reset release because the reprogramming of the flash memory is not completed, so that reprogramming of the flash memory in the parallel I/O mode or serial I/O mode is required. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-161 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode 2.13.7 Flash memory mode application examples The control pin processing example on the system board in the standard serial I/O mode and the control example in the CPU rewrite mode are described below. (1) Control pin connection example on system board in standard serial I/O mode As shown in Figure 2.13.6, in the standard serial I/O mode, the built-in flash memory can be rewritten with the microcomputer mounted on board. Connection examples of control pins (P4 4/RxD, P45/TxD, P4 6/S CLK1, P4 7/S RDY1/CNTR 2, CNVSS, and RESET pin) in the standard serial I/O mode are described below. RS-232C Serial programmer M3 80 49 FF HS P/ FP /H P/ KP Fig. 2.13.6 Rewrite example of built-in flash memory in standard serial I/O mode Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-162 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode ➀ W hen control signals are not affected to user system circuit When the control signals in the standard serial I/O mode are not used or not affected to the user system circuit, they can be connected as shown in Figure 2.13.7. Target board ✽1 Not used or to user system circuit M38049FFHSP/FP/HP/KP ✽2 TXD(P45) SCLK1(P46) RXD(P44) BUSY(P47) CNVSS VCC AVSS VSS RESET User reset signal (Low active) XIN XOUT ✽1: When not used, set to input mode and pull up or pull down, or set to output mode and open. ✽2: It is necessary to apply Vcc to SCLK1 (P46) pin only when reset is released in the serial I/O mode 1. It is necessary to apply Vss to SCLK1 (P46) pin only when reset is released in the serial I/O mode 2. Fig. 2.13.7 Connection example in standard serial I/O mode (1) ➁ W hen control signals are affected to user system circuit-1 Figure 2.13.8 shows an example that the jumper switch cut-off the control signals not to supply to the user system circuit in the standard serial I/O mode. Target board To user system circuit M38049FFHSP/FP/HP/KP ✽ TXD(P45) SCLK1(P46) RXD(P44) BUSY(P47) CNVSS RESET User reset signal (Low active) VCC AVSS VSS XIN XOUT ✽: It is necessary to apply Vcc to SCLK1 (P46) pin only when reset is released in the serial I/O mode 1. It is necessary to apply Vss to SCLK1 (P46) pin only when reset is released in the serial I/O mode 2. Fig. 2.13.8 Connection example in standard serial I/O mode (2) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-163 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode ➂ W hen control signals are affected to user system circuit-2 Figure 2.13.9 shows an example that the analog switch (74HC4066) cut-off the control signals not to supply to the user system circuit in the standard serial I/O mode. Target board 74HC4066 To user system circuit M38049FFHSP/FP/HP/KP ✽ TXD(P45) SCLK1(P46) RXD(P44) BUSY(P47) CNVss RESET User reset signal (Low active) VCC AVSS VSS XIN XOUT ✽: It is necessary to apply Vcc to SCLK1 (P46) pin only when reset is released in the serial I/O mode 1. It is necessary to apply Vss to SCLK1 (P46) pin only when reset is released in the serial I/O mode 2. Fig. 2.13.9 Connection example in standard serial I/O mode (3) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-164 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode (2) Control pin termination example in CPU rewrite mode In this example, data is received by using serial I/O, and the data is programmed to the built-in flash memory in the CPU rewrite mode. Figure 2.13.10 shows an example of the reprogramming system for the built-in flash memory in the CPU rewrite mode. For the CPU rewrite mode beginning/release method, refer to “2.13.6 CPU rewrite mode.” M38049FFHSP/FP/HP/KP Clock input BUSY output Data input Data output SCLK1 SRDY1(BUSY) RXD TXD VCC AVSS VSS RESET CNVSS User reset signal XIN XOUT Fig. 2.13.10 Example of rewrite system for built-in flash memory in CPU rewrite mode (single-chip mode) Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-165 APPLICATION 3804 Group (Spec.H) 2.13 Flash memory mode 2.13.8 Notes on CPU rewrite mode (1) Operation speed During CPU rewrite mode, set the system clock φ 4.0 MHz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003B 16). (2) Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during the CPU rewrite mode. (3) Interrupts inhibited against use The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory. (4) Watchdog timer In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. (5) Reset Reset is always valid. In case of CNV SS = “ H ” w hen reset is released, boot mode is active. So the program starts from the address contained in address FFFC 16 a nd FFFD 16 i n boot ROM area. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 2-166 CHAPTER 3 APPENDIX 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Electrical characteristics Standard characteristics Notes on use Countermeasures against noise List of registers Package outline Machine instructions List of instruction code SFR memory map Pin configurations APPENDIX 3804 Group (Spec.H) 3.1 Electrical characteristics 3.1 ELECTRICAL CHARACTERISTICS 3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings Symbol Parameter VCC Power source voltages Input voltage P00–P07, P10–P17, P20–P27, VI P30, P31, P34–P37, P40–P47, P50–P57, P60–P67, VREF VI Input voltage P32, P33 ____________ VI Input voltage RESET, XIN VI Input voltage CNVSS VO Output voltage P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67, XOUT VO Output voltage P32, P33 Pd Power dissipation Topr Operating temperature Storage temperature Tstg Note: This value is 300 mW except SP package. Conditions All voltages are based on Vss. Output transistors are cut off. Ratings –0.3 to 6.5 –0.3 to VCC +0.3 Unit V V –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 V V V V Ta = 25°C –0.3 to 5.8 1000 (Note) –20 to 85 –65 to 125 V mW °C °C Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3-2 APPENDIX 3804 Group (Spec.H) 3.1 Electrical characteristics 3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC Parameter Power source voltage (Note 1) Conditions When start oscillating (Note 2) High-speed mode f(XIN) ≤ 8.4 MHz f(φ) = f(XIN)/2 f(XIN) ≤ 12.5 MHz f(XIN) ≤ 16.8 MHz f(XIN) ≤ 12.5 MHz Middle-speed mode f(XIN) ≤ 16.8 MHz f(φ) = f(XIN)/8 Min. 2.7 2.7 4.0 4.5 2.7 4.5 0.8VCC Limits Typ. 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 VCC Unit V V V V V V V V VSS VIH VIH VIH VIH VIH VIH VIL VIL VIL Power source voltage “H” input voltage P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 “H” input voltage P32, P33 “H” input voltage (when I2C-BUS input level is selected) SDA, SCL “H” input voltage (when SMBUS input level is selected) SDA, SCL “H” input voltage ____________ RESET, XIN, CNVSS “H” input voltage XCIN “L” input voltage P00–P07, P10–P17, P20–P27, P30–P37,P40–P47, P50–P57, P60–P67 “L” input voltage (when I2C-BUS input level is selected) SDA, SCL “L” input voltage (when SMBUS input level is selected) SDA, SCL ____________ 0.8VCC 0.7VCC 5.5 5.5 V V 1.4 5.5 V 0.8VCC 2 0 VCC VCC 0.2VCC V V V 0 0.3Vcc V 0 0.6 V VIL VIL VIL “L” input voltage RESET, CNVSS “L” input voltage XIN “L” input voltage XCIN 0 0.2VCC 0.16VCC 0.4 V V V Notes 1: When using A/D converter, see A/D converter recommended operating conditions. 2: The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3-3 APPENDIX 3804 Group (Spec.H) Table 3.1.3 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol f(XIN) Parameter Main clock input oscillation frequency (Note 1) Conditions High-speed mode f(φ) = f(XIN)/2 2.7 ≤ VCC < 4.0 V 4.0 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V 2.7 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V f(XCIN) Sub-clock input oscillation frequency (Notes 1, 2) 32.768 Limits Min. Typ. Max. (9✕VCC-0.3)✕1.05 3 (24✕VCC-60)✕1.05 3 16.8 (15✕VCC+39)✕1.1 7 16.8 50 Unit MHz MHz MHz MHz MHz kHz 3.1 Electrical characteristics Middle-speed mode f(φ) = f(XIN)/8 Notes 1: When the oscillation frequency has a duty cycle of 50%. 2: W hen using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3-4 APPENDIX 3804 Group (Spec.H) Table 3.1.4 Recommended operating conditions (3) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current “H” peak output current “L” peak output current “L” peak output current “H” average output current “L” average output current “L” average output current Parameter P00–P07, P10–P17, P20–P27, P30, P31, P34–P37 (Note 1) P40–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P30–P37 (Note 1) P20–P27 (Note 1) P40–P47,P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30, P31, P34–P37 (Note 1) P40–P47,P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P30–P37 (Note 1) P20–P27 (Note 1) P40–P47,P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 (Note 2) P00–P07, P10–P17, P30–P37, P40–P47, P50–P57, P60–P67 (Note 2) P20–P27 (Note 2) P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 (Note 3) P00–P07, P10–P17, P30–P37, P40–P47, P50–P57, P60–P67 (Note 3) P20–P27 (Note 3) Min. Limits Typ. Max. –80 –80 80 80 80 –40 –40 40 40 40 –10 10 20 –5 5 10 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 3.1 Electrical characteristics Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3-5 APPENDIX 3804 Group (Spec.H) 3.1 Electrical characteristics 3.1.3 Electrical characteristics Table 3.1.5 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 (Note 1) “L” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67 “L” output voltage P20–P27 Test conditions IOH = –10 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 1.8 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V IOL = 20 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V Limits Min. VCC–2.0 VCC–1.0 2.0 1.0 2.0 0.4 0.4 Typ. Max. Unit V V V V V V V VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM Hysteresis CNTR0, CNTR1, CNTR2, INT0–INT4 Hysteresis RxD1, SCLK1, SIN2, SCLK2, RxD3, SCLK3 ____________ Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67 ____________ “H” input current RESET, CNVSS “H” input current XIN “L” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67 ____________ “L” input current RESET,CNVSS “L” input current XIN “L” input current (at Pull-up) P00–P07, P10–P17, P20–P27, P30, P31, P34–P37, P40–P47, P50–P57, P60–P67 RAM hold voltage 0.5 V 0.5 VI = VCC (Pin floating. Pull-up transistors “off”) VI = VCC VI = VCC VI = VSS (Pin floating. Pull-up transistors “off”) VI = VSS VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped 5.0 V µA 5.0 4.0 –5.0 µA µA µA –5.0 –80 –30 1.8 –4.0 –210 –70 –420 –140 VCC µA µA µA µA V Note 1: P35 is measured when the P35/TxD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. P45 is measured when the P45/TxD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3-6 APPENDIX 3804 Group (Spec.H) 3.1 Electrical characteristics Table 3.1.6 Electrical characteristics (2) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768kHZ (Stoped in middle-speed mode), Output transistors “off”, AD converter not operated) Limits Symbol ICC Parameter Power source current High-speed mode VCC = 5V Test conditions f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 2.1 MHz f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 6.3 MHz f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state Ta = 25 °C Ta = 85 °C f(XIN) = 16.8 MHz, VCC = 5V In Middle-, high-speed mode Min. Typ. 5.5 4.5 3.5 2.2 2.2 2.7 1.8 1.1 3.0 2.4 2.0 2.1 1.7 1.5 1.3 410 4.5 400 3.7 0.55 0.75 1000 Max. 8,3 6.8 5.3 3.3 3.3 4.1 2.7 1.7 4.5 3.6 3.0 3.2 2.6 2.3 2.0 630 6.8 600 5.6 3.0 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA µA µA µA µA µA µA µA VCC = 3V Middle-speed mode VCC = 5V VCC = 3V Low-speed mode VCC = 5V VCC = 3V In STP state (All oscillation stopped) Increment when A/D conversion is executed Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3-7 APPENDIX 3804 Group (Spec.H) 3.1 Electrical characteristics 3.1.4 A/D converter characteristics Table 3.1.7 A/D converter recommended operating conditions (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V,Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC VREF AVSS VIA f(XIN) Parameter Power source voltage (When A/D converter is used) Analog reference voltage Analog power source voltage Analog input voltage Main clock oscillation frequency (When A/D converter is used) Conditions 8-bit A/D mode (Note 1) 10-bit A/D mode (Note 2) Limits Min. 2.7 2.7 2.0 0 0.5 0.5 0.5 Typ. 5.0 5.0 0 2.7 ≤ VCC < 4.0 V 4.0 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V Note 1: 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2: 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. Max. 5.5 5.5 VCC VCC (9✕VCC-0.3)✕1.05 3 (24✕VCC-60)✕1.05 3 16.8 Unit V V V V MHZ Table 3.1.8 A/D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol – – tCONV Resolution Absolute accuracy (excluding quantization error) Conversion time Parameter Test conditions 8-bit A/D mode (Note 1) 10-bit A/D mode (Note 2) 8-bit A/D mode (Note 1) 10-bit A/D mode (Note 2) 8-bit A/D mode (Note 1) 10-bit A/D mode (Note 2) Min. Limits Typ. Max. 8 10 ±2 ±4 50 61 100 200 5 5 Unit bit LSB 2tc(XIN) kΩ µA µA µA 2.7 ≤ VREF ≤ 5.5 V 2.7 ≤ VREF ≤ 5.5 V RLADDER Ladder resistor IVREF Reference power at A/D converter operated VREF = 5.0 V source input current at A/D converter stopped VREF = 5.0 V II(AD) A/D port inout current Note 1: 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2: 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. 12 50 35 150 3.1.5 D/A converter characteristics Table 3.1.9 D/A converter characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol – – tsu RO IVREF Resolution Absolute accuracy Parameter 4.0 ≤ VREF ≤ 5.5 V 2.7 ≤ VREF < 4.0 V 2 3.5 Test conditions Limits Min. Typ. Max. 8 1.0 2.5 3 5 3.2 Unit bit % % µs kΩ mA Setting time Output resistor Reference power source input current (Note 1) Note 1: Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “0016”. 3.1.6 Power source circuit timing characteristics Table 3.1.10 Power source circuit timing characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol td(P–R) Parameter Internal power source stable time at power-on Test conditions 2.7 ≤ Vcc < 5.5 V Limits Min. Typ. Max. 2 Unit ms Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3-8 APPENDIX 3804 Group (Spec.H) 3.1 Electrical characteristics 3.1.7 Timing requirements and switching characteristics Table 3.1.11 Timing requirements (1) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) Reset input “L” pulse width Main clock XIN input cycle time Main clock XIN input “H” pulse width Main clock XIN input “L” pulse width Sub-clock XCIN input cycle time Sub-clock XCIN input “H” pulse width Sub-clock XCIN input “L” pulse width CNTR0–CNTR2 input cycle time CNTR0–CNTR2 input “H” pulse width CNTR0–CNTR2 input “L” pulse width INT00, INT01, INT1, INT2, INT3, INT40, INT41 input “H” pulse width INT00, INT01, INT1, INT2, INT3, INT40, INT41 input “L” pulse width Parameter Limits Min. 4.5≤VCC≤5.5 V 4.0≤VCC