Preliminary Datasheet
R1EX25512ASA00A
R1EX25512ATA00A
Serial Peripheral Interface
512K EEPROM (64-Kword × 8-bit)
R10DS0046EJ0200
Rev.2.00
Oct.04, 2010
Description
R1EX25xxx series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MONOS memory technology and CMOS process and low voltage circuitry technology. They also have a
128-byte page programming function to make their write operation faster.
Note: Renesas Electronics' serial EEPROMs are authorized for using consumer applications such as cellular phones,
camcorders and audio equipments. Therefore, please contact Renesas Electronics' sales office before using
industrial applications such as automotive systems, embedded controllers and meters.
Features
• Single supply: 1.8 V to 5.5 V
• Serial Peripheral Interface compatible (SPI bus)
SPI mode 0 (0,0), 3 (1,1)
• Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
• Power dissipation:
Standby: 5 µA (max)
Active (Read): 5 mA (max)
Active (Write): 5 mA (max)
• Automatic page write: 128-byte/page
• Write cycle time: 5 ms (max)
• Endurance: 1,000k Cycles @25 °C
• Data retention: 100 Years @25 °C
• Small size packages: SOP-8pin, TSSOP-8pin
• Shipping tape and reel
TSSOP-8pin : 3,000 IC/reel
SOP-8pin
: 2,500 IC/reel
• Temperature range: −40 to +85°C
• Lead free product.
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 1 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Ordering Information
Type No.
Internal organization Operating voltage
Frequency
Package
R1EX25512ASA00A 512k bit (65536 × 8-bit) 1.8 V to 5.5 V
5 MHz
150 mil 8-pin plastic SOP
(2.5 V to 5.5 V) PRSP0008DF-B (FP-8DBV)
Lead free
3 MHz
(1.8 V to 5.5V)
R1EX25512ATA00A 512k bit (65536 × 8-bit) 1.8 V to 5.5 V
5 MHz
8-pin plastic TSSOP
(2.5 V to 5.5 V) PTSP0008JC-B (TTP-8DAV)
Lead free
3 MHz
(1.8 V to 5.5V)
Pin Arrangement
8-pin SOP/TSSOP
S
1
8
VCC
Q
2
7
HOLD
W
3
6
C
VSS
4
5
D
(Top view)
Pin Description
Pin name
C
D
Q
Function
Serial clock
Serial data input
Serial data output
S
W
HOLD
Chip select
Write protect
Hold
VCC
Supply voltage
VSS
Ground
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Oct.04, 2010
Page 2 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Block Diagram
High voltage generator
C
HOLD
D
Memory array
Y-select & Sense amp.
Y
decoder
W
Address generator
S
Control logic
VSS
X
decoder
VCC
Serial-parallel converter
Q
Absolute Maximum Ratings
Parameter
Supply voltage relative to VSS
Input voltage relative to VSS
Operating temperature range*1
Storage temperature range
Symbol
VCC
VIN
Topr
Tstg
Value
−0.6 to +7.0
−0.3 to VCC +0.3
−40 to +85
−55 to +125
Unit
V
V
°C
°C
Notes: 1. Including electrical characteristics and data retention.
DC Operating Conditions
Parameter
Supply voltage
Input voltage
Operating temperature range
Symbol
VCC
VSS
VIH
VIL
Topr
Min
1.8
0
VCC × 0.7
−0.3
−40
Typ
0
Max
5.5
0
VCC + 0.3
VCC × 0.3
+85
Unit
V
V
V
V
°C
Capacitance
(Ta = +25°C, f = 1 MHz)
Parameter
Input capacitance (D,C, S, W ,HOLD)
Output capacitance (Q)
Note:
Symbol
1
Cin*
1
CI/O*
Min
Typ
Max
Unit
6.0
8.0
pF
pF
Test conditions
Vin = 0 V
Vout = 0 V
1. Not 100% tested.
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 3 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Memory cell characteristics
(VCC = 1.8 V to 5.5 V)
Ta=25°C
1,000k Cycles min.
100 Years min.
Endurance
Data retention
Ta=85°C
100k Cycles min.
10 Years min.
Notes
1
1
Notes: 1. Not 100% tested
Data at shipment
Memory array : “ 1 ” (FF Hex)
Status register SRWD, BP0, BP1: “ 0 ”
DC Characteristics
Parameter
Input leakage current
Symbol
ILI
Min
Max
2
Unit
µA
Output leakage current
ILO
2
µA
VCC = 5.5 V, VOUT = 0 to 5.5 V
(Q)
Standby
ISB
5
µA
VIN = VSS or VCC, S = VCC
VCC = 5.5 V
Active
ICC1
3
mA
VCC = 3.3 V, Read at 5 MHz
VIN = VCC × 0.1 / VCC × 0.9
Q = OPEN
5
mA
VCC = 5.5 V, Read at 5 MHz
VIN = VCC × 0.1 / VCC × 0.9
Q = OPEN
3
mA
VCC = 3.3 V, Write at 5 MHz
VIN = VCC × 0.1 / VCC × 0.9
5
mA
VCC × 0.8
VCC × 0.8
0.4
0.4
V
V
V
V
VCC = 5.5 V, Write at 5 MHz
VIN = VCC × 0.1 / VCC × 0.9
VCC = 2.5 to 5.5 V, IOL = 2 mA
VCC = 1.8 to 2.5 V, IOL = 1.5 mA
VCC = 2.5 to 5.5 V, IOH = −2 mA
VCC = 1.8 to 2.5 V, IOH= −0.4 mA
VCC current
ICC2
Output voltage
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
VOL1
VOL2
VOH1
VOH2
Test conditions
VCC = 5.5 V, VIN = 0 to 5.5 V
(S, D, C, HOLD, W)
Page 4 of 20
R1EX25512ASA00A/R1EX25512ATA00A
AC Characteristics
Test Conditions
• Input pulse levels:
VIL = VCC × 0.2
VIH = VCC × 0.8
• Input rise and fall time: ≤ 5 ns
• Input timing reference levels: VCC × 0.5
• Output reference levels: VCC × 0.5
• Output load: 1TTL Gate + 100 pF
(Ta = −40 to +85°C, VCC = 2.5 V to 5.5 V)
Parameter
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock high setup time before HOLD active
Clock high setup time before HOLD not
active
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output low-Z
HOLD low to output low-Z
Write time
Symbol
fC
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCHHL
Min
90
90
90
90
90
90
90
20
30
70
40
60
60
Max
5
1
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
Notes
tCHHH
Alt
fSCK
tCSS1
tCSS2
tCS
tCSH
tCLH
tCLL
tRC
tFC
tDSU
tDH
tSHQZ
tCLQV
tCLQX
tQLQH
tQHQL
tHHQX
tHLQZ
tW
tDIS
tV
tHO
tRO
tFO
tLZ
tHZ
tWC
0
100
60
50
50
50
100
5
ns
ns
ns
ns
ns
ns
ns
ms
2
1
1
2
2
2
2
2
2
Notes: 1. tCH + tCL ≥ 1/fC
2. Not 100% tested
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
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R1EX25512ASA00A/R1EX25512ATA00A
(Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock high setup time before HOLD active
Symbol
fC
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCHHL
Clock high setup time before HOLD not
active
Output disable time
tCHHH
Alt
fSCK
tCSS1
tCSS2
tCS
tCSH
tCLH
tCLL
tRC
tFC
tDSU
tDH
tSHQZ
tDIS
200
ns
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output low-Z
HOLD low to output low-Z
Write time
tCLQV
tCLQX
tQLQH
tQHQL
tHHQX
tHLQZ
tW
tV
0
150
100
100
100
100
5
ns
ns
ns
ns
ns
ns
ms
tHO
tRO
tFO
tLZ
tHZ
tWC
Min
100
100
250
100
100
150
150
30
50
200
200
120
120
Max
3
1
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
Notes
2
1
1
2
2
2
2
2
2
Notes: 1. tCH + tCL ≥ 1/fC
2. Not 100% tested
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Oct.04, 2010
Page 6 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Timing Waveforms
Serial Input Timing
tSHSL
S
tCHSL
tCHSH
tSHCH
tSLCH
C
tDVCH
D
tCHCL
tCLCH
tCHDX
MSB IN
LSB IN
High Impedance
Q
Hold Timing
S
tHHCH
tHLCH
tCHHL
C
tCHHH
D
tHLQZ
tHHQX
Q
HOLD
Output Timing
S
tSHQZ
tCH
C
tCL
D
ADDR
LSB IN
tCLQV
tCLQX
Q
tCLQX
tCLQV
LSB OUT
tQLQH
tQHQL
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Oct.04, 2010
Page 7 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Pin Function
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial
clock (C).
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to
be written. Values are latched on the rising edge of serial clock (C).
Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data
input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after the falling
edge of serial clock (C).
Chip select (S)
When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. Unless an
internal write cycle is in progress, the device will be in the standby mode. Driving chip select (S) low enables the
device, placing it in the active power mode. After power-up, a falling edge on chip select (S) is required prior to the
start of any instruction.
Hold (HOLD)
The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C)
are don’t care. To start the hold condition, the device must be selected, with chip select (S) driven low.
Write protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against write
instructions (as specified by the values in the BP1 and BP0 bits of the status register). This pin must be driven either
high or low, and must be stable during all write operations.
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Oct.04, 2010
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R1EX25512ASA00A/R1EX25512ATA00A
Functional Description
Status Register
The following figure shows the Status Register Format. The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific instructions.
Status Register Format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Disable
Block Protect Bits
Write Enable Latch Bits
Write In Progress Bits
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Write instructions. BP1, BP0 are “ 0 “ status at shipment.
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal.
The Status Register Write Disable (SRWD) bit and write protect (W) signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.
SRWD is “ 0 “ status at shipment.
Instructions
Each instruction starts with a single-byte code, as summarized in the following table. If an invalid instruction is sent
(one not contained in the following table), the device automatically deselects itself.
Instruction Set
Instruction
Description
WREN
WRDI
Write Enable
Write Disable
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Instruction Format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Page 9 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Write Enable (WREN):
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is
to send a Write Enable instruction to the device. As shown in the following figure, to send this instruction to the device,
chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then
enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high.
Write Enable (WREN) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
Q
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
1
2
3
4
5
6
7
VIH
VIL
Instruction
VIH
VIL
High-Z
Page 10 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Write Disable (WRDI):
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown
in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction
byte are shifted in, on serial data input (D).
The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. The
Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
Write Disable (WRDI) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
Q
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
1
2
3
4
5
6
7
VIH
VIL
Instruction
VIH
VIL
High-Z
Page 11 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Read Status Register (RDSR):
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at
any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is
recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also
possible to read the Status Register continuously, as shown in the following figure.
Read Status Register (RDSR) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
D
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
VIH
VIL
VIH
VIL
Status Register Out
Q
High-Z
7
6
5
4
3
2
1
0
7
The status and control bits of the Status Register are as follows:
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the
internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write or Write Status
Register instructions are accepted.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When
one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as defined in the Write Protect
Block Size table) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set.
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect (W) signal.
The Status Register Write Disable (SRWD) bit and write protect (W) signal allows the device to be put in the Hardware
Protected mode (When the Status Register Write Disable (SRWD) bit is set to 1, and write protect (W) signal is driven
low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write
Status Register (WRSR) instruction is no longer accepted for execution.
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R1EX25512ASA00A/R1EX25512ATA00A
Write Status Register (WRSR):
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The instruction sequence is
shown in the following figure. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of
the Status Register. b6, b5 and b4 are always read as 0. Chip select (S) must be driven high after the rising edge of
serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as chip select (S) is driven high, the
self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in
progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle
is completed, Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to
change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as
defined in the Status Register Format table.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable
(SRWD) bit in accordance with the write protect (W) signal. The Status Register Write Disable (SRWD) bit and write
protect (W) signal allows the device to be put in the Hardware Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current
values just before the start of the execution of the Write Status Register (WRSR) instruction. The new, updated values
take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction.
Write Status Register (WRSR) Sequence
S
W
VIH
VIL
VIH
VIL
0
C
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
VIH
VIL
Status Register In
D
VIH
VIL
Q
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Oct.04, 2010
7
6
5
4
3
2
1
0
MSB
High-Z
Page 13 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an
internal address register, and the byte of data at that address is shifted out, on serial data output (Q).
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of
data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued
indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at
any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted,
and is not executed, if a Write cycle is currently in progress.
Read from Memory Array (READ) Sequence
S
W
C
D
VIH
VIL
VIH
VIL
VIH
0
1
2
VIL
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
16-Bit Address
Instruction
VIH
15 14 13
3
2
1
0
VIL
Data Out 1
High-Z
Q
7
6
5
4
3
Data Out 2
2
1
0
7
Note: 1. The memory size is shown in the following table.
Address Range Bits
Device
Address bits
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R1EX25512A
A15 to A0
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R1EX25512ASA00A/R1EX25512ATA00A
Write to Memory Array (WRITE):
As shown in the following figures, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D).
The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case of the first
figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to
write a single byte. The self-timed Write cycle starts, and continues for a period tW (as specified in AC Characteristics).
At the end of the cycle, the Write In Progress (WIP) bit is reset to 0.
If, though, chip select (S) continues to be driven low, as shown in the second figure, the next byte of the input data is
shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be
written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the
number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the
beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these
device is 128 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
If a Write cycle is already in progress
If the device is deselected
If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Byte Write (WRITE) Sequence (1 Byte)
S
W
C
VIH
VIL
VIH
VIL
VIH
0
1
2
3
4
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
VIL
Instruction
D
5
VIH
16-Bit Address
15 14 13
3
2
Data Byte 1
1
0
7
6
5
4
3
2
1
0
VIL
Q
High-Z
Note: 1. The memory size is shown in the Address Range Bits table.
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R1EX25512ASA00A/R1EX25512ATA00A
Byte Write (WRITE) Sequence (Page)
S
W
C
VIH
VIL
VIH
VIL
0
VIH
1
2
3
4
5
6
7
8
9
16-Bit Address
VIH
15 14 13
W
C
2
1
0
7
6
5
4
3
2
1
1
0
0
High-Z
VIH
VIL
VIH
VIL
VIH
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
VIL
Data Byte 2
D
3
Data Byte 1
VIL
Q
S
20 21 22 23 24 25 26 27 28 29 30 31
VIL
Instruction
D
10
7
6
Q
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
High-Z
Note: 1. The memory size is shown in the Address Range Bits table.
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 16 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Data Protect
The protection features of the device are summarized in the following tables. When the Status Register Write Disable
(SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
whether write protect (W) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered,
depending on the state of write protect (W):
If write protect (W) is driven high, it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
If write protect (W) is driven low, it is not possible to write to the Status Register even if the Write Enable Latch
(WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status
Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory
area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also
hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
By setting the Status Register Write Disable (SRWD) bit after driving write protect (W) low.
By driving write protect (W) low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect (W) high.
If write protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
Write Protected Block Size
Status register bits
BP1
BP0
0
1
0
1
0
0
1
1
Protected blocks
None
Upper quarter
Upper half
Whole memory
Array addresses protected
R1EX25512A
None
C000h − FFFFh
8000h − FFFFh
0000h − FFFFh
Protection Modes
W signal
SRWD bit
1
0
0
0
1
1
0
1
Note:
Mode
Write protection of the
status register
Memory protect
1
Protected area*
Unprotected area*1
Software
Status register is writable Write protected
protected (SPM) (if the WREN instruction
has set the WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Ready to accept Write
instructions
Write protected
Hardware
Status register is
protected (HPM) hardware write
protected. The values in
the BP1 and BP0 bits
cannot be changed.
Ready to accept Write
instructions
1. As defined by the values in the Block Protected (BP1, BP0) bits of the Status Register, as shown in the Write
Protected Block Size table.
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 17 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Hold Condition
The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking
sequence.During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial
clock (C) are don’t care.To enter the hold condition, the device must be selected, with chip select (S) low.
Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device while it is in
the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to
reset any processes that had been in progress.
The hold condition starts when the hold (HOLD) signal is driven low at the same time as serial clock (C) already being
low (as shown in the following figure).The hold condition ends when the hold (HOLD) signal is driven high at the same
time as serial clock (C) already being low.
The following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock
(C) being low.
Hold Condition Activation
HOLD status
HOLD status
C
HOLD
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger and turn
the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power
on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly.
• S should be fixed to VCC during VCC on/off. Low to high or high to low transition during VCC on/off may
cause the trigger for the unintentional programming.
• VCC should be turned on/off after the EEPROM is placed in a standby state.
• VCC should be turned on from the ground level (VSS) in order for the EEPROM not to enter the unintentional
programming mode.
• VCC turn on rate should be slower than 2 µs/V.
• When WRSR or WRITE instruction is executed before VCC turns off, VCC should be turned off after waiting
write cycle time (tW).
• When setting the chip select signal (S) to the low level at power on, wait for 10 ms or longer after the supply
voltage 1.8V.
1.8V
(Vccmin)
Vcc
S
10ms min
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 18 of 20
R1EX25512ASA00A/R1EX25512ATA00A
Package Dimensions
R1EX25512ASA00A (PRSP0008DF-B / Previous Code: FP-8DBV)
JEITA Package Code
P-SOP8-3.9x4.89-1.27
RENESAS Code
PRSP0008DF-B
*1
Previous Code
FP-8DBV
D
8
MASS[Typ.]
0.08g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
5
*2
c
E
HE
bp
Reference
Symbol
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Min
Nom
Max
D
4.89
5.15
E
3.90
A2
1
Z
4
e
*3
A1
bp
x
0.14
L1
0.35
0.40
0.45
0.15
0.20
0.25
6.02
6.20
b1
c
A
c
A1
θ
L
y
Detail F
0.254
1.73
bp
1
θ
0°
HE
5.84
8°
1.27
e
x
0.25
y
0.10
Z
0.69
0.406
L
L
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
0.102
A
M
1
0.60
0.889
1.06
Page 19 of 20
R1EX25512ASA00A/R1EX25512ATA00A
R1EX25512ATA00A (PTSP0008JC-B / Previous Code: TTP-8DAV)
JEITA Package Code
P-TSSOP8-4.4x3-0.65
RENESAS Code
PTSP0008JC-B
*1
Previous Code
TTP-8DAV
MASS[Typ.]
0.034g
D
8
F
5
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
c
*2
E
HE
bp
Terminal cross section
( Ni/Pd/Au plating )
Reference Dimension in Millimeters
Symbol
Index mark
L1
1
e
*3
bp
x
M
θ
A1
A
Z
4
L
Detail F
y
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Min Nom Max
3.00 3.30
4.40
0.03 0.07 0.10
1.10
0.15 0.20 0.25
0.10 0.15 0.20
0°
8°
6.20 6.40 6.60
0.65
0.13
0.10
0.805
0.40 0.50 0.60
1.00
Page 20 of 20
Revision History
Rev.
1.00
2.00
Date
Jan. 15, 2010
Oct. 04, 2010
R1EX25512ASA00A/R1EX25512ATA00A Data Sheet
Description
Summary
Page
Initial issue
Apply to Renesas Electronics' new format and new document number.
Addition of 8-pin SOP package. Which product Type No. is R1EX25512ASA00A.
All trademarks and registered trademarks are the property of their respective owners.
C-1
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