Preliminary Datasheet
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, R01DS0029EJ0001
70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Rev.0.01
−V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E− RENESAS MCU
Sep 30, 2010
Description
The μPD70F3826, 70F3827, 70F3828, 70F3829 (V850ES/JF3-E), and μPD70F3830, 70F3831, 70F3832, 70F3833
(V850ES/JF3-E), and μPD70F3834, 70F3835, 70F3836, 70F3837 (V850ES/JG3-E) are products of the V850 32-bit
single-chip microcontrollers, and include peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an
A/D converter, a DMA controller , a CAN controller , a USB function controller , and a Ethernet controller.
In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/JE3-E,
V850ES/JF3-E, and V850ES/JG3-E include instructions executed via a hardware multiplier, saturation instructions, and
bit manipulation instructions.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850ES/JE3-E, V850ES/JF3-E, V850ES/JG3-E Hardware User’s Manual: To be prepared
V850ES Architecture User’s Manual:
U15943E
Features
{ Number of instructions: 83
{ Minimum instruction execution time:
20 ns (@ 50 MHz operation with main clock (fXX))
{ Clock
• Main clock oscillation: fX = 3 to 6.25 MHz
• Subclock oscillation: fXT = 32.768 kHz
• Internal oscillation: fR = 220 kHz (TYP.)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set:
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
{ Memory space:
64 MB linear address space
{ Internal memory
Flash memory: 64/128/256 KB
RAM:
32/48/64 KB
(Including 16 KB of data RAM area)
{ I/O lines Total: 26/42/62
{ Interrupts and exceptions
Non-maskable interrupts: 2 sources
Maskable interrupts:
63/78/85 sources
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
{ Timer/counters
16-bit timer/event counter AA (TAA): 5 channels
16-bit timer/event counter AB (TAB): 1 channel
Motor control function supported
16-bit interval timer M (TMM):
4 channels
16-bit encoder timer T (TMT):
1 channel
{ Real-time counter: 1 channel
{ Watchdog timer: 1 channel
{ Real-time output function: 6 channels
{ A/D converter: 10-bit resolution × 10/10 channels
{ Ethernet controller:
1 channel
{ USB function controller:
1 channel
{ Serial interface
• CAN :1 channel (μPD70F3829, 70F3833, 70F3837 only)
• Asynchronous serial interface C(UARTC): 3/4 channels
• Clocked serial interface F(CSIF):
2/3/5 channels
• I2C bus interface:
2/3 channels
{ DMA controller: 4 channels
{ Power save function:
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
{ On-chip debug function
{ Package: 64-pin LQFP (V850ES/JE3-E)
64-pin WQFN (V850ES/JE3-E)
80-pin LQFP (V850ES/JF3-E)
100-pin LQFP (V850ES/JG3-E)
113-pin FBGA (Under planing)
{ Operating supply voltage: 2.85 to 3.6 V
Page 1 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Function list (V850ES/JE3-E)
Generic Name
V850ES/JE3-E
Product Name
Internal
μPD70F3826
μPD70F3827
μPD70F3828
μPD70F3829
Flash memory
memory Internal RAM
Data RAM
64 KB
128 KB
256 KB
256 KB
16 KB
32 KB
48 KB
48 KB
16 KB
16 KB
16 KB
16 KB
Memory space
64 MB
General-purpose register
32 bits × 32 registers
Clocks
PLL mode : fX = 3 to 6.25 MHz, fXX = 24 to 50 MHz (multiplication by 8)
Main clock oscillation
Clock through mode : fX = 3 to 6.25 MHz ( internal : fXX = 3 to 6.25 MHz)
Subclock oscillation
fXT = 32.768 kHz
Internal oscillation
fR = 220 kHz (TYP.)
Minimum instruction
20 ns (@ 50 MHz operation with main system clock (fXX))
execution time
I/O ports
Timer
I/O: 26 (5 V tolerant : 12)
16-bit TAA
5 channels (among which two channels have the interval function only)
−
16-bit TAB
16-bit TMM
4 channels
16-bit TMT
1 channel (Interval function only)
−
Motor control
Watch timer
1 channel (RTC)
WDT
1 channel
Real-time output function
6 bits × 1 channel
10-bit A/D converter
10 channels
Serial
CSIF/UARTC
interface
CSIF/UARTC/I C
1 channel
2
1 channel
−
CSIF
2
UARTC/I C
−
1 channel
−
2
UARTC/I C/CAN
USB function
1 channel
Ethernet controller
1 channel
DMA controller
Interrupt
External
source
Internal
1 channel
4 channels (transfer target: on-chip peripheral I/O, internal RAM)
Note 1, 2
Power-save function
7(7)
7(7)
7(7)
7(7)
54
54
54
58
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE modes
Reset factor
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
On-chip debugging
MINICUBE , MINICUBE2 supported
Operating supply voltage
2.85 to 3.6 V
®
Operating ambient temperature
−40 to +85°C
Package
64-pin plastic LQFP (fine pitch) (10 × 10 mm), 64-pin plastic WQFN (9 × 9 mm),
Notes 1. The figure in parentheses indicates the number of external interrupts that can release the STOP mode.
Notes 2. Include NMI.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 2 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Function list (V850ES/JF3-E)
Generic Name
V850ES/JF3-E
Product Name
Internal
μPD70F3830
μPD70F3831
μPD70F3832
μPD70F3833
Flash memory
memory Internal RAM
Data RAM
64 KB
128 KB
256 KB
256 KB
16 KB
32 KB
48 KB
48 KB
16 KB
16 KB
16 KB
16 KB
Memory space
64 MB
General-purpose register
32 bits × 32 registers
Clocks
PLL mode : fX = 3 to 6.25 MHz, fXX = 24 to 50 MHz (multiplication by 8)
Main clock oscillation
Clock through mode : fX = 3 to 6.25 MHz ( internal : fXX = 3 to 6.25 MHz)
Subclock oscillation
fXT = 32.768 kHz
Internal oscillation
fR = 220 kHz (TYP.)
Minimum instruction
20 ns (@ 50 MHz operation with main system clock (fXX))
execution time
I/O ports
Timer
I/O: 42 (5 V tolerant : 28)
16-bit TAA
5 channels
16-bit TAB
1 channel
16-bit TMM
4 channels
16-bit TMT
1 channel
Motor control
1 channel
Watch timer
1 channel (RTC)
WDT
1 channel
Real-time output function
6 bits × 1 channel
10-bit A/D converter
10 channels
Serial
CSIF/UARTC
interface
CSIF/UARTC/I C
1 channel
2
2 channels
−
CSIF
2
UARTC/I C
−
1 channel
−
2
UARTC/I C/CAN
USB function
1 channel
Ethernet controller
1 channel
DMA controller
Interrupt
External
source
Internal
1 channel
4 channels (transfer target: on-chip peripheral I/O, internal RAM)
Note 1, 2
Power-save function
19(19)
19(19)
19(19)
19(19)
57
57
57
61
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE modes
Reset factor
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
On-chip debugging
MINICUBE, MINICUBE2 supported
Operating supply voltage
2.85 to 3.6 V
Operating ambient temperature
−40 to +85°C
Package
80-pin plastic LQFP (fine pitch) (12 × 12 mm)
Notes 1. The figure in parentheses indicates the number of external interrupts that can release the STOP mode.
Notes 2. Include NMI.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 3 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
Function list (V850ES/JG3-E)
Generic Name
V850ES/JG3-E
Product Name
Internal
μPD70F3834
μPD70F3835
μPD70F3836
μPD70F3837
Flash memory
memory Internal RAM
Data RAM
64 KB
128 KB
256 KB
256 KB
16 KB
32 KB
48 KB
48 KB
16 KB
16 KB
16 KB
16 KB
Memory space
64 MB
General-purpose register
32 bits × 32 registers
Clocks
PLL mode : fX = 3 to 6.25 MHz, fXX = 24 to 50 MHz (multiplication by 8)
Main clock oscillation
Clock through mode : fX = 3 to 6.25 MHz ( internal : fXX = 3 to 6.25 MHz)
Subclock oscillation
fXT = 32.768 kHz
Internal oscillation
fR = 220 kHz (TYP.)
Minimum instruction
20 ns (@ 50 MHz operation with main system clock (fXX))
execution time
I/O ports
I/O: 62 (5 V tolerant : 35)
Timer
16-bit TAA
5 channels
16-bit TAB
1 channel
16-bit TMM
4 channels
16-bit TMT
1 channel
Motor control
1 channel
Watch timer
1 channel (RTC)
WDT
1 channel
Real-time output function
6 bits × 1 channel
10-bit A/D converter
10 channels
Serial
CSIF/UARTC
interface
CSIF/UARTC/I C
1 channel
2 channels
CSIF
2 channels
2
2
UARTC/I C
−
1 channel
−
2
UARTC/I C/CAN
USB function
1 channel
Ethernet controller
1 channel
DMA controller
Interrupt
External
source
Internal
1 channel
4 channels (transfer target: on-chip peripheral I/O, internal RAM)
Note 1, 2
Power-save function
22(22)
22(22)
22(22)
22(22)
61
61
61
65
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE modes
Reset factor
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
On-chip debugging
MINICUBE, MINICUBE2 supported
Operating supply voltage
2.85 to 3.6 V
Operating ambient temperature
−40 to +85°C
Package
100-pin plastic LQFP (fine pitch) (14 × 14 mm), 113-pin plastic FBGA
Note3
Notes 1. The figure in parentheses indicates the number of external interrupts that can release the STOP mode.
Notes 2. Include NMI.
3. Under planning.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 4 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
APPLICATIONS
{ Applications that require Ethernet controller
Home audio, printers, and scanners.
ORDERING INFORMATION
• V850ES/JE3-E
Part Number
μPD70F3826GB-GAH-AX
μPD70F3827GB-GAH-AX
μPD70F3828GB-GAH-AX
μPD70F3829GB-GAH-AX
μPD70F3826K8-6B4-AX
μPD70F3827K8-6B4-AX
μPD70F3828K8-6B4-AX
μPD70F3829K8-6B4-AX
Package
On-Chip Flash Memory
64-pin plastic LQFP (fine pitch) (10 × 10)
64 KB
64-pin plastic LQFP (fine pitch) (10 × 10)
128 KB
64-pin plastic LQFP (fine pitch) (10 × 10)
256 KB
64-pin plastic LQFP (fine pitch) (10 × 10)
256 KB
64-pin plastic WQFN (9 × 9)
64 KB
64-pin plastic WQFN (9 × 9)
128 KB
64-pin plastic WQFN (9 × 9)
256 KB
64-pin plastic WQFN (9 × 9)
256 KB
• V850ES/JF3-E
Part Number
μPD70F3830GK-GAK-AX
μPD70F3831GK-GAK-AX
μPD70F3832GK-GAK-AX
μPD70F3833GK-GAK-AX
Package
On-Chip Flash Memory
80-pin plastic LQFP (fine pitch) (12 × 12)
64 KB
80-pin plastic LQFP (fine pitch) (12 × 12)
128 KB
80-pin plastic LQFP (fine pitch) (12 × 12)
256 KB
80-pin plastic LQFP (fine pitch) (12 × 12)
256 KB
• V850ES/JG3-E
Part Number
μPD70F3834GC-UEU-AX
μPD70F3835GC-UEU-AX
μPD70F3836GC-UEU-AX
μPD70F3837GC-UEU-AX
μPD70F3837F1-CAH-AXNote
Package
64 KB
100-pin plastic LQFP (fine pitch) (14 × 14)
128 KB
100-pin plastic LQFP (fine pitch) (14 × 14)
256 KB
100-pin plastic LQFP (fine pitch) (14 × 14)
256 KB
113-pin plastic FBGA (8 × 8)
256 KB
Note
Under planning
Remark
The V850ES/Jx3-E microcontrollers are lead-free products.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
On-Chip Flash Memory
100-pin plastic LQFP (fine pitch) (14 × 14)
Page 5 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
PIN CONFIGURATION
• V850ES/JE3-E
64-pin plastic LQFP (fine pitch) (10 × 10)
8
X2
9
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P42/SCKF0/TIAA40/TOAA40/RTP02
P41/SOF0/RXDC3/SCL01/RTP01
P40/SIF0/TXDC3/SDA01/RTP00
P37/RXDC2/SCL02(/CRXD0Note3)
P36/TXDC2/SDA02(/CTXD0Note3)
PDL5/FLMD1
62
61
60
59
58
57
56
55
54
53
52
51
50
49
14
15
26
27
28
29
30
31
32
P1TXD1
P1TXD2
P1TXD3
P1TXER
P1TXEN
P1TXCLK
EVDD
25
24
VSS
23
UVDD
P1TXD0
22
16
UDPF
P50/INTP07/DDI
13
21
P32/ASCKC0/SCKF2/TIAA10/TOAA10
12
20
P30/TXDC0/SIF2/TIAA00/TOA00
P31/RXDC0/SOF2/TIAA01/TOAA01
11
UDMF
XT2
10
P54/INTP11/DRST
XT1
P70/ANI0
7
X1
RESET
63
6
P53/INTP10/DMS
VSS
5
19
REGC
4
18
VDD
Note2
3
17
P02/NMI
P20/INTP01
2
P52/INTP09/DCK
AVSS
1
P51/INTP08/DDO
AVREF0
μPD70F3827GB-GAH-AX
μPD70F3829GB-GAH-AX
64
μPD70F3826GB-GAH-AX
μPD70F3828GB-GAH-AX
48
P1MDIO
47
P1MDC
46
P1COL
45
P1CRS
44
EVDD
43
VSS
42
FLMD0Note1
41
REGCNote2
40
VDD
39
P1RXCLK
38
P1RXER
37
P1RXDV
36
P1RXD3
35
P1RXD2
34
P1RXD1
33
P1RXD0
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7 μF (preliminary value) capacitor.
3. μ PD70F3829 only.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 6 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
• V850ES/JE3-E
64-pin plastic WQFN (9 × 9)
6
VSS
7
X1
8
X2
9
P36/TXDC2/SDA02(/CTXD0Note3)
PDL5/FLMD1
50
49
P79/ANI9
55
P37/RXDC2/SCL02(/CRXD0Note3)
P78/ANI8
56
P40/SIF0/TXDC3/SDA01/RTP00
P77/ANI7
57
51
P76/ANI6
58
P41/SOF0/RXDC3/SCL01/RTP01
P75/ANI5
59
52
P74/ANI4
60
53
P73/ANI3
61
P42/SCKF0/TIAA40/TOAA40/RTP02
P72/ANI2
62
54
P71/ANI1
14
15
22
23
24
25
26
27
28
29
30
31
32
UVDD
EVDD
VSS
P1TXD0
P1TXD1
P1TXD2
P1TXD3
P1TXER
P1TXEN
P1TXCLK
16
UDPF
P50/INTP07/DDI
13
21
P31/RXDC0/SOF2/TIAA01/TOAA01
P32/ASCKC0/SCKF2/TIAA10/TOAA10
12
20
P30/TXDC0/SIF2/TIAA00/TOA00
11
UDMF
XT2
10
P54/INTP11/DRST
XT1
19
RESET
P70/ANI0
5
Note2
REGC
63
4
P53/INTP10/DMS
VDD
3
18
P20/INTP01
2
17
P02/NMI
exposed die pad
P52/INTP09/DCK
AVSS
1
P51/INTP08/DDO
AVREF0
μPD70F3827K8-6B4-AX
μPD70F3829K8-6B4-AX
64
μPD70F3826K8-6B4-AX
μPD70F3828 K8-6B4-AX
48
P1MDIO
47
P1MDC
46
P1COL
45
P1CRS
44
EVDD
43
VSS
42
FLMD0Note1
41
REGCNote2
40
VDD
39
P1RXCLK
38
P1RXER
37
P1RXDV
36
P1RXD3
35
P1RXD2
34
P1RXD1
33
P1RXD0
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7 μF (preliminary value) capacitor.
3. μ PD70F3829 only.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 7 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
• V850ES/JF3-E
80-pin plastic LQFP (fine pitch) (12 × 12)
P94/TOAB1T3/TIAB13/KR4/INTP15
P95/TOAB1B3/EVTAB1/KR5/INTP16
P912/TOAB1OFF/INTP18
PDL5/FLMD1
P35/TIAA21/TOAA21/TOAA1OFF/INTP06
P37/RXDC2/SCL02(/CRXD0Note3)
P36/TXDC2/SDA02(/CTXD0Note3)
P40/SIF0/TXDC3/SDA01/RTP00
P41/SOF0/RXDC3/SCL01/RTP01
P42/SCKF0/TIAA40/TOAA40/RTP02
P79/ANI9
P78/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
μPD70F3831GK-GAK-AX
μPD70F3833GK-GAK-AX
P71/ANI1
P70/ANI0
μPD70F3830GK-GAK-AX
μPD70F3832GK-GAK-AX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
54
P1COL
X1
8
53
P1CRS
X2
9
52
EVDD
RESET
10
51
EVSS
XT1
11
50
FLMD0Note1
XT2
12
49
REGCNote2
P23/SIF1/TXDC1/SDA00/INTP03
13
48
VDD
P24/SOF1/RXDC1/SCL00/INTP04
14
47
P1RXCLK
P25/SCKF1/TIAA30/TOAA30
15
46
P1RXER
P26/TIAA31/TOA31/INTP05
16
45
P1RXDV
P30/TXDC/SIF2/TIAA00/TOAA00
17
44
P1RXD3
P31/RXDC0/SOF2/TIAA01/TOAA01
18
43
P1RXD2
P32/ASCKC0/SCKF2/TIAA10/TOAA10
19
42
P1RXD1
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P1RXD0
P51/INTP08/DDO
P50/INTP07/DDI
P1TXCLK
7
P1TXEN
P1MDC
VSS
P1TXER
55
P1TXD3
6
P1TXD2
P1MDIO
REGCNote2
P1TXD1
56
P1TXD0
5
P98/TEC01/INTP17
P90/TOAB1T1/TOAB11/TIAB11/KR0/INTP12
VDD
P97/TENC00/TIT01/KR7/TOT01
57
P96/TECR0/TIT00/KR6/TOT00
4
VSS
P91/TOAB1B1/TIAB10/KR/TOAB10
P20/INTP01
EVDD
58
UVDD
3
UDPF
P92/TOAB1T2/TOAB12/TIAB12/KR2/INTP13
P02/NMI
UDMF
59
P913/INTP19
P93/TOAB1B2/TRGAB1/KR3/INTP14
2
P54/INTP11/DRST
60
AVss
P53/INTP10/DMS
1
P52/INTP09/DCK
AVREF0
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7 μF (preliminary value) capacitor.
3. μ PD70F3833 only.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 8 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
• V850ES/JG3-E
100-pin plastic LQFP (fine pitch) (14 × 14)
μPD70F3835GC-UEU-AX
μPD70F3837GC-UEU-AX
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P45/TIAA41/TOAA41/RTP05
P44/RTP04
P43/RTP03
P42/SCKF0/TIAA40/TOAA40/RTP02
P41/SOF0/RXDC3/SCL01/RTP01
P40/SIF0/TXDC3/SDA01/RTP00
PDL7
PDL6
P37/RXDC2/SCL2(/CRXD0Note3)
P36/TXDC2/SDA2(/CTXD0Note3)
P35/SCKF4/TIAA21/TOAA21/TOAA1OFF/INTP06
PDL5/FLMD1
P912/TOAB1OFF/INTP18
P95/TOAB1b3/EVTAB1/KR5/INTP16
P94/TOAB1t3/TOAB13/TIAB13/KR4/INTP15
μPD70F3834GC-UEU-AX
μPD70F3836GC-UEU-AX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P93/TOAB1B2/TRGAB1/KR3/INTP14
P92/TOAB1T2/TOAB12/TIAB12/KR2/INTP13
P91/TOAB1B1/TIAB10/KR1/TOAB10
P90/TOAB1T1/TOAB11/TIAB11/KR0/INTP12
P1MDIO
P1MDC
P1COL
P1CRS
PDL4
PDL3
EVDD
VSS
FLMD0Note1
REGCNote2
VDD
PDL2
PDL1
PDL0
P1RXCLK
P1RXER
P1RXDV
P1RXD3
P1RXD2
P1RXD1
P1RXD0
P51/INTP08/DDO
P52/INTP09/DCK
P53/INTP10/DMS
P54/INTP11/DRST
P913/SIF3/INTP19
P914/SOF3/INTP20
P915/SCKF3
PDL8
PDL9
UDMF
UDPF
UVDD
EVDD
VSS
P96/TECR0/TIT00/KR6/TOT00
P97/TENC00/TIT01/KR7/TOT01
P98/TENC01/INTP17
PDL10
P1TXD0
P1TXD1
P1TXD2
P1TXD3
P1TXER
P1TXEN
P1TXCLK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AVREF0
AVSS
P02/NMI
P03/INTP00/ADTRG/EXCLK
P20/INTP01
P21/RTCDIV/RTCCL
P22/RTC1HZ/INTP02
VDD
REGCNote2
VSS
X1
X2
RESET
XT1
XT2
P23/SIF1/TXDC1/SDA00/INT03
P24/SOF1/RXDC1/SCL00/INTP04
P25/SCKF1/TIA30/TOAA30
P26/TIAA31/TOAA31/INTP05
P30/TXDC0/SIF2/TIAA00/TOA00
P31/RXDC0/SOF2/TIAA01/TOAA01
P32/ASCKC0/SCKF2/TIAA10/TOAA10
P33/SIF4/TIA11/TOAA11
P34/SOF4/TIAA20/TOAA20
P50/INTP07/DDI
Notes 1. Connect to VSS in normal mode.
2. Connect the REGC pin to VSS via a 4.7 μF (preliminary value) capacitor.
3. μ PD70F3837 only.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 9 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
PIN IDENTIFICATION
ADTRG:
A/D Trigger Input
RXDC0 to RXDC3
Receive Data
ANI0 to ANI9:
Analog Input
SCKF0 to SCKF4:
Serial Clock
ASCKC0:
Asynchronous Serial Clock
SCL00 to SCL02:
Serial Clock
AVREF0:
Analog Reference Voltage
SDA00 to SDA02:
Serial Data
AVSS:
Grand for Analog Pin
SIF0 to SIF4:
Serial Input
CRXD0:
CAN Receive Data
SOF0 to SOF4:
Serial Output
CTXD0:
CAN Transmit Data
TECR0:
Timer Encoder Clear Input
DCK:
Debug Clock
TENC00, TENC01:
Timer Encoder Input
DDI:
Debug Data Input
TIAA00, TIAA01,
Timer Input
DDO:
Debug Data Output
TIAA10, TIAA11,
DMS:
Debug Mode Select
TIAA20, TIAA21,
DRST:
Debug Reset
TIAA30, TIAA31,
EVDD:
Power Supply for External Pin
TIAA40, TIAA41,
EVTAB1:
Timer Event Count Input
TIAB10 to TIAB13,
EXCLK
USB clock
TIT00, TIT01:
FLMD0, FLMD1:
Flash Programming Mode
TOAA00, TOAA01,
INTP00 to INTP20:
External Interrupt Input
TOAA10, TOAA11,
KR0 to KR7:
Key Return
TOAA20, TOAA21,
NMI:
Non-maskable Interrupt Request
TOAA30, TOAA31,
P02, P03:
Port0
TOAA40, TOAA41,
P1COL, P1CRS,
Ethernet PHY Interface
TOAB10 to TOAB13,
Timer Output
P1MDC, P1MDIO,
TOAB1B1 to TOAB1B3,
P1RXCLK,
TOAB1T1 to TOAB1T3,
P1RXD0 to P1RXD3,
TOT00, TOT01:
P1RXDV, P1RXER
TOAA1OFF,
P1TXCLK,
TOAB1OFF
P1TXD0 to P1TXD3,
TRGAB1:
Timer Trigger Input
P1TXEN, P1TXER:
TXDC0 to TXDC3:
Serial Output
Timer Output Off
P20 to P26
Port2
UDMF:
USB Data I/O (-) Function
P30 to P37:
Port3
UDPF:
USB Data I/O (+) Function
P40 to P45:
Port4
UVDD:
Power Supply for External USB
P50 to P54:
Port5
VDD:
Power Supply
P70 to P79:
Port7
VSS:
Ground
P90 to P98,
Port9
X1, X2:
Crystal for Main Clock
XT1, XT2:
Crystal for Sub-clock
P912 to P915:
PDL0 to PDL10:
Port DL
REGC:
Regulator Control
RESET:
Reset
RTC1HZ, RTCCL,
Real-time Counter Clock Output
RTCDIV:
RTP00 to RTP05:
Real-time Output Port
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 10 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
INTERNAL BLOCK DIAGRAM
• V850ES/JE3-E
TIMER / COUNTER FUNCTION
16-bit timer
counter AB
: 1 ch
ROM
RAM
Note1
Note2
USB
function
CPU
PC
Multiplier
16 × 16 → 32
TIAA00, TIAA10, TIAA40,
TIAA01
TOAA00, TOAA10, TOAA40,
TOAA01
Ethernet
controller
DMA
16-bit
timer/event
counter AA
: 5 ch
32-bit
barrel shifter
BCU
System
registers
ALU
General-purpose
registers 32 bits × 32
16-bit
interval timer M
: 4 ch
16-bit
timer counter T
: 1 ch
Ports
A/D
converter
SERIAL INTERFACE FUNCTION
RXDC0, RXDC2, RXDC3
TXDC0, TXDC2, TXDC3
ASCKC0
SIF0, SIF2
SOF0, SOF2
SCKF0, SCKF2
SDA01, SDA02
SCL01, SCL02
UARTC
: 3 ch
CSIF
: 2 ch
NMI
INTP01,
INTP07 to INTP11
X1
X2
XT1
XT2
RESET
Flash
controller
Regulator
FLMD0
FLMD1
VDD
REGC
EVDD
IIC0
: 2 ch
UVDD
DEBUG FUNCTION
CRXD0
CTXD0
PLL
AVREF0
AVSS
ANI0 to ANI9
INTERRUPT FUNCTION
INTC
CLKOUT
CG
P02
P20
P40 to P42
P30 to P32, P36, P37
RTO
P50 to P54
RTP00 to RTP05
P70 to P79
RTC
PDL5
WDT
VSS
DRST
CANNote 3
: 1 ch
DMS
DCU
DDI
DCK
DDO
Notes 1. μPD70F3826:
μPD70F3827:
μPD70F3828, 70F3829:
2. μPD70F3826:
μPD70F3827:
μPD70F3828, 70F3829:
3. μPD70F3829 only.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
64 KB
128 KB
256 KB
32 KB (Including 16 KB of data RAM)
48 KB (Including 16 KB of data RAM)
64 KB (Including 16 KB of data RAM)
Page 11 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
• V850ES/JF3-E
TIMER / COUNTER FUNCTION
TIAB10 to TIAB13,
EVTAB1,
TRGAB1,
TOAB1OFF
TOAB10 to TOAB13
16-bit
timer/event
counter AB
: 1 ch
RAM
Note1
Note2
Ethernet
controller
DMA
USB
function
CPU
PC
Multiplier
16 × 16 → 32
TOAB1T1 to TOAB1T3,
TOAB1B1 to TOAB1B3
TIAA00, TIAA10, TIAA30, TIAA40,
TIAA01, TIAA21, TIAA31,
TOAA1OFF
TOAA00, TOAA10, TOAA30, TOAA40,
TOAA01, TOAA21, TOAA31,
ROM
16-bit
timer/event
counter AA
: 5 ch
32-bit
barrel shifter
BCU
System
registers
ALU
General-purpose
registers 32 bits × 32
16-bit
interval timer M
: 4 ch
TOT00, TOT01
16-bit
timer/counter T
: 1 ch
Ports
A/D
converter
RXDC0 to RXDC3
TXDC0 to TXDC3
ASCKC0
UARTC
: 4 ch
SIF0 to SIF2
SOF0 to SOF2
SCKF0 to SCKF2
CSIF
: 3 ch
SDA00 to SDA02
SCL00 to SCL02
IIC0
: 3 ch
INTERRUPT FUNCTION
INTC
Key interrupt
function
NMI
INTP01,
INTP03 to INTP19
PLL
X1
X2
XT1
XT2
RESET
Flash
controller
Regulator
FLMD0
FLMD1
VDD
REGC
KR0 to KR7
EVDD
UVDD
DEBUG FUNCTION
CRXD0
CTXD0
CLKOUT
CG
P02
P20, P22 to P26
P40 to P42
P30 to P32, P35 to P37
SERIAL INTERFACE FUNCTION
P50 to P54
RTO
P70 to P79
RTP00 to RTP05
P90 to P98, P912, P913
RTC
PDL5
WDT
AVREF0
AVSS
ANI0 to ANI9
TECR0, TENC00, TENC01,
EVTT0, TIT00, TIT01
VSS
DRST
CANNote 3
: 1 ch
DMS
DCU
DDI
DCK
DDO
Notes 1. μPD70F3830:
μPD70F3831:
μPD70F3832, 70F3833:
2. μPD70F3830:
μPD70F3831:
μPD70F3832, 70F3833:
3. μPD70F3833 only.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
64 KB
128 KB
256 KB
32 KB (Including 16 KB of data RAM)
48 KB (Including 16 KB of data RAM)
64 KB (Including 16 KB of data RAM)
Page 12 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
• V850ES/JG3-E
TIMER / COUNTER FUNCTION
TIAB10 to TIAB13,
EVTAB1,
TRGAB1,
TOAB1OFF
TOAB10 to TOAB13
16-bit
timer/event
counter AB
: 1 ch
RAM
Note1
Note2
Ethernet
controller
DMA
USB
function
CPU
PC
Multiplier
16 × 16 → 32
TOAB1T1 to TOAB1T3,
TOAB1B1 to TOAB1B3
TIAA00 to TIAA40,
TIAA01 to TIAA41,
TOAA1OFF
TOAA00 to TOAA40,
TOAA01 to TOAA41
ROM
16-bit
timer/event
counter AA
: 5 ch
EXCLK
32-bit
barrel shifter
BCU
System
registers
ALU
General-purpose
registers 32 bits × 32
16-bit
interval timer M
: 4 ch
TOT00, TOT01
16-bit
timer/counter T
: 1 ch
Ports
A/D
converter
SERIAL INTERFACE FUNCTION
RXDC0 to RXDC3
TXDC0 to TXDC3
ASCKC0
UARTC
: 4 ch
SIF0 to SIF4
SOF0 to SOF4
SCKF0 to SCKF4
CSIF
: 5 ch
SDA00 to SDA02
SCL00 to SCL02
IIC0
: 3 ch
P02, P03
P20 to P26
P30 to P37
P40 to P45
P50 to P54
RTO
P70 to P79
RTP00 to RTP05
RTC
P90 to P98, P912 to P915
RTC1HZ
RTCCL
RTCDIV
PDL0 to PDL15
WDT
X2
XT1
XT2
RESET
Flash
controller
FLMD0
FLMD1
INTP00 to INTP20
Regulator
Key interrupt
function
X1
NMI
VDD
REGC
KR0 to KR7
EVDD
UVDD
DEBUG FUNCTION
CRXD0
CTXD0
PLL
CG
INTERRUPT FUNCTION
INTC
CLKOUT
AVREF0
AVSS
ANI0 to ANI9
TECR0, TENC00, TENC01,
EVTT0, TIT00, TIT01
VSS
DRST
CANNote 3
: 1 ch
DMS
DCU
DDI
DCK
DDO
Notes 1. μPD70F3834:
μPD70F3835:
μPD70F3836, 70F3837:
2. μPD70F3834:
μPD70F3835:
μPD70F3836, 70F3837:
3. μPD70F3837 only.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
64 KB
128 KB
256 KB
32 KB (Including 16 KB of data RAM)
48 KB (Including 16 KB of data RAM)
64 KB (Including 16 KB of data RAM)
Page 13 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
CONTENTS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
PIN FUNCTIONS ................................................................................................. 15
1.1
Port Pins.................................................................................................... 15
1.2
Non-Port Pins............................................................................................ 17
1.3
Pin I/O Circuits and Recommended Connection of Unused Pins............. 22
CPU FUNCTIONS ............................................................................................... 26
MEMORY MAP .................................................................................................... 27
PORTS.................................................................................................................. 29
CLOCK GENERATION FUNCTION ................................................................... 30
16-BIT TIMER/EVENT COUNTER AA (TAA)................................................... 32
16-BIT TIMER/EVENT COUNTER AB (TAB)................................................... 34
16-BIT TIMER/EVENT COUNTER T (TMT) ..................................................... 36
16-BIT INTERVAL TIMER M (TMM)................................................................. 38
MOTOR CONTROL FUNCTION ........................................................................ 39
REAL-TIME COUNTER ........................................................................................ 41
WATCHDOG TIMER 2 FUNCTIONS ................................................................ 43
REAL-TIME OUTPUT FUNCTION (RTO) ......................................................... 44
A/D CONVERTER ............................................................................................... 45
ASYNCHRONOUS SERIAL INTERFACE C (UARTC) .................................... 47
CLOCKED SERIAL INTERFACE F (CSIF) ......................................................... 49
I2C BUS ................................................................................................................ 51
CAN CONTROLLER............................................................................................. 53
USB FUNCTION CONTROLLER (USBF) ............................................................ 54
ETHERNET CONTROLLER ................................................................................. 55
DMA CONTROLLER ........................................................................................... 56
INTERRUPT/EXCEPTION PROCESSING FUNCTION..................................... 58
KEY INTERRUPT FUNCTION (V850ES/JF3-E, V850ES/JG3-E)...................... 62
STANDBY FUNCTION ........................................................................................ 63
RESET FUNCTIONS ........................................................................................... 64
CLOCK MONITOR, LOW-VOLTAGE DETECTOR ........................................... 65
CRC FUNCTIONS ............................................................................................... 66
REGULATOR FUNCTION ................................................................................... 67
FLASH MEMORY ................................................................................................ 68
ON-CHIP DEBUG FUNCTION ........................................................................... 69
PACKAGE DRAWINGS....................................................................................... 70
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 14 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
1. PIN FUNCTIONS
1.1 Port Pins
(1/2)
Pin
I/O
Function
Alternate Function
Name
Pin number
JE3-E
JF3-E
JG3-E
NMI
3
3
3
INTP00/ADTRG/EXCLK
−
−
4
Port 2
INTP01
4
4
5
7-bit I/O port(V850ES/JG3-E)
RTGDIV/RTCCL
−
−
6
RTC1HZ/INTP02
−
−
7
SIF1/TXDC1/SDA00/INTP03
−
13
16
P24
SOF1/RXDC1/SDL00/INTP04
−
14
17
P25
SCKF1/TIAA30/TOAA30
−
15
18
P02
I/O
Port 0
2-bit I/O port(V850ES/JG3-E)
P03
1-bit I/O port(V850ES/JE3-E, V850ES/JF3-E)
Input/output can be specified in 1-bit units.
P20
I/O
P21
5-bit I/O port(V850ES/JF3-E)
P22
1-bit I/O port(V850ES/JE3-E)
P23
Input/output can be specified in 1-bit units.
TIAA31/TOAA31/INTP05
−
16
19
Port 3
TXDC0/SIF2/TIAA00/TOAA00
13
17
20
8-bit I/O port(V850ES/JG3-E)
RXDC0/SOF2/TIAA01/TOAA01
14
18
21
ASCKC0/SCKF2/TIAA10/TOAA10
15
19
22
P26
P30
I/O
P31
6-bit I/O port(V850ES/JF3-E)
P32
5-bit I/O port(V850ES/JE3-E)
SIF4/TIAA11/TOAA11
−
−
23
P34
SOF4/TIAA20/TOAA20
−
−
24
P35
SCKF4/TIAA21/TOAA21
−
−
80
P33
Input/output can be specified in 1-bit units.
/TOAA1OFF/INTP06
−
65
−
Note
50
66
81
Note
51
67
82
TIAA21/TOAA21/TOAA1OFF/INTP06
P36
TXDC2/SDA02/CTXD0
P37
RXDC2/SCL02/CRXD0
P40
I/O
P41
Port 4
SIF0/TXDC3/SDA01/RTP00
52
68
85
6-bit I/O port(V850ES/JG3-E)
SOF0/RXDC3/SCL01/RTP01
53
69
86
3-bit I/O port(V850ES/JE3-E, V850ES/JF3-E)
P42
SCKF0/TIAA40/TOAA40/RTP02
54
70
87
P43
RTP03
−
−
88
P44
RTP04
−
−
89
P45
TIAA41/TOAA41/RTP05
−
−
90
P50
P51
P52
Input/output can be specified in 1-bit units.
I/O
Port 5
INTP07/DDI
16
20
25
5-bit I/O port
INTP08/DDO
17
21
26
INTP09/DCK
18
22
27
INTP10/DMS
19
23
28
INTP11/DRST
20
24
29
Input/output can be specified in 1-bit units.
P53
P54
Note
Available only in on-chip CAN controller products
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 15 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
(2/2)
Pin
I/O
Function
Alternate Function
Name
JF3-E
JG3-E
Port 7
ANI0
64
80
100
10-bit I/O port
ANI1
63
79
99
ANI2
62
78
98
P73
ANI3
61
77
97
P74
ANI4
60
76
96
P75
ANI5
59
75
95
P76
ANI6
58
74
94
P77
ANI7
57
73
93
P78
ANI8
56
72
92
P79
ANI9
55
71
91
TOAB1T1/TOAB11/TIAB11/KR0/INTP12
−
57
72
P70
I/O
Pin number
JE3-E
P71
Input/output can be specified in 1-bit units.
P72
P90
I/O
Port 9
13-bit I/O port(V850ES/JG3-E)
TOAB1B1/TIAB10/KR1/TOAB10
−
58
73
TOAB1T2/TOAB12/TIAB12/KR2/INTP13
−
59
74
P93
TOAB1B2/TRGAB1/KR3/INTP14
−
60
75
P94
TOAB1T3/TOAB13/TIAB13/KR4/INTP15
−
61
76
P95
TOAB1B3/EVTB1/KR5/INTP16
−
62
77
P96
TECR0/TIT00/KR6/TOT00
−
31
40
P97
TENC00/TIT01/KR7/TOT01
−
32
41
P98
TENC01/INTP17
−
33
42
P912
TOAB1OFF/INTP18
−
63
78
P913
SIF31/INTP19
−
−
30
INTP19
−
25
−
SOF3/INTP20
−
−
31
P91
11-bit I/O port(V850ES/JF3-E)
P92
Input/output can be specified in 1-bit units.
P914
−
−
32
Port DL
−
−
−
58
11-bit I/O port(V850ES/JG3-E)
−
−
−
59
−
−
−
60
PDL3
−
−
−
66
PDL4
−
−
−
67
49
64
79
P915
PDL0
PDL1
PDL2
SCKF3
I/O
1-bit I/O port(V850ES/JF3-E, V850ES/JE3-E)
Input/output can be specified in 1-bit units.
PDL5
FLMD1
PDL6
−
−
−
83
PDL7
−
−
−
84
PDL8
−
−
−
33
PDL9
−
−
−
34
PDL10
−
−
−
43
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 16 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
1.2 Non-Port Pins
(1/5)
Pin Name
I/O
Function
Alternate Function
Pin number
JE3-E JF3-E JG3-E
ADTRG
Input
External trigger input for A/D converter
P03/INTP00/EXCLK
−
−
4
ANI0
Input
Analog voltage input for A/D converter
P70
64
80
100
ANI1
P71
63
79
99
ANI2
P72
62
78
98
ANI3
P73
61
77
97
ANI4
P74
60
76
96
ANI5
P75
59
75
95
ANI6
P76
58
74
94
ANI7
P77
57
73
93
ANI8
P78
56
72
92
ANI9
P79
55
71
91
P32/SCKF2/TIAA10/TOAA10
15
19
22
1
1
1
ASCKC0
Input
−
AVREF0
UARTC0 baud rate clock input
−
Reference voltage input for A/D converter, and positive
power supply for port 7
−
AVSS
CTXD0
−
2
2
2
Note
Input
CAN receive data input
P37/RXDC2/SCL02
51
67
82
Note
Output
CAN transmit data output
P36/TXDC2/SDA02
50
66
81
P52/INTP09
18
22
27
CRXD0
Ground voltage for A/D converter
DCK
Input
Clock input for on-chip debugging
DDI
Input
Data input for on-chip debugging
DDO
Output Data output for on-chip debugging
P50/INTP07
16
20
25
P51/INTP08
17
21
26
In the on-chip debug mode, high-level output is forcibly
set.
DMS
Input
Mode select signal input for on-chip debugging
P53/INTP10
19
23
28
DRST
Input
Reset signal input for on-chip debugging
P54/INTP11
20
24
29
EVDD
−
−
Positive power supply for external (same potential as VDD)
24, 44 29, 52 38, 65
EVTAB1
Input
External event count input of TAB1
P95/TOAB1B3/KR5/INTP16
−
62
77
EXCLK
Input
USB clock signal input
P03/INTP00/ADTRG
−
−
4
FLMD0
Input
Flash programming mode setting pins
42
50
63
FLMD1
Input
INTP00
Input
−
PDL5/AD5
49
64
79
External interrupt request input (maskable, analog
P03/ADTRG/EXCLK
−
−
4
noise elimination).
P20
4
4
5
P22/RTC1HZ
−
−
7
INTP03
P23/SIF1/TXDC1/SDA00
−
13
16
INTP04
P24/SOF1/RXDC1/SDL00
−
14
17
INTP05
P26/TIAA31/TOAA31
−
16
19
INTP06
P35/SCKF4/TIAA21/TOAA21
−
−
80
INTP01
INTP02
Analog noise elimination or digital noise elimination
selectable for INTP02 pin.
/TOAA1OFF
P35/TIAA21/TOAA21/TOAA1OFF
−
65
−
INTP07
P50/DDI
16
20
25
INTP08
P51/DDO
17
21
26
INTP09
P52/DCK
18
22
27
P53/DMS
19
23
28
INTP10
Note
Available only in on-chip CAN controller products
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 17 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
(2/5)
Pin Name
I/O
Function
Alternate Function
Pin number
JE3-E JF3-E JG3-E
INTP11
Input
External interrupt request input (maskable, analog
noise elimination).
INTP12
P54/DRST
20
24
29
P90/TOAB1T1/TOAB11/TIAB11
−
57
72
−
59
74
/KR0
INTP13
P92/TOAB1T2/TOAB12/TIAB12
/KR2
INTP14
P93/TOAB1B2/TRGAB1/KR3
−
60
75
INTP15
P94/TOAB1T3/TOAB13/TIAB13
−
61
76
/KR4
INTP16
P95/TOAB1B3/EVTAB1/KR5
−
62
77
INTP17
P98/TENC01
−
33
42
INTP18
P912/TOAB1OFF
−
63
78
INTP19
P913/SIF3
−
−
30
P913
−
25
−
P914/SOF3
−
−
31
P90/TOAB1T1/TOAB11/TIAB11
−
57
72
INTP20
KR0
Input
Key interrupt input (analog noise elimination)
/INTP12
KR1
P91/TOAB1B1/TIAB10/TOAB10
−
58
73
KR2
P92/TOAB1T2/TOAB12/TIAB12
−
59
74
/INTP13
KR3
P93/TOAB1B2/TRGAB1/INTP14
−
60
75
KR4
P94/TOAB1T3/TOAB13/TIAB13
−
61
76
/INTP15
KR5
P95/TOAB1B3/EVTAB1/INTP16
−
62
77
KR6
P96/TECR0/TIT00/TOT00
−
31
40
KR7
P97/TENC00/TIT01/TOT01
−
32
41
P02
3
3
3
NMI
Input
External interrupt
(non-maskable, ananlog noise elimination)
P1COL
Input
Collision detection input for Ethernet
−
46
54
69
P1CRS
Input
Carrier detection input for Ethernet
−
45
53
68
P1MDC
Output Seria transmit clock output
−
32
40
50
P1MDIO
I/O
Serial I/O
−
47
55
70
P1RXCLK
Input
Receive clock input for Ethernet
−
48
56
71
P1RXD0
Input
Receive data input for Ethernet
−
39
47
57
P1RXD1
Input
Receive data input for Ethernet
−
33
41
51
P1RXD2
Input
Receive data input for Ethernet
−
34
42
52
P1RXD3
Input
Receive data input for Ethernet
−
35
43
53
P1RXDV
Input
Receive data VALID input for Ethernet
−
36
44
54
P1RXER
Input
Receive data error input for Ethernet
−
37
45
55
P1TXCLK
Output Transmit clock output for Ethernet
−
38
46
56
P1TXD0
Output Transmit data output for Ethernet
−
26
34
44
P1TXD1
Output Transmit data output for Ethernet
−
27
35
45
P1TXD2
Output Transmit data output for Ethernet
−
28
36
46
P1TXD3
Output Transmit data output for Ethernet
−
29
37
47
P1TXEN
Output Transmit data enable output for Ethernet
−
31
39
49
P1TXER
Output Transmit error output for Ethernet
−
30
38
48
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 18 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
(3/5)
Pin Name
I/O
Function
Alternate Function
Pin number
JE3-E JF3-E JG3-E
REGC
−
Connecting capacitor for regulator output stabilization
−
6, 41
6, 49
9, 62
−
10
10
13
(4.7 μF (preliminary value))
RESET
Input
System reset input
RTC1HZ
Output Real-time counter correction clock (1 Hz) output
P22/INTP02
−
−
7
RTCCL
Output Real-time counter clock (original 32 kHz clock) output
P21/RTCDIV
−
−
6
RTCDIV
Output Real-time counter clock (divided 32 kHz clock) output
P21/RTCCL
−
−
6
RTP00
Output Real-time output port
P40/SIF0/TXDC3/SDA01
52
68
85
53
69
86
RTP00, RTP01 are N-ch open-drain output selectable. P41/SOF0/RXDC3/SCL01
RTP01
RTP02
P42/SCKF0/TIAA40/TOAA40
54
70
87
RTP03
P43
−
−
88
RTP04
P44
−
−
89
RTP05
P45TIAA41/TOAA41
−
−
90
RXDC0
P31/SOF2/TIAA01/TOAA01
14
18
21
RXDC1
P24/SOF1/SDL00/INTP04
−
14
17
RXDC2
P37/SCL02/CRXD0
51
67
82
RXDC3
P41/SOF0/SCL01/RTP01
53
69
86
SCKF0
Input
I/O
Serial receive data input (UARTC0 to UARTC3)
Serial clock I/O (CSIF0 to CSIF4)
Note
P42/TIAA40/TOAA40/RTP02
54
70
87
SCKF1
P25/TIAA30/TOAA30
−
15
18
SCKF2
P32/ASCKC0/TIAA10/TOAA10
15
19
22
SCKF3
P915
−
−
32
SCKF4
P35/TIAA21/TOAA21/TOAA1OFF
−
−
80
/INTP06
SCL00
I/O
SCL01
Serial clock I/O (I C00 to I C02)
P24/SOF1/RXDC1/INTP04
−
14
17
N-ch open-drain output selectable.
P41/SOF0/RXDC3/RTP01
53
69
86
51
67
82
2
2
P37/RXDC2/CRXD0
SCL02
SDA00
I/O
SDA01
Serial transmit/receive data I/O (I C00 to I C02)
P23/SIF1/TXDC1/INTP03
−
13
16
N-ch open-drain output selectable.
P40/SIF0/TXDC3/RTP00
52
68
85
50
66
81
52
68
85
2
2
P36/TXDC2/CTXD0
SDA02
SIF0
Input
Note
Serial receive data input (CSIF0 to CSIF4)
Note
P40/TXDC3/SDA01/RTP00
SIF1
P23/TXDC1/SDA00/INTP03
−
13
16
SIF2
P30/TXDC0/TIAA00/TOAA00
13
17
20
SIF3
P913/INTP19
−
−
30
SIF4
P33/TIAA11/TOAA11
−
−
23
SOF0
Output Serial transmit data output (CSIF0 to CSIF4)
P41/RXDC3/SCL01/RTP01
53
69
86
P24/RXDC1/SDL00/INTP04
−
14
17
SOF2
P31/RXDC0/TIAA01/TOAA01
14
18
21
SOF3
P914/INTP20
−
−
31
N-ch open-drain output selectable.
SOF1
P34/TIAA20/TOAA20
−
−
24
Encoder clear input of TMT0
P96/TIT00/KR6/TOT00
−
31
40
Encoder input/external event input/external trigger
P97/TIT01/KR7/TOT01
−
32
41
P98/INTP17
−
33
42
SOF4
TECR0
TENC00
Input
input of TMT0
TENC01
Note
Encoder input of TMT0
Available only in on-chip CAN controller products
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 19 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
(4/5)
Pin Name
I/O
Function
Alternate Function
Pin number
JE3-E JF3-E JG3-E
TIAA00
Input
Capture trigger input/external event input/external
P30/TXDC0/SIF2/TOAA00
13
17
20
trigger input (TAA0)
TIAA01
Capture trigger input (TAA0)
P31/RXDC0/SOF2/TOAA01
14
18
21
TIAA10
Capture trigger input/external event input/external
P32/ASCKC0/SCKF2/TOAA10
15
19
22
trigger input (TAA1)
TIAA11
Capture trigger input (TAA1)
P33/SIF4/TXDB0/TOAA11
−
−
23
TIAA20
Capture trigger input/external event input/external
P34/SOF4/RXDB0/TOAA20
−
−
24
P35/SCKF4/TOAA21/TOAA1OFF
−
−
80
−
65
−
P25/SCKF1/TOAA30
−
15
18
trigger input (TAA2)
TIAA21
Capture trigger input (TAA2)
/INTP06
TIAA21/TOAA21/TOAA1OFF/INT
P06
TIAA30
Capture trigger input/external event input/external
trigger input (TAA3)
TIAA31
Capture trigger input (TAA3)
P26/TOAA31/INTP05
−
16
19
TIAA40
Capture trigger input/external event input/external
P42/SCKF0/TOAA40/RTP02
54
70
87
Capture trigger input (TAA4)
P45/SCKE0/TOAA41/RTP05
−
−
90
Capture trigger input/external event input/external
P91/TOAB1B1/KR1/TOAB10
−
58
73
trigger input (TAA4)
TIAA41
TIAB10
Input
trigger input (TAB1)
N-ch open-drain output selectable.
TIAB11
Capture trigger input (TAB1)
P90/TOAB1T1/TOAB11/KR0/INTP12
−
57
72
TIAB12
N-ch open-drain output selectable.
P92/TOAB1T2/TOAB12/KR2/INTP13
−
59
74
P94/TOAB1T3/TOAB13/KR4/INTP15
−
61
76
Capture trigger input of TMT0
P96/TECR0/KR6/TOT00
−
31
40
N-ch open-drain output selectable.
P97/TENC00/KR7/TOT01
−
32
41
P30/TXDC0/SIF2/TIAA00
13
17
20
P31/RXDC0/SOF2/TIAA01
14
18
21
TIAB13
TIT00
Input
TIT01
TOAA00
Output Timer output (TAA0)
TOAA01
N-ch open-drain output selectable.
TOAA10
Timer output (TAA1)
P32/ASCKC0/SCKF2/TIAA10
15
19
22
TOAA11
N-ch open-drain output selectable.
P33/SIF4/TIAA11
−
−
23
TOAA1OFF Input
TAA1 High-impedance output control signal input
P35/SCKF4/TIAA21/TOAA21/INTP06
−
−
80
P35/TIAA21/TOAA21/INTP06
−
65
−
P34/SOF4/TIAA20
−
−
24
P35/SCKF4/TIAA21/TOAA1OFF
−
−
80
P35/TIAA21/TOAA1OFF/INTP06
−
65
−
−
15
18
TOAA20
TOAA21
Output Timer output (TAA2)
N-ch open-drain output selectable.
/INTP06
TOAA30
Timer output (TAA3)
P25/SCKF1/TIAA30/
TOAA31
N-ch open-drain output selectable.
P26/TIAA31/INTP05
−
16
19
TOAA40
Timer output (TAA4)
P42/SCKF0/TIAA40/RTP02
54
70
87
TOAA41
N-ch open-drain output selectable.
P45/SCKE0/TIAA41/RTP05
−
−
90
P91/TOAB1B1/TIAB10/KR1
−
58
73
TOAB10
Output Timer output (TAB1)
N-ch open-drain output selectable.
P90/TOAB1T1/TIAB11/KR0/INTP12
−
57
72
TOAB12
P92/TOAB1T2/TIAB12/KR2/INTP13
−
59
74
TOAB13
P94/TOAB1T3/TIAB13/KR4/INTP15
−
61
76
TOAB11
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 20 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
(5/5)
Pin Name
I/O
Function
Alternate Function
Pin number
JE3-E JF3-E JG3-E
TOAB1B1
Output Pulse signal output for 6-phase PWM low arm of TAB1 P91/TIAB10/KR1/TOAB10
−
58
73
TOAB1B2
P93/TRGAB1/KR3/INTP14
−
60
75
TOAB1B3
P95/EVTAB1/KR5/INTP16
−
62
77
P912/INTP18
−
63
78
P90/TOAB11/TIAB11/KR0/INTP12
−
57
72
TOAB1T2
TAB1.
P92/TOAB12/TIAB12/KR2/INTP13
−
59
74
TOAB1T3
N-ch open-drain output selectable.
P94/TOAB13/TIAB13/KR4/INTP15
−
61
76
TOAB1OFF Input
TOAB1T1
TOT00
P96/TECR0/TIT00/KR6
−
31
40
N-ch open-drain output selectable
P97/TENC00/TIT01/KR7
−
32
41
External trigger input of TAB1
P93/TOAB1B2/KR3/INTP14
−
60
75
P30/SIF2/TIAA00/TOAA00
13
17
20
Output Timer output of TMT0
TOT01
TRGAB1
TAB1 High-impedance output control signal input
Output Pulse signal output for 6-phase PWM high arm of
Input
N-ch open-drain output selectable
TXDC0
Output Serial transmit data output (UARTC0 to UARTC3)
N-ch open-drain output selectable.
TXDC1
P23/SIF1/SDA00/INTP03
Note
TXDC2
P36/SDA02/CTXD0
TXDC3
P40/SIF0/SDA01/RTP00
UDMF
I/O
USB data I/O (−) function
−
−
13
16
50
66
81
52
68
85
21
26
35
USB data I/O (+) function
−
22
27
36
UVDD
−
3.3 V positive power supply for USB
−
23
28
37
VDD
−
Positive power supply for internal circuit
−
5
5
8
VSS
−
Ground potential for internal circuit
−
7
7
10
X1
Input
X2
−
UDPF
XT1
Input
XT2
−
Note
Connecting resonator for main clock
Connecting resonator for subclock
−
8
8
11
−
9
9
12
−
8
11
14
−
9
12
15
Available only in on-chip CAN controller products.
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 21 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 1-1. For the
schematic circuit diagram of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuits (1/3)
Pin
Alternate Function
Recommended Connection of Unused Pins
10-D
NMI
Input:
Independently connect to EVDD or VSS via a
3
3
3
Output: Leave open.
−
−
4
Input:
Independently connect to EVDD or VSS via a
4
4
5
resistor.
−
−
6
−
−
7
resistor.
P03
INTP00/ADTRG/EXCLK
P20
TOAB02/INTP01
P21
P22
JE3-E JF3-E JG3-E
Type
Name
P02
I/O Circuit
10-D
RTCDIV/RTCCL
Output: Leave open.
RTC1HZ/INTP02
P23
SIF1/TXDC1/SDA00/INTP03
−
13
16
P24
SOF1/RXDC1/SCL00/INTP04
−
14
17
P25
SCKF1/TIAA30/TOAA30
−
15
18
P26
TIAA31/TOAA31/INTP05
−
16
19
P27
TIAB03/TOAB03/INTP21
P30
TXDC0/SIF2/TIAA00/TOAA00
P31
RXDC0/SOF2/TIAA01/TOAA01
P32
10-D
Input:
4
4
5
Independently connect to EVDD or VSS via a
13
17
20
resistor.
14
18
21
15
19
22
Output: Leave open.
ASCKC0/SCKF2/TIAA10/TOAA10
P33
SIF4/TIAA11/TOAA11
−
−
23
P34
SOF4/TIAA20/TOAA20
−
−
24
P35
SCKF4/TIAA21/TOAA21
−
−
80
−
65
−
/TOAA1OFF/INTP06
TIAA21/TOAA21/TOAA1OFF/INTP06
Note
P36
TXDC2/SDA02/CTXD0
P37
RXDC2/SCL02/CRXD0
P40
SIF0/TXDC3/SDA01/RTP00
P41
50
66
81
51
67
82
Independently connect to EVDD or VSS via a
52
68
85
resistor.
53
69
86
Note
10-D
Input:
SOF0/RXDC3/SCL01/RTP01
Output: Leave open.
P42
SCKF0/TIAA40/TOAA40/RTP02
54
70
87
P43
RTP03
−
−
88
P44
RTP04
−
−
89
P45
TIAA41/TOAA41/RTP05
−
−
90
Independently connect to EVDD or VSS via a
16
20
25
resistor.
17
21
26
18
22
27
19
23
28
20
24
29
P50
INTP07/DDI
P51
INTP08/DDO
P52
INTP09/DCK
P53
INTP10/DMS
P54
INTP11/DRST
10-D
Input:
Output: Leave open.
10-N
Input:
Independently connect to VSS via a resistor.
Fixing to VDD level is prohibited.
Output: Leave open.
Internally pull-down after reset by RESET
pin.
P70
ANI0 to ANI9
11-G
Input:
to
P79
Note
Independently connect to AVREF0 or AVSS via 64 to
a resistor.
55
80 to 100 to
71
91
Output: Leave open.
Available only in on-chip CAN controller products.
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 22 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
Table 1-1. Types of Pin I/O Circuits (2/3)
Pin
Alternate Function
Recommended Connection of Unused Pins
JE3-E JF3-E JG3-E
Type
Name
P90
I/O Circuit
TOAB1T1/TOAB11/TIAB11/KR0
10-D
Input:
/INTP12
Independently connect to EVDD or VSS via a
−
57
72
−
58
73
−
59
74
resistor.
P91
TOAB1B1/TIAB10/KR1/TOAB10
P92
TOAB1T2/TOAB12/TIAB12/KR2
Output: Leave open.
/INTP13
P93
TOAB1B2/TRGAB1/KR3/INTP14
−
60
75
P94
TOAB1T3/TOAB13/TIAB13/KR4
−
61
76
/INTP15
P95
TOAB1B3/EVTB1/KR5/INTP16
−
62
77
P96
TECR0/TIT00/KR6/TOT00
−
31
40
P97
TENC00/TIT01/KR7/TOT01
−
32
41
P98
TENC01/INTP17
−
33
42
P912
TOAB1OFF/INTP18
−
63
78
P913
SIF3/INTP19
−
−
30
INTP19
−
25
−
P914
SOF3/INTP20
−
−
31
P915
SCKF3
−
−
32
−
−
58 to
−
PDL0 to
5
PDL4
PDL5
PDL6 to
Input:
Independently connect to EVDD or VSS via a
67
resistor.
FLMD1
5
−
Output: Leave open.
5
49
64
79
−
−
83,84,
33,34,
PDL10
43
AVREF0
−
−
Directly connect to VDD and always supply power.
1
1
1
AVSS
−
−
Directly connect to VSS.
2
2
2
EVDD
−
−
Directly connect to VDD and always supply power.
FLMD0
−
−
Connect to VSS in other than flash mode.
42
50
63
P1COL
−
5
Independently connect to EVDD or VSS via a resistor.
46
54
69
P1CRS
−
5
45
53
68
P1MDIO
−
5
47
55
70
P1RXCLK
−
5
48
56
71
P1RXD0
−
5
39
47
57
P1RXD1
−
5
33
41
51
P1RXD2
−
5
34
42
52
P1RXD3
−
5
35
43
53
P1RXDV
−
5
36
44
54
P1RXER
−
5
37
45
55
P1TXCLK
−
5
38
46
56
P1MDC
−
5
32
40
50
P1TXD0
−
5
26
34
44
P1TXD1
−
5
27
35
45
P1TXD2
−
5
28
36
46
P1TXD3
−
5
29
37
47
P1TXEN
−
5
31
39
49
P1TXER
−
5
30
38
48
Leave open.
24, 44 29, 52 38, 65
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 23 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
Table 1-1. Types of Pin I/O Circuits (3/3)
Pin
Alternate Function
Recommended Connection of Unused Pins
JE3-E JF3-E JG3-E
Type
Name
REGC
I/O Circuit
−
−
Connect to regulator output stabilization (4.7 μF 6, 41
6, 49
9, 62
(preliminary value)) capacitor.
RESET
−
2
10
10
13
UDMF
−
−
Leave open.
−
21
26
35
UDPF
−
−
Leave open.
22
27
36
UVDD
−
−
Directly connect to VDD and always supply power.
23
28
37
VDD
−
−
−
5
5
8
VSS
−
−
−
7
7
10
X1
−
−
−
8
8
11
X2
−
−
−
9
9
12
XT1
−
16-C
Connect to VSS via a resistor.
8
11
14
XT2
−
16-C
Leave open.
9
12
15
Remark JE3-E: V850ES/JE3-E, JF3-E: V850ES/JF3-E, JG3-E: V850ES/JG3-E
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 24 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
1. PIN FUNCTIONS
Figure 1-1. Pin I/O Circuits
Type 2
Type 10-N
EVDD
data
P-ch
IN
IN/OUT
open drain
N-ch
output
disable
Schmitt-triggered input with hysteresis characteristics
Note
input
enable
Type 5
VSS
N-ch
OCDM0 bit
EVDD
data
P-ch
IN/OUT
output
disable
Type 11-G
N-ch
AVREF0
data
P-ch
VSS
input
enable
IN/OUT
output
disable
N-ch
AVSS
Type 10-D
EVDD
data
P-ch
IN/OUT
open drain
N-ch
output
disable
Note
input
enable
VSS
P-ch
Comparator
+
_
VREF0
(threshold voltage)
N-ch
AVSS
input enable
Type 16-C
feedback cut-off
P-ch
XT1
Note
XT2
Hysteresis characteristics are not available in port mode.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 25 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
2. CPU FUNCTIONS
2. CPU FUNCTIONS
The CPU of the V850ES/JE3-E, V850ES/JF3-E and V850ES/JG3-E is based on RISC architecture and executes
most instructions in a 1-clock cycle by using a 5-stage pipeline.
The features of the CPU are as follows.
{ Minimum instruction execution time: 20 ns (@ 50 MHz operation with main clock (fXX))
30.5 μs (@ 32.768 kHz operation with sub-clock (fXT))
{ Memory space
Program space: 64 MB linear
Data space:
4 GB linear
{ General-purpose registers: 32 bits × 32 registers
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiplication/division instructions
{ Saturation operation instructions
{ 1-clock 32-bit shift instruction
{ Load/store instructions with long/short format
{ Internal memory
Table 2-1. ROM/RAM
Generic Name
V850ES/JE3-E
V850ES/JF3-E
V850ES/JG3-E
Products
Flash Memory Size
RAM Size
Internal RAM
Data RAM
μPD70F3826
64 KB
16 KB
16 KB
μPD70F3827
128 KB
32 KB
16 KB
μPD70F3828
256 KB
48 KB
16 KB
μPD70F3829
256 KB
48 KB
16 KB
μPD70F3830
64 KB
16 KB
16 KB
μPD70F3831
128 KB
32 KB
16 KB
μPD70F3832
256 KB
48 KB
16 KB
μPD70F3833
256 KB
48 KB
16 KB
μPD70F3834
64 KB
16 KB
16 KB
μPD70F3835
128 KB
32 KB
16 KB
μPD70F3836
256 KB
48 KB
16 KB
μPD70F3837
256 KB
48 KB
16 KB
{ Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 26 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
3. MEMORY MAP
3. MEMORY MAP
The memory maps of the V850ES/JE3-E, V850ES/JF3-E and V850ES/JF3-E are shown below.
{ Address Space
Image 63
4 GB
•
•
•
Data space
Peripheral I/O area
Program space
Image 1
Use prohibited area
Internal RAM area
Internal RAM area
64 MB
Use prohibited area
Use prohibited area
64 MB
Image 0
Use prohibited area
Internal ROM area
16 MB
Internal ROM area
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 27 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
3. MEMORY MAP
{ Data Memory Map
03FFFFFFH
(80 KB)
On-chip peripheral I/O area
(4 KB)
03FFFFFFH
03FFF000H
03FFEFFFH
03FEC000H
03FEBFFFH
Internal RAM area
(60 KB)
03FF0000H
03FEFFFFH
Use prohibited
Note 1
03FEF000H
03FEEFFFH
Programmable peripheral
I/O areaNote 2 or
use prohibitedNote 3
03FEC000H
Use prohibited
00400000H
003FFFFFH
001FFFFFH
USB function/
Ethernet/Data RAM area
Use prohibited
00200000H
001FFFFFH
00100000H
000FFFFFH
(2 MB)
00000000H
Internal ROM area
(1 MB)
00000000H
Notes 1. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because they overlap an on-chip
peripheral I/O area.
2. The programmable peripheral I/O area is seen as 256 MB areas in the 4 GB address space.
3. In on-chip CAN controller products, addresses 03FEC000H to 03FEEFFFH are assigned to
addresses 03FEC000H to 03FECBFFH as a programmable peripheral I/O area. In other products,
use of this area is prohibited.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 28 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
4. .PORTS
4. PORTS
The number of I/O ports of the V850ES/Jx3-E is shown below.
Product Name
V850ES/JF3-E
V850ES/JF-E
V850ES/JG3-E
Number of ports (5 V tolerant)
26 (12)
42 (28)
62 (35)
The following figure shows the basic configurations of ports.
(a) V850ES/JE3-E
Port 0
Port 2
Port 3
P02
P20
P50
P30
P54
P70
P32
P36
P37
P40
Port 5
Port 7
P79
PDL5
Port DL
Port 4
P42
(b) V850ES/JF3-E
Port 0
Port 2
P02
P20
P23
P50
Port 5
P54
P70
P26
P30
Port 3
P32
P35
P37
P40
Port 4
Port 7
P79
P90
P98
P912
P913
Port 9
PDL5
Port DL
P45
(c) V850ES/JG3-E
Port 0
P02
P03
P50
Port 5
P20
P54
P70
P26
P79
Port 2
P30
Port 3
P37
P40
Port 7
P90
P98
P912
Port DH
Port 4
P45
P915
PDL0
Port DL
PDL10
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 29 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 5. CLOCK GENERATION FUNCTION
5. CLOCK GENERATION FUNCTION
The clock generation function has the following features.
{ Main clock oscillator
• PLL mode (×8):
fX = 3 to 6.25 MHz (fXX = 24 to 50 MHz)
• Clock through mode:
fX = 3 to 6.25 MHz (fXX = 3 to 6.25 MHz)
{ Subclock oscillator
• fXT = 32.768 kHz
{ Internal oscillator (fR = 220 kHz)
• Default clock of watchdog timer
• Sampling clock for clock monitor function of the main clock oscillator
• Can be used as the internal system clock after the main clock is stopped
{ Internal system clock generation
• 7 levels (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
{ Peripheral clock generation
{ Clock output function
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 30 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 5. CLOCK GENERATION FUNCTION
The following figure shows the configuration of the clock generation function.
FRC bit
XT1
Subclock
oscillator
XT2
fXT
RTC clock,
WDT clock
fXT
RTC clock
Prescaler 3
Main clock
oscillator
stop control
CK2-CK0
bit
Prescaler 2
fXX/32
fXX/16
fXX/8
fXX/4
fXX/2
fXX
STOP mode
SELPLL
bit
Internal
oscillator
fR
HALT
mode
Selector
PLL
IDLE fXX
control
Selector
Main clock
oscillator
X2
fX
CK3 bit
IDLE mode
Selector
X1
IDLE
control
PLLON
bit
Selector
MFRC
bit
1/8 divider
HALT fCPU
control
fCLK
CPU clock
Internal
system clock
WDT clock,
timer M clock
RSTOP bit
EXCLK
Note
Note
Remark
Prescaler 1
Selector
UCKSEL
bit
Peripheral clock
(include Ethernet)
USB clock
V850ES/JG3-E only
fX :
Main clock oscillation frequency
fR:
Internal oscillation frequency
fXX:
Main clock frequency
fXT:
Subclock frequency
fCPU: CPU clock frequency
fCLK: Internal system clock frequency
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 31 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
6. TAA
6. 16-BIT TIMER/EVENT COUNTER AA (TAA)
The number of TAA of the V850ES/Jx3-E is shown below.
Product Name
Number of channel
V850ES/JF3-E
5 channels (TAA0 to TAA4
Number of timer output
Note
)
4
V850ES/JF-E
V850ES/JG3-E
5 channels (TAA0 to TAA4)
5 channels (TAA0 to TAA4)
7
10
Note TAA2 and TAA3 have Interval timer function only.
The timer/counter function has the following features.
• 16 bit timer/counter (TAAn)
• Clock selection: 8 ways
• Capture/trigger input pins (TIAA
n0, TIAAn1): 2
• External event count input pinNote: 1
• External trigger input pinNote: 1
• Timer/counter: 1
• Capture/compare registers: 2
(32-bit capture function available by using a cascade connection with timer AA.)
• Capture/compare match interrupt request signals: 2
• Timer output pins (TOAAn0, TOAAn1): 2
The TAAn function has the following features.
• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Timer tuning function
• Simultaneous start function
Note
The external event count input pin and external trigger input pin also function as the capture trigger input pin
(TIAAn0).
Remark n = 0 to 4
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 32 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
6. TAA
The following figure shows the configuration of TAA.
Internal bus
Selector
TAAnCNT
Clear
TIAAn1
Edge detector
CCR0
buffer
register
TIAAn0
INTTAAnOV
16-bit counter
Output
controller
Selector
Note
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
CCR1
buffer
register
TOAAn0
TOAAn1
INTTAAnCC0
INTTAAnCC1
TAAnCCR0
TAAnCCR1
Internal bus
Note
fXX/2, fXX/4, fXX/8, fXX/16, fXX/64, fXX/256, fXX/512, fXX/1024 for TAA2, TAA3
Remark
fXX = Main clock frequency
n = 0 to 4
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 33 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
7. TAB
7. 16-BIT TIMER/EVENT COUNTER AB (TAB)
The number of TAB of the V850ES/Jx3-E is shown below.
Product Name
Number of channel
V850ES/JF3-E
1 channel (TAB1
Number of timer output
Note
)
-
V850ES/JF-E
V850ES/JG3-E
1 channel (TAB1)
1 channel (TAB1)
4
4
Note Interval timer function only.
The TAB function has the following features.
• 16-bit timer/counter (TAB1)
• Clock selection: 8 ways
• Capture/trigger input pins (TIAB10 to TIAB13): 4
• External event count input pin (EVTAB1): 1
• External trigger input pin (TRGAB1): 1
• Timer/counter: 1
• Capture/compare registers: 4
• Capture/compare match interrupt request signals: 4
• Timer output pins (TOAB10 to TOAB13 ): 4
The TAB1 function has the following features .
• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Triangular wave PWM output
• Timer tuning function
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 34 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
7. TAB
The following figure shows the configuration of TAB.
Internal bus
Selector
TAB1CNT
INTTAB1OV
16-bit counter
Clear
Output controller
Selector
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
CCR0
buffer
register
EVTAB1
TIAB10
TIAB11
TIAB12
Edge detector
TRGAB1
CCR1
buffer
register
CCR2
buffer
register
TAB1CCR0
CCR3
buffer
register
TAB1CCR1
TOAB10
TOAB11
TOAB12
TOAB13
INTTAB1CC0
INTTAB1CC1
INTTAB1CC2
INTTAB1CC3
TAB1CCR2
TIAB13
TAB1CCR3
Internal bus
Remark fXX: Main clock frequency
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 35 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
8. TMT
8. 16-BIT TIMER/EVENT COUNTER T (TMT)
The number of TAB of the V850ES/Jx3-E is shown below.
Product Name
Number of channel
V850ES/JF3-E
1 channel (TMT0
Number of timer output
Note
)
V850ES/JF-E
V850ES/JG3-E
1 channel (TMT0)
1 channel (TMT0)
2
2
-
Note Interval timer function only.
The TMT function has the following features.
• 16 bit timer/counter (TMT)
• Clock selection: 8 ways
• Capture/trigger input pins (TIT00, TIT01) : 2
• External event count input pinNote 1 : 1
• Encoder input pin (TENC00, TENC01) : 2
• Encoder clear input pin (TECR0) : 1
• External trigger input pinNote 1: 1
• Timer/counter: 1
• Capture/compare registers: 2
• Capture/compare match interrupt request signals: 2
• Timer output pins (TOT00, TOT01) : 2
The TMT function has the following features Note 2.
• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Triangular wave PWM output
• Encoder count function
Notes1. The external trigger input pin and the external event count input pin also function as the encoder input pin
(TENC00)
2. The TMT0 function of V850ES/JE3-E is only Interval timer.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 36 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
8. TMT
The following figure shows the configuration of TMT.
Internal bus
Counter
control
Edge detection/
Noise eliminator
TENC00
Edge detection/
Noise eliminator
TENC01
Edge detection/
Noise eliminator
TIT00
Edge detection/
Noise eliminator
TIT01
Edge detection/
Noise eliminator
fXX
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
Remark
Selector
TECR0
TT0TCW
INTTT0OV
16-bit counter
Clear
Output
controller
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
Selector
TT0CNT
CCR0
buffer
register
CCR1
buffer
register
TOT00
TOT01
INTTT0CC0
INTTT0CC1
TT0CCR0
TT0CCR1
INTTT0EC
Sampling
clock
Internal bus
fXX: Main clock frequency
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 37 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
9. TMM
9. 16-BIT INTERVAL TIMER M (TMM)
The number of TMM of the V850ES/Jx3-E is shown below.
Product Name
V850ES/JF3-E
Number of channel
V850ES/JF-E
V850ES/JG3-E
4 channels
4 channels
4 channels
(TMM0 to TMM3)
(TMM0 to TMM3)
(TMM0 to TMM3)
The TMM function has the following features.
• Interval function
• Clock selection: 8 ways
• 16 bit counter × 1 (Not available to counter lead in timer count operation)
• Compare register × 1 (Not available to write compare register in timer count operation)
• Compare match interrupt × 1
The following figure shows the configuration of TMM.
Internal bus
TMnCTL0
TMnCE TMnCKS2 TMnCKS1TMnCKS0
TMnCMP0
Match
Note
Remark
Selector
Note
fXX/2
fXX/4
fXX/8
fXX/16
fXX/64
fXX/256
fXX/512
fXX/1024
Controller
INTTMnEQ0
16-bit counter
Clear
In case of TMM0, fXX, fXX/2, fXX/4, fXX/64, fXX/512, fXX/1048, fR, fXT.
fXX:
Main clock frequency
fXT:
Subclock frequency
fR:
Internal oscillation frequency
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 38 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 10. MOTOR CONTROL FUNCTION
10. MOTOR CONTROL FUNCTION
In the V850ES/JF3-E and V850ES/JG3-E, one channel of motor control function is provided.
Timer AB1 (TAB) and the TAB option (TABOP) can be used as an inverter function that controls a motor.
It performs a tuning operation with timer AA4 (TAA4) and A/D conversion of the A/D converter can be started when
the value of TAB matches the value of TAA4. The following operations can be performed as motor control functions.
• 6-phase PWM output function with 16-bit resolution (with dead-timer, for upper and lower arms)
• Timer tuning operation function (tunable with TAA4)
• Cycle setting function (cycle can be changed during operation of crest or valley interrupt)
• Compare register rewriting: Anytime rewrite, batch rewrite, or intermittent rewrite
(selectable during TAB operation)
• Interrupt and transfer culling functions
• Dead-time setting function
• A/D trigger timing function of the A/D converter (four types of timing can be generated)
• 0% output and 100% output available
• 0% output and 100% output selectable by crest interrupt and valley interrupt
• Forced output stop function
•
At valid edge detection by external pin input (INTP06/TOAA1OFF, INTP18/TOAB1OFF)
•
When stoppage of the main clock oscillation is detected by clock monitor function
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 39 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 10. MOTOR CONTROL FUNCTION
The following figure shows the configuration of motor control function.
TOAB10
TAB1
• Carrier
• 3-phase PWM
generation
TAA4
• A/D trigger timing
generation in
tuning operation
with TAB1
TOAB1T1
TAB option
• 6-phase PWM
generation with
dead time from
3-phase PWM
• Culling control
• A/D trigger selection
TOAB1B1
TOAB1T2
TOAB1B2
TOAB1T3
TAA1
TOAB1B3
• PWM generation
TOAA11
High-impedance
output
controller
Crest interrupt
(INTTAB1CC0)
INTC
• Interrupt control
Valley interrupt
(INTTAB1OV)
Noise elimination
INTP18/TOAB1OFF
Noise elimination
INTP06/TOAA1OFF
A/D trigger of A/D converter
Edge detection
Edge detection
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 40 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
11. REAL-TIME COUNTER
11. REAL-TIME COUNTER
In the V850ES/Jx3-E, one channel of real-time counter is provided.
The real-time counter has the following features.
• It has counters for year, month, week, day, hours, minutes and seconds, and it can count up to 99 years.
• The year, month, week, day, hour, minute and second counters show the count in BCD codeNote 1.
• Alarm interrupt function
• Fixed-cycle interrupt function (cycle: 1 month to 0.5 seconds)
• Interval interrupt function (cycle: 1.95 to 125 ms)
• 1 Hz pin output
• 32.768 kHz pin output
• 512 Hz or 16.384 kHz pin output
• Watch error correction function
• Subclock operation or main clock operationNote 2 selectable
Notes 1.
BCD (binary-coded decimal) code is the code that represents each digit of a decimal number in 4-bit
binary numerals.
2. The main clock can be divided into 32.768 kHz fBRG with the baud rate generator dedicated to the real-time
counter.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 41 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
11. REAL-TIME COUNTER
The following figure shows the configuration of real-time timer.
CLOE1
RTC1HZ
Hour
alarm
Minute
alarm
Day-of-week
alarm
Selector
INTRTC1
fBRG
fXT
Selector
Count clock
= 32.768 kHz
1 minute
Sub-counter
(16-bit)
Second
counter
(7-bit)
1 hour
Minute
counter
(7-bit)
1 month
1 day
Day
counter
(3-bit)
Hour
counter
(6-bit)
INTRTC0
Day-of week
counter
(3-bit)
Month
counter
(5-bit)
Year
counter
(8-bit)
Count enable/
disable circuit
Second
counter
write buffer
Minute
counter
write buffer
Hour
counter
write buffer
Day
counter
write buffer
Week
counter
write buffer
Month
counter
write buffer
Year
counter
write buffer
ICT2 to ICT0
fXT/26
fXT/2
INTRTC2
CKDIV
Selector
fXT/211
fXT/210
fXT/29
fXT/28
fXT/27
fXT/26
RINTE
Selector
12-bit counter
fXT/212
CLOE2
RTCDIV
CLOE0
RTCCL
Remark
fBRG:
Real-time counter count clock frequency
fXT:
Subclock frequency
INTRTC0: Real-time counter fixed-cycle signal
INTRTC1: Real-time counter alarm match signal
INTRTC2: Real-time counter interval signal
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 42 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
12. WDT2
12. WATCHDOG TIMER 2 FUNCTIONS
In the V850ES/Jx3-E, one channel of watchdog timer 2 is provided.
The watchdog timer has the following functions.
• Reset mode:
Reset operation upon overflow of watchdog timer (generates the
WDT2RES signal)
• Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer (generates the
INTWDT2 signal)
The following figure shows the configuration of the watchdog timer functions.
fX/27
Clock
input
controller
fR/23
fX/216 to fX/223,
fR/212 to fR/219
16-bit
counter
2
Watchdog timer enable
register (WDTE)
Selector
3
Clear
0
Output
controller
INTWDT2
WDT2RES
(internal reset signal)
3
WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Watchdog timer mode
register 2 (WDTM2)
Internal bus
Remark
fX:
Main clock oscillation frequency
fR:
Internal oscillation clock frequency
INTWDT2: Non-maskable interrupt request signal from watchdog timer 2
WDT2RES: Watchdog timer 2 reset signal
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 43 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
13. RTO
13. REAL-TIME OUTPUT FUNCTION (RTO)
In the V850ES/Jx3-E, one channel of real-time output is provided.
The RTO has the following features.
• 6-bit real-time output port: 1 channel
• The real-time output port can be set to the port mode or real-time output port mode in 1-bit units.
Internal bus
The RTO has the following configurations.
Real-time output
buffer register 0H
(RTBH0)
Real-time output
latch 0H
2
Real-time output
buffer register 0L
(RTBL0)
Real-time output
latch 0L
4
RTP04,
RTP05
RTP00 to
RTP03
Selector
INTTAA0CC0
INTTAA4CC0
Transfer trigger (H)
Transfer trigger (L)
INTTAA5CC0
2
RTPOE0 RTPEG0 BYTE0
EXTR0
Real-time output port
control register 0 (RTPC0)
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
4
RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00
Real-time output port
mode register 0 (RTPM0)
Page 44 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
14. A/D CONVERTER
14. A/D CONVERTER
An A/D converter unit with ten channels is provided in the V850ES/Jx3-E.
The A/D converter has the following features.
{ 10-bit resolution
{ 10 channels
{ Successive approximation method
{ Operating voltage: AVREF0 = 3.0 to 3.6 V
{ Analog input voltage: 0 V to AVREF0
{ The following functions are provided as operation modes.
• Continuous select mode
• Continuous scan mode
• One-shot select mode
• One-shot scan mode
{ The following functions are provided as trigger modes.
• Software trigger mode
• External trigger mode (external, 1)
• Timer trigger mode
{ Power-fail monitor function (conversion result compare function)
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 45 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
14. A/D CONVERTER
The following figure shows the configuration of the A/D converter.
AVREF0
:
:
:
:
Sample & hold circuit
Selector
ANI0
ANI1
ANI2
ADA0CE bit
ADA0CE bit
Voltage comparator
&
Compare voltage
generation DAC
AVSS
ANI9
SAR
ADA0TMD1 bit
ADA0TMD0 bit
INTAD
INTTAA2CC1
Note
TQTADTO
Edge
detection
ADTRG
Selector
INTTAA2CC0
Controller
ADA0CR0
ADA0CR1
.
.
.
ADA0ETS0 bit
ADA0ETS1 bit
ADA0CR7
Controller
ADA0PFE bit
ADA0PFC bit
Voltage
comparator
ADA0CR8
ADA0M0
ADA0M1
ADA0M2
ADA0S
ADA0CR9
ADA0PFT ADA0PFM
Internal bus
Note Timer trigger signal from 6-phase PWM output circuit (TABOP)
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 46 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
15. UARTC
15. ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
The number of UARTC of the V850ES/Jx3-E is shown below.
Product Name
V850ES/JF3-E
Number of channel
V850ES/JF-E
V850ES/JG3-E
3 channels
4 channels
4 channels
(UARTC0, UARTC2 and UARTC3)
(UARTC0 to UARTC3)
(UARTC0 to UARTC3)
The UARTC has the following features.
{ Transfer rate: 300 bps to 3.125 Mbps (using internal system clock of 24 MHz and dedicated baud rate generator)
{ Full-duplex communication:
On-chip UARTCn receive data register (UCnRX)
On-chip UARTCn transmit data register (UCnTX)
{ 2-pin configuration: TXDCn: Transmit data output pin
RXDCn: Receive data input pin
{ Reception error detect function
• Parity error
• Framing error
• Overrun error
• LIN communication data consistency error detect function
• SBF reception success detect function
{ Interrupt sources: 2 types
• Reception completion interrupt (INTUCnR): This interrupt occurs upon transfer of receive data from the receive
shift register to receive data register after serial transfer completion,
in the reception enabled status.
• Transmission enable interrupt (INTUCnT): This interrupt occurs upon transfer of transmit data from the transmit
data register to the transmit shift register in the transmission
enabled status.
{ Character length: 7, 8, 9 bits
{ Parity function: Odd, even, 0, none
{ Transmission stop bit: 1, 2 bits
{ On-chip dedicated baud rate generator
{ MSB-/LSB-first transfer selectable
{ Transmit/receive data inverted input/output possible
{ SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format
possible
• 13 to 20 bits are selectable for SBF transmission
• Recognition of 11 bits or more possible for SBF reception in LIN format
• SBF reception flag provided
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 47 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
15. UARTC
The following figure shows the configuration of UARTC.
Internal bus
INTUCnT
INTUCnR
Reception unit
Transmission
unit
UCnRX
Receive
shift register
Reception
controller
Transmission
controller
Filter
Baud rate
generator
Baud rate
generator
UCnTX
Transmit
shift register
Selector
RXDCn
Clock
selector
Selector
fXX to fXX/210
ASCKC0Note
TXDCn
UCnCTL0
UCnCTL1
UCnCTL2
UCnSTR
UCnOTP0
Internal bus
Note
UARTC0 only
Remark fXX : Main clock frequency
Remark
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 48 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
16. CSIF
16. CLOCKED SERIAL INTERFACE F (CSIF)
The number of CSIF of the V850ES/Jx3-E is shown below.
Product Name
V850ES/JF3-E
Number of channel
{ Transfer rate:
V850ES/JF-E
V850ES/JG3-E
2 channels
3 channels
5 channels
(CSIF0 and CSIF2)
(CSIF0 to CSIF2)
(CSIF0 to CSIF4)
8 Mbps max. (fXX = 50 MHz, using internal clock)
{ Master mode and slave mode selectable
{ 8-bit to 16-bit transfer, 3-wire serial interface
{ Interrupt request signals (INTCFnT, INTCFnR)
{ Serial clock and data phase switchable
{ Transfer data length selectable in 1-bit units between 8 and 16 bits
{ Transfer data MSB-first/LSB-first switchable
{ 3-wire
SOFn:
Serial data output
SIFn:
Serial data input
SCKFn: Serial clock I/O
Transmission mode, reception mode, and transmission/reception mode specifiable
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 49 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
16. CSIF
The following figure shows the configuration of CSIF.
Internal bus
CFnCTL1
CFnCTL0
CFnCTL2
CFnSTR
INTCFnT
fXX/4
fXX/6
fXX/8
fXX/12
fXX/16
fXX/32
Selector
Controller
fCCLK
INTCFnR
Phase control
fBRG
CFnTX
SCKFn
SIFn
SO latch
Shift register
Phase
control
SOFn
CFnRX
Remark fXX:
fBRG:
Main clock frequency
Baud rate generator count clock
fCCLK: Communication clock
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 50 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
2
17. I C BUS
17. I2C BUS
The number of I2C bus of the V850ES/Jx3-E is shown below.
Product Name
V850ES/JF3-E
Number of channel
2 channels
2
2
(I C01 and I C02)
V850ES/JF-E
3 channels
2
2
(I C00 to I C02)
V850ES/JG3-E
3 channels
2
2
(I C00 to I C02)
{ Transfer rate: Standard mode (100 kbps max.)/high-speed mode (400 kbps max.)
{ Conforms to I2C bus format (multimaster supported)
{ 2-wire
SCL0n: Serial clock pin
SDA0n: Serial data bus pin
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 51 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
2
17. I C BUS
The following figure shows the configuration of I2C.
Internal bus
IIC status register n (IICSn)
MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
IIC control register n
(IICCn)
IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn
Slave address
register n (SVAn)
SDA0n
Start
condition
generator
Clear
Set
Match
signal
Noise
eliminator
IIC shift
register n (IICn)
DFCn
D Q
Data
retention time
correction
circuit
TRCn
N-ch open-drain
output
Stop
condition
generator
SO latch
CLn1,
CLn0
ACK
generator
Output control
Wakeup controller
ACK detector
Start condition
detector
Stop condition
detector
SCL0n
Noise
eliminator
Interrupt request
signal generator
Serial clock counter
DFCn
N-ch open-drain
output
Serial clock
controller
IICSn.MSTSn,
EXCn, COIn
Serial clock
wait controller
IIC shift
register n (IICn)
IICCn.STTn, SPTn
IICSn.MSTSn, EXCn, COIn
fxx
Prescaler
INTIICn
Bus status
detector
Prescaler
fxx to fxx/5
OCKSENn OCKSTHn OCKSn1 OCKSn0
CLDn DADn SMCn DFCn CLn1 CLn0
IIC division clock select
register n (OCKSn)
CLXn
IIC clock select
register n (IICCLn)
STCFn IICBSYn STCENn IICRSVn
IIC function expansion
register n (IICXn)
IIC flag register n
(IICFn)
Internal bus
Remark fXX: Main clock frequency
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 52 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
18. CAN CONTROLLER
18. CAN CONTROLLER
In the μPD70F3829, 70F3833, 70F3837, one channel of CAN controller is provided.
• Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test)
• Standard frame and extended frame transmission/reception enabled
• Transfer rate: 1 Mbps max. (CAN clock input ≥ 8 MHz)
• 32 message buffers/channels
• Receive/transmit history list function
• Automatic block transmission function
• Multi-buffer receive block function
• Mask setting of four patterns is possible for each channel
The following figure shows the configuration of CAN controller.
CPU
Interrupt request
INTC0TRX
INTC0REC
INTC0ERR
INTC0WUP
Internal bus
CAN bus
CAN module
NPB
interface
MAC
(Memory Access Controller)
CAN
protocol
layer
CTXD0
CRXD0
CAN
transceiver
CAN_H0
CAN_L0
CAN RAM
CnMASK1
CnMASK2
CnMASK3
CnMASK4
...
Message
buffer 0
Message
buffer 1
Message
buffer 2
Message
buffer 3
Message
buffer 31
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 53 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
19. USBF
19. USB FUNCTION CONTROLLER (USBF)
In the V850ES/Jx3-E, one channel of USBF is provided.
• Conforms to the Universal Serial Bus (USB) Specification.
• USB 2.0-compatible full-speed transfer (12 Mbps) supported
• Endpoint for transfer incorporated
Endpoint Name
FIFO Size (Bytes)
Transfer Type
Remark
Endpoint0 Read
64
Control transfer
−
Endpoint0 Write
64
Control transfer
−
Endpoint1
64 × 2
Bulk 1 transfer (IN)
2-buffer configuration
Endpoint2
64 × 2
Bulk 1 transfer (OUT)
2-buffer configuration
Endpoint3
64 × 2
Bulk 2 transfer (IN)
2-buffer configuration
Endpoint4
64 × 2
Bulk 2 transfer (OUT)
2-buffer configuration
Endpoint7
8
Interrupt transfer (IN)
−
The following figure shows the configuration of USB function controller.
Bridge interrupt enable register
(BRGINTE)
Internal CPU
Bridge circuit
USBF interrupt
(INTUSBF0)
USBF
controller
Endpoint
Endpoint0 Read (64 bytes)
Endpoint0 Write (64 bytes)
Endpoint1
(64 bytes × 2)
Endpoint2
(64 bytes × 2)
Endpoint3
(64 bytes × 2)
Endpoint4
(64 bytes × 2)
Endpoint7
(8 bytes)
SIE
I/O
buffer
UDMF
UDPF
USB resume
interrupt
(INTUSBF1)
USB clock
Remark Area enclosed with dashed line: Functions included in USB function controller
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 54 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
20. ETHERNET CONTROLLER
20. ETHERNET CONTROLLER
In the V850ES/Jx3-E, one channel of Ethernet controller is provided.
{ 10 Mbps/100 Mbps MAC function conforming to the IEEE802.3 standard
• Full-duplex and half-duplex communications and a flow control function are supported
• On-chip packet filtering function based on address type
• On-chip VLAN detection function
{ Ethernet-dedicated DMA controller
• Reception status DMA transfer possible
• Reading (in pointer-chain format), analysis, and writing back of buffer descriptors possible
• Interrupt control functions for packet transfers
{ FIFO controller
• Transmission/reception FIFO size: Transmission FIFO (2 KB), reception FIFO (2 KB)
• On-chip FIFO status register
• Interrupts occur in accordance with the transmission/reception status and FIFO status.
{ MII is supported as the interface with physical-layer devices (PHY)
{ On-chip reception checksum calculation function conforming to RFC1071
The following figure shows the configuration of USB function controller.
V850ES/Jx3-E
Internal bus
FIFO
controller
Internal
bus interface
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
DMA
controller
Transmission
FIFO
(2 KB)
Reception
FIFO
(2 KB)
TPO+
Ethernet
MAC
MII/RMII
I/O
buffer
TPOPHY
TPI+
TPI-
Page 55 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
21. DMA CONTROLLER
21. DMA CONTROLLER
In the V850ES/Jx3-E, four channels of DMA controller are provided.
{ 4 independent DMA channels
{ Transfer unit: 8/16 bits
{ Maximum transfer count: 65,536 (216)
{ Transfer type: Two-cycle transfer
{ Transfer mode: Single transfer mode
{ Transfer requests
• Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, real-time counter,
A/D converter) or interrupts from external input pin
• Requests by software trigger
{Transfer targets
• Internal RAM ⇔ Peripheral I/O
• Peripheral I/O ⇔ Peripheral I/O
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 56 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
21. DMA CONTROLLER
The following figure shows the configuration of DMA controller.
On-chip
peripheral I/O
Internal RAM
Internal bus
On-chip peripheral I/O bus
CPU
Data
control
Address
control
DMA source address
register n (DSAnH/DSAnL)
DMA destination address
register n (DDAnH/DDAnL)
Count
control
DMA transfer count
register n (DBCn)
DMA channel control
register n (DCHCn)
DMA addressing control
register n (DADCn)
Channel
control
DMA trigger factor
register n (DTFRn)
DMAC
Remark
n = 0 to 3
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 57 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 22. INTERRUPT/EXCEPTION PROCESSING FUNCTION
22. INTERRUPT/EXCEPTION PROCESSING FUNCTION
The features of interrupt/exception processing function is shown below.
{ Interrupts
Internal
V850ES/JE3-E
V850ES/JF3-E
V850ES/JG3-E
External
Non maskable
Maskable
Total
Non maskable
Maskable
Total
μPD70F3826
1
53
54
1
6
7
μPD70F3827
1
53
54
1
6
7
μPD70F3828
1
53
54
1
6
7
μPD70F3829
1
57
58
1
6
7
μPD70F3830
1
56
57
1
18
19
μPD70F3831
1
56
57
1
18
19
μPD70F3832
1
56
57
1
18
19
μPD70F3833
1
60
61
1
18
19
μPD70F3834
1
60
61
1
21
22
μPD70F3835
1
60
61
1
21
22
μPD70F3836
1
60
61
1
21
22
μPD70F3837
1
64
65
1
21
22
• 8 levels of programmable priorities
• Masks interrupt requests according to priority
• Masks can be specified for each maskable interrupt request.
• Noise elimination, edge detection, and valid edge specification for external interrupt request signals.
{ Exceptions
• Software exceptions: 32 sources
• Exception trap: 2 sources (illegal opcode exception, debug trap)
Interrupt/exception sources are listed in Table 22-1.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 58 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 22. INTERRUPT/EXCEPTION PROCESSING FUNCTION
Table 22-1. Interrupt Source List (1/3)
Type
Classification Default
Name
Trigger
Priority
Generating
Interrupt
Unit
Control
JE3E JF3E JG3E
Register
Reset
Interrupt
−
RESET
RESET pin input/reset input from internal source
RESET
−
√
√
√
Non-
Interrupt
−
NMI
NMI pin valid edge input
Pin
−
√
√
√
−
INTWDT2
WDT2 overflow
WDT2
−
√
√
√
−
TRAP0n
TRAP instruction
−
−
√
√
√
TRAP instruction
−
−
√
√
√
ILGOP/DBG0
Illegal instruction code/DBTRAP instruction
−
−
√
√
√
√
√
√
maskable
Software
Exception
exception
(n = 0-FH)
−
TRAP1n
(n = 0-FH)
Exception
Exception
−
Interrupt
0
INTLVI
Detection of low voltage
POCLVI
LVIIC
1
INTP00
Detection of external interrupt pin input edge (INTP00)
Pin
PIC0
2
INTP01
Detection of external interrupt pin input edge (INTP01)
Pin
PIC1
√
√
√
3
INTP02
Detection of external interrupt pin input edge (INTP02)
Pin
PIC2
−
−
√
4
INTP03
Detection of external interrupt pin input edge (INTP03)
Pin
PIC3
−
√
√
5
INTP04
Detection of external interrupt pin input edge (INTP04)
Pin
PIC4
−
√
√
6
INTP05
Detection of external interrupt pin input edge (INTP05)
Pin
PIC5
−
√
√
7
INTP06
Detection of external interrupt pin input edge (INTP06)
Pin
PIC6
−
√
√
8
INTP07
Detection of external interrupt pin input edge (INTP07)
Pin
PIC7
√
√
√
9
INTP08
Detection of external interrupt pin input edge (INTP08)
Pin
PIC8
√
√
√
10
INTP09
Detection of external interrupt pin input edge (INTP09)
Pin
PIC9
√
√
√
11
INTP10
Detection of external interrupt pin input edge (INTP10)
Pin
PIC10
√
√
√
12
INTP11
Detection of external interrupt pin input edge (INTP11)
Pin
PIC11
√
√
√
13
INTP12
Detection of external interrupt pin input edge (INTP12)
Pin
PIC12
−
√
√
14
INTP13
Detection of external interrupt pin input edge (INTP13)
Pin
PIC13
−
√
√
15
INTP14
Detection of external interrupt pin input edge (INTP14)
Pin
PIC14
−
√
√
16
INTP15
Detection of external interrupt pin input edge (INTP15)
Pin
PIC15
−
√
√
17
INTP16
Detection of external interrupt pin input edge (INTP16)
Pin
PIC16
−
√
√
18
INTP17
Detection of external interrupt pin input edge (INTP17)
Pin
PIC17
−
√
√
19
INTP18
Detection of external interrupt pin input edge (INTP18)
Pin
PIC18
−
√
√
20
INTP19
Detection of external interrupt pin input edge (INTP19)
Pin
PIC19
−
√
√
21
INTP20
Detection of external interrupt pin input edge (INTP20)
Pin
PIC20
−
−
√
32
INTTAB1OV
TAB1 overflow
TAB1
TAB1OVIC
√
√
√
33
INTTAB1CC0
TAB1 capture 0/compare 0 match
TAB1
TAB1CCIC0
√
√
√
34
INTTAB1CC1
TAB1 capture 1/compare 1 match
TAB1
TAB1CCIC1
√
√
√
35
INTTAB1CC2
TAB1 capture 2/compare 2 match
TAB1
TAB1CCIC2
√
√
√
trap
Maskable
√
36
INTTAB1CC3
TAB1 capture 3/compare 3 match
TAB1
TAB1CCIC3
√
√
√
37
INTTT0OV
TMT0 overflow
TMT0
TT0OVIC
√
√
√
38
INTTT0CC0
TMT0 capture 0/compare 0 match
TMT0
TT0CCIC0
√
√
√
39
INTTT0CC1
TMT0 capture 1/compare 1 match
TMT0
TT0CCIC1
√
√
√
40
INTTT0EC
TMT0 encoder input
TMT0
TT0ECIC
−
−
√
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 59 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 22. INTERRUPT/EXCEPTION PROCESSING FUNCTION
Table 22-1. Interrupt Source List (2/3
Type
Classification Default
Name
Trigger
Priority
Generating
Interrupt
Unit
Control
JE3E JF3E JG3E
Register
Maskable
Interrupt
TAA0
TAA0OVIC
√
√
√
INTTAA0CC0 TAA0 capture 0/compare 0 match
TAA0
TAA0CCIC0
√
√
√
INTTAA0CC1 TAA0 capture 1/compare 1 match
TAA0
TAA0CCIC1
√
√
√
TAA1
TAA1OVIC
√
√
√
TAA1
TAA1CCIC0
√
√
√
TAA1
TAA1CCIC1
√
√
√
TAA2
TAA2OVIC
√
√
√
INTTAA2CC0 TAA2 capture 0/compare 0 match
TAA2
TAA2CCIC0
√
√
√
INTTAA2CC1 TAA2 capture 1/compare 1 match
TAA2
TAA2CCIC1
√
√
√
41
INTTAA0OV
TAA0 overflow
42
43
44
INTTAA1OV
45
INTTAA1CC0 TAA1 capture 0/compare 0 match
46
INTTAA1CC1 TAA1 capture 1/compare 1 match
47
INTTAA2OV
48
49
TAA1 overflow
TAA2 overflow
50
INTTAA3OV
TAA3
TAA3OVIC
√
√
√
51
INTTAA3CC0 TAA3 capture 0/compare 0 match
TAA3
TAA3CCIC0
√
√
√
52
INTTAA3CC1 TAA3 capture 1/compare 1 match
TAA3
TAA3CCIC1
√
√
√
53
INTTAA4OV
TAA4
TAA4OVIC
√
√
√
54
INTTAA4CC0 TAA4 capture 0/compare 0 match
TAA4
TAA4CCIC0
√
√
√
55
INTTAA4CC1 TAA4 capture 1/compare 1 match
TAA4
TAA4CCIC1
√
√
√
59
INTTM0EQ0
TMM0 compare match
TMM0
TM0EQIC0
√
√
√
60
INTTM1EQ0
TMM1 compare match
TMM1
TM1EQIC0
√
√
√
61
INTTM2EQ0
TMM2 compare match
TMM2
TM2EQIC0
√
√
√
62
INTTM3EQ0
TMM3 compare match
TMM3
TM3EQIC0
√
√
√
67
INTCF0R
CSIF0 transfer completion/UARTC3 reception
CSIF0
CE0RIC
√
√
√
/INTUC3R
completion/UARTC3 reception error/IIC1 transfer
/UARTC3
/UC3RIC
/INTIIC1
completion
/IIC1
/IICIC1
INTCF0T
CSIF0 continuous transfer write enable/ UARTC3
CSIF0
CF0TIC
√
√
√
/INTUC3T
continuous transfer write enable
/UARTC3
/UC3TIC
INTCF1R
CSIF1 reception completion/ CSIF1 reception error
CSIF1
CF1RIC
−
−
√
/INTUC1R
/UARTC1 reception completion/UARTC1 reception
/UARTC1
/UC1RIC
−
−
√
√
√
√
√
√
√
68
69
70
71
72
TAA3 overflow
TAA4 overflow
/INTIIC0
error/IIC0 transfer completion
/IIC0
/IICIC0
INTCF1T
CSIF1 continuous transfer write enable/ UARTC1
CSIF1
CF1TIC
/INTUC1T
continuous transfer write enable
/UARTC1
/UC1TIC
INTCF2R
CSIF2 reception completion/CSIF2 reception error/
CSIF2
CF2RIC
/INTUC0R
UARTC0 reception completion/UARTC0 reception error /UARTC0
/UC0RIC
INTCF2T
CSIF2 continuous transfer write enable/UARTC0
CSIF2
CF2TIC
/INTUC0T
continuous transfer write enable
/UARTC0
/UC0TIC
73
INTCF3R
CSIF3 reception completion/CSIF3 reception error
CSIF3
CF3RIC
−
√
√
74
INTCF3T
CSIF3 continuous transfer write enable
CSIF3
CF3TIC
−
√
√
78
INTCF4R
CSIF4 reception completion/CSIF4 reception error
CSIF4
CF4RIC
−
√
√
79
INTCF4T
CSIF4 continuous transfer write enable
CSIF4
CF4TIC
−
√
√
87
INTUC2R
UARTC2
UC2RIC
√
√
√
/INTIIC2
error/IIC2 transfer completion
/IIC2
/IICIC2
88
INTUC2T
UARTC2 continuous transfer write enable
UARTC2
UC2TIC
√
√
√
90
INTAD
A/D converter completion
A/D
ADIC
√
√
√
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
reception
completion/UARTC2
reception UARTC2
Page 60 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 22. INTERRUPT/EXCEPTION PROCESSING FUNCTION
Table 22-1. Interrupt/Exception Source List (3/3)
Type
Classification Default
Name
Trigger
Priority
Generating
Interrupt
Unit
Control
JE3E JF3E JG3E
Register
Maskable
Interrupt
91
INTDMA0
DMA0 transfer completion
DMA
DMAIC0
√
√
√
92
INTDMA1
DMA1 transfer completion
DMA
DMAIC1
√
√
√
93
INTDMA2
DMA2 transfer completion
DMA
DMAIC2
√
√
√
94
INTDMA3
DMA3 transfer completion
DMA
DMAIC3
√
√
√
95
INTKR
Key return interrupt
KR
KRIC
√
√
√
96
INTRTC0
RTC fixed-cycle signal
RTC
RTC0IC
√
√
√
97
INTRTC1
RTC alarm match
RTC
RTC1IC
√
√
√
98
INTRTC2
RTC interval signal
RTC
RTC2IC
√
√
√
99
INTUSBF0
USBF interrupt
USBF
UFIC0
√
√
√
100
INTUSBF1
USBF resume interrupt
USBF
UFIC1
√
√
√
101
INTETMRX
Packet reception
Ethernet
ETMRXIC
√
√
√
102
INTETMTX
Packet transmission
Ethernet
ETMTXIC
√
√
√
103
INTETMRQ
Received packet read request
Ethernet
ETMRQIC
√
√
√
104
INTETMFS
FIFO status
Ethernet
ETMFSIC
√
√
√
105
INTETMTS
Transmission status
Ethernet
ETMTSIC
√
√
√
106
INTETMRS
Reception status
Ethernet
ETMRSIC
√
√
√
107
INTETMOV
Statistic counter overflow
Ethernet
ETMOVIC
√
√
√
√
108
INTETBER
Error interrupt
Ethernet
ETBERIC
110
INTC0ERR
CAN0 error
CAN0
ERRIC0
√
111
INTC0WUP1
CAN0 wakeup
CAN0
WUPIC0
√
√
√
Note 1
√
Note 2
√
Note 3
Note 1
√
Note 2
√
Note 3
Note 1
√
Note 2
√
Note 3
Note 1
√
Note 2
√
Note 3
112
INTC0REC
CAN0 reception
CAN0
RECIC0
√
113
INTC0TRX
CAN0 transmission
CAN0
TRXIC0
√
Notes 1. μ PD70F3829 only
2. μ PD70F3833 only
3. μ PD70F3837 only
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 61 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
23. KEY INTERRUPT FUNCTION
23. KEY INTERRUPT FUNCTION (V850ES/JF3-E, V850ES/JG3-E)
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to
KR7).
The following figure shows the configuration of key interrupt.
KR7
KR6
KR5
KR4
INTKR
KR3
KR2
KR1
KR0
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
Key return mode register (KRM)
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 62 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
24. STANDBY FUNCTION
24. STANDBY FUNCTION
The power consumption of the system can be effectively reduced by using the standby modes in combination and
selecting the appropriate mode for the application. The available standby modes are listed in Table 24-1.
Table 24-1. Standby Modes
Mode
Function Overview
HALT mode
Mode to stop only the operating clock of the CPU
IDLE1 mode
Mode to stop all the operations of the internal circuit except the oscillator, PLL operation
Note
,
and flash memory
IDLE2 mode
Mode to stop all the operations of the internal circuit except the oscillator
STOP mode
Mode to stop all the operations of the internal circuit except the subclock oscillator
Subclock operation mode
Mode to operate internal system clock by subclock
Sub-IDLE mode
Mode to stop all the operations of the internal circuit except the oscillator in subclock
operation mode
Note PLL retains the previous operation status.
The following figure shows the status transitions of the standby function.
Reset
Internal oscillation
clock operation
Sub-IDLE mode
(fx operates, PLL operates)
WDT overflow
Oscillation
stabilization wait
Normal operation mode
Subclock operation mode
(fx operates, PLL operates)
Clock through mode
(PLL operates)
PLL lockup
time wait
HALT mode
(fx operates, PLL operates)
PLL mode
(PLL operates)
Oscillation
stabilization wait
Clock through mode
(PLL stops)
IDLE1 mode
(fx operates, PLL operates)
Subclock operation mode
(fx stops, PLL stops)
Sub-IDLE mode
(fx stops, PLL stops)
Oscillation
stabilization wait
IDLE2 mode
(fx operates, PLL stops)
HALT mode
(fx operates, PLL stops)
Oscillation
stabilization wait
IDLE1 mode
(fx operates, PLL stops)
STOP mode
(fx stops, PLL stops)
Remark fX: Main clock oscillation frequency
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 63 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
25. RESET FUNCTON
25. RESET FUNCTIONS
The following reset functions are available.
(1) Four types of reset sources
• External reset input via the RESET pin
• Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES)
• System reset by comparing the supply voltage and detection voltage by using the low-voltage detector (LVI)
• System reset by the clock monitor (CLM) upon detection of oscillation stop
After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF).
(2) Emergency operation mode
If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock
oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock.
The outline of the reset functions is shown below.
Internal bus
Reset source flag
register (RESF)
WDT2RF
WDT2 reset signal
CLMRF
LVIRF
Set
Set
Set
Clear
Clear
Clear
CLM reset signal
Reset signal
RESET
Reset signal to
LVIM register
LVI reset signal
Reset signal
Remark LVIM: Low-voltage detection register
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 64 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
26. CLM, LVI
26. CLOCK MONITOR, LOW-VOLTAGE DETECTOR
(1) Clock monitor
The clock monitor samples the main clock by using the internal oscillation clock (fR) and generates a reset
request signal when oscillation of the main clock is stopped.
(2) Low-voltage detector
The low-voltage detector (LVI) has the following functions.
• Compares the supply voltage (VDD) and detection voltage (VLVI) and generates an interrupt request signal or
internal reset signal when VDD < VLVI.
• An interrupt request signal or internal reset signal can be selected.
• Can operate in STOP mode.
• Operation can be stopped by software.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 65 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
27. CRC FUNCTION
27. CRC FUNCTIONS
The outline of the CRC function is shown below.
• CRC operation circuit for detection of data block errors
• Generation of 16-bit CRC code using a CRC-CCITT (X16 + X12 + X5 + 1) generation polynomial for blocks of data
of any length in 8-bit units
• CRC code is set to the CRCD data register each time 1-byte data is transferred to the CRCIN register, after the
initial value is set to the CRCD register.
Internal bus
CRC input register (CRCIN) (8 bits)
CRC code generator
CRC data register (CRCD) (16 bits)
Internal bus
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 66 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 28. REGULATOR FUNCTION
28. REGULATOR FUNCTION
The V850ES/Jx3-E includes a regulator to reduce power consumption and noise.
This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits
except the A/D converter and output buffers). The regulator output voltage is set to 2.5 V (TYP.).
The outline of the regulator functions is shown below.
AVREF0
A/D converter
UVDD
EVDD I/O buffer
EVDD
USB
FLMD0
Sub-oscillator
VDD
Regulator
Flash
memory
Regulator
VDD
REGC
REGC
Internal digital circuits
2.5 V (TYP.)
Main
oscillator
EVDD I/O buffer
EVDD
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
EVDD
Bidirectional level shifter
Page 67 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
29. FLASH MEMORY
29. FLASH MEMORY
Flash memory versions offer the following advantages for development environments and mass production
applications.
{ For altering software after the V850ES/Jx3-E is soldered onto the target system.
{ For data adjustment when starting mass production.
{ For differentiating software according to the specification in small scale production of various models.
{ For facilitating inventory management.
{ For updating software after shipment.
The flash memory in the V850ES/Jx3-E has the following features.
{ 4-byte/1-clock access (when instruction is fetched)
{ Memory size: 64/128/256 KB
{ Rewrite voltage: Erase/write with a single power supply
{ Rewriting method
• Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board
programming)
• Rewriting flash memory by user program (self programming)
{ Flash memory write prohibit function supported (security function)
{ Safe rewriting of entire flash memory area by self programming using boot swap function
{ Interrupts can be acknowledged during self programming.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 68 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 30. ON-CHP DEBUG FUNCTION
30. ON-CHIP DEBUG FUNCTION
Debugging can be implemented with the V850ES/Jx3-E mounted on the target system.
The NEC Electronics on-chip debug emulators MINICUBE and MINICUBE2 are planned to support the V850ES/Jx3-E.
{ MINICUBE
An on-chip debug function is implemented by using the DCU (debug control unit) in the V850ES/Jx3-E, using the
DRST, DCK, DMS, DDI, and DDO pins as the debug interface pins.
{ MINICUBE2
An on-chip debug function is implemented by using the user resources (on-chip flash memory, internal RAM, etc.)
instead of the DCU, and using the SIF0, SOF0, and SCKF0 pins or the SIF3, SOF3, and SCKF3 pins or the
RXDC0 and TXDC0 pins as the interface pins.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 69 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
31. PACKAGE DRAWINGS
31. PACKAGE DRAWINGS
• V850ES/JE3-E
64-PIN PLASTIC LQFP(FINE PITCH)(10x10)
HD
D
detail of lead end
48
A3
33
49
c
32
θ
L
Lp
E
L1
HE
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
A
A2
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
A1
ITEM
D
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
0.25
b
+0.07
0.20 −0.03
c
0.125 +0.075
−0.025
L
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
P64GB-50-GAH
Page 70 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
31. PACKAGE DRAWINGS
• V850ES/JF3-E
80-PIN PLASTIC LQFP (FINE PITCH) (12x12)
HD
detail of lead end
D
60
A3
41
c
61
40
θ
L
Lp
E
L1
HE
(UNIT:mm)
21
80
1
20
ZE
e
ZD
b
x
M
S
A2
S
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
DIMENSIONS
12.00±0.20
E
12.00±0.20
HD
14.00±0.20
HE
14.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
0.25
+0.07
0.20 −0.03
b
A
y
ITEM
D
A1
c
0.125 +0.075
−0.025
L
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
P80GK-50-GAK
Page 71 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
31. PACKAGE DRAWINGS
• V850ES/JG3-E
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
HD
detail of lead end
D
L1
75
76
51
50
A3
c
θ
E
L
HE
Lp
(UNIT:mm)
26
25
100
1
ZE
e
b
ZD
x
M
S
A
A2
S
y
S
A1
ITEM
D
DIMENSIONS
14.00±0.20
E
14.00±0.20
HD
16.00±0.20
HE
16.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40± 0.05
A3
0.25
b
0.20 + 0.07
0.03
c
0.125 + 0.075
0.025
L
0.50
Lp
0.60±0.15
L1
e
1.00±0.20
3° + 5°
3°
0.50
x
0.08
y
0.08
ZD
1.00
θ
ZE
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
1.00
P100GC-50-UEU-1
Page 72 of 75
μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831,
Revision History
Rev.
0.01
Date
Sep 30, 2010
70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 Data Sheet
Description
Summary
Page
−
First Eddition Issued
All documents should contain the following section break and paragraph as the last item. The footers of this document
refer to the paragraph in order to reference the last page of the document.
Caution:
®
This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.
EEPROM is a trademark of Renesas Electronics Corporation.
MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark
in the United States of America.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries, including the
United States and Japan.
All trademarks and registered trademarks are the property of their respective owners.
C-1
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
7.
Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
(Note 2)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan, R.O.C.
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2010 Renesas Electronics Corporation. All rights reserved.
Colophon 1.0
工商网监
湘ICP备2023018690号
