SIW3000GIP1

SiW3000 0 Features • Single-chip IC with 2.4 GHz transceiver, baseband processor, and on-chip protocol stack for Bluetooth® wireless technology • Compliant with Bluetooth specification 1.2 features. • Low cost 0.18 µm CMOS process technology. • 1.8 V analog and digital core voltages; 1.62 V to 3.63 V external I/O interface voltage. • Typical -85 dBm receiver sensitivity, +2 dBm transmitter power for up to 100 meters nominal range. • On-chip VCO and PLL support multiple GSM/GPRS and CDMA cellular reference clock frequencies. • Hardware AGC dynamically adjusts receiver performance in changing environments. • Integrated 32-bit ARMTDMI® processor for extended features. • Full piconet connectivity with support for up to 7 active and 8 parked slaves. • Scatternet compatible with Microsoft® HID devices. • Supports three SCO voice channels. • Channel Quality Driven Data Rate (CQDDR) controls multi-slot packets to minimize packet overhead and maximize data throughput. • Option for Bluetooth + Wi-Fi coexistence. ULTIMATEBLUE™ RADIO PROCESSOR Sleep Control 2.4 GHz Direct Conversion Transceiver Power Management ARM7TDMI® Processor SRAM Data ROM HCI Firmware Up to 2 Mbs USB Full Speed MODEM Internal 32 kHz Clock UART USB GPIO Audio CODEC Interface To Antenna Bluetooth Baseband with CVSD System I/O CODEC Master or Slave Product Description The SiW3000 UltimateBlue™ Radio Processor is a recent innovation for Bluetooth® wireless technology. It combines the industry's best performing and most highly integrated radio design with an ARMTDMI® processor using CMOS technology. The SiW3000 uses direct conversion (zero-IF) architecture. This allows digital filtering for excellent interference rejection as compared to low IF solutions and also results in fewer spurious responses. The lower-layer protocol stack software is integrated into the on-chip ROM. Optional external Flash memory is also supported. The SiW3000 is compliant with Bluetooth specification 1.2 features. The device is available in multiple packages and bare die form with a guaranteed operating temperature range from -40°C to +85°C and an extended high temperature range to +105°C. 2.3 ~ 3.63 V Voltage Reg Fast Locking PLL Crystal or Reference Clock Block Diagram Applications • • • • • Mobile phones. Notebook and desktop PCs. Cordless headsets. Personal digital assistants (PDAs). Computer accessories, peripherals, and wireless printers/ keyboards/mice). Ordering Information SiW3000 UltimateBlue™ Radio Processor Optimum Technology Matching® Applied Si BJT Si Bi-CMOS GaInP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 60 0049 R01Drf SiW3000 Radio Processor DS September 30, 2004 1 of 24 SiW3000 Radio Features • • • • • • • • • • • • • • • • • • • • • • • • • • • Direct-conversion architecture with no external IF filter or VCO resonator components. Single ended RF I/O reduces system bill of materials (BOM) costs by eliminating the need to use external balun and switch circuits. On-chip VCO and PLL support multiple GSM, CDMA, GPRS standard reference clock frequencies. Low out-of-band spurious emission transmitter prevents blocking of sensitive mobile phone RF circuits. No tuning during production. Internal temperature compensation circuit stabilizes performance across wide operating temperature. Fast settling synthesizer reduces power consumption. Up to 100 meter operating range in standard configuration without using an external PA. ARM7TDMI processor core running at 16 MHz. Digital GFSK modem for maximum performance and lower packet error rate. On-chip CVSD conversion with hardware based gain adjustments to enhance audio quality. Sleep control interface for low power operation modes. Software execution from ROM or external FLASH memory. Full piconet connectivity with support for up to 7 active and 8 parked slaves. Able to establish up to 3 SCO connections. Scatternet capable and compatible with Microsoft HID devices. Standard Bluetooth test modes. Low power connection states supported with hold, sniff, and park modes. Channel Quality Driven Data Rate (CQDDR) optimizes data transfer rate in noisy or weak signal environments Audio (SCO) routing over HCI interface for VOIP applications. Support for Bluetooth + Wi-Fi coexistence technology. Verified compatibility with multiple upper-layer stack vendors. Extensive vendor specific HCI commands enables hardware specific controls. Optional upper-layer stack and profiles can be licensed and integrated into the IC. Adaptive frequency hopping (AFH). Faster connections. LMP improvements. Baseband Features Standard Protocol Stack Features Additional Protocol Stack Features Bluetooth 1.2 Features External System Interfaces Host HCI Transport (H:2 USB) The USB device interface provides a physical transport between the SiW3000 and the host for the transfer of Bluetooth control signals and data. This transport layer is fully compliant with Section H:2 of the Bluetooth specification with all end points supported. The SiW3000 USB interface encompasses three I/O signals: USB_DPLS, USB_DMNS, and USB_DPLS_PULLUP. If the USB transport is not used, the USB_DPLS and USB_DMNS pins should be grounded to reduce current consumption. 2 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Host HCI Transport (H:4 UART) The high speed UART interface provides the physical transport between the SiW3000 and the application host for the transfer of Bluetooth control signals and data compliant to Section H:4 of the Bluetooth specification. The table below shows the supported baud rates. The default baud rate is 115,200, but can be configured depending on the application. SiW3000 Radio Processor HCI UART Parameters Number of data bits Parity bit Stop bit Flow control Host flow-off response requirement from the SiW3000 SiW3000 IC flow-off response requirement from host Supported baud rates a.Default baud rate. 8 No parity 1 stop bit RTS/CTS 8 bytes 2 bytes 9.6k, 19.2k, 38.4k, 57.6k, 115.2ka, 230.4k, 460.8k, 500k, 921.6k, 1M, 1.5M, 2M Required Host Setting Host HCI Transport (H:5 3-Wire UART) To reduce the number of signals and increase reliability of the HCI UART interface, a 3-wire UART using either the Bluetooth H:5 or BCSP protocol is supported. The selection between H:4, H:5, and BCSP is done automatically by the SiW3000, or can be set in NVM. SiW3000 Radio Processor HCI 3-Wire UART Parameters Number of data bits Parity bit Stop bit Error detection Sleep modes Required Host Setting 8 Even 1 stop bit Slip and checksum Shallow and deep Audio CODEC Interface The SiW3000 supports direct interface to an external audio CODEC or PCM host device. The interface is easily configured to support: • • • Standard 64-kHz PCM clock rate. Up to 2-MHz clock rates with support for multi-slot handshakes and synchronization. Either master or slave (Motorola SSI) mode. Configuration of the CODEC interface is done by the firmware during boot-up by reading non-volatile memory (NVM) parameters. The following are examples of supported CODEC modes: • • • • Generic 64-kHz audio CODEC (e.g., OKI MSM-7702). Motorola MC145481 or similar CODEC as master. QUALCOMM MSM chip set audio port. GSM/GPRS baseband IC audio ports. Programmable I/O (PIO) Up to twenty-nine (29) programmable IO (PIO) ports are available for customer use in the SiW3000. Three of these PIOs are dedicated and the remaining PIOs are shared with other functions. Availability of PIOs will depend on system configuration. The table below identifies the all twenty-nine PIOs and their usage. The PIO ports can be set to input or output. Reading, writing, and controlling the PIO pins by the host application software can be done via vendor specific HCI commands. 60 0049 R01Drf SiW3000 Radio Processor DS 3 of 24 SiW3000 PIO# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Shared I/O None None None D[8] D[4] D[5] D[6] D[7] PWR_REG_EN D[15] WE_N A[16] A[17] A[11] USB_DPLS_PULLUP Sampled at Reset Yes Yes Yes No No No No No No No No No No No No PIO# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Shared I/O PCM_OUT PCM_IN PCM_CLK PCM_SYNC EXT_WAKE HOST_WAKEUP UART_RXD UART_TXD UART_CTS UART_RTS A[18] TX_RX_SWITCH D[9] D[10] Sampled at Reset No No No No No No No No No No No No No No External Memory Interface The Ultimate 3000 Radio Processor is a true single chip device and does not require additional memory for standard below HCI protocol functions. An external memory interface is available for adding optional memory. If external Flash memory will be used, the read access time of the device must be 100 ns or less. The external memory interface permits connection to Flash and SRAM devices. The interface has an 18-bit address bus and a 16-bit data bus for a total addressable memory of 512 KB. In certain embedded applications, both SRAM and Flash can be installed by using the high order address bit as an alternate chip select. Signal Address A[1] - A[18] Data D[0] - D[15] FCS_N OE_N WE_N Description 18-bit address bus 16-bit data bus Chip select Output enable Write enable External EEPROM Controller and Interface This interface is intended for use with ROM-based solutions. The EEPROM is not required for configurations with external flash. The EEPROM is the non-volatile memory (NVM) in the system and contains the system configuration parameters such as the Bluetooth device address, the CODEC type, as well as other parameters. These default parameters are set at the factory, and some parameters will change depending on the system configuration. Optionally, the non-volatile memory parameters can be downloaded from the host processor at boot up eliminating the need for EEPROM. Please consult the application support team for details. The EEPROMs should have a serial I2C interface with a minimum size of 2 Kbits and 16-byte page write buffer capabilities. Power Management The HOST_WAKEUP and EXT_WAKE signals are used for power management. HOST_WAKEUP is an output signal used to wake up the host. EXT_WAKE is an input signal used by the host to wake up the SiW3000 Radio Processor from sleep mode. For more information on the usage of HOST_WAKE and EXT_WAKE, please refer to RFMD application note 62 0031. 4 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 General System Requirements System Reference Clock The SiW3000 chip can use either an external crystal or a reference clock as the system clock input. The supported frequencies are: 9.6 MHz, 12 MHz, 12.8 MHz, 13 MHz, 14.4 MHz, 15.36 MHz, 16 MHz, 16.8 MHz, 19.2 MHz, 19.68 MHz, 19.8 MHz, 26 MHz, 32 MHz, 38.4 MHz, and 48 MHz. The default reference frequency can be selected by setting the proper system configuration parameter in the non-volatile memory (NVM). If the USB HCI transport will be used, the reference clock must be 32 MHz. The system reference crystal/clock must have accuracy of ±20 PPM or better to meet the specification of Bluetooth. To facilitate design and production, the SiW3000 processor incorporates internal crystal calibration circuits to allow factory calibration of initial crystal frequency accuracy. Low Power Clock For the Bluetooth low power clock, a 32.768-kHz crystal may be used to drive the SiW3000 oscillator circuit, or alternatively, a 32.768-kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not required during low-power modes such as sniff, hold, park, and idle modes, the 32.768-kHz crystal may be omitted in the design. If the 32.768-kHz clock source will be used, the clock source should be connected to the CLK32_IN pin and must meet the following requirements: • • For AC-coupled via 100 pF or greater (peak-to-peak voltage): 400 mVP-P < CLK32_IN < VDD_C For DC-coupled: CLK32_IN minimum peak voltage < VIL CLK32_IN maximum peak voltage > VIH Where VIL = 0.3 * VDD_C Where VIH = 0.7 * VDD_C For both cases, the signal is not to exceed: -0.3 V < CLK32_IN < VDD_C + 0.3 V Also, the CLK32_OUT pin must be coupled to VDD_P or GND through a 100 nF capacitor. Power Supply Description The SiW3000 Radio Processor operates at 1.8 V core voltage for internal analog and digital circuits. The chip has internal analog and digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regulators can be supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can be by-passed if 1.8 V regulated source is available on the system. Function Regulator input pin Regulator output pin Internal Analog Regulator VBATT_ANA = 2.3 to 3.63 V VCC_OUT = 1.8 V Internal Digital Regulator VBATT_DIG = 2.3 to 3.63 V VDD_C = 1.8 V Table 1. Internal Regulator Used Function Circuit voltage supply pin Analog Core Circuits VCC = 1.8 V Digital Core Circuits VDD_C = 1.8 V Table 2. Internal Regulator Bypassed Note: Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the VBATT_ANA and VCC_OUT pins must be tied together and the external analog voltage (1.8 V) should be applied to the VBATT_ANA pin. When bypassing the digital regulator, the VBATT_DIG pin should be left unconnected and the external digital voltage (1.8 V) should be applied to VBB_OUT pin. The power for the I/Os is taken from a separate source (VDD_P). VDD_P can range from 1.62 to 3.63 Volts to maintain compatibility with a wide range of peripheral devices. Please check the pin list for the exact pins that are powered from the VDD_P source. Power for the USB circuits is taken from a separate source (VDD_USB). 60 0049 R01Drf SiW3000 Radio Processor DS 5 of 24 SiW3000 RF I/O Description The SiW3000 processor employs single-ended RF input and output pins for reduced external components. In typical Class-2 (0 dBm nominal) applications, simple LC network matching circuits will be required to combine the two ports into a single antenna port and provide impedance matching. Please refer to the RF impedance table and the application circuits for values and matching circuit examples. The SiW3000 can be used to design Class-1 (+20 dBm) products with the addition of power amplifier circuits. Control signals are available to facilitate the design of the external PA circuit. Reset The SiW3000 processor can be reset by asserting the RESET_N signal to the chip (active low). Upon applying power, the RESET_N must be asserted until voltage supply and internal voltage regulators have stabilized. A simple RC circuit can be used to provide the power-on reset signal to the SiW3000. On-Chip Memory The SiW3000 Radio Processor integrates both SRAM and ROM. The ROM is pre-programmed with Bluetooth protocol stack software (HCI software) and boot code that executes automatically upon reset. The boot code serves to control the boot sequence as well as to direct the execution to the appropriate memory for continued operation. Configuration Selection HCI Transport Interface Selection The HCI transport (USB or UART) is selected on power up by sampling PIO2. If UART is selected, the selection of the particular UART transport (H:4 or H:5) is performed automatically by the software. Value (PIO 2) 0 1 Description UART USB Reference Frequency Selection The SiW3000 radio processor is designed to operate with multiple reference frequencies. During boot up the processor samples PIO pins to determine the default reference frequency. If the USB transport is selected, the default reference frequency will always be 32 MHz. If the UART transport is selected, the reference frequency setting will be set according to the following table: PIO 1 1 0 0 USB_DPLS_PULLUP Don't Care 0 1 Reference Frequency Selection Reference frequency per NVM system configuration setting, or if NVM is not set, defaults to 32 MHz. 13 MHz 26 MHz Application Software Memory Selection The SiW3000 can support application (protocol stack) software execution from internal ROM and external FLASH memory. To run from internal ROM, D[9] and D[10] pins must be connected together as shown in the application circuit section of this document. To run from external FLASH memory the FLASH must be connected as shown in the application circuit diagram and contain valid application code. If an external memory does not have valid program data, the device enters a download mode in which a valid program may be loaded into the external memory through a sequence of commands over the HCI transport layer. 6 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Pin Description The following table provides detailed listings of pin descriptions arranged by functional groupings. Name Radio (Power from VCC) RF_IN RF_OUT VTUNE CHG_PUMP XTAL_N XTAL_P/CLK IDAC VREFP_CAP VREFN_CAP CLK32K_IN CLK32K_OUT RESET_N Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog A2 A4 A6 F1 A7 B7 B1 C1 C2 K10 L11 C6 RF signal input into the receiver. RF signal output from the transmitter. Pin for reference PLL loop filter, only used if reference frequency is not integer multiples of 4 MHz. Pin for RF loop filter. System clock crystal negative input. If a reference clock is used, this pin should be left unconnected. System clock crystal positive input or reference clock input. Power control to external power amplifier. This output provides a variable current source that can be used to control the external power amp. Leave unconnected if not used. Decoupling capacitor for internal A/D converter voltage reference. Decoupling capacitor for internal A/D converter voltage reference. For crystal or external clock input (32.768 kHz). Drive for crystal. System level reset (active low). Enable for an external voltage regulator. Programmable active high or active low. Also used as PIO[8], which is the default mode until the appropriate configuration bit is set. Tie to ground if not used. Output signal used to indicate the current state of the radio. This could be used as a direction control for an external power amplifier.The polarity is programmable with the default set as: Low = Transmit mode High = Receive mode Pad Type Ball Description Low Power Oscillator and Reset (Power from VDD_P) Power Control Interface (Power from VDD_P) PWR_REG_EN/PIO[8] CMOS bi-directional G1 TX_RX_SWITCH CMOS output J9 Table 3. SiW3000 Radio Processor Pin List 60 0049 R01Drf SiW3000 Radio Processor DS 7 of 24 SiW3000 Name Pad Type Ball Programmable input/output. PIO[0] CMOS bi-directional K5 Needs to be low until internal reset goes high or tie to ground if not used. Programmable input/output. Sampled following reset for frequency selection: PIO[1] CMOS bi-directional B8 If UART transport is selected and PIO[1] = 0, frequency is selected by the state of USB_DPLS_PULLUP pin. If UART transport is selected and PIO[1] = 1, frequency is selected by NVM parameter. Default for proper UART operation will be configured as 32 MHz. If USB transport is selected, PIO[1] is ignored and the frequency will be configured as 32 MHz. Programmable input/output. PIO[2] CMOS bi-directional J10 Sampled following reset for transport selection: PIO[2] = 0, selects UART transport PIO[2] = 1, selects USB transport PCM data to the PCM CODEC. PCM data from the remote device. Normally an input. PCM synchronous data clock to the remote device. Normally an output. Input for Motorola SSI slave mode. PCM synchronization data strobe to the remote device. Normally an output. Input for Motorola SSI slave mode. UART receive data. UART transmit data. UART flow control clear to send. UART flow control ready to send. Wake up signal from host. Wake up signal to host. USB differential pair positive signal. USB differential pair negative signal. Output signal for controlling the on/off of the pull-up of the USB_DPLS line. For UART transport, this pin is sampled following reset for frequency selection if PIO[1] = 0: USB_DPLS_ PULLUP = 0, selects 13 MHz USB_DPLS_ PULLUP = 1, selects 26 MHz Description Programmable I/O (Power from VDD_P) PCM Interface (Power from VDD_P) PCM_IN PCM_OUT PCM_CLK PCM_SYNC CMOS output CMOS input CMOS bi-directional CMOS bi-directional E10 F10 G10 H10 UART Interface (Power from VDD_P) UART_RXD UART_TXD UART_CTS UART_RTS EXT_WAKE HOST_WAKEUP USB_DPLS USB_DMNS CMOS input CMOS output CMOS input CMOS output CMOS input CMOS output Analog Analog K7 K3 K6 G9 F3 G2 K9 K8 USB Interface (Power from VDD_USB) USB_DPLS_ PULLUP CMOS bi-directional J8 Table 3. SiW3000 Radio Processor Pin List (Continued) 8 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Name A[18] A[17]/EEPROM_SCL A[16]/EEPROM_SDA A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]/PIO[3] D[7]/PIO[7] D[6]/PIO[6] D[5]/PIO[5] D[4]/PIO[4] D[3] D[2] D[1] D[0] OE_N WE_N/EEPROM_WP FCS_N Pad Type Ball L1 G3 H1 A8 H2 C9 H3 J1 K4 J7 L4 A11 L7 F9 E11 E9 D11 D9 B11 C10 C11 B10 G11 H11 H9 J2 J11 D10 L3 L2 J4 J3 K2 K1 A10 K11 B9 D3 L8 D1 F11 L5 L10 A9 L6 A1 B6 C4 C5 E1 E3 C7 J5 C8 J6 L9 Description External Memory Interface (power from VDD_P) Address lines. Note: A[17] and A[16] can be used to support an optional external serial EEPROM when using the internal ROM in place of the external Flash memory. CMOS output Data lines. Note: D[4] through D[8] can be used as programmable I/O when using the internal ROM in place of the external Flash memory. Note: Connect D[9] to D[10] to use internal ROM. CMOS bi-directional with internal pull-down CMOS output CMOS output CMOS output Power Power Power Power Power Power Output enable for external memory (active low). Write enable for external memory (active low). Note: Can be used to support an optional external serial EEPROM when using the internal ROM in place of external Flash memory. Chip select for external memory (active low). Positive supply to internal analog voltage regulator. Positive supply to internal digital voltage regulator. Regulated output from internal analog voltage regulator. Positive supply for digital input/output ports including peripheral interface, external memory interface, and UART interface. Positive supply for USB Interface. Positive supply for digital circuitry or output of internal digital voltage. Power and Ground VBATT_ANA VBATT_DIG VCC_OUT VDD_P VDD_USB VDD_C VCC Power Positive supply for RF and analog circuitry. VSS_P VSS_C VSS_USB GND GND GND Ground connections for digital input/output ports including peripheral interface, external memory interface, and UART Interface. Ground connections for internal digital circuitry. Ground connections for USB Interface. Table 3. SiW3000 Radio Processor Pin List (Continued) 60 0049 R01Drf SiW3000 Radio Processor DS 9 of 24 SiW3000 Name Pad Type Ball A3 A5 B2 B3 B4 B5 C3 D2 E2 F2 Description GND GND Ground connections for RF and analog circuitry. Table 3. SiW3000 Radio Processor Pin List (Continued) 10 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 System Specifications Absolute Maximum Ratings Parameter Description Min Max Unit V V V V °C dBm VCC Analog circuit supply voltage -0.3 3.63 VDD_IO I/O supply voltage -0.3 3.63 VBATT_ANA Analog regulator supply voltage -0.3 3.63 VBATT_DIG Digital regulator supply voltage -0.3 3.63 TST Storage temperature -55 +125 RFMAX Maximum RF input level – +5 Absolute maximum ratings indicate limits beyond which the useful life of the device may be impaired or damage may occur. Recommended Operating Conditions Parameter TOP TEOP VBATT_ANA VBATT_DIG VCC VDD_C VDD_P VDD_USB Description Operating temperature (industrial grade) Extended operating temperature Unregulated supply voltage into internal analog regulator Unregulated supply voltage into internal digital regulator Regulated supply voltage directly into analog circuits Regulated supply voltage directly into digital circuits Digital interface I/O supply voltage Regulated supply voltage for USB Interface to meet USB specification requirements Min -40 -40 2.3 2.3 1.71 1.62 1.62 3.1 Max +85 +105 3.63 3.63 1.89 2.16 3.63 3.63 Unit °C °C V V V V V V ESD Rating Symbol ESD ESD protection - all pins Description Rating 2000 V Note: This device is a high performance RF integrated circuit with an ESD rating of 2,000 volts (HBM conditions per Mil-Std-883, Method 3015). Handling and assembly of this device should only be done using appropriate ESD controlled processes. Electrical Characteristics Symbol VIL VIH VOL VOH IOH IOL IILI Input low voltage Input high voltage Output low voltage Output high voltage DC Specification (TOP =+25 °C, VDD_P =3.0 V) Description Min. GND-0.1 0.7 VDD_P GND 0.8 VDD_P – – – – – . . Typ. – – – – 1 4 1 4 1 Max. 0.3 . VDD_P VDD_P 0.2 VDD_P VDD_P – – – – – . Unit V V V V mA mA mA mA µA Output high current Output high current (ball J8) Output low current Output low current (ball J8) Input leakage current AC Characteristics (TOP = +25 °C, VDD_P =3.0 V, CLOAD =15 pF) Symbol Description tr tf Rise time Fall time Max. 30 24 Unit ns ns 60 0049 R01Drf SiW3000 Radio Processor DS 11 of 24 SiW3000 Current Consumption (TOP = +25 °C, VBATT =3.0 V using internal regulators) Operating Mode Standby Parked slave, 1.28 sec. interval Page/Inquiry scan, 1.28 sec. interval ACL connection, sniff mode, 100 ms interval ACL data transfer 720 kbps, DH5 continuous packets SCO connection, HV1 packets SCO connection, HV3 packets Average 25 160 1.5 1.2 60 60 32 Unit µA µA mA mA mA mA mA Digital Regulator Specification (TOP = 25 °C) Parameter Output voltage Line regulation Load regulation Dropout voltage Output maximum current Quiescent current Ripple rejection (I OUT = 10 mA) (I OUT = 0 mA, VBATT_DIG = 2.3 V to 3.63 V) (I OUT = 3 mA to 80 mA) (I OUT = 10 mA) – – f RIPPLE = 400 Hz Description Min 1.62 – – – – – – Typ 1.85 8.0 9.0 – – 10 40 Max 2.16 – – 250 80 – – Unit V mV mV mV mA µA dB Radio Specification Parameter VCO Operating Range PLL lock time Frequency – Description Min 2402 – Typ – 55 Max 2480 100 Unit MHz µs RF Impedances Parametera RF impedance TX on TX off RX on RX off Description Min – – – – Typ 769//1.1 26//2.4 142//1.8 45.7//0 Max – – – – Unit Ω/pF Ω/pF Ω/pF Ω/pF a.The impedance values are for typical samples in 96-pin VFBGA package. 12 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Receiver Specification (VBATT = 3.3 V, VCC =int. analog reg. output, nominal Bluetooth test conditions) Parameter Receiver sensitivity BER < 0.1% Maximum usable signal C/I co-channel (0.1% BER) C/I 1 MHz (0.1% BER) C/I 2 MHz (0.1% BER) C/I ≥ 3 MHz (0.1% BER) Out-of-band blocking BER < 0.1% Co-channel selectivity Adjacent channel selectivity 2nd adjacent channel selectivity 3rd adjacent channel selectivity 30 MHz - 2000 MHz 2000 MHz - 2399 MHz 2498 MHz - 3000 MHz 3000 MHz - 12.75 GHz Intermodulation Receiver spurious emission Note: Max interferer level to maintain 0.1% BER, interference signals at 3 and 6 MHz offset. 30 MHz to 1 GHz 1 GHz to 12.75 GHz Description Min – – – – – – -10 -27 -27 -10 -39 – – Typ -85 0 8 -4 -38 -43 – – – – -36 – – Max -80 – 11 0 -35 -40 – – – – – -57 -47 Unit dBm dBm dB dB dB dB dBm dBm dBm dBm dBm dBm dBm Nominal and extreme Bluetooth test conditions as defined by the Bluetooth Test and Interoperability Working Group published RF Test Specification 1.1. Transmitter Specification (VBATT = 3.3 V, VCC = int. analog reg. output, nom. Bluetooth test conditions) Parameter Description Min -2 0.28 -75 -25 -40 -40 – – – – – – – – Typ +2 0.306 – – – – – – -74 -74 -70 -70 – – Max +6 0.35 +75 +25 +40 +40 400 1000 -55 -55 -55 -50 -62 -47 Units dBm – kHz kHz kHz kHz Hz/µs kHz dBm dBm dBm dBm dBm dBm Output RF transmit At maximum power output level power Modulation index Initial carrier frequency accuracy Carrier frequency drift 20 dB occupied bandwidth In-band spurious emission Out-of-band spurious emission – – One slot packet Two slot packet Five slot packet Max drift rate Bluetooth specification 2 MHz offset >3 MHz offset 30 MHz to 1 GHz, operating mode 1 GHz to 12.75 GHz, operating modea 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz a.Except transmit harmonics. 60 0049 R01Drf SiW3000 Radio Processor DS 13 of 24 SiW3000 System Requirements Analog Voltage Supply Requirements The SiW3000 processor is designed for use with integrated low noise analog voltage regulators and is recommended for all applications. If necessary, the internal analog regulator can be bypassed. In situations where bypassing the internal analog regulator is required, the supply voltage to the analog circuit must satisfy the following requirements to preserve the RF performance characteristics. Parameter VCC Minimum load current Minimum ripple rejection Output noise External regulator current at 400Hz Integrated 10 Hz to 80 kHz noise Description Analog supply voltage to all VCC input pins Min 1.71 80 40 – Max 1.89 – – 22 Unit V mA dB mV RMS External Reference Requirements It is possible to provide a number of reference frequencies that are typical on most cellular phones directly into ball B7 (XTAL_P/CLK) of the device. The following reference frequencies (in MHz) can be used: 3.84, 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48 MHz. For other frequencies, please contact RFMD. Parameter 100 Hz offset Phase noise 1 kHz offset 10 kHz offset AC amplitude Drive level DC level a Description Min – – – 0.5 0.3 Max -100 -120 -140 VCC VCC Units dBc/Hz dBc/Hz dBc/Hz VP-P V a.If DC-coupled, the external reference signal voltage must stay within this range at all times. Reference Crystal Requirements Many reference frequencies are supported by the device. If a crystal is used as the reference frequency source, the typical required parameters are listed below: Parameter Drive level ESR CO CL CM – Effective serial resistance Holder capacitance Load capacitance b b a Description Min – – – – – Typ – – 3 12 6 Max 0.3 150 5 18 – Unit mW W pF pF fF Motional capacitance a.For 32-MHz crystal. b.The actual values for CO and CL are dependent on the crystal manufacturer and can be compensated for by an internal crystal calibration capability. 14 of 24 60 0049 R01Drf SiW3000 Radio Processor DS VBATT VDD_P VDD_USB C2 1uF C3 0.1uF C4 0.1uF VCC is the output from the internal voltage regulator. VCC C1 1uF C5 8.2pF C9 18pF C10 1uF D1 C4 B6 A1 C5 E3 E1 D3 L8 L6 A9 F11 L5 VDD_P VDD_P L10 C6 8.2pF VCC L1 18nH C8 18pF C12 2.7pF A7 U1 XTAL_N VDD_C VDD_C C13 1.8pF VCC VCC VCC VCC VCC VCC B7 L2 3.3nH Y1 XTL 32MHz 1 3 Note: Filter is not required to meet BT and FCC specifications but may be added if better out-of-band performance is desired. C7 8.2pF FL1 Shosin Filter HMD846H C11 2.7pF RF_IN_OUT 2 OUT IN 1 L3 3.9nH VCC_OUT VBATT_ANA VBATT_DIG VDD_USB CLK32K_IN CLK32K_OUT K10 L11 G1 L4 4.7nH RF_OUT A2 RF_IN A4 XTAL_P/CLK R2, C16, and C17 are not required for 32MHz applications. For component values using other frequencies, refer to the reference design application note. TX_RX_SWITCH IDAC VREFP_CAP VREFN_CAP GND GND GND GND GND GND GND GND GND GND VSS_P VSS_P VSS_C VSS_C VSS_USB B1 L6 C18 2.7nH C19 0.1uF C2 0.1uF C1 PCM_CLK PCM_SYNC PCM_IN PCM_OUT G10 H10 E10 F10 A[18] A[17]/EEPROM_SCL A[16]/EEPROM_SDA A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A3 A5 B2 B3 B4 B5 C3 D2 E2 F2 C7 J5 C8 J6 L9 L1 G3 H1 A8 H2 C9 H3 J1 K4 J7 L4 A11 L7 F9 E11 E9 D11 D9 B11 C10 C11 B10 G11 H11 H9 J2 J11 D10 L3 L2 J4 J3 K2 K1 D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]/PIO[3] D[7]/PIO[7] D[6]/PIO[6] D[5]/PIO[5] D[4]/PIO[4] D[3] D[2] D[1] D[0] B2 E6 D6 C6 A6 B6 D5 C5 A5 B5 A2 C2 D2 B1 A1 C1 D1 E1 G6 F5 G5 F4 G3 F3 G2 F2 E5 H5 E4 H4 H3 E3 H2 E2 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WE CE OE U2 A4 F1 G1 K11 B9 WE_N/EEPROM_WP A10 FCS_N OE_N RESET_N C6 VDD_P R3 100K VCC BYTE# RESET# GND GND RY/BY# NC NC NC NC NC G4 F6 B4 A3 C21 0.1uF C20 0.1uF H1 H6 B3 C3 D3 C4 D4 Application Circuit for External Flash-based Products 2M or 4M FLASH HOST INTERFACE UART_RXD UART_TXD UART_CTS UART_RTS EXT_WAKE HOST_WAKEUP PIO[0] PIO[1] PIO[2] K7 K3 K6 G9 F3 G2 K5 B8 J10 60 0049 R01Drf SiW3000 Radio Processor DS PWR_REG_EN/PIO[8] C14 22pF USB_DPLS_PULLUP USB_DPLS USB_DMNS J8 K9 K8 C15 CHG_PUMP 180pF R1 47K F1 L5 3.3nH SiW3000 (EXTERNAL FLASH CONFIGURATION) VCC VTUNE R2 DNI C17 J9 DNI C16 DNI A6 SiW3000 15 of 24 A7 B7 D1 C4 B6 A1 C5 E3 E1 D3 L8 L6 A9 F11 L5 OUT IN U1 XTAL_N VDD_C VDD_C VDD_P VDD_P C13 1.8pF VCC VCC VCC VCC VCC VCC L3 3.9nH L10 VCC_OUT XTAL_P/CLK VBATT_ANA VBATT_DIG VDD_USB R2, C16, and C17 are not required for 32MHz applications. For component values using other frequencies, refer to the reference design application note. TX_RX_SWITCH IDAC VREFP_CAP VREFN_CAP GND GND GND GND GND GND GND GND GND GND VSS_P VSS_P VSS_C VSS_C VSS_USB B1 L6 C18 2.7nH C19 0.1uF C2 0.1uF C1 PCM_CLK PCM_SYNC PCM_IN PCM_OUT G10 H10 E10 F10 A[18] A[17]/EEPROM_SCL A[16]/EEPROM_SDA A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A3 A5 B2 B3 B4 B5 C3 D2 E2 F2 C7 J5 C8 J6 L9 L1 G3 H1 A8 H2 C9 H3 J1 K4 J7 L4 A11 L7 F9 E11 E9 D11 D9 B11 C10 C11 B10 G11 H11 H9 J2 J11 D10 L3 L2 J4 J3 K2 K1 D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]/PIO[3] D[7]/PIO[7] D[6]/PIO[6] D[5]/PIO[5] D[4]/PIO[4] D[3] D[2] D[1] D[0] K11 B9 WE_N/EEPROM_WP A10 FCS_N OE_N RESET_N C6 VDD_P VDD_P VDD_P R4 10K R5 10K Connect D[9] to D[10] to select internal ROM mode. C20 0.1uF R3 100K U2 VCC C21 0.1uF GND 1 2 3 A0 A1 A2 WP SCL SDA 7 6 5 4 8 Application Circuit for Internal ROM-based Products 60 0049 R01Drf SiW3000 Radio Processor DS EEPROM HOST INTERFACE 16 of 24 SiW3000 VBATT VDD_P C2 1uF C3 0.1uF C4 0.1uF VDD_USB Note: Filter is not required to meet BT and FCC specifications but may be added if better out-of-band performance is desired. VCC is the output from the internal voltage regulator. VCC C1 1uF VCC L1 18nH C8 18pF C10 1uF C12 2.7pF L2 3.3nH C9 18pF Y1 XTL 32MHz 1 3 C5 8.2pF C6 8.2pF C7 8.2pF FL1 Shosin Filter HMD846H C11 2.7pF RF_IN_OUT 2 1 CLK32K_IN CLK32K_OUT K10 L11 G1 L4 4.7nH RF_OUT A2 RF_IN A4 PWR_REG_EN/PIO[8] L5 3.3nH C15 CHG_PUMP 180pF R1 47K F1 C14 22pF USB_DPLS_PULLUP USB_DPLS USB_DMNS J8 K9 K8 K7 K3 K6 G9 UART_RXD UART_TXD UART_CTS UART_RTS EXT_WAKE HOST_WAKEUP PIO[0] PIO[1] PIO[2] SiW3000 (INTERNAL ROM CONFIGURATION) VCC VTUNE R2 DNI C17 J9 DNI C16 DNI A6 F3 G2 K5 B8 J10 SiW3000 I/O Configuration (Top View) 1 A A1 VCC 2 A2 RF_IN 3 A3 GND 4 A4 RF_OUT 5 A5 GND 6 A6 VTUNE 7 A7 XTAL_N 8 A8 A[15] 9 A9 VDD_C 10 A10 OE_N 11 A11 A[7] B B1 IDAC B2 GND B3 GND B4 GND B5 GND B6 VCC B7 XTAL_P/CLK B8 PIO[1] B9 FCS_N B10 D[12] B11 D[15] C C1 C2 C3 GND C4 VCC C5 VCC C6 RESET_N C7 VSS_P C8 VSS_C C9 A[13] C10 D[14] C11 D[13] VREFP_CAP VREFN_CAP D D1 VCC_OUT D2 GND D3 VBATT_ANA D9 A[1] D10 D[6]/PIO[6] D11 A[2] E E1 VCC E2 GND E3 VCC E9 A[3] E10 PCM_IN E11 A[4] F F1 CHP_PUMP F2 GND F3 EXT_WAKE S iW3000 TOP VIEW F9 A[5] F10 PCM_OUT F11 VDD_P G G1 PWR_REG_EN/ PIO[8] G2 HOST_ WAKEUP G3 A[17]/ EEPROM_SCL G9 G10 G11 D[11] UART_RTS PCM_CLK H H1 A[16]/ EEPROM_SDA H2 A[14] H3 A[12] H9 D[9] H10 PCM_SYNC H11 D[10] J J1 A[11] J2 D[8]/PIO[3] J3 D[2] J4 D[3] J5 VSS_P J6 VSS_C J7 A[9] J8 USB_DPLS_ PULLUP J9 J10 J11 D[7]/PIO[7] TX_RX_SWITCH PIO[2] K K1 D[0] K2 D[1] K3 UART_TXD K4 A[10] K5 PIO[0] K6 K7 K8 K9 K10 K11 WE_N/ EEPROM_WP UART_CTS UART_RXD USB_DMNS USB_DPLS CLK32K_IN L L1 A[18] L2 L3 L4 A[8] L5 VDD_P L6 VDD_C L7 A[6] L8 VBATT_DIG L9 L10 L11 CLK32K_OUT D[4]/PIO[4] D[5]/PIO[5] VSS_USB VDD_USB POWER DIGITAL GROUND RF GROUND 60 0049 R01Drf SiW3000 Radio Processor DS 17 of 24 SiW3000 Packaging and Product Marking Package Drawing 96-Pin, 6 mm x 6 mm, VFBGA Drawing and Dimensions Symbol A A1 A2 A3 b D E e D1 E1 Min 0.8 0.2 Max 1.0 0.3 0.22 REF 0.45 REF 0.25 0.35 6 BSC 6 BSC 0.5 BSC 5 BSC 5 BSC Notes: 1. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 2. Datum Z is defined by the spherical crowns of the solder balls. 3. Parallelism measurement shall exclude any effect of mark on top surface of package. 4. All dimensions are in millimeters. 18 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Package Drawing 96-Pin, 10 mm x 10 mm, LFBGA Drawing and Dimensions Symbol A A1 A2 A3 b D E e D1 E1 Min 0.27 Max 1.4 0.37 0.26 REF 0.8 REF 0.35 10 BSC 10 BSC 0.8 BSC 8 BSC 8 BSC 0.45 Notes: 1. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 2. Datum Z is defined by the spherical crowns of the solder balls. 3. Parallelism measurement shall exclude any effect of mark on top surface of package. 4. All dimensions are in millimeters. 5. Dimensions and tolerances: ASME Y14.5M. 6. Reference document: JEDEC-MO-210. 60 0049 R01Drf SiW3000 Radio Processor DS 19 of 24 SiW3000 Product Marking Pin 1 Corner SIW Trace Code 4 Digit Date Code 3000GIP1 LLLLL YYWW SiW3000AIP1 LLLLL YYWW ARM ARM Note: Drawing not to scale. 10-by-10-mm LFBGA 6-by-6-mm VFBGA Tape and Reel Specification Carrier Tape: Reel Type: QTY/Reel Peel Test: Cover Tape: Leader: Trailer: Peel Speed: ADV ML0707-A Klik Reel (16 mm) 13" dia. 2500 20–80 grams RS Standard (anti-static) 500 mm (minimum 400 mm) 250 mm (minimum 160 mm) 300 mm/minute 20 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Tape Detail (6 mm x 6 mm VFBGA) DIRECTION OF FEED 0.25 See Note 1 See Note 6 0.30 ±0.05 4.0 2.0 1.50 (MIN) 1.50 +0.1 0.0 1.75 A R0.30 (TYP.) 7.5 See Note 6 Bo R0.25 16 ±0.3 B A Ao Ko SECTION A-A 12.0 B Ao= 6.30 mm Bo= 6.30 mm Ko= 1.50 mm SECTION B-B Note: 1. 2. 3. 4. 5. 6. 7. 8. Tolerances ±0.10 unless otherwise specified. 10 sprocket hole pitch cumulative tolerance ±0.2 Camber not to exceed 1mm in 100 mm. Material: Black Advantek Polystyrene. Ao and Bo measured on a plane 0.3 mm above the bottom of the pocket. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. All dimensions in millimeters. 21 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Reel Dimensions: Klik Reel Tape Width 16 A 330 B(min) 1.50 C 13.00+0.5 D (min) 20.20 N (min) 100 W1 16.4+2.0 -0.00 W2 (max) W3 (min) W3 (max) 22.40 15.90 19.40 Note: All dimensions in millimeters (mm) unless otherwise stated. 22 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Ordering Information Part Number SiW3000GIP1 SiW3000GIP1-T13 SiW3000GIG1 SiW3000GIG1-T13 SiW3000AIP1 SiW3000AIP1-T13 1 Operational Temperature Range1 Industrial Industrial Industrial Industrial Industrial Industrial Package 96-pin VFBGA 6-by-6-mm 96-pin VFBGA 6-by-6-mm 96-pin VFBGA 6-by-6-mm Green 96-pin VFBGA 6-by-6-mm Green 96-pin LFBGA 10-by-10-mm 96-pin LFBGA 10-by-10-mm Ordering Quantity 429 pcs. per tray 2500 on 13” reel 429 pcs. per tray 2500 on 13” reel 360 pcs. per tray 1500 on 13” reel Industrial temperature range: -40°C to +85°C 60 0049 R01Drf SiW3000 Radio Processor DS 23 of 24 SiW3000 RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RF Micro Devices reserves the right to make changes to its products without notice and advises customers to verify that the information being used is current. The described products are not designed, manufactured or intended for use in equipment for medical, life support, aircraft control or navigation, or any other applications that require failsafe operation. RF Micro Devices does not assume responsibility for the use of the described products. RF MICRO DEVICES®, RFMD®, Providing Communication Solutions™, the diamond logo design, Silicon Wave, and the SiW product name prefix are trademarks of RFMD, LLC. BLUETOOTH® is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RF Micro Devices, Inc. Manufactured under license from ARM Limited. ARM, ARM7TDMI and the ARM logo are the registered trademarks of ARM Limited in the EU and other countries. All other product, service, and company names are trademarks, registered trademarks or service marks of their respective owners. 24 of 24 60 0049 R01Drf SiW3000 Radio Processor DS