KM62256DLTG-5L

KM62256D Family Document Title 32Kx8 bit Low Power CMOS Static RAM CMOS SRAM Revision History Revision No History 0.0 0.1 Initial draft First revision - KM62256DL/DLI ISB1 = 100 → 50µA KM62256DL-L ISB1 = 20 → 10µA KM62256DLI-L ISB1 = 50 → 15µA - CIN = 6 → 8pF, CIO = 8 → 10pF - KM62256D-4/5/7 Family tOH = 5 → 10ns - KM62256DL/DLI IDR = 50→30µA KM62256DL-L/DLI-L I DR = 30 → 15µA Finalize - Remove ICC write value - Improved operating current ICC2 = 70 → 60mA - Improved standby current KM62256DL/DLI ISB1 = 50 → 30µA KM62256DL-L I SB1 = 10 → 5µA KM62256DLI-L ISB1 = 15 → 5µA - Improved data retention current KM62256DL/DLI IDR = 30 → 5µA KM62256DL-L/DLI-L IDR = 15 → 3µ A - Remove 45ns part from commercial product and 100ns part from industrial product. Replace test load 100pF to 50pF for 55ns part Draft Data May 18, 1997 April 1, 1997 Remark Design target Preliminily 1.0 November 11, 1997 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. Revision 1.0 November 1997 KM62256D Family 32Kx8 bit Low Power CMOS Static RAM FEATURES • • • • • • Process Technology : TFT Organization : 32Kx8 Power Supply Voltage : 4.5~5.5V Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : 28-DIP-600B, 28-SOP-450 28-TSOP1-0813.4 F/R CMOS SRAM GENERAL DESCRIPTION The KM62256D families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family KM62256DL KM62256DL-L KM62256DLI KM62256DLI-L 1. The parameter is tested with 50pF test load. Operating Temperature VCC Range Speed Standby (ISB1, Max) 30µA 5µA 30µA 5µA Operating (Icc2, Max) PKG Type Commercial (0~70°C) 4.5 to 5.5V Industrial (-40~85 °C) 551)/70ns 28-DIP,28-SOP 28-TSOP1-F/R 60mA 28-SOP 28-TSOP1-F/R 70ns PIN DESCRIPTION OE A11 A9 A8 VCC A13 WE WE VCC A13 A14 A12 A8 A7 A6 A9 A5 A4 A11 A3 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 FUNCTIONAL BLOCK DIAGRAM A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A13 A8 A12 A14 A4 A5 A6 A7 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 Clk gen. Precharge circuit. A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 28-TSOP Type1 - Forward 23 22 21 20 19 18 17 16 15 Row select Memory array 256 rows 128×8 columns 28-DIP 28-SOP 22 21 20 19 18 17 16 15 I/O1 I/O8 Data cont I/O Circuit Column select 28-TSOP Type1 - Reverse 21 22 23 24 25 26 27 28 Data cont A10 A3 A0 A1 A2 A9 A11 Pin Name CS OE WE A0 ~A14 Function Chip Select Input Output Enable Input Write Enable Input Address Inputs Pin Name I/O1 ~I/O8 Vcc Vss NC Function Data Inputs/Outputs Power Ground No connect CS WE OE Control Logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Revision 1.0 November 1997 KM62256D Family PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name KM62256DLP-5 KM62256DLP-5L KM62256DLP-7 KM62256DLP-7L KM62256DLG-5 KM62256DLG-5L KM62256DLG-7 KM62256DLG-7L KM62256DLTG-5 KM62256DLTG-5L KM62256DLTG-7 KM62256DLTG-7L KM62256DLRG-5 KM62256DLRG-5L KM62256DLRG-7 KM62256DLRG-7L Function 28-DIP, 55ns, L-pwr 28-DIP, 55ns, LL-pwr 28-DIP, 70ns, L-pwr 28-DIP, 70ns, LL-pwr 28-SOP, 50ns, L-pwr 28-SOP, 50ns, LL-pwr 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP1 F, 55ns, L-pwr 28-TSOP1 F, 55ns, LL-pwr 28-TSOP1 F, 70ns, L-pwr 28-TSOP1 F, 70ns, LL-pwr 28-TSOP1 R, 55ns, L-pwr 28-TSOP1 R, 55ns, LL-pwr 28-TSOP1 R, 70ns, L-pwr 28-TSOP1 R, 70ns, LL-pwr CMOS SRAM Industrial Temperature Products(-40~85°C) Part Name KM62256DLGI-7 KM62256DLGI-7L KM62256DLTGI-7 KM62256DLTGI-7L KM62256DLRGI-7 KM62256DLRGI-7L Function 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP1 F, 70ns, L-pwr 28-TSOP1 F, 70ns, LL-pwr 28-TSOP1 R, 70ns, L-pwr 28-TSOP1 R, 70ns, LL-pwr FUNCTIONAL DESCRIPTION CS H L L L OE X 1) WE X 1) I/O High-Z High-Z Dout Din Mode Deselected Output Disabled Read Write Power Standby Active Active Active H L X1) H H L 1. X means don′t care (Must be in high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol VIN,VOUT VCC PD TSTG TA TSOLDER Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 260°C, 10sec (Lead Only) Unit V V W °C °C °C Remark KM62256DL KM62256DLI - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Revision 1.0 November 1997 KM62256D Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.53) Typ 5.0 0 - CMOS SRAM Max 5.5 0 Vcc+0.5V2) 0.8 Unit V V V V Note: 1. Commercial Product : TA=0 to 70°C, otherwise specified Industrial Product : TA=-40 to 85°C, otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width≤30ns 3. Undershoot : -3.0V in case of pulse width≤30ns 4. Overshoot and undershoot are sampled, not 100% tested CAPACITANCE1) (f=1MHz, TA=25°C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled not, 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current (CMOS) VOL VOH ISB ISB1 VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc IIO=0mA, CS=VIL, VIN=VIH or VIL, Read Cycle time=1 µs, 100% duty, IIO=0mA CS≤0.2V, VIN≤0.2V, V IN≥Vcc -0.2V Read Write 2.4 Low Power Low Low Power Test Conditions Min -1 -1 Typ 5 2 45 1 0.2 Max 1 1 10 5 20 60 0.4 1 30 5 mA V V mA µA µA Unit µA µA mA mA Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs=VIH or VIL CS≥Vcc-0.2V, Other inputs=0~Vcc Revision 1.0 November 1997 KM62256D Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL=50pF+1TTL CL1) CMOS SRAM 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=4.5~5.5V, KM62256D Family:TA=0 to 70°C, KM62256DI Family:TA=-40 to 85°C) Speed Bins Parameter List Symbol 55 ns Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z 1. The parameter is tested with 50pF test load. 1) 70ns Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 Max 70 70 35 30 30 25 - Units Max 55 55 25 20 20 20 - tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS≥Vcc-0.2V Vcc=3.0V, CS≥Vcc-0.2V L-Ver LL-Ver See data retention waveform Min 2.0 0 5 Typ 1 0.2 Max 5.5 15 3 ms Unit V µA Revision 1.0 November 1997 KM62256D Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA CMOS SRAM Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tOE OE tOLZ tLZ Data Valid tOHZ tHZ tOH Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. Revision 1.0 November 1997 KM62256D Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) CMOS SRAM tWC Address tCW(2) CS tAW tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) CS tAW tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC 4.5V tSDR Data Retention Mode tRDR 2.2V VDR CS≥VCC - 0.2V CS GND Revision 1.0 November 1997 KM62256D Family PACKAGE DIMENSIONS 28 PIN DUAL INLINE PACKAGE(600mil) CMOS SRAM Units: millimeter(inch) 0.25 +0.10 -0.05 + 0.004 0.010-0.002 #28 #15 13.60± 0.20 0.535± 0.008 #1 36.72 MAX 1.446 36.32± 0.20 1.430± 0.008 #14 3.81± 0.20 0.150± 0.008 5.08 0.200 MAX 15.24 0.600 0~15° ( 1.65 ) 0.065 0.46± 0.10 0.018± 0.004 1.52± 0.10 0.060± 0.004 3.30± 0.30 0.130± 0.012 2.54 0.100 0.38 0.015 MIN 28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil) 0~8° #28 #15 11.81± 0.30 0.465 ± 0.012 8.38± 0.20 0.330± 0.008 #1 18.69 MAX 0.736 18.29± 0.20 0.720 ± 0.008 #14 2.59± 0.20 0.102± 0.008 3.00 0.118MAX 0.15 11. 43 0.4 50 +0.10 -0.05 0.004 0.006+0.002 - 1.02± 0.20 0.040± 0.008 0.10 MAX 0.004 MAX ( 0.89 ) 0.035 0.41± 0.10 0.016± 0.004 1.27 0.050 0.05 MIN 0.002 Revision 1.0 November 1997 KM62256D Family PACKAGE DIMENSIONS 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F) +0.10 -0.05 + 0.004 0.008-0.002 CMOS SRAM Units: millimeter(inch) 0.20 13.40± 0.20 0.528± 0.008 #28 #1 0.10 MAX 0.004 MAX ( 8. 40 0.3 31 MAX 8. 00 0.3 15 0.425 ) 0.017 0.55 0.0217 #14 0.25 0.010 TYP 11.80± 0.10 0.465 ± 0.004 #15 +0.10 -0.05 + 0.004 0.006-0.002 0.15 0~8° 1.00± 0.10 0.039 ± 0.004 1.20 0.047 MAX 0.05 0.002 MIN 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R) 0.10 MAX 0.004 MAX + 0.10 -0.05 + 0.004 0.008-0.002 0.20 13.40± 0.20 0.528 ± 0.008 #15 ( 8 .40 0. 331 MAX 8.00 0.315 0.425 ) 0.017 #14 0.55 0.0217 #1 #28 1.00± 0.10 0.039± 0.004 1.20 0.047 MAX 0.05 0.002 MIN 0.25 0.010 TYP 11.80± 0.10 0.465± 0.004 +0.10 -0.05 0.004 0.006+0.002 - 0.15 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 Revision 1.0 November 1997