LC875BM2A

Ordering number : ENN7972 LC875BP4A LC875BM2A LC875BJ0A LC875BH4A Overview CMOS IC ROM 256K/224K/192K/176K byte, RAM 4096K byte on-chip 8-bit 1-chip Microcontroller The LC875BP4A, LC875BM2A, LC875BJ0A, LC875BH4A is 8-bit single chip microcontroller with the following onechip features : • CPU : Operable at a minimum bus cycle time of 100ns • On-chip ROM Capacity : LC875BP4A 256K bytes : LC875BM2A 224K bytes : LC875BJ0A 192K bytes : LC875BH4A 176K bytes • On-chip RAM Capacity : 4K bytes • Two high performance 16-bit timer/counters (can be divided into 8-bit timers) • Four 8-bit timers with prescalers • Timer for use as date/time clock • Two synchronous serial I/O ports (with automatic block transmit/receive function) • One asynchronous/synchronous serial I/O port • Two UART ports (full duplex) • 12-bit PWM × 4 • 12-channel × 8-bit AD converter • High speed clock counter • System clock divider • 27-source 10-vectored interrupt system Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. Ver.1.00 92706 / 81205HKIM B8-7735 No.7972-1/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Features Read Only Memory (ROM) • 262144 × 8-bits (LC875BP4A) • 229376 × 8-bits (LC875BM2A) • 196608 × 8-bits (LC875BJ0A) • 180224 × 8-bits (LC875BH4A) Random Access Memory (RAM) : 4096 × 9-bit Bus Cycle Time • 100ns (10MHz) Note : Bus cycle time indicates the speed to read ROM. Minimum Instruction Cycle Time (tCYC) • 300ns (10MHz) Ports • Input/output ports Input/output programmable for each bit individually Data direction programmable in two bits Data direction programmable in nibble units • Input ports • Oscillator pins • Reset pin • Power supply 64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn, S2Pn, PWM0, PWM1, XT2) 16 (PEn, PFn) 8 (P0n) 1 (XT1) 2 (CF1, CF2) 1 (RES) 8 (VSS1 to 4, VDD1 to 4) Timer • Timer 0 : 16-bit timer/counter with capture register Mode 0 :8-bit timer with 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels Mode 1 :8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with 8-bit capture register) Mode 2 :16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3 :16-bit counter (with a 16-bit capture register) • Timer 1 : 16-bit timer/counter that support PWM/ toggle output Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs ) Mode 1 : 8-bit PWM with an 8-bit prescaler × 2-channels Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (Toggle outputs also present at the lower-order 8-bits) Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8-bits can be used as PWM.) • Timer 4 : 8-bit timer with a 6-bit prescaler • Timer 5 : 8-bit timer with a 6-bit prescaler • Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1. The clock is selectable from sub-clock (32.768kHz crystal oscillation), system clock or programmable prescaler output of timer 0. 2. Interrupt are programmablein 5 different time schemes. High Speed Clock Counter 1. Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2. Can generate output real time. No.7972-2/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Serial Interface • SIO 0 : 8-bit synchronous serial interface 1. LSB first/MSB first-function available 2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC) 3. Consecutive automatic data communication (1 to 256-bits) • SIO 1 : 8-bit asynchronous/synchronous serial interface Mode 0 : Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1 : Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tCYC) Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection) • SIO2 : 8-bit synchronous serial interface 1. LSB-first 2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC) 3. Consecutive automatic data communication (1 to 32 bytes) UART :2-channels 1. Full duplex 2. 7/8/9 bit data bits selectable 3. 1stop bit 4. built-in baudrate generator AD Converter • 12-channel × 8-bit AD converter PWM • 4-channel × synchronous variable 12-bit PWM Remote Receiver Circuit (share with P73/INT3/T0IN terminal) • Noise rejection function (The filtering time of the noise rejection filter (1tCYC/32 tCYC/128 tCYC) can be switched by program.) Watchdog Ttimer • External RC circuit is required. • Interrupt or system reset is activated when the timer overflows. Interrupts • 27-source and 10-vectored interrupt function : 1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting possible. During interrupt handling, an equal or lower level interrupt request is refused. 2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Selectable Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/INT5/base timer T0H T1L/T1H SIO0/UART1, 2 receive SIO1/SIO2/UART1, 2 transmit ADC/T6/T7/PWM4, PWM5 Port 0/T4/T5/PWM0, PWM1 Interrupt Signal • Priority Level : X > H > L • For equal priority levels, vector with lowest address takes precedence. No.7972-3/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Subroutine Stack Levels • A maximum of 3072 levels (set stack inside RAM) Multiplication and division • 16-bits × 8-bits (5 instruction-cycle times) • 24-bits × 16-bits (12 instruction-cycle times) • 16-bits ÷ 8-bits (8 instruction-cycle times) • 24-bits ÷ 16-bits (12 instruction-cycle times) Oscillation Circuits • Built-in RC oscillation circuit used for the system clock • CF oscillation circuit used for the system clock • Crystal oscillation circuit used for the system clock System Clock Divider • Operable on the lowest power consumption • Minimum instruction cycle time (300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched by program (when using 10MHz main clock) Standby Function • HALT mode The HALT mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. This operation mode can be released by a system reset or an interrupt request. • HOLD mode The HOLD mode stops program execution and all oscillation circuits : CF, RC and Crystal oscillations. This mode can be released by the following conditions. 1. Supply "L" level to the reset terminal (RES) 2. Supply the selected level to at lease one of INT0, INT1, INT2, INT4, INT5. 3. Supply an interrupt condition to Port 0. • X’tal HOLD mode The X’tal HOLD mode stops program execution and all peripheral circuits except for the base timer. The crystal oscillator maintains its state at HOLD mode inception. This mode can be released by the following conditions. 1. Supply "L" level to the reset terminal (RES). 2. Supply the selected level to at least one of INT0, INT1, INT2, INT4, INT5. 3. Supply an interrupt condition to Port 0. 4. Supply an interrupt condition to the base timer circuit. Shipping Form • QFP100E (Lead Free Product) • TQFP100 (Lead Free Product) Development Tools • Evaluation (EVA) chip : LC87EV690 • Emulator : EVA62S + ECB876600D + SUB875200 + POD100QFP or POD100SQFP Type B : ICE-B877300 + SUB875200 + POD100QFP or POD100SQFP Type B No.7972-4/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Package Dimensions unit : mm 3151A Package Dimensions unit : mm 3274 No.7972-5/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Pin Assignment P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT4/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/INT4/T1IN P20/INT4/T1IN SI2P3/SCK20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VSS3 VDD3 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA0 PA1 PA2 SI2P2/SCK2 P31/PWM5 P30/PWM4 P35/URX2 P33/URX1 P34/UTX2 P32/UTX1 P05/CKO P07/T7O P06/T6O VDD2 PWM0 PWM1 VSS2 PB7 P36 P04 P03 P02 P01 P00 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 SI2P1/SI2/SB2 SI2P0/SO2 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 VDD4 VSS4 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 LC875BP4A/ LC875BM2A/ LC875BJ0A/ LC875BH4A QIP100E 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P70/INT0/T0LCP/AN8 P72/INT2/T0IN P71/INT1/T0HCP/AN9 P73/INT3/T0IN P17/T1PWMH/BUZ P14/SI1/SB1 P10/SO0 XT1/AN10 XT2/AN11 P11/Si0/SB0 P13/SO1 RES P16/T1PWML PA3 PA4 PA5 VSS1 VDD1 CF1 CF2 P12/SCK0 P15/SCK1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 Top view No.7972-6/25 LC875BP4A/875BM2A/875BJ0A/875BH4A P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/INT4/T1IN P20/INT4/T1IN P31/PWM5 P30/PWM4 P35/URX2 P33/URX1 P34/UTX2 P32/UTX1 P05/CKO P07/T7O P06/T6O 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P36 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VSS3 VDD3 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA0 PA1 PA2 PA3 PA4 PA5 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PWM0 50 49 48 47 46 45 44 43 42 VDD2 VSS2 P04 P03 P02 P01 P00 PWM1 SI2P3/SCK20 SI2P2/SCK2 SI2P1/SI2/SB2 SI2P0/SO2 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 VDD4 VSS4 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 P17/T1PWMH/BUZ P16/T1PWML LC875BP4A/ LC875BM2A/ LC875BJ0A/ LC875BH4A TQFP100 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P70/INT0/T0LCP/AN8 P72/INT2/T0IN P71/INT1/T0HCP/AN9 P73/INT3/T0IN P11/SI0/SB0 P14/SI1/SB1 XT1/AN10 XT2/AN11 P10/SO0 P13/SO1 RES VSS1 VDD1 P12/SCK0 P15/SCK1 CF1 CF2 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 Top view No.7972-7/25 LC875BP4A/875BM2A/875BJ0A/875BH4A PAD Coordinate Values QIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NAME PA3 PA4 PA5 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VSS4 VDD4 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 SI2P0/SO2 SI2P1/SI2/SB2 TQFP 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 QIP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME SI2P2/SCK2 SI2P3/SCK20 PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05/CKO P06/T6O P07/T7O P20/INT4/T1IN P21/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN P30/PWM4 P31/PWM5 P32/UTX1 P33/URX1 P34/UTX2 P35/URX2 P36 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VSS3 VDD3 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA0 PA1 PA2 TQFP 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 No.7972-8/25 LC875BP4A/875BM2A/875BJ0A/875BH4A System Block Diagram Interrupt Control IR PLA ROM Standby Control CF RC Xtal MRC SIO0 Bus Interface ACC Clock Generator PC SIO1 Port 0 B Register SIO2 Port 1 C Register Timer 0 Port 3 ALU Timer 1 Port 7 Timer 4 Port 8 PSW Timer 5 ADC RAR INT0-3 Noise Rejection Filter Port 2 INT4, 5 Stack Pointer PWM0 RAM PWM1 Base Timer Port A Watch Dog Timer Timer 6 Port B Timer 7 Port C UART1 Port E UART2 Port F PWM5 PWM4 No.7972-9/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Pin Description Name VSS1, VSS2 VSS3, VSS4 VDD1, VDD2 VDD3, VDD4 Port 0 P00 to P07 I/O Power supply pin (-) Function description No Option - Power supply pin (+) No I/O • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistor can be turned on and off in 4-bit units • HOLD release input • Port 0 interrupt input • Pin functions P05 : System clock output P06 : Timer 6 toggle output P07 : Timer 7 toggle output Yes Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P10: SIO0 data output P11 : SIO0 data input, bus I/O P12 : SIO0 clock I/O P13 : SIO1 data output P14 : SIO1 data input, bus I/O P15 : SIO1 clock I/O P16 : Timer 1 PWML output P17 : Timer 1 PWMH output/buzzer output Yes Port 2 P20 to P27 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Other functions P20 to P23 : INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/timer 0H capture input P24 to P27 : NT5 input/HOLD release input/timer 1 event input/timer 0L capture input/timer 0H capture input • Interrupt detection style Rising INT4 INT5 enable enable Falling enable enable Rising/ falling enable enable H level disable disable L level disable disable Yes Port 3 P30 to P36 I/O • 7-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P30 : PWM4 output P31 : PWM5 output P32 : UART1 transmit P33 : UART1 receive P34 : UART2 transmit P35 : UART2 receive Yes Continued on next page. No.7972-10/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Continued from preceding page. Name Port 7 P70 to P73 I/O I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Other functions P70 : INT0 input/HOLD release input/timer 0L capture input/output for watchdog timer P71 : INT1 input/HOLD release input/timer 0H capture input P72 : INT2 input/HOLD release input/timer 0 event input/timer 0L capture input P73 : INT3 input with noise filter/timer 0 event input/timer 0H capture input • Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising/ falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Function description No Option • AD converter input port : AN8 (P70), AN9 (P71) Port 8 P80 to P87 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Other functions P80 to P87 : AD converter input port Port A PA0 to PA5 Port B PB0 to PB7 Port C PC0 to PC7 Port E PE0 to PE7 Port F PF0 to PF7 SIO2 Port SI2P0 to SI2P3 I/O I/O I/O I/O I/O I/O • 6-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • 8-bit I/O port • I/O specifiable in 2-bit units • Pull-up resistor can be turned on and off in 1-bit units • 8-bit I/O port • I/O specifiable in 2-bit units • Pull-up resistor can be turned on and off in 1-bit units • 4-bit I/O port • I/O specifiable in 1-bit units • Other functions SI2P0 : SIO2 data output SI2P1 : SIO2 data input, bus input/output SI2P2 : SIO2 clock input/output SI2P3 : SIO2 clock output PWM0 PWM1 RES XT1 No Yes Yes Yes No No No O O I I • PWM0 output port • General-purpose I/O available • PWM1 output port • General-purpose I/O available Reset pin • Input terminal for 32.768kHz X'tal oscillation • Other function AN10 : AD converter input port General input port When not in use, connect terminal to VDD1. • Output terminal for 32.768kHz X'tal oscillation • Other function AN11 : AD converter input port General input port When not in use, set as oscillation and leave terminal open No No No No XT2 I/O No CF1 CF2 I O Input terminal for ceramic resonator Output terminal for ceramic resonator No No No.7972-11/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Port Output Configuration Output configuration and pull-up resistor options are shown in the following table. Input is possible even when a port is in output mode. Terminal P00 to P07 Option applies to : 1 bit Option 1 2 P10 to P17 P20 to P27 P30 to P36 PA0 to PA5 PB0 to PB7 PC0 to PC7 PE0 to PE7 PF0 to PF7 P70 P71 to P73 P80 to P87 SI2P0, SI2P2 SI2P3 PWM0, PWM1 SI2P1 XT1 XT2 None None None CMOS (when used as general port) Nch-open drain (when used for SIO2 data) Input only Output for 32.768kHz crystal oscillation Nch-open drain (when in general-purpose output mode) None None None None None None None Nch-open drain CMOS Nch-open drain CMOS Programmable Programmable None None None CMOS Programmable 1 bit 1 2 CMOS Nch-open drain Programmable Programmable 1 bit 1 2 CMOS Nch-open drain CMOS Nch-open drain Output format Pull-up resistor Programmable (Note 1) None Programmable Programmable Note 1 Programmable pull-up resistor of Port 0 is specified in nibble units (P00 to P03, P04 to P07). Note : To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, VSS3 and VSS4 should connect to each other and they should also be grounded. Example 1 : During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 No.7972-12/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Example 2 : During backup in hold mode, output is not held high and its value in unsettled. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 No.7972-13/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Absolute Maximum Ratings / Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Limits Parameter Supply voltage Input voltage Output voltage Input/output voltage Symbol VDD max VI (1) VO (1) VIO (1) Pins VDD1, VDD2, VDD3, VDD4 XT1, XT2, CF1 PWM0, PWM1 • Ports 0, 1, 2 • Ports 3, 7, 8 • Ports A, B, C, E, F • SI2P00 to SI2P03 • PWM0, PWM1 High level output current IOPH (2) Total output current Peak output current IOPH (1) • Ports 0, 1, 2, 3 • Ports A, B, C, E, F • SI2P00 to SI2P03 • PWM0, PWM1 P71 to P73 P71 to P73 • Port 1 • PWM0, PWM1 • Port 3 • SI2P00 to SI2P03 For each pin. Total of all pins Total of all pins -30 -5 -5 • CMOS output • For each pin. -10 -0.3 Conditions VDD[V] VDD1=VDD2 =VDD3=VDD4 min -0.3 -0.3 -0.3 typ max +6.5 unit VDD+0.3 VDD+0.3 V VDD+0.3 ΣIOAH (1) ΣIOAH (2) ΣIOAH (3) ΣIOAH (4) ΣIOAH (5) Low level output current IOPL (2) IOPL (3) Total output current Peak output current IOPL (1) Ports 0, 2 Port B Ports A, C • P02 to P07 • Ports 1, 2, 3 • Ports A, B, C, E, F • SI2P00 to SI2P03 • PWM0, PWM1 P00, P01 Ports 7, 8 Port 7 Port 8 • PWM0, PWM1 • Port 3 • SI2P00 to SI2P03 Total of all pins Total of all pins Total of all pins For each pin. -20 -20 -20 20 mA For each pin. For each pin. Total of all pins Total of all pins Total of all pins 30 5 15 15 40 ΣIOAL (1) ΣIOAL (2) ΣIOAL (3) ΣIOAL (4) ΣIOAL (5) ΣIOAL (6) ΣIOAL (7) ΣIOAL (8) Maximum power consumption Operating temperature range Storage temperature range Tstg Topr Pd max Ports 0, 2, 3 Port B Ports A, C Port F Port 1, E QIP100E TQFP100 Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Ta= -30 to +70°C 80 40 40 40 70 519 363 -30 -55 70 °C 125 mW No.7972-14/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Recommended Operating Range / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Operating supply voltage range HOLD voltage Input high voltage VHD VIH (1) VDD1=VDD2 =VDD3=VDD4 • Ports 1, 2, 3 • SI2P00 to 03 • P71 to P73 • P70 port input /interrupt VIH (2) VIH (3) VIH (4) Input low voltage VIL (1) • Ports 0, 8 • Ports A, B, C, E, F Port 70 watchdog timer XT1, XT2, CF1, RES • Ports 1, 2, 3 • SI2P00 to 03 • P71 to P73 • P70 port input /interrupt VIL (2) VIL (5) VIL (6) Operation cycle time External system clock frequency FEXCF (1) CF1 • Leave CF2 pin open • System clock divider set to 1/1 • External clock DUTY=50±5% • Leave CF2 pin open • System clock divider set to 1/1 • External clock DUTY=50±5% • Leave CF2 pin open • System clock divider set to 1/2 • Leave CF2 pin open • System clock divider set to 1/2 Oscillation frequency Range (Note1) FmCF (2) CF1, CF2 FmCF (1) CF1, CF2 10MHz ceramic resonator oscillation Refer to figure 1 5MHz ceramic resonator oscillation Refer to figure 1 FmRC FmMRC FsX’tal XT1, XT2 RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal resonator oscillation Refer to figure 2 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 0.3 1.0 50 2.0 2.5 to 5.5 5 4.5 to 5.5 10 2.5 to 5.5 4.5 to 5.5 0.2 0.1 20.4 10 MHz 2.5 to 5.5 0.1 5 tCYC • Ports 0, 8 • Ports A, B, C, E, F Port 70 Watchdog timer XT1, XT2, CF1, RES 4.5 to 5.5 2.5 to 5.5 4.5 to 5.5 0.1 10 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 VSS VSS VSS 0.294 0.588 VSS 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 0.3VDD +0.7 0.9VDD VDD VDD VDD V Symbol VDD (1) Pins VDD1=VDD2 =VDD3=VDD4 Conditions 0.294µs ≤ tCYC ≤ 200µs 0.588µs ≤ tCYC ≤ 200µs RAM and register data are kept in HOLD mode. 2.5 to 5.5 0.3VDD +0.7 VDD Limits VDD[V] min 4.5 2.5 2.0 typ max 5.5 5.5 5.5 unit 0.75VDD 0.1VDD +0.4 0.15VDD +0.4 0.8VDD -1.0 0.25VDD 200 200 µs 32.768 kHz Note 1 : The oscillation parameters are shown on Tables 1 and 2. No.7972-15/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Electrical Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Input high current Symbol IIH (1) Pins • Ports 0, 1, 2 • Ports 3, 7, 8 • Ports A, B, C • SI2P00 to SI2P03 • RES • PWM0, PWM1 IIH (2) IIH (3) Input low current IIL (1) XT1, XT2 CF1 • Ports 0, 1, 2 • Ports 3, 7, 8 • Ports A, B, C, E, F • SI2P00 to SI2P03 • RES • PWM0, PWM1 IIL (2) IIL (3) Output high voltage VOH (1) VOH (2) VOH (3) VOH (4) VOH (5) VOH (6) Output low voltage VOL (1) VOL (2) VOL (3) VOL (4) VOL (5) Pull-up resistor Rpu XT1, XT2 • Using as an input port • VIN=VSS CF1 • Ports 0, 1, 2, 3 • Ports A, B, C, E, F • SI2P00 to SI2P03 Port 71, 72, 73 PWM0, PWM1 P30, P31 (PWM4, 5 output mode) • Ports 0, 1, 2, 3 • Ports A, B, C, E, F • SI2P00 to SI2P03 • PWM0, PWM1 P00, P01 Ports 7, 8 • Ports 0, 1, 2, 3 • Port 7 • Ports A, B, C, E, F Hysteresis voltage VHIS • RES • Port 1 • Port 2 • Port 3 • Port 7 • SIP00 to SIP03 Pin capacitance CP All pins • All pins except the measured terminal : VIN=VSS • f=1MHz • Ta=25°C 2.5 to 5.5 10 pF 0.1VDD V 2.5 to 5.5 VIN=VSS IOH= -1.0mA IOH= -0.1mA IOH= -1.5mA IOH= -6.0mA IOH= -1.6mA IOH= -1.0mA IOL=10mA IOL=1.6mA IOL=1.0mA IOL=30mA IOL=1.0mA VOH=0.9VDD 2.5 to 5.5 4.5 to 5.5 2.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 2.5 to 5.5 4.5 to 5.5 4.5 to 5.5 2.5 to 5.5 4.5 to 5.5 2.5 to 5.5 2.5 to 5.5 15 40 70 kΩ 2.5 to 5.5 -1 -15 VDD-1 VDD-0.5 VDD-1 VDD-1 VDD-0.4 VDD-0.4 1.5 0.4 0.4 1.5 0.4 V • Using as an input port • VIN=VDD VIN=VDD • Output disable • Pull-up resistor OFF • VIN=VSS (including the off-leak current of the output Tr.) -1 2.5 to 5.5 2.5 to 5.5 2.5 to 5.5 1 15 Conditions • Output disable • Pull-up resistor OFF • VIN=VDD (including the off-leak current of the output Tr.) 1 Limits VDD[V] 2.5 to 5.5 min typ max unit µA No.7972-16/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Serial Input/Output Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Limits Parameter Cycle Low level pulse width Symbol tSCK (1) tSCKL (1) tSCKLA (1) tSCKH (1) tSCKHA (1) tSCK (2) tSCKL (2) tSCKH (2) tSCK (3) tSCKL (3) tSCKLA (2) SCK0 (P12), SI2P2 SI2P3 • CMOS output • Refer to figure 6 SCK0 (P12) SIO0 SI2P2, SI2P3 SIO2 2.5 to 5.5 SCK1 (P15) Refer to figure 6 2.5 to 5.5 Pins SCK0 (P12), SI2P2 Conditions Refer to figure 6 VDD [V] 2.5 to 5.5 min 2 1 1 1 4(SIO0) 5(SIO2) Cycle Low level pulse width High level pulse width Cycle Low level pulse width 2 1 1 4/3 1/2 3/4 1 tSCK 1/2 SCK0 (P12) SIO0 SI2P2, SI2P3 SIO2 Cycle Low level pulse width High level pulse width Data set-up time tSCKH (4) tsDI SB0 (P11), SB1 (P14), SI2P1 Data hold time thDI SI0 SI1 Output delay time tdD0 SO0 (P10), SO1 (P13), SB0 (O11), SB1 (P14), SI2P0, SI2P1 • Data hold from SI0CLK • Time delay from SI0CLK trailing edge to the SO data change in the open drain • Refer to figure 6 2.5 to 5.5 • Data set-up to SI0CLK • Data hold from SI0CLK • Refer to figure 6 0.03 2.5 to 5.5 0.03 tSCK (4) tSCKL (4) SCK1 (P15) • CMOS output • Refer to figure 6 1/2 tSCK 1/2 2.5 to 5.5 2 2 7/4 tCYC tCYC typ max unit Input clock Serial clock Output clock High level pulse width High level pulse width tSCKH (3) tSCKHA (2) Serial input µs 1/3tCYC +0.05 Serial output No.7972-17/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Pulse Input Conditions / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter High/low level pulse width Symbol tPIH (1) tPIL (1) Pins INT0 (P70), INT1 (P71), INT2 (P72) INT4 (P20 to P23) INT5 (P24 to P27) tPIH (2) tPIL (2) tPIH (3) tPIL (3) tPIH (4) tPIL (4) tPIL (5) INT3 (P73) (The noise rejection clock is selected to 1/1.) INT3 (P73) (The noise rejection clock is selected to 1/32.) INT3 (P73) (The noise rejection clock is selected to 1/128.) RES • Interrupt acceptable • Timer 0 event input acceptable • Interrupt acceptable • Timer 0 event input acceptable • Interrupt acceptable • Timer 0 event input acceptable Reset acceptable 2.5 to 5.5 200 2.5 to 5.5 256 2.5 to 5.5 64 2.5 to 5.5 2 tCYC Conditions • Interrupt acceptable • Timer 0 and 1 event input acceptable 1 Limits VDD [V] 2.5 to 5.5 min typ max unit µs AD Converter Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Resolution Absolute precision Conversion time Symbol N ET TCAD Pins AN0 (P80) to AN7 (P87) AN8 (P70) AN9 (P71) AN10 (XT1) AN11 (XT2) (Note 2) AD conversion time=32 × tCYC (ADCR2=0) (Note 3) 3.0 to 5.5 Conditions VDD [V] 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 15.10 (tCYC= 0.588µs) 31.36 (tCYC= 0.980µs) AD conversion time=64 × tCYC (ADCR2=1) (Note 3) 3.0 to 5.5 4.5 to 5.5 18.82 (tCYC= 0.294µs) 62.72 (tCYC= 0.980µs) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS 3.0 to 5.5 3.0 to 5.5 -1 VAIN 3.0 to 5.5 VSS min typ 8 ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) 97.92 (tCYC= 1.53µs) VDD 1 V Limits max unit bit LSB µs µA Note 2 : Absolute precision excludes the quantizing error (±1/2 LSB). Note 3 : The conversion time is the time from executing the AD conversion instruction to setting the complete digital conversion value in the register. No.7972-18/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Current Dissipation Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Current drain during basic operation (Note 4) Symbol IDDOP (1) Pins VDD1 =VDD2 =VDD3 =VDD4 Conditions • FmCF=10MHz by ceramic resonator • FmX’tal=32.768kHz by crystal oscillation • System clock : CF oscillation (10MHz) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/1 divided IDDOP (2) • CF1=20MHz by external clock • FmX’tal=32.768kHz by crystal oscillation • System clock : CF1 oscillation (20MHz) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/2 divided IDDOP (3) • FmCF=5MHz by ceramic resonator • FmX'tal=32.768kHz by crystal oscillation • System clock : CF oscillation (5MHz) IDDOP (4) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/1 divided IDDOP (5) • FmCF=0Hz (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation IDDOP (6) • System clock : RC oscillation • Frequency variable RC oscillation stops • 1/2 divided IDDOP (7) • FmCF=0Hz (when oscillation stops) • FmX'al=32.768kHz by crystal oscillation IDDOP (8) • System clock : 1MHz with frequency variable RC oscilatin • Internal RC oscillation stops • 1/2 divided IDDOP (9) • FmCF=0Hz (when oscillation stops) • FmX'al=32.768kHz by crystal oscillation IDDOP (10) • System clock : X'tal oscillation (32.768kHz) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/2 divided 2.5 to 4.5 12 40 4.5 to 5.5 27 60 2.5 to 5.5 0.7 3.5 4.5 to 5.5 2 6 2.5 to 4.5 0.3 1.5 4.5 to 5.5 0.7 4 2.5 to 4.5 3 6 mA 4.5 to 5.5 5.5 8 10.5 16 2.5 to 5.5 10 15 Limits VDD [V] 4.5 to 5.5 min typ max unit µA Note 4 : The current of the output transistors and pull-up MOS transistors are excluded. Continued on next page. No.7972-19/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Continued from preceding page. Parameter Current drain in HALT mode (Note 4) Symbol IDDHALT (1) Pins VDD1 =VDD2 =VDD3 =VDD4 • HALT mode • FmCF=10MHz by ceramic resonator • FmX’tal=32.768kHz by crystal oscillation • System clock : CF oscillation (10MHz) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/1 divided IDDHALT (2) • HALT mode • CF1=20MHz by external clock • FmX’tal=32.768kHz by crystal oscillation • System clock : CF1 oscillation (20MHz) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/2 divided IDDHALT (3) • HALT mode • FmCF=5MHz by ceramic resonator • FmX’tal=32.768kHz by crystal oscillation • System clock : CF oscillation (5MHz) IDDHALT (4) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/1 divided IDDHALT (5) • HALT mode • FmCF=0Hz (when oscillation stops) IDDHALT (6) • FmX’tal=32.768kHz by crystal oscillation • System clock : RC oscillation • Frequency variable RC oscillation stops • 1/2 divided IDDHALT (7) • HALT mode • FmCF=0Hz (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation IDDHALT (8) • System clock : 1MHz with frequency variable RC oscilatin • Internal RC oscillation stops • 1/2 divided IDDHALT (9) • HALT mode • FmCF=0Hz (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation IDDHALT (10) • System clock : X'tal oscillation (32.768kHz) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/2 divided Current drain during HOLD mode Current drain during time-base clock HOLD mode IDDHOLD (4) IDDHOLD (2) IDDHOLD (3) VDD1 IDDHOLD (1) VDD1 • HOLD mode • CF1=VDD or leave it open (when using external clock) • Time-base clock HOLD mode • CF1=VDD or leave it open (when using external clock) • FmX'tal=32.768kHz by crystal oscillation 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5 0.015 0.001 14 3.8 10 5 35 20 2.5 to 4.5 5 25 4.5 to 5.5 16 40 2.5 to 4.5 0.6 1.8 4.5 to 5.5 1.6 2.5 2.5 to 4.5 0.15 0.5 4.5 to 5.5 0.3 1 2.5 to 4.5 0.7 1.5 mA 4.5 to 6.0 1.5 3 3.2 6 4.5 to 5.5 2.5 5 Conditions Limits VDD [V] 4.5 to 5.5 min typ max unit µA Note 4 : The current of the output transistors and pull-up MOS transistors are excluded. No.7972-20/25 LC875BP4A/875BM2A/875BJ0A/875BH4A UART (full duplex) Operating Conditions / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Clock rate Symbol UBR, UBR2 Pins UTX1 (P32), RTX1 (P33), UTX2 (P33), RTX2 (P34) Conditions VDD [V] 2.5 to 5.5 16/3 8192/3 tCYC min typ Limits max unit Data length : Stop bits : Parity bits : 7, 8 and 9 bits (LSB first) 1-bit Non Continuous 8-bit data transmit mode (first transmit data = 55H) Start bit Beginning of transmission Stop bit Transmit data (LSB first) End of transmittion UBR, UBR2 Continuous 8-bit data receive mode (first transmit data = 55H) Stop bit Received data (LSB first) End of reception Start bit Beginning of reception UBR, UBR2 No.7972-21/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Main System Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions : 1. Using the standard oscillation evaluation board SANYO has provided. 2. Using the external peripheral parts with the indicated value. 3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. Table 1. Recommended circuit parameters for the main system clock using the ceramic resonator Recommended circuit Frequency Manufacturer Oscillator C1 10MHz MURATA CSLS10M0G53-R0 CSTLS10M0G52-B0 5MHz MURATA CSTLS5M00G53-R0 CSTLS5M00G53-B0 (10pF) (10pF) (15pF) (15pF) parameters C2 (10pF) (10pF) (15pF) (15pF) Rd1 150Ω 100Ω 470Ω 470Ω Operating supply voltage range 4.5 to 5.5V 4.5 to 5.5V 2.5 to 5.5V 2.5 to 5.5V Oscillation stabilizing time typ max Internal C1,C2 Internal C1,C2 Internal C1,C2 Internal C1,C2 Note *The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure 4) Subsystem Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions : 1. Using the standard oscillation evaluation board SANYO has provided. 2. Using the external peripheral parts with the indicated value. 3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. Table 2. Recommended circuit parameters for the subsystem clock using the crystal oscillation Recommended circuit Frequency Manufacturer Oscillator C3 32.768kHz SEIKO EPSON MC-306 15pF Parameters C4 15pF Rf OPEN Rd2 390kΩ Operating supply voltage range 2.5 to 5.5V Oscillation stabilizing time typ max Note *The oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which starts the sub-clock oscillator or after releasing a HOLD mode. (Refer to Figure 4) Notes : Since the oscillation frequency precision is affected by the circuit pattern, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length. CF1 CF2 Rd1 XT1 XT2 Rf Rd2 C1 CF C2 C3 X’tal C4 Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing point No.7972-22/25 LC875BP4A/875BM2A/875BJ0A/875BH4A VDD Power Supply VDD limit GND Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution Reset time and oscillation stabilizing time HOLD release signal HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsXtal XT1, XT2 Operation mode HOLD HALT HOLD release signal and oscillation stabilizing time Figure 4 Oscillation stabilizing time No.7972-23/25 LC875BP4A/875BM2A/875BJ0A/875BH4A VDD RRES RES CRES (Note) Select CRES and RRES value to assure that at least 200µs reset time is generated after the VDD becomes higher than the minimum operating voltage. Figure 5 Reset circuit SI0CLK : DATAIN : DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT : DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transmission period (only SIO0, 2) DO8 tSCK tSCKL SI0CLK : tsDI DATAIN : tdDO DATAOUT : Data RAM transmission period (only SIO0, 2) tSCKLA SI0CLK : tsDI DATAIN : tdDO DATAOUT : thDI tSCKHA thDI tSCKH Figure 6 Serial input/output test condition tPIL tPIH Figure 7 Pulse input timing condition No.7972-24/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 2005. Specifications and information herein are subject to change without notice. PS No.7972-25/25