C8051F043

C8051F043 25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU Analog Peripherals 10-Bit ADC High-Speed 8051 µC Core - - ±1 LSB INL; guaranteed monotonic Programmable throughput up to 100 ksps 13 external inputs; programmable as single-ended or differential Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 Data-dependent windowed interrupt generator Built-in temperature sensor (±3 °C) 60 V common mode input range Offset adjust from –60 to +60 V 16 gain settings from 0.05 to 16 Programmable throughput up to 500 ksps 8 external inputs; programmable as single-ended or differential Programmable amplifier gain: 4, 2, 1, 0.5 Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler 4352 bytes data RAM 64 kB Flash; in-system programmable in 512-byte sectors (512 bytes are reserved) External parallel data memory interface 32 message objects ”Mailbox" implementation only interrupts CPU when needed 32 port I/O; all are 5 V tolerant Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial ports available concurrently Programmable 16-bit counter array with 6 capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using timer 3 or PCA Internal programmable 2% oscillator: up to 25 MHz External oscillator: Crystal, RC, C, or Clock Typical operating current: 10 mA at 25 MHz Multiple power saving sleep and shutdown mode Memory High-Voltage Differential Amplifier CAN Bus 2.0B Digital Peripherals 8-Bit ADC Two 12-Bit DACs Three Comparators Internal Voltage Reference Precision VDD Monitor/Brown-out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor, program trace memory Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan Clock Sources Supply Voltage: 2.7 to 3.6 V 64-Pin TQFP - Temperature Range: –40 to +85 °C UART0 UART1 P0 Drv P0.0 P0.7 VDD VDD VDD DGND DGND DGND AV+ AV+ AGND AGND TCK TMS TDI TDO RST Digital Power Analog Power JTAG Logic Boundary Scan Debug HW Reset 8 0 5 1 C o r e SFR Bus SMBus SPI Bus PCA Timers 0,1,2,3,4 64 kB FLASH 32x136 CANRAM 256 byte RAM 4 kB XRAM MONEN VDD Monitor External Oscillator Circuit VREF DAC1 (12-Bit) DAC0 (12-Bit) Port 0,1,2,3 &4 Latches C R O S S B A R P1 Drv P1.0/AIN1.0 P1.7/AIN1.7 P2 Drv P2.0/CPx P2.7/CPx P3 Drv P3.0/AIN0.6 P3.7/AIN0.7 CTX0 CRX0 WDT XTAL1 XTAL2 VREF CAN 2.0B ADC 500 ksps (8-Bit) VREFA CP1 CP2 Prog Gain System Clock A M U X 8:1 DAC1 Internal 2% Oscillator CP0 + + + - P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 DAC0 VREFA AIN0.0 AIN0.1 AIN0.2 AIN0.3 A M U X Prog Gain ADC 100 ksps (10-Bit) Port 4 External Data Memory Bus Bus Control Address [15:0] P4 DRV Ctrl Latch P5 Latch Addr [7:0] P6 Latch Addr [15:8] P7 Latch P5 DRV P6 DRV P7 DRV TEMP SENSOR A M U X HVAIN+ HVAMP 8:2 Data [7:0] HVAINHVREF HVCAP Data Latch CAN 2.0B Copyright © 2004 by Silicon Laboratories 6.15.2004 C8051F043 25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current (CPU Clock = 25 MHz active) Clock = 1 MHz Clock = 32 kHz; VDD Monitor Enabled Supply Current Oscillator not running; VDD Monitor (shutdown) Disabled Clock Frequency Range A/D CONVERTER Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Distortion Throughput Rate Input Voltage Range D/A CONVERTERS Resolution Differential Nonlinearity Output Settling Time COMPARATORS Supply Current (each Comparator) Response Time | CP+ – CP- | = 100 mV MIN 2.7 10 0.5 20 0.1 DC 10 ±1 ±1 59 0 12 ±1 10 1.5 4 100 VREF 25 TYP MAX 3.6 UNITS V mA mA µA µA MHz bits LSB LSB dB ksps V LSB LSB µs µA µs Package Information D D1 C8051F040DK Development Kit MIN NOM MAX (mm) (mm) (mm) A - - 1.20 0.15 1.05 A1 0.05 E1 E A2 0.95 b 0.17 0.22 0.27 12.00 10.00 0.50 12.00 10.00 - 64 PIN 1 DESIGNATOR 1 A2 e A b A1 D D1 e E E1 CAN 2.0B Copyright © 2004 by Silicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders