SI2200-X-GM

Si2200 RF SYNTHESIZER WITH INTEGRATED VCOS FOR SATELLITE RADIO Features ! Dual-band RF synthesizers " " ! ! ! ! ! ! RF1: 2300 to 2500 MHz RF2: 2025 to 2300 MHz 62.5 to 1000 MHz ! ! IF synthesizer " Integrated VCOs, loop filters, varactors, and resonators Minimal external components required Low phase noise 5 µA standby current 25.7 mA typical supply current 2.9 to 3.6 V operation 28-lead QFN " Ordering Information: See page 28. Lead-Free and RoHS Compliant Applications ! Pin Assignments Satellite Radio Si2200-GM Description The Si2200 is a monolithic integrated circuit that performs both IF and RF synthesis for wireless communications applications. The Si2200 includes three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and powerdown settings are programmable through a three-wire serial interface. SDATA IFOUT SCLK VDDI GND SEN GND 28 27 26 25 24 23 22 GND GND NC 1 2 3 4 5 6 7 8 GND 21 20 19 GND IFLB IFLA GND VDDD GND XIN Functional Block Diagram GND NC GND GND 18 17 16 15 XIN Reference Amplifier Power Down Control ÷1/÷2 ÷RRF1 Phase Detect RF1 GND 9 GND 10 11 12 13 14 AUXOUT PWDN RFOUT VDDR GND PWDN ÷NRF1 ÷RRF2 Phase Detect ÷2 RFOUT SDATA SCLK SEN Serial Interface 22-bit Data Register RF2 ÷NRF2 ÷RIF Phase Detect ÷2 Patents pending IFDIV IFOUT AUXOUT Test Mux IF ÷NIF IFLA IFLB Rev. 1.0 5/05 Copyright © 2005 by Silicon Laboratories Si2200 S i2200 2 Rev. 1.0 S i2200 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2. Setting the IF VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3. Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4. Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5. PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6. RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7. Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8. Powerdown Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.9. Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4. Pin Descriptions: Si2200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6. Package Outline: Si2200-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Rev. 1.0 3 S i2200 1. Electrical Specifications Table 1. Recommended Operating Conditions1,2 Parameter Ambient Operating Temperature Ambient Functional Temperature Supply Voltage Supply Voltages Difference Symbol TA TF VDD V∆ (VDDR – VDDD), (VDDI – VDDD) Test Condition Min –40 –40 2.9 –0.3 Typ 25 25 3.3 — Max 85 95 3.6 0.3 Unit °C °C V V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. Minimum and maximum specifications are not guaranteed across the functional temperature range. Table 2. Absolute Maximum Ratings1,2 Parameter DC Supply Voltage Input Current3 Input Voltage3 Storage Temperature Range Symbol VDD IIN VIN TSTG Value –0.5 to 4.0 ±10 –0.3 to VDD+0.3 –55 to 150 Unit V mA V oC Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDATA, SEN, PWDN, and XIN. 4 Rev. 1.0 S i2200 Table 3. DC Characteristics (VDD = 2.7 to 3.6 V, TA = –40 to 85 °C) Parameter Total Supply Current 1 Symbol Test Condition RF1 and IF operating Min — — — — Typ 28.7 19.5 18.5 10 1 — — — — — — Max 35 24 23 12 — — 0.3 VDD 10 10 — 0.4 Unit mA mA mA mA µA V V µA µA V V RF1 Mode Supply Current1 RF2 Mode Supply Current1 IF Mode Supply Current1 Standby Current High Level Input Voltage2 Low Level Input Voltage2 High Level Input Current2 Low Level Input Current2 High Level Output Voltage3 Low Level Output Voltage3 VIH VIL IIH IIL VOH VOL VIH = 3.6 V, VDD = 3.6 V VIL = 0 V, VDD= 3.6 V IOH = –500 µA IOH = 500 µA PWDN = 0 — 0.7 VDD — –10 –10 VDD–0.4 — Notes: 1. RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0. 2. For signals SCLK, SDATA, SEN, and PWDN. 3. For signal AUXOUT. Rev. 1.0 5 S i2200 Table 4. Serial Interface Timing (VDD = 2.7 to 3.6 V, TA = –40 to 85 °C) Parameter1 SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time SDATA Setup Time to SCLK↑2 SDATA Hold Time from SCLK↑2 SEN↓ to SCLK↑ Delay Time 2 Symbol tclk tr tf th tl tsu thold ten1 ten2 ten3 tw Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 40 — — 10 10 5 0 10 12 12 10 Typ — — — — — — — — — — — Max — 50 50 — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns SCLK↑ to SEN↑ Delay Time2 SEN↑ to SCLK↑ Delay Time2 SEN Pulse Width Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to the 50% level of the waveform. See Figure 2. tr 80% tf SCLK 50% 20% th tclk tl Figure 1. SCLK Timing Diagram 6 Rev. 1.0 S i2200 A A Figure 2. Serial Interface Timing Diagram First bit clocked in Last bit clocked in DDDDDDDDDDDDDDDDDDAAAA 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 data field Figure 3. Serial Word Format address field Rev. 1.0 7 S i2200 Table 5. RF and IF Synthesizer Characteristics (VDD = 2.7 to 3.6 V, TA = –40 to 85 °C) Parameter1 Symbol Test Condition Min Typ Max Unit XIN Input Frequency XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency fREF fREF VREF fφ XINDIV2 = 0 XINDIV2 = 1 2 25 0.5 — — — — 25 50 VDD +0.3 V 1.0 MHz MHz VPP MHz fφ = fREF/R for XINDIV2 = 0 fφ = fREF/2R for XINDIV2 = 1 0.010 RF1 VCO Tuning Range2 RF2 VCO Tuning Range2 IF VCO Center Frequency Range IFOUT Tuning Range from fCEN IFOUT VCO Tuning Range from fCEN RF1 VCO Pushing RF2 VCO Pushing IF VCO Pushing RF1 VCO Pulling RF2 VCO Pulling IF VCO Pulling RF1 Phase Noise RF1 Integrated Phase Error RF2 Phase Noise RF2 Integrated Phase Error IF Phase Noise at 800 MHz IF Integrated Phase Error 1 MHz offset 100 Hz to 100 kHz 1 MHz offset 100 Hz to 100 kHz 100 kHz offset 100 Hz to 100 kHz VSWR = 2:1, all phases, open loop fCEN with IFDIV Note: L ±10% Open loop 2300 2025 526 62.5 –5 — — — — — — — — — — — — — — — — — 0.75 0.65 0.10 0.250 0.100 0.025 –130 1.2 –131 1.0 –104 0.4 2500 2300 952 1000 5 — — — — — — — — — — — — MHz MHz MHz MHz % MHz/V MHz/V MHz/V MHz p-p MHz p-p MHz p-p dBc/Hz degrees rms dBc/Hz degrees rms dBc/Hz degrees rms Notes: 1. fφ(RF) = 1 MHz, fφ(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0. 2. RF VCO tuning range limits are fixed by inductance of internally bonded wires. 3. From powerup request (PWDN↑ or SEN↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From powerdown request (PWDN↓, or SEN↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. 8 Rev. 1.0 S i2200 Table 5. RF and IF Synthesizer Characteristics (Continued) (VDD = 2.7 to 3.6 V, TA = –40 to 85 °C) Parameter1 Symbol Test Condition Min Typ Max Unit RF1 Harmonic Suppression RF2 Harmonic Suppression IF Harmonic Suppression RFOUT Power Level RFOUT Power Level IFOUT Power Level RF1 Output Reference Spurs Second Harmonic — — — –28 –23 –26 –1 –1 –4 –63 –68 –70 –63 –68 –70 80 40/fφ — –20 –20 –20 3 3 0 — — — — — — 100 50/fφ 100 dBc dBc dBc dBm dBm dBm dBc dBc dBc dBc dBc dBc µs ZL = 50 Ω, RF1 active ZL = 50 Ω, RF2 active ZL = 50 Ω Offset = 1 MHz Offset = 2 MHz Offset = 3 MHz –3 –3 –8 — — — — — — — — — RF2 Output Reference Spurs Offset = 1 MHz Offset = 2 MHz Offset = 3 MHz Powerup Request to Synthesizer Ready3 Time Powerup Request to Synthesizer Ready3 Time Powerdown Request to Synthesizer Off4 Time tpup tpup tpdn Figures 4, 5 fφ > 500 kHz Figures 4, 5 fφ ≤ 500 kHz Figures 4, 5 ns Notes: 1. fφ(RF) = 1 MHz, fφ(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0. 2. RF VCO tuning range limits are fixed by inductance of internally bonded wires. 3. From powerup request (PWDN↑ or SEN↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From powerdown request (PWDN↓, or SEN↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. Rev. 1.0 9 S i2200 RF synthesizers settled to within 0.1 ppm frequency error. tpup tpdn RF synthesizers settled to within 0.1 ppm frequency error. tpup tpdn IT IPWDN SEN IT IPWDN PWDN SDATA PDIB = 1 PDRB = 1 PDIB = 0 PDRB = 0 Figure 4. Software Power Management Timing Diagram Figure 5. Hardware Power Management Timing Diagram 10 Rev. 1.0 S i2200 Figure 6. Typical Transient Response RF1 at 2.4 GHz with 1 MHz Phase Detector Update Frequency Rev. 1.0 11 S i2200 -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 Offset Frequency (Hz) 1.E+05 1.E+06 Typical RF1 Phase Noise at 2.4 GHz Figure 7. Typical RF1 Phase Noise at 2.4 GHz with 1 MHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 2.4 GHz with 1 MHz Phase Detector Update Frequency 12 Rev. 1.0 S i2200 -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 Offset Frequency (Hz) 1.E+05 1.E+06 Typical RF2 Phase Noise at 2.1 GHz Figure 9. Typical RF2 Phase Noise at 2.1 GHz with 1 MHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 2.1 GHz with 1 MHz Phase Detector Update Frequency Rev. 1.0 13 S i2200 -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 Offset Frequency (Hz) 1.E+05 1.E+06 Typical IF Phase Noise at 800 MHz Figure 11. Typical IF Phase Noise at 800 MHz with 1 MHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 800 MHz with 1 MHz Phase Detector Update Frequency 14 Rev. 1.0 S i2200 VDD 30 Ω ∗ 0.022µF From System Controller LMATCH 560 pF IFOUT 28 27 26 25 24 23 22 SDATA SCLK GND 1 2 3 4 5 6 7 IFOUT VDDI GND SEN GND GND NC GND NC GND GND IFLB IFLA 21 20 19 18 Printed Trace Inductor or Chip Inductor Si2200 GND VDDD GND AUXOUT VDD 0.022µF 17 16 560 pF VDDR PWDN GND GND GND RFOUT XIN GND 15 External Clock 8 9 13 10 11 12 14 0.022µF VDD PWDN 560 pF RFOUT *Add 30 Ω series resistor if using IF output divide values 2, 4, or 8 and fCEN < 600 MHz. AUXOUT Figure 13. Typical Application Circuit: Si2200 Rev. 1.0 15 S i2200 2. Functional Description The Si2200 is a monolithic integrated circuit that performs IF and dual-band RF synthesis for many wireless communications applications. This integrated circuit (IC), along with a minimum number of external components, is all that is necessary to implement the frequency synthesis function in applications, such as satellite radio. The Si2200 has three complete phase-locked loops (PLLs) with integrated voltage-controlled oscillators (VCOs). The low phase noise of the VCOs makes the Si2200 suitable for use in demanding wireless communications applications. Also integrated are phase detectors, loop filters, and reference and output frequency dividers. The IC is programmed through a three-wire serial interface. Two PLLs are provided for RF synthesis. These RF PLLs are multiplexed so that only one PLL is active at a given time (as determined by the setting of an internal register). The active PLL is the last one written. The center frequency of the VCO in each PLL is set by the internal bond wire inductance within the package. Inaccuracies in these inductances are compensated for by the self-tuning algorithm. The algorithm is run following power-up or following a change in the programmed output frequency. The RF PLLs contain a divide-by-2 circuit before the Ndivider. As a result, the phase detector frequency (fφ) is equal to half the desired channel spacing. For example, for a 200 kHz channel spacing, fφ would equal 100 kHz. The IF PLL does not contain the divide-by-2 circuit before the N-divider. In this case, fφ is equal to the desired channel spacing. Each RF VCO is optimized for a particular frequency range. The RF1 VCO is optimized to operate from 2.3 to 2.5 GHz, while the RF2 VCO is optimized to operate between 2.025 and 2.3 GHz. One PLL is provided for IF synthesis. The center frequency of this circuit’s VCO is set by an external inductance. The PLL can adjust the IF output frequency by ±5% of the VCO center frequency. Inaccuracies in the value of the external inductance are compensated for by the Si2200’s proprietary self-tuning algorithm. This algorithm is initiated each time the PLL is poweredup (by either the PWDN pin or by software) and/or each time a new output frequency is programmed. The IF VCO can have its center frequency set as low as 526 MHz and as high as 952 MHz. An IF output divider is provided to divide down the IF output frequencies, if needed. The divider is programmable and capable of dividing by 1, 2, 4, or 8. In order to accommodate designs running at XIN frequencies greater than 25 MHz, the Si2200 includes a programmable divide-by-2 option (XINDIV2 in Register 0, D6) on the XIN input. By enabling this option, the Si2200 can accept a range of TCXO frequencies from 25 to 50 MHz. The unique PLL architecture used in the Si2200 produces settling (lock) times that are comparable in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. 2.1. Serial Interface A timing diagram for the serial interface is shown in Figure 2 on page 7. Figure 3 on page 7 shows the format of the serial word. The Si2200 is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. When the serial interface is enabled (i.e., when SEN is low) data and address bits on the SDATA pin are clocked into an internal shift register on the rising edge of SCLK. Data in the shift register is then transferred on the rising edge of SEN into the internal data register addressed in the address field. The serial interface is disabled when SEN is high. Table 11 on page 21 summarizes the data register functions and addresses. It is not necessary (although it is permissible) to clock into the internal shift register any leading bits that are “don’t cares.” 2.2. Setting the IF VCO Center Frequencies The IF PLL can adjust its output frequency ±5% from the center frequency as established by the value of an external inductance connected to the VCO. The RF1 and RF2 PLLs have fixed operating ranges due to the inductance set by the internal bond wires. Each center frequency is established by the value of the total inductance (internal and/or external) connected to the respective VCO. Manufacturing tolerance of ±10% for the external inductor is acceptable for the IF VCO. The Si2200 will compensate for inaccuracies by executing a self-tuning algorithm following PLL power-up or following a change in the programmed output frequency. Because the total tank inductance is in the low nH range, the inductance of the package needs to be considered in determining the correct external inductance. The total inductance (LTOT) presented to the IF VCO is the sum of the external inductance (LEXT) and the package inductance (LPKG). The IF VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as follows: 16 Rev. 1.0 S i2200 1 1 f CEN = ---------------------------------------------- = -----------------------------------------------------------------------2 π L TOT × C NOM 2 π ( L PKG + L EXT ) × C NOM 2.3. Self-Tuning Algorithm The self-tuning algorithm is initiated immediately following power-up of a PLL or, if the PLL is already powered, following a change in its programmed output frequency. This algorithm attempts to tune the VCO so that its free-running frequency is near the desired output frequency. In so doing, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the IF VCO. It will also reduce the frequency error for which the PLL must correct to get the precise desired output frequency. The self-tuning algorithm will leave the VCO oscillating at a frequency in error by somewhat less than 1% of the desired output frequency. After self-tuning, the PLL controls the VCO oscillation frequency. The PLL will complete frequency locking, eliminating any remaining frequency error. Thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations. The Si2200’s self-tuning algorithm will compensate for component value errors at any temperature within the specified temperature range. However, the ability of the PLL to compensate for drift in component values that occur after self-tuning is limited. For external inductances with temperature coefficients around ±150 ppm/°C, the PLL will be able to maintain lock for changes in temperature of approximately ±30 °C. Applications where the PLL is regularly powered-down or the frequency is periodically reprogrammed minimize or eliminate the potential effects of temperature drift because the VCO is re-tuned in either case. In applications where the ambient temperature can drift substantially after self-tuning, it may be necessary to monitor the lock-detect bar (LDETB) signal on the AUXOUT pin to determine whether a PLL is about to run out of locking capability. (See “Auxiliary Output (AUXOUT)” for how to select LDETB.) The LDETB signal will be low after self-tuning has completed but will rise when either the IF or RF PLL nears the limit of its compensation range. (LDETB will also be high when either PLL is executing the self-tuning algorithm.) The output frequency will still be locked when LDETB goes high, but the PLL will eventually lose lock if the temperature continues to drift in the same direction. Therefore, if LDETB goes high both the IF and RF PLLs should promptly be retuned by initiating the self-tuning algorithm. Table 6 summarizes the characteristics of the IF VCO. Table 6. Si2200-GM VCO Characteristics FCEN Range (MHz) Min IF 526 Max 952 6.5 2.1 LEXT Range (nH) Min 2.2 Max 12.0 VCO CNOM LPKG (pF) (nH) Si4136XM LPKG 2 LEXT IFLA LPKG 2 IFLB Figure 14. Example of IF External Inductor As a design example, suppose synthesizing frequencies in a 30 MHz band between 735 and 765 MHz is desired. The center frequency should be defined as midway between the two extremes, or 750 MHz. The PLL will be able to adjust the VCO output frequency ±5% of the center frequency, or ±37.5 MHz of 750 MHz (i.e., from approximately 713 to 788 MHz). The IF VCO has a CNOM of 6.5 pF, and a 6.9 nH inductance (correct to two digits) in parallel with this capacitance will yield the desired center frequency. An external inductance of 4.8 nH should be connected between IFLA and IFLB, as shown in Figure 14. This, in addition to 2.1 nH of package inductance, will present the correct total inductance to the VCO. In manufacturing, the external inductance can vary ±10% of its nominal value, and the Si2200 will correct for the variation with the self-tuning algorithm. For more information on designing the external trace inductor, please refer to “AN31: Inductor Design for the Si41xx Synthesizer Family”. Rev. 1.0 17 S i2200 2.4. Output Frequencies The IF and RF output frequencies are set by programming the R- and N-Divider registers. Each PLL has its own R and N registers so that each can be programmed independently. Programming either the Ror N-Divider register for RF1 or RF2 automatically selects the associated output. When XINDIV2 = 0, the reference frequency on the XIN pin is divided by R, and this signal is the input to the PLL’s phase detector. The other input to the phase detector is the PLL’s VCO output frequency divided by 2N for the RF PLLs or N for the IF PLL. After an initial transient: Table 7. Gain Values (Register 1) KP Bits Relative P.D. Gain 10 11 1/4 1/8 In general, a higher phase detector gain will decrease in-band phase noise and increase the speed of the PLL transient until the point at which stability begins to be compromised. The optimal gain depends on N. Table 8 lists recommended settings for different values of N. Equation 1. fOUT = (2N/R) " fREF (for the RF PLLs) Equation 2. fOUT = (N/R) " fREF (for the IF PLL). The integers R are set by programming the RF1 RDivider register (Register 6), the RF2 R-Divider register (Register 7) and the IF R-Divider register (Register 8). The integers N are set by programming the RF1 NDivider register (register 3), the RF2 N-Divider register (Register 4), and the IF N-Divider register (Register 5). If the optional divide-by-2 circuit on the XIN pin is enabled (XINDIV2 = 1), after an initial transient: fOUT = (N/R) " fREF (for the RF PLLs) fOUT = (N/2R) " fREF (for the IF PLL). Each N-Divider is implemented as a conventional highspeed divider. That is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. However, the control of these sub-circuits is handled automatically. Only the appropriate N value should be programmed. N Table 8. Optimal KP Settings RF1 KP1 RF2 KP2 IF KPI ≤2047 00 00 01 10 11 00 01 10 11 11 00 01 10 11 11 2048 to 4095 4096 to 8191 8192 to 16383 ≥16384 The VCO gain and loop filter characteristics are not programmable. The settling time for each PLL is directly proportional to its phase detector update period Tφ (Tφ equals 1/fφ). During the first 13 update periods, the Si2200 executes the self-tuning algorithm. Thereafter, the PLL controls the output frequency. Because of the unique architecture of the Si2200 PLLs, the time required to settle the output frequency to 0.1 ppm error is only about 25 update periods. Thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled—including time for self-tuning—is around 40 update periods. Note: This settling time analysis holds for fφ ≤ 500 kHz. For fφ > 500 kHz, the settling time can be a maximum of 100 µs as specified in Table 5. 2.5. PLL Loop Dynamics The transient response for each PLL is determined by its phase detector update rate fφ (equal to fREF/R) and the phase detector gain programmed for each RF1, RF2, or IF synthesizer. (See Register 1.) Four different settings for the phase detector gain are available for each PLL. The highest gain is programmed by setting the two phase detector gain bits to 00 and the lowest by setting the bits to 11. The values of the available gains, relative to the highest gain, are listed in Table 7. 2.6. RF and IF Outputs (RFOUT and IFOUT) The RFOUT and IFOUT pins are driven by amplifiers that buffer the RF VCOs and IF VCO, respectively. The RF output amplifier receives its input from either the RF1 or RF2 VCO, depending upon which R- or NDivider register was last written. For example, programming the N-Divider register for RF1 automatically selects the RF1 VCO output. Table 7. Gain Values (Register 1) KP Bits Relative P.D. Gain 00 01 1 1/2 18 Rev. 1.0 S i2200 Figure 13 on page 15 shows an application diagram for the Si2200. The RF output signal must be ac-coupled to its load through a capacitor. The IFOUT pin must also be ac-coupled to its load through a capacitor. The IF output level is dependent upon the load. Figure 17 displays the output level versus load resistance. For resistive loads greater than 500 Ω, the output level saturates, and the bias currents in the IF output amplifier are higher than they need to be. The LPWR bit in the Main Configuration register (Register 0) can be set to 1 to reduce the bias currents and, therefore, reduce the power dissipated by the IF amplifier. For loads less than 500 Ω, LPWR should be set to 0 to maximize the output level. For IF frequencies greater than 500 MHz, a matching network is required in order to drive a 50 Ω load. See Figure 15 below. The value of LMATCH can be determined by Table 9. Typical values range between 8 nH and 40 nH. >500 pF 450 400 350 LPWR=1 LPWR=0 300 Output Voltage (mVrms) 250 200 150 100 50 0 0 200 400 600 Load Resistance (Ω ) 800 1000 1200 Figure 17. Typical IF Output Voltage vs. Load Resistance at 550 MHz 2.7. Reference Frequency Amplifier The Si2200 provides a reference frequency amplifier. If the driving signal has CMOS levels, it can be connected directly to the XIN pin. Otherwise, the reference frequency signal should be ac coupled to the XIN pin through a 560 pF capacitor. IFO UT L MATCH 50 Ω 2.8. Powerdown Modes Table 10 summarizes the powerdown functionality. The Si2200 can be powered down by taking the PWDN pin low or by setting bits in the Powerdown register (Register 2). When the PWDN pin is low, the Si2200 will be powered down regardless of the Powerdown register settings. When the PWDN pin is high, power management is under control of the Powerdown register bits. The IF and RF sections of the Si2200 circuitry can be individually powered down by setting the Powerdown register bits, PDIB and PDRB, low. The reference frequency amplifier will also be powered up if either the PDRB or PDIB bits are high. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (Register 0) is equivalent to setting both bits in the Powerdown register to 1. The serial interface remains available and can be written in all power-down modes. Figure 15. IF Frequencies > 500 MHz Table 9. LMATCH Values Frequency LMATCH 500–600 MHz 600–800 MHz 800–1 GHz 40 nH 27 nH 18 nH For frequencies less than 500 MHz, the IF output buffer can directly drive a 200 Ω resistive load or higher. For resistive loads greater than 500 Ω (f < 500 MHz) the LPWR bit can be set to reduce the power consumed by the IF output buffer. See Figure 16 below. >500 pF 2.9. Auxiliary Output (AUXOUT) The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). >200 Ω IFO UT Figure 16. IF Frequencies < 500 MHz The LDETB signal can be selected by setting the AUXSEL bits to 011. This signal can be used to indicate that the IF or RF PLL is about to lose lock due to excessive ambient temperature drift and should be retuned. Rev. 1.0 19 S i2200 Table 10. Powerdown Configuration PWDN Pin AUTOPDB PDIB PDRB IF Circuitry RF Circuitry PWDN = 0 x 0 0 x 0 0 1 1 x x 0 1 0 1 x OFF OFF OFF ON ON ON OFF OFF ON OFF ON ON PWDN = 1 0 0 1 Note: x = don’t care. 20 Rev. 1.0 S i2200 3. Control Registers Table 11. Register Summary Register Name Bit Bit Bit Bit 17 16 15 14 Bit 13 Bit 12 Bit 11 Bit Bit Bit Bit 10 9 8 7 Bit 6 Bit 5 Bit 4 Bit 3 AUTO PDB Bit 2 Bit 1 Bit 0 0 1 Main Configuration Phase Detector Gain Powerdown RF1 N Divider RF2 N Divider IF N Divider RF1 R Divider RF2 R Divider IF R Divider Reserved 0 0 0 0 0 0 0 0 AUXSEL IFDIV 0 0 1 0 1 0 0 0 XIN LPWR DIV2 0 0 1 KP1 0 0 0 0 KPI KP2 2 3 4 5 6 7 8 9 . . . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB NRF1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRF2 NIF RRF1 RRF2 RIF 15 Reserved Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior. Rev. 1.0 21 S i2200 Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 LPWR D4 D3 AUTO PDB D2 D1 D0 0 0 0 0 AUXSEL IFDIV 1 1 0 XIN DIV2 0 0 1 0 Bit Name Function 17:14 13:12 Reserved AUXSEL Program to zero. Auxiliary Output Pin Definition. 00 = Reserved. 01 = Force output low. 11 = Lock Detect (LDETB). IF Output Divider 00 = IFOUT = IFVCO Frequency 01 = IFOUT = IFVCO Frequency/2 10 = IFOUT = IFVCO Frequency/4 11 = IFOUT = IFVCO Frequency/8 11:10 IFDIV 9:7 6 Reserved XINDIV2 Program to 110. XIN Divide-By-2 Mode. 0 = XIN not divided by 2. 1 = XIN divided by 2. Output Power-Level Settings for IF Synthesizer Circuit. 0 = RLOAD < 500 Ω—normal power mode. 1 = RLOAD ≥ 500 Ω—low power mode. 5 LPWR 4 3 Reserved AUTOPDB Program to zero. Auto Powerdown 0 = Software powerdown is controlled by Register 2. 1 = Equivalent to setting all bits in Register 2 = 1. 2 1 0 Reserved Reserved Reserved Program to zero. Program to one. Program to zero. 22 Rev. 1.0 S i2200 Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001 Bit Name Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 Function KPI KP2 KP1 Name 17:6 5:4 Reserved KPI Program to zero. IF Phase Detector Gain Constant. N Value KPI 8191 11 RF2 Phase Detector Gain Constant. N Value KP2 8191 11 RF1 Phase Detector Gain Constant. N Value KP1 16383 11 3:2 KP2 1:0 KP1 Rev. 1.0 23 S i2200 Register 2. Powerdown Address Field (A[3:0]) = 0010 Bit Name Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 Name 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB Function 17:2 1 Reserved PDIB Program to zero. Powerdown IF Synthesizer. 0 = IF synthesizer powered down. 1 = IF synthesizer on. Powerdown RF Synthesizer. 0 = RF synthesizer powered down. 1 = RF synthesizer on. 0 PDRB Register 3. RF1 N Divider Address Field (A[3:0]) = 0011 Bit Name Bit Name D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NRF1 Function N Divider for RF1 Synthesizer. NRF1 ≥ 992. 17:0 NRF1 Register 4. RF2 N Divider Address Field = A[3:0] = 0100 Bit Name Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 Name NRF2 Function 17 16:0 Reserved NRF2 Program to zero. N Divider for RF2 Synthesizer. NRF2 ≥ 240. 24 Rev. 1.0 S i2200 Register 5. IF N Divider Address Field (A[3:0]) = 0101 Bit Name Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Name NIF Function 17:16 15:0 Reserved NIF Program to zero. N Divider for IF Synthesizer. NIF ≥ 56. Register 6. RF1 R Divider Address Field (A[3:0]) = 0110 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Name 0 0 RRF1 Function 17:13 12:0 Reserved RRF1 Program to zero. R Divider for RF1 Synthesizer. RRF1 can be any value from 7 to 8189 if KP1 = 00 8 to 8189 if KP1 = 01 10 to 8189 if KP1 = 10 14 to 8189 if KP1 = 11 Register 7. RF2 R Divider Address Field (A[3:0]) = 0111 Bit Name Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Name 0 0 RRF2 Function 17:13 12:0 Reserved RRF2 Program to zero. R Divider for RF2 Synthesizer. RRF2 can be any value from 7 to 8189 if KP2 = 00 8 to 8189 if KP2 = 01 10 to 8189 if KP2 = 10 14 to 8189 if KP2 = 11 Rev. 1.0 25 S i2200 Register 8. IF R Divider Address Field (A[3:0]) = 1000 Bit Name Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Name 0 0 RIF Function 17:13 12:0 Reserved RIF Program to zero. R Divider for IF Synthesizer. RIF can be any value from 7 to 8189 if KP1 = 00 8 to 8189 if KP1 = 01 10 to 8189 if KP1 = 10 14 to 8189 if KP1 = 11 26 Rev. 1.0 S i2200 4. Pin Descriptions: Si2200 SDATA IFOUT SCLK VDDI GND SEN GND 28 27 26 25 24 23 22 GND GND NC GND NC GND GND 1 2 3 4 5 6 7 8 GND 21 20 19 GND IFLB IFLA GND VDDD GND XIN GND 18 17 16 15 9 GND 10 11 12 13 14 AUXOUT PWDN RFOUT VDDR GND Pin Number(s) Name Description 1, 2, 4, 6, 7–9, 14, GND 16, 18, 21, 22, 28 3, 5 10 11 12 13 15 17 19, 20 23 24 25 26 27 NC RFOUT VDDR AUXOUT PWDN XIN VDDD IFLA, IFLB IFOUT VDDI SEN SCLK SDATA Common ground No connect Radio frequency (RF) output of the selected RF VCO Supply voltage for the RF analog circuitry Auxiliary output Powerdown input pin Reference frequency amplifier input Supply voltage for digital circuitry Pins for inductor connection to IF VCO Intermediate frequency (IF) output of the IF VCO Supply voltage for IF analog circuitry Enable serial port input Serial clock input Serial data input Rev. 1.0 27 S i2200 5. Ordering Guide Ordering Part Number Description Temp. Range Si2200-X-GM 2.5 GHz/2.3 GHz/IF OUT, Lead-free, QFN –40 to 85 oC Notes: 1. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 2. “X” denotes product revision. 28 Rev. 1.0 S i2200 6. Package Outline: Si2200-GM Figure 18 illustrates the package details for the Si2200-GM. Table 12 lists the values for the dimensions shown in the illustration. Figure 18. 28-Pin Quad Flat No-Lead (QFN) Table 12. Si2200-GM Package Diagram Dimensions Dimension Min. Nom. Max. A A1 b D D2 e E E2 L Q aaa bbb ccc ddd 0.80 0.00 0.18 2.55 0.85 0.01 0.23 5.00 BSC. 2.70 0.50 BSC. 5.00 BSC. 0.90 0.05 0.30 2.85 2.55 0.50 — — — — — 2.70 0.60 — — — — — 2.85 0.70 12° 0.10 0.10 0.05 0.10 Rev. 1.0 29 S i2200 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: SDARSinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 30 Rev. 1.0