SI4731-C40-GM

Si4730/31-C40 B ROADCAST AM/FM R ADIO R ECEIVER Features    Integrated LDO regulator  2.0 to 5.5 V supply voltage (SSOP)  2.7 to 5.5 V supply voltage (QFN) air loop antennas supported     Modules  Clock radios  Mini HiFi  Entertainment systems Description The Si4730/31 is the first digital CMOS AM/FM radio receiver IC that integrates the complete tuner function from antenna input to audio output. Functional Block Diagram Si473x AMI RDS (Si4731) LNA AGC LOW-IF ADC AGC ADC AFC RCLK LDO Rev. 1.0 12/09 DFS GPO/DCLK DAC ROUT DAC LOUT 1 19 18 17 16 FMI 2 15 DOUT RFGND 3 14 LOUT GND PAD AMI 4 13 ROUT RST 5 12 GND 6 7 8 9 10 11 VDD Si4730/31 (SSOP) DOUT 1 24 LOUT DFS 2 23 ROUT GPO3/DCLK 3 22 DBYP GPO2/INT 4 21 VDD GPO1 5 20 VIO NC 6 19 RCLK NC 7 18 SDIO FMI 8 17 SCLK RFGND 9 16 SEN NC 10 15 RST NC 11 14 GND AMI 12 13 GND DSP 2.7– 5.5 V (QFN) 2.0– 5.5 V (SSOP) VDD GND DOUT CONTROL INTERFACE VIO 1.85–3.6 V RST LNA SEN FMI SCLK FM ANT DIGITAL AUDIO (Si4731) SDIO RFGND 20 RoHS compliant NC Table and portable radios Stereos Mini/micro systems CD/DVD players Boom boxes AM ANT Si4730/31 (QFN)  QFN and SSOP packages Applications  Pin Assignments  Wide range of ferrite loop sticks and   Ordering Information: See page 31. DFS   2-wire and 3-wire control interface GPO3/DCLK   Optional digital audio out (Si4731) VIO   RDS/RBDS processor (Si4731) GPO2/INT   Adjustable soft mute control GPO1   Volume control SDIO   Programmable reference clock RCLK   No manual alignment necessary NC   EN55020 compliant SEN  (64–108 MHz) Worldwide AM band support (520–1710 kHz) Excellent real-world performance Freq synthesizer with integrated VCO Advanced AM/FM seek tuning Automatic frequency control (AFC) Automatic gain control (AGC) Digital FM stereo decoder Programmable AVC max gain Programmable de-emphasis Seven selectable AM channel filters AM/FM digital tuning SCLK  Worldwide FM band support Copyright © 2009 by Silicon Laboratories This product, its features, and/or its architecture is covered by one or more of the following patents, as well as other patents, pending and issued, both foreign and domestic: 7,127,217; 7,272,373; 7,272,375; 7,321,324; 7,355,476; 7,426,376; 7,471,940; 7,339,503; 7,339,504. Si4730/31-C40 Si4730/31-C40 2 Rev. 1.0 Si4730/31-C40 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Typical Application Schematic (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4. Bill of Materials (QFN/SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.5. Digital Audio Interface (Si4731 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.7. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.9. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.10. RDS/RBDS Processor (Si4731 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.11. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.12. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.13. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.14. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.15. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.16. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.17. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.18. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. Pin Descriptions: Si4730/31-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. Pin Descriptions: Si4730/31-GU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.1. Si4730/31 Top Mark (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2. Top Mark Explanation (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.3. Si4730/31 Top Mark (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.4. Top Mark Explanation (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11. Package Outline: Si4730/31 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12. PCB Land Pattern: Si4730/31 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13. Package Outline: Si4730/31 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. PCB Land Pattern: Si4730/31 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Rev. 1.0 3 Si4730/31-C40 1. Electrical Specifications Table 1. Recommended Operating Conditions1 Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage2 VDD 2.7 — 5.5 V Interface Supply Voltage VIO 1.85 — 3.6 V Power Supply Powerup Rise Time VDDRISE 10 — — µs Interface Power Supply Powerup Rise Time VIORISE 10 — — µs TA –20 25 85 C Ambient Temperature Note: 1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. 2. SSOP devices operate down to VDD = 2 V at 25 °C. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit Supply Voltage VDD –0.5 to 5.8 V Interface Supply Voltage VIO –0.5 to 3.9 V Input Current3 IIN 10 mA Voltage3 VIN –0.3 to (VIO + 0.3) V Operating Temperature TOP –40 to 95 C Storage Temperature TSTG –55 to 150 C 0.4 VPK Input RF Input Level4 Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4730/31 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. At RF input pins, FMI and AMI. 4 Rev. 1.0 Si4730/31-C40 Table 3. DC Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit — 19.2 22 mA — 19.9 23 mA — 19.2 23 mA — 15.4 20.5 mA FM Mode Supply Current1 IFM 2 IFM Supply Current RDS Supply Current1 Low SNR level IFM AM Mode Supply Current1 IAM Analog Output Mode Supplies and Interface Interface Supply Current IIO — 320 600 µA VDD Powerdown Current IDDPD — 10 20 µA VIO Powerdown Current IIOPD — 1 10 µA SCLK, RCLK inactive 3 VIH 0.7 x VIO — VIO + 0.3 V 3 VIL –0.3 — 0.3 x VIO V 3 IIH VIN = VIO = 3.6 V –10 — 10 µA 3 IIL VIN = 0 V, VIO = 3.6 V –10 — 10 µA High Level Output Voltage4 VOH IOUT = 500 µA 0.8 x VIO — — V 4 VOL IOUT = –500 µA — — 0.2 x VIO V High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Low Level Output Voltage Notes: 1. Specifications are guaranteed by characterization. 2. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. Rev. 1.0 5 Si4730/31-C40 Table 4. Reset Timing Characteristics1,2,3 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µs GPO1, GPO2/INT Hold from RST tHRST 30 — — ns Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. 4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and GPO2 low. tSRST RST 70% GPO1 70% GPO2/ INT tHRST 30% 30% 70% 30% Figure 1. Reset Timing Parameters for Busmode Select 6 Rev. 1.0 Si4730/31-C40 Table 5. 2-Wire Control Interface Characteristics1,2,3 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fSCL 0 — 400 kHz SCLK Low Time tLOW 1.3 — — µs SCLK High Time tHIGH 0.6 — — µs SCLK Input to SDIO  Setup (START) tSU:STA 0.6 — — µs SCLK Input to SDIO  Hold (START) tHD:STA 0.6 — — µs SDIO Input to SCLK  Setup tSU:DAT 100 — — ns SDIO Input to SCLK  Hold4,5 tHD:DAT 0 — 900 ns SCLK input to SDIO  Setup (STOP) tSU:STO 0.6 — — µs STOP to START Time tBUF 1.3 — — µs SDIO Output Fall Time tf:OUT — 250 ns — 300 ns Cb 20 + 0.1 ----------1pF SDIO Input, SCLK Rise/Fall Time tf:IN tr:IN Cb 20 + 0.1 ----------1pF SCLK, SDIO Capacitive Loading Cb — — 50 pF Input Filter Pulse Suppression tSP — — 50 ns Notes: 1. When VIO = 0 V, SCLK and SDIO are low impedance. 2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4730/31 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT specification. 5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be violated as long as all other timing parameters are met. Rev. 1.0 7 Si4730/31-C40 SCLK 70% SDIO 70% tSU:STA tHD:STA tLOW START tr:IN tHIGH tr:IN tf:IN tSP tSU:STO tBUF 30% 30% tf:IN, tf:OUT tHD:DAT tSU:DAT STOP START Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, R/W SDIO START ADDRESS + R/W D7-D0 ACK DATA D7-D0 ACK DATA ACK Figure 3. 2-Wire Control Interface Read and Write Timing Diagram 8 Rev. 1.0 STOP Si4730/31-C40 Table 6. 3-Wire Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0 — 2.5 MHz SCLK High Time tHIGH 25 — — ns SCLK Low Time tLOW 25 — — ns tS 20 — — ns SDIO Input to SCLKHold tHSDIO 10 — — ns SEN Input to SCLKHold tHSEN 10 — — ns SCLKto SDIO Output Valid tCDV Read 2 — 25 ns SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns SDIO Input, SEN to SCLKSetup Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SCLK 70% 30% tR tF tHSDIO tS SEN 70% SDIO 70% tHIGH tLOW tHSEN tS 30% A7 30% A6-A5, R/W, A4-A1 A0 D15 D14-D1 Address In D0 Data In Figure 4. 3-Wire Control Interface Write Timing Parameters SCLK 70% SEN 70% 30% tHSDIO tS tCDV tHSEN tCDZ tS 30% 70% SDIO A7 30% A6-A5, R/W, A4-A1 Address In A0 D15 ½ Cycle Bus Turnaround D14-D1 D0 Data Out Figure 5. 3-Wire Control Interface Read Timing Parameters Rev. 1.0 9 Si4730/31-C40 Table 7. SPI Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0 — 2.5 MHz SCLK High Time tHIGH 25 — — ns SCLK Low Time tLOW 25 — — ns tS 15 — — ns SDIO Input to SCLKHold tHSDIO 10 — — ns SEN Input to SCLKHold tHSEN 5 — — ns SCLKto SDIO Output Valid tCDV Read 2 — 25 ns SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns SDIO Input, SEN to SCLKSetup Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SCLK 70% 30% tR tHIGH SEN 70% SDIO 70% tS tLOW tF tHSDIO tHSEN tS 30% C7 C6–C1 C0 D7 D6–D1 D0 30% Control Byte In 8 Data Bytes In Figure 6. SPI Control Interface Write Timing Parameters SCLK 70% 30% tCDV tS SEN 70% tHSEN tHSDIO tS 30% tCDZ SDIO 70% C7 C6–C1 C0 D7 D6–D1 D0 30% Control Byte In Bus Turnaround 16 Data Bytes Out (SDIO or GPO1) Figure 7. SPI Control Interface Read Timing Parameters 10 Rev. 1.0 Si4730/31-C40 Table 8. Digital Audio Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit DCLK Cycle Time tDCT 26 — 1000 ns DCLK Pulse Width High tDCH 10 — — ns DCLK Pulse Width Low tDCL 10 — — ns DFS Set-up Time to DCLK Rising Edge tSU:DFS 5 — — ns DFS Hold Time from DCLK Rising Edge tHD:DFS 5 — — ns tPD:DOUT 0 — 12 ns DOUT Propagation Delay from DCLK Falling Edge tDCH tDCL DCLK tDCT DFS tHD:DFS tSU:DFS DOUT tPD:OUT Figure 8. Digital Audio Interface Timing Parameters, I2S Mode Rev. 1.0 11 Si4730/31-C40 Table 9. FM Receiver Characteristics1,2 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Input Frequency Test Condition fRF Min Typ Max Unit 76 — 108 MHz Sensitivity with Headphone Network3,4,5 (S+N)/N = 26 dB — 2.2 3.5 µV EMF Sensitivity with 50  Network3,4,5,6 (S+N)/N = 26 dB — 1.1 — µV EMF RDS Sensitivity6 f = 2 kHz, RDS BLER < 5% — 15 — µV EMF 3 4 5 k 4 5 6 pF 100 105 — dBµV EMF m = 0.3 40 50 — dB Adjacent Channel Selectivity ±200 kHz 35 50 — dB Alternate Channel Selectivity ±400 kHz 60 70 — dB In-band 35 — — dB 72 80 90 mVRMS — — 1 dB LNA Input Resistance6,7 LNA Input Capacitance Input 6,7 IP36,8 AM Suppression3,4,6,7 Spurious Response Rejection6 Audio Output Voltage3,4,7 3,7,9 Audio Output L/R Imbalance Low6 –3 dB — — 30 Hz Audio Frequency Response High6 –3 dB 15 — — kHz 32 42 — dB 55 63 — dB — 58 — dB — 0.1 0.5 % FM_DEEMPHASIS = 2 70 75 80 µs FM_DEEMPHASIS = 1 45 50 54 µs Audio Frequency Response Audio Stereo Separation7,9 Audio Mono S/N 3,4,5,7,10 Audio Stereo S/N 4,5,6,7,10,11 Audio THD3,7,9 De-emphasis Time Constant6 Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. Blocker Amplitude = 100 dBµV 13. Sensitivity measured at (S+N)/N = 26 dB. 14. At temperature (25°C). 12 Rev. 1.0 Si4730/31-C40 Table 9. FM Receiver Characteristics1,2 (Continued) (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit f = ±400 kHz — 32 — dBµV f = ±4 MHz — 38 — dBµV f = ±400 kHz, ±800 kHz — 40 — dBµV f = ±4 MHz, ±8 MHz — 35 — dBµV RL Single-ended 10 — — k CL Single-ended — — 50 pF RCLK tolerance = 100 ppm — — 60 ms/channel From powerdown — — 110 ms Input levels of 8 and 60 dBµV at RF Input –3 — 3 dB Blocking Sensitivity3,4,5,6,12,13 Intermode Sensitivity 3,4,5,6,12,13 Audio Output Load Resistance6,10 Audio Output Load Seek/Tune Time Powerup Time6 RSSI Offset14 6 Capacitance6,10 Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. Blocker Amplitude = 100 dBµV 13. Sensitivity measured at (S+N)/N = 26 dB. 14. At temperature (25°C). Rev. 1.0 13 Si4730/31-C40 Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit 64 — 75.9 MHz — 4.0 — µV EMF LNA Input Resistance7 3 4 5 k LNA Input Capacitance7 4 5 6 pF 100 105 — dBµV EMF m = 0.3 40 50 — dB Adjacent Channel Selectivity ±200 kHz — 50 — dB Alternate Channel Selectivity ±400 kHz — 70 — dB 72 80 90 mVRMS — — 1 dB Input Frequency fRF (S+N)/N = 26 dB Sensitivity with Headphone Network3,4,5 Input IP3 Test Condition 8 AM Suppression 3,4,7 3,4,7 Audio Output Voltage 3,7,9 Audio Output L/R Imbalance Audio Frequency Response Low –3 dB — — 30 Hz Audio Frequency Response High –3 dB 15 — — kHz 55 63 — dB — 0.1 0.5 % FM_DEEMPHASIS = 2 70 75 80 µs FM_DEEMPHASIS = 1 45 50 54 µs RL Single-ended 10 — — k CL Single-ended — — 50 pF RCLK tolerance = 100 ppm — — 60 ms/channel From powerdown — — 110 ms Input levels of 8 and 60 dBµV EMF –3 — 3 dB Audio Mono S/N Audio 3,4,5,7,10 THD3,7,9 De-emphasis Time Constant 10 Audio Output Load Resistance Audio Output Load Capacitance Seek/Tune Time Powerup Time RSSI Offset11 10 Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. At temperature (25 °C). 14 Rev. 1.0 Si4730/31-C40 Table 11. AM Receiver Characteristics1,2 (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Input Frequency Sensitivity 3,4,5,6 Large Signal Voltage Handling4,6,7 Power Supply Rejection Ratio6 Symbol Test Condition Min Typ Max Unit 520 — 1710 kHz (S+N)/N = 26 dB — 25 35 µV EMF THD < 8% — 300 — mVRMS ΔVDD = 100 mVRMS, 100 Hz — 40 — dB fRF Audio Output Voltage3,4,8 54 60 67 mVRMS S/N3,4,5,8 50 56 — dB Audio THD3,4,8 — 0.1 0.5 % 180 — 450 µH — — 110 ms Audio Antenna Inductance6,9 Powerup Time6 From powerdown Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 520 kHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter. 4. Analog audio output mode. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method. 8. VIN = 5 mVrms. 9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels. Rev. 1.0 15 Si4730/31-C40 Table 12. Reference Clock and Crystal Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 31.130 32.768 40,000 kHz –100 — 100 ppm 1 — 4095 31.130 32.768 34.406 kHz — 32.768 — kHz –100 — 100 ppm — — 3.5 pF Reference Clock RCLK Supported Frequencies1 2 RCLK Frequency Tolerance REFCLK_PRESCALE REFCLK Crystal Oscillator Crystal Oscillator Frequency Crystal Frequency Tolerance2 Board Capacitance Notes: 1. The Si4730/31 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx Programming Guide”. 2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing. 16 Rev. 1.0 Si4730/31-C40 2. Typical Application Schematic (QFN) GPO1 GPO2/INT R1 R2 GPO3/DCLK 2 FMI 3 RFGND FMIP L1 C5 4 AMI 5 GPO3/DCLK DFS U1 Si4730/31-GM DOUT 15 R3 DOUT Optional: Digital Audio Output 14 13 ROUT/DOUT 12 LOUT/DFS GND VDD RST LOUT ROUT 11 VBATTERY 2.7 to 5.5 V C1 RST 6 7 8 9 10 SEN SCLK SDIO RCLK VIO AM antenna NC GPO2/INT 1 GPO1 NC 20 19 18 17 16 DFS X1 GPO3 SEN SCLK SDIO C2 RCLK VIO 1.85 to 3.6 V RCLK C3 Optional: for crystal oscillator option L2 RFGND AMI T1 C5 Optional: AM air loop antenna Notes: 1. Place C1 close to VDD pin. 2. All grounds connect directly to GND plane on PCB. 3. Pins 1 and 20 are no connects, leave floating. 4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface. 6. Place Si4730/31 as close as possible to antenna and keep the FMI and AMI traces as short as possible. Rev. 1.0 17 Si4730/31-C40 3. Typical Application Schematic (SSOP) Optional: Digital Audio Output R3 DOUT 1 C4 R2 DFS 2 R1 3 GPO3/DCLK 4 GPO2/INT 5 GPO1 NC 6 NC 7 FMI L1 AM antenna 24 LOUT 23 ROUT DBYP 22 C1 2.0 to 5.5 V 21 VDD VIO 1.85 to 3.6 V 20 19 RCLK SDIO 18 8 RFGND 9 10 NC 11 NC AMI 12 17 16 15 14 13 SCLK SEN RST GND C5 X1 GPIO3 C2 F2 RCLK RFGND C3 AMI T1 C5 Optional: AM air loop antenna Optional: for crystal oscillator option Notes: 1. Place C1 close to VDD and DBYP pins. 2. All grounds connect directly to GND plane on PCB. 3. Pins 6 and 7 are no connects, leave floating. 4. Pins 10 and 11 are unused. Tie these pins to GND. 5. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 6. Pin 8 connects to the FM antenna interface, and pin 12 connects to the AM antenna interface. 7. Place Si4730/31 as close as possible to antenna and keep the FMI and AMI traces as short as possible. 18 Rev. 1.0 Si4730/31-C40 4. Bill of Materials (QFN/SSOP) Component(s) Value/Description Supplier C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R Murata L1 Ferrite loop stick, 180–450 µH Jiaxin U1 Si4730/31 AM/FM Radio Tuner Silicon Laboratories Optional Components T1 Transformer, 1–5 turns ratio Jiaxin, UMEC L2 Air loop antenna, 10–20 µH Various Crystal load capacitors, 22 pF, ±5%, COG (Optional for crystal oscillator option) Venkel C4 Noise mitigating capacitor, 2~5 pF(Optional for digital audio) Murata X1 32.768 kHz crystal (Optional for crystal oscillator option) Epson R1 Resistor, 2 k(Optional for digital audio) Venkel R2 Resistor, 2 k(Optional for digital audio) Venkel R3 Resistor, 600 (Optional for digital audio) Venkel C2, C3 Rev. 1.0 19 Si4730/31-C40 5. Functional Description 5.1. Overview Si473x AMI RDS (Si4731) LNA AGC LOW-IF DIGITAL AUDIO (Si4731) ADC LNA ROUT DAC LOUT DSP ADC AGC 2.7– 5.5 V (QFN) 2.0– 5.5 V (SSOP) VDD LDO AFC RCLK GND DFS GPO/DCLK DAC CONTROL INTERFACE SDIO FMI SCLK FM ANT DOUT VIO 1.85–3.6 V RST RFGND SEN AM ANT Figure 9. Functional Block Diagram The Si4730/31 is the industry's first fully integrated, 100% CMOS AM/FM radio receiver IC. Offering unmatched integration and PCB space savings, the Si4730/31 requires only two external components and less than 15 mm2 of board area, excluding the antenna inputs. The Si4730/31 AM/FM radio provides the space savings and low power consumption necessary for portable devices while delivering the high performance and design simplicity desired for all AM/FM solutions. Leveraging Silicon Laboratories' proven and patented Si4700/01 FM tuner's digital low intermediate frequency (low-IF) receiver architecture, the Si4730/31 delivers superior RF performance and interference rejection in both AM and FM bands. The high integration and complete system production test simplifies design-in, increases system quality, and improves manufacturability. The Si4730/31 is a feature-rich solution that includes advanced seek algorithms, soft mute, auto-calibrated digital tuning, and FM stereo processing. In addition, the Si4730/31 provides analog and digital audio outputs and a programmable reference clock. The device supports I2C-compatible 2-wire control interface, SPI, and a Si4700/01 backwards-compatible 3-wire control interface. 20 The Si4730/31 utilizes digital processing to achieve high fidelity, optimal performance, and design flexibility. The chip provides excellent pilot rejection, selectivity, and unmatched audio performance, and offers both the manufacturer and the end-user extensive programmability and flexibility in the listening experience. The Si4731 incorporates a digital processor for the European Radio Data System (RDS) and the North American Radio Broadcast Data System (RBDS) including all required symbol decoding, block synchronization, error detection, and error correction functions. Using this feature, the Si4731 enables broadcast data such as station identification and song name to be displayed to the user. 5.2. Operating Modes The Si4730/31 operates in either an FM receive or an AM receive mode. In FM mode, radio signals are received on FMI and processed by the FM front-end circuitry. In AM mode, radio signals are received on AMI and processed by the AM front-end circuitry. In addition to the receiver mode, there is a clocking mode to choose to clock the Si4730/31 from a reference clock or crystal. On the Si4731, there is an audio output mode to choose between an analog and/or digital audio output. Rev. 1.0 Si4730/31-C40 In the analog audio output mode, ROUT and LOUT are used for the audio output pins. In the digital audio mode, DOUT, DFS, and DCLK pins are used. Concurrent analog/digital audio output mode is also available requiring all five pins. The receiver mode and the audio output mode are set by the POWER_UP command listed in Table 14, “Selected Si473x Commands,” on page 26. 5.3. FM Receiver The Si4730/31 FM receiver is based on the proven Si4700/01 FM tuner. The receiver uses a digital low-IF architecture allowing the elimination of external components and factory adjustments. The Si4730/31 integrates a low noise amplifier (LNA) supporting the worldwide FM broadcast band (64 to 108 MHz). An AGC circuit controls the gain of the LNA to optimize sensitivity and rejection of strong interferers. An imagereject mixer downconverts the RF signal to low-IF. The quadrature mixer output is amplified, filtered, and digitized with high resolution analog-to-digital converters (ADCs). This advanced architecture allows the Si4730/31 to perform channel selection, FM demodulation, and stereo audio processing to achieve superior performance compared to traditional analog architectures. 5.4. AM Receiver The highly-integrated Si4730/31 supports worldwide AM band reception from 520 to 1710 kHz using a digital low-IF architecture with a minimum number of external components and no manual alignment required. This digital low-IF architecture allows for high-precision filtering offering excellent selectivity and SNR with minimum variation across the AM band. The DSP also provides adjustable channel step sizes in 1 kHz increments, AM demodulation, soft mute, seven different channel bandwidth filters, and additional features, such as a programmable automatic volume control (AVC) maximum gain allowing users to adjust the level of background noise. Similar to the FM receiver, the integrated LNA and AGC optimize sensitivity and rejection of strong interferers allowing better reception of weak stations. 5.5. Digital Audio Interface (Si4731 Only) The digital audio interface operates in slave mode and supports three different audio data formats: I2S  Left-Justified  DSP Mode  5.5.1. Audio Data Formats In I2S mode, by default the MSB is captured on the second rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is low, and the right channel is transferred when the DFS is high. In Left-Justified mode, by default the MSB is captured on the first rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is high, and the right channel is transferred when the DFS is low. In DSP mode, the DFS becomes a pulse with a width of 1DCLK period. The left channel is transferred first, followed right away by the right channel. There are two options in transferring the digital audio data in DSP mode: the MSB of the left channel can be transferred on the first rising edge of DCLK following the DFS pulse or on the second rising edge. In all audio formats, depending on the word size, DCLK frequency and sample rates, there may be unused DCLK cycles after the LSB of each word before the next DFS transition and MSB of the next word. In addition, if preferred, the user can configure the MSB to be captured on the falling edge of DCLK via properties. The number of audio bits can be configured for 8, 16, 20, or 24 bits. 5.5.2. Audio Sample Rates The device supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 kHz. The digital audio interface enables low-power operation by eliminating the need for redundant DACs on the audio baseband processor. The Si4730/31 provides highly-accurate digital AM tuning without factory adjustments. To offer maximum flexibility, the receiver supports a wide range of ferrite loop sticks from 180–450 µH. An air loop antenna is supported by using a transformer to increase the effective inductance from the air loop. Using a 1:5 turn ratio inductor, the inductance is increased by 25 times and easily supports all typical AM air loop antennas which generally vary between 10 and 20 µH. Rev. 1.0 21 Si4730/31-C40 (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK LEFT CHANNEL DFS I2S (OMODE = 0000) RIGHT CHANNEL 1 DCLK 1 DCLK 1 DOUT 2 n-2 3 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 10. I2S Digital Audio Format (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK DFS LEFT CHANNEL RIGHT CHANNEL Left-Justified (OMODE = 0110) 1 DOUT 2 3 n-2 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 11. Left-Justified Digital Audio Format (OFALL = 0) DCLK DFS RIGHT CHANNEL LEFT CHANNEL (OMODE = 1100) DOUT (MSB at 1st rising edge) 1 2 3 n-2 n-1 MSB (OMODE = 1000) 1 LSB MSB n-1 n 1 LSB MSB 2 3 n-2 1 2 3 n-1 n LSB LEFT CHANNEL 1 DCLK DOUT (MSB at 2nd rising edge) n RIGHT CHANNEL n-2 MSB 2 3 n-2 n-1 n LSB Figure 12. DSP Digital Audio Format 5.6.1. Stereo Decoder The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was developed in 1961, and is used worldwide. Today's MPX signal format consists of left + right (L+R) audio, left – right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS data as shown in Figure 13 below. The Si4730/31's integrated stereo decoder automatically decodes the MPX signal using DSP techniques. The 0 to 15 kHz (L+R) signal is the mono output of the FM tuner. Stereo is generated from the (L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is used as a reference to recover the (L–R) signal. Output left and right channels are obtained by adding and subtracting the (L+R) and (L–R) signals respectively. The Si4731 uses frequency information from the 19 kHz stereo pilot to recover the 57 kHz RDS/RBDS signal. Modulation Level 5.6. Stereo Audio Processing Mono Audio Left + Right 0 Stereo Pilot 15 19 23 5.6.2. Stereo-Mono Blending Stereo Audio Left - Right 38 Frequency (kHz) Figure 13. MPX Signal Spectrum 22 RDS/ RBDS 53 57 Adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (L+R) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. Stereo/mono status can be monitored with the FM_RSQ_STATUS command. Mono operation can be forced with the FM_BLEND_MONO_THRESHOLD property. Rev. 1.0 Si4730/31-C40 5.7. De-emphasis 5.12. Seek Pre-emphasis and de-emphasis is a technique used by FM broadcasters to improve the signal-to-noise ratio of FM receivers by reducing the effects of high-frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. The Si4730/31 incorporates a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. Two time constants are used in various regions. The deemphasis time constant is programmable to 50 or 75 µs and is set by the FM_DEEMPHASIS property. Seek tuning will search up or down for a valid channel. Valid channels are found when the receive signal strength indicator (RSSI) and the signal-to-noise ratio (SNR) values exceed the set threshold. Using the SNR qualifier rather than solely relying on the more traditional RSSI qualifier can reduce false stops and increase the number of valid stations detected. Seek is initiated using the FM_SEEK_START and AM_SEEK_START commands. The RSSI and SNR threshold settings are adjustable using properties (see Table 15). 5.8. Stereo DAC 5.13. Reference Clock High-fidelity stereo digital-to-analog converters (DACs) drive analog audio signals onto the LOUT and ROUT pins. The audio output may be muted. Volume is adjusted digitally with the RX_VOLUME property. The Si4730/31 reference clock is programmable, supporting RCLK frequencies in Table 12. Refer to Table 3, “DC Characteristics,” on page 5 for switching voltage levels and Table 9, “FM Receiver Characteristics,” on page 12 for frequency tolerance information. An onboard crystal oscillator is available to generate the 32.768 kHz reference when an external crystal and load capacitors are provided. Refer to "2. Typical Application Schematic (QFN)" on page 17. This mode is enabled using the POWER_UP command. Refer to Table 14, “Selected Si473x Commands,” on page 26. The Si4730/31 performance may be affected by data activity on the SDIO bus when using the integrated internal oscillator. SDIO activity results from polling the tuner for status or communicating with other devices that share the SDIO bus. If there is SDIO bus activity while the Si4730/31 is performing the seek/tune function, the crystal oscillator may experience jitter, which may result in mistunes, false stops, and/or lower SNR. 5.9. Soft Mute The soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. The softmute attenuation level is adjustable using the FM_SOFT_MUTE_MAX_ATTENUATION and AM_SOFT_MUTE_MAX_ATTENUATION properties. 5.10. RDS/RBDS Processor (Si4731 Only) The Si4731 implements an RDS/RBDS* processor for symbol decoding, block synchronization, error detection, and error correction. The Si4731 device is user configurable and provides an optional interrupt when RDS is synchronized, loses synchronization, and/or the user configurable RDS FIFO threshold has been met. The Si4731 reports RDS decoder synchronization status and detailed bit errors in the information word for each RDS block with the FM_RDS_STATUS command. The range of reportable block errors is 0, 1–2, 3–5, or 6+. More than six errors indicates that the corresponding block information word contains six or more non-correctable errors or that the block checkword contains errors. *Note: RDS/RBDS is referred to only as RDS throughout the remainder of this document. For best seek/tune results, Silicon Laboratories recommends that all SDIO data traffic be suspended during Si4730/31 seek and tune operations. This is achieved by keeping the bus quiet for all other devices on the bus, and delaying tuner polling until the tune or seek operation is complete. The seek/tune complete (STC) interrupt should be used instead of polling to determine when a seek/tune operation is complete. 5.14. Control Interface 5.11. Tuning The tuning frequency is directly programmed using the FM_TUNE_FREQ and AM_TUNE_FREQ commands. The Si4730/31 supports channel spacing steps of 10 kHz in FM mode and 1 kHz in AM mode. A serial port slave interface is provided, which allows an external controller to send commands to the Si4730/31 and receive responses from the device. The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4730/31 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal pull-up resistor, which is connected while Rev. 1.0 23 Si4730/31-C40 RST is low, and the GPO2 pin includes an internal pulldown resistor, which is connected while RST is low. Therefore, it is only necessary for the user to actively drive pins which differ from these states. See Table 13. Table 13. Bus Mode Select on Rising Edge of RST Bus Mode 2-Wire SPI 3-Wire GPO1 1 1 0 (must drive) GPO2 0 1 (must drive) 0 After the rising edge of RST, the pins GPO1 and GPO2 are used as general purpose output (O) pins, as described in Section “5.15. GPO Outputs”. In any bus mode, commands may only be sent after VIO and VDD supplies are applied. In any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (CTS bit is high). 5.14.1. 2-Wire Control Interface Mode When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. Also, a start condition must not occur within 300 ns before the rising edge of RST. The 2-wire bus mode uses only the SCLK and SDIO pins for signaling. A transaction begins with the START condition, which occurs when SDIO falls while SCLK is high. Next, the user drives an 8-bit control word serially on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 7-bit device address, followed by a read/write bit (read = 1, write = 0). The Si4730/31 acknowledges the control word by driving SDIO low on the next falling edge of SCLK. Although the Si4730/31 will respond to only a single device address, this address can be changed with the SEN pin (note that the SEN pin is not used for signaling in 2-wire mode). When SEN = 0, the 7-bit device address is 0010001b. When SEN = 1, the address is 1100011b. For write operations, the user then sends an 8-bit data byte on SDIO, which is captured by the device on rising edges of SCLK. The Si4730/31 acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. The user may write up to 8 data bytes in a single 2-wire transaction. The first byte is a command, and the next seven bytes are arguments. 24 For read operations, after the Si4730/31 has acknowledged the control byte, it will drive an 8-bit data byte on SDIO, changing the state of SDIO on the falling edge of SCLK. The user acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. If a data byte is not acknowledged, the transaction will end. The user may read up to 16 data bytes in a single 2-wire transaction. These bytes contain the response data from the Si4730/31. A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high. For details on timing specifications and diagrams, refer to Table 5, “2-Wire Control Interface Characteristics” on page 7; Figure 2, “2-Wire Control Interface Read and Write Timing Parameters,” on page 8, and Figure 3, “2Wire Control Interface Read and Write Timing Diagram,” on page 8. 5.14.2. 3-Wire Control Interface Mode When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. The 3-wire bus mode uses the SCLK, SDIO, and SEN_ pins. A transaction begins when the user drives SEN low. Next, the user drives a 9-bit control word on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 9-bit device address (A7:A5 = 101b), a read/write bit (read = 1, write = 0), and a 5-bit register address (A4:A0). For write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising edges of SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4730/31 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time. SCLK may either stop or continue to toggle while SEN is high. In 3-wire mode, commands are sent by first writing each argument to register(s) 0xA1–0xA3, then writing the command word to register 0xA0. A response is retrieved by reading registers 0xA8–0xAF. For details on timing specifications and diagrams, refer to Table 6, “3-Wire Control Interface Characteristics,” on page 9; Figure 4, “3-Wire Control Interface Write Timing Parameters,” on page 9, and Figure 5, “3-Wire Control Interface Read Timing Parameters,” on page 9. Rev. 1.0 Si4730/31-C40 5.14.3. SPI Control Interface Mode 5.16. Firmware Upgrades When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. The Si4730/31 contains on-chip program RAM to accommodate minor changes to the firmware. This allows Silicon Labs to provide future firmware updates to optimize the characteristics of new radio designs and those already deployed in the field. SPI bus mode uses the SCLK, SDIO, and SEN pins for read/write operations. The system controller can choose to receive read data from the device on either SDIO or GPO1. A transaction begins when the system controller drives SEN = 0. The system controller then pulses SCLK eight times, while driving an 8-bit control byte serially on SDIO. The device captures the data on rising edges of SCLK. The control byte must have one of five values:  0x48 = write a command (controller drives 8 additional bytes on SDIO).  0x80 = read a response (device drives 1additional byte on SDIO).  0xC0 = read a response (device drives 16 additional bytes on SDIO).  0xA0 = read a response (device drives 1 additional byte on GPO1).  0xE0 = read a response (device drives 16 additional bytes on GPO1). For write operations, the system controller must drive exactly 8 data bytes (a command and seven arguments) on SDIO after the control byte. The data is captured by the device on the rising edge of SCLK. For read operations, the controller must read exactly 1 byte (STATUS) after the control byte or exactly 16 data bytes (STATUS and RESP1–RESP15) after the control byte. The device changes the state of SDIO (or GPO1, if specified) on the falling edge of SCLK. Data must be captured by the system controller on the rising edge of SCLK. Keep SEN low until all bytes have transferred. A transaction may be aborted at any time by setting SEN high and toggling SCLK high and then low. Commands will be ignored by the device if the transaction is aborted. For details on timing specifications and diagrams, refer to Figure 6 and Figure 7 on page 10. 5.15. GPO Outputs The Si4730/31 provides three general-purpose output pins. The GPO pins can be configured to output a constant low, constant high, or high-impedance. The GPO pins can be reconfigured as specialized functions. GPO2/INT can be configured to provide interrupts and GPO3 can be configured to provide external crystal support or as DCLK in digital audio output mode. 5.17. Reset, Powerup, and Powerdown Setting the RST pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. Setting the RST pin high will bring the device out of reset. A powerdown mode is available to reduce power consumption when the part is idle. Putting the device in powerdown mode will disable analog and digital circuitry while keeping the bus active. 5.18. Programming with Commands To ease development time and offer maximum customization, the Si4730/31 provides a simple yet powerful software interface to program the receiver. The device is programmed using commands, arguments, properties, and responses. To perform an action, the user writes a command byte and associated arguments, causing the chip to execute the given command. Commands control an action such as powerup the device, shut down the device, or tune to a station. Arguments are specific to a given command and are used to modify the command. A partial list of commands is available in Table 14, “Selected Si473x Commands,” on page 26. Properties are a special command argument used to modify the default chip operation and are generally configured immediately after powerup. Examples of properties are de-emphasis level, RSSI seek threshold, and soft mute attenuation threshold. A partial list of properties is available in Table 15, “Selected Si473x Properties,” on page 27. Responses provide the user information and are echoed after a command and associated arguments are issued. All commands provide a 1-byte status update, indicating interrupt and clear-to-send status information. For a detailed description of the commands and properties for the Si4730/31, see “AN332: Si47xx Programming Guide.” Rev. 1.0 25 Si4730/31-C40 6. Commands and Properties Table 14. Selected Si473x Commands 26 Cmd Name Description 0x01 POWER_UP 0x10 GET_REV 0x11 POWER_DOWN Powerdown device. 0x12 SET_PROPERTY Sets the value of a property. 0x13 GET_PROPERTY Retrieves a property’s value. 0x20 FM_TUNE_FREQ Selects the FM tuning frequency. 0x21 FM_SEEK_START Begins searching for a valid frequency. 0x23 FM_RSQ_STATUS Queries the status of the Received Signal Quality (RSQ) of the current channel. 0x24 FM_RDS_STATUS Returns RDS information for current channel and reads an entry from the RDS FIFO (Si4731 only). 0x40 AM_TUNE_FREQ Selects the AM tuning frequency. 0x41 AM_SEEK_START Begins searching for a valid frequency. 0x43 AM_RSQ_STATUS Queries the status of the RSQ of the current channel. Powerup device and mode selection. Modes include AM or FM receive, analog or digital output, and reference clock or crystal support. Returns revision information on the device. Rev. 1.0 Si4730/31-C40 Table 15. Selected Si473x Properties Prop Name 0x1100 FM_DEEMPHASIS 0x1105 FM_BLEND_STEREO_ THRESHOLD 0x1106 FM_BLEND_MONO_ THRESHOLD 0x1200 FM_RSQ_INT_ SOURCE 0x1300 FM_SOFT_MUTE_RATE 0x1500 FM_SOFT_MUTE_ MAX_ATTENUATION FM_SOFT_MUTE_ SNR_THRESHOLD FM_SEEK_BAND_ BOTTOM FM_SEEK_BAND_TOP FM_SEEK_FREQ_ SPACING FM_SEEK_TUNE_ SNR_THRESHOLD FM_SEEK_TUNE_ RSSI_TRESHOLD RDS_INT_SOURCE 0x1501 RDS_INT_FIFO_COUNT 0x1502 RDS_CONFIG 0x3100 AM_DEEMPHASIS 0x3102 AM_CHANNEL_FILTER 0x1302 0x1303 0x1400 0x1401 0x1402 0x1403 0x1404 0x3103 0x3200 0x3300 0x3302 0x3303 0x3400 Description Default Sets de-emphasis time constant. Default is 75 µs. 0x0002 Sets RSSI threshold for stereo blend (full stereo above threshold, blend below threshold). To force stereo set this to 0. 0x0031 To force mono set this to 127. Default value is 49 dBµV. Sets RSSI threshold for mono blend (full mono below threshold, blend above threshold). To force stereo, set this to 0. To force 0x001E mono, set this to 127. Default value is 30 dBµV. Configures interrupt related to RSQ metrics. Sets the attack and decay rates when entering and leaving soft mute. Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. Default is 16 dB. 0x0000 0x0040 0x0010 Sets SNR threshold to engage soft mute. Default is 4 dB. 0x0004 Sets the bottom of the FM band for seek. Default is 8750. 0x222E Sets the top of the FM band for seek. Default is 10790. 0x2A26 Selects frequency spacing for FM seek. 0x000A Sets the SNR threshold for a valid FM Seek/Tune. Default value is 3 dB. Sets the RSSI threshold for a valid FM Seek/Tune. Default value is 20 dBuV. Configures RDS interrupt behavior. Sets the minimum number of RDS groups stored in the receive RDS FIFO required before RDS RECV is set. Configures RDS setting. Sets de-emphasis time constant. Can be set to 50 us. Deemphasis is disabled by default. Selects the bandwidth of the channel filter for AM reception. The choices are 6, 4, 3, 2.5, 2, 1.8, or 1 kHz. In addition, a power line rejection filter can be applied. The default is the 2 kHz bandwidth filter without power line rejection. AM_AUTOMATIC_VOLUME_ Selects the maximum gain for automatic volume control. CONTROL_MAX_GAIN Configures interrupt related to RSQ metrics. All interrupts are AM_RSQ_INTERRUPTS disabled by default. Sets the rate of attack when entering or leaving soft mute. The AM_SOFT_MUTE_RATE default is 278 dB/s. AM_SOFT_MUTE_MAX_ Sets maximum attenuation during soft mute (dB). ATTENUATION AM_SOFT_MUTE_SNR_ Sets SNR threshold to engage soft mute. Default is 0 dB, which THRESHOLD disables soft mute. AM_SEEK_BAND_ Sets the bottom of the AM band for seek. Default is 520. BOTTOM Rev. 1.0 0x0003 0x0014 0x0000 0x0000 0x0000 0x0000 0x0003 0x1543 0x0000 0x0040 0x0008 0x0008 0x0208 27 Si4730/31-C40 Table 15. Selected Si473x Properties (Continued) Prop Name 0x3401 AM_SEEK_BAND_TOP AM_SEEK_FREQ_ SPACING 0x3402 0x3403 AM_SEEK_SNR_ THRESHOLD 0x3404 AM_SEEK_RSSI_ THRESHOLD 0x4000 RX_VOLUME 0x4001 RX_HARD_MUTE 28 Description Default Sets the top of the AM band for seek. 0x06AE Selects frequency spacing for AM seek. Default is 10 kHz 0x000A spacing. Sets the SNR threshold for a valid AM Seek/Tune. If the value is zero, then SNR threshold is not considered when doing a seek. 0x0005 Default value is 5 dB. Sets the RSSI threshold for a valid AM Seek/Tune. If the value is zero, then RSSI threshold is not considered when doing a 0x0019 seek. Default value is 25 dBuV. Sets the output volume. 0x003F Mutes the audio output. L and R audio outputs may be muted 0x0000 independently in FM mode. Rev. 1.0 Si4730/31-C40 GPO2/INT GPO3/DCLK DFS 1 GPO1 NC NC 7. Pin Descriptions: Si4730/31-GM 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 14 LOUT GND PAD AMI 4 13 ROUT 6 7 8 9 10 SCLK SDIO RCLK VIO 12 GND SEN RST 5 11 VDD Pin Number(s) Name Description 1, 20 NC No connect. Leave floating. 2 FMI FM RF inputs. FMI should be connected to the antenna trace. 3 RFGND 4 AMI AM RF input. AMI should be connected to the AM antenna. 5 RST Device reset (active low) input. 6 SEN Serial enable input (active low). 7 SCLK Serial clock input. 8 SDIO Serial data input/output. 9 RCLK External reference oscillator input. 10 VIO I/O supply voltage. 11 VDD Supply voltage. May be connected directly to battery. 12, GND PAD GND Ground. Connect to ground plane on PCB. 13 ROUT Right audio line output in analog output mode. 14 LOUT Left audio line output in analog output mode. 15 DOUT Digital output data in digital output mode. 16 DFS 17 GPO3/DCLK 18 GPO2/INT 19 GPO1 RF ground. Connect to ground plane on PCB. Digital frame synchronization input in digital output mode. General purpose output, crystal oscillator, or digital bit synchronous clock input in digital output mode. General purpose output or interrupt pin. General purpose output. Rev. 1.0 29 Si4730/31-C40 8. Pin Descriptions: Si4730/31-GU DOUT 1 24 LOUT DFS 2 23 ROUT GPO3/DCLK 3 22 DBYP GPO2/INT 4 21 VDD GPO1 5 20 VIO NC 6 19 RCLK NC 7 18 SDIO FMI 8 17 SCLK RFGND 9 16 SEN NC 10 15 RST NC 11 14 GND AMI 12 13 GND Pin Number(s) Name 1 DOUT 2 DFS 3 GPO3/DCLK 4 GPO2/INT 5 GPO1 6,7 NC No connect. Leave floating. 8 FMI FM RF inputs. FMI should be connected to the antenna trace. 9 RFGND 30 Description Digital output data in digital output mode. Digital frame synchronization input in digital output mode. General purpose output, crystal oscillator, or digital bit synchronous clock input in digital output mode. General purpose output or interrupt pin. General purpose output. RF ground. Connect to ground plane on PCB. 10,11 NC Unused. Tie these pins to GND. 12 AMI AM RF input. AMI should be connected to the AM antenna. 13,14 GND Ground. Connect to ground plane on PCB. 15 RST Device reset (active low) input. 16 SEN Serial enable input (active low). 17 SCLK Serial clock input. 18 SDIO Serial data input/output. 19 RCLK External reference oscillator input. 20 VIO I/O supply voltage. 21 VDD Supply voltage. May be connected directly to battery. 22 DBYP Dedicated bypass for VDD and VIO. 23 ROUT Right audio line output in analog output mode. 24 LOUT Left audio line output in analog output mode. Rev. 1.0 Si4730/31-C40 9. Ordering Guide Part Number* Description Package Type Operating Temperature/Voltage Si4730-C40-GM AM/FM Broadcast Radio Receiver QFN Pb-free –20 to 85 °C 2.7 to 5.5 V Si4730-C40-GU AM/FM Broadcast Radio Receiver SSOP Pb-free –20 to 85 °C 2.0 to 5.5 V Si4731-C40-GM AM/FM Broadcast Radio Receiver with RDS/RBDS QFN Pb-free –20 to 85 °C 2.7 to 5.5 V Si4731-C40-GU AM/FM Broadcast Radio Receiver with RDS/RBDS SSOP Pb-free –20 to 85 °C 2.0 to 5.5 V *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. SSOP devices operate down to VDD = 2 V at 25 °C. Rev. 1.0 31 Si4730/31-C40 10. Package Markings (Top Marks) 10.1. Si4730/31 Top Mark (QFN) 3040 CTTT YWW 3140 CTTT YWW 10.2. Top Mark Explanation (QFN) Mark Method: YAG Laser Line 1 Marking: Part Number 30 = Si4730, 31 = Si4731. Firmware Revision 40 = Firmware Revision 4.0. Die Revision C = Revision C Die. TTT = Internal Code Internal tracking code. Line 2 Marking: Line 3 Marking: Circle = 0.5 mm Diameter Pin 1 Identifier. (Bottom-Left Justified) Y = Year WW = Workweek 32 Assigned by the Assembly House. Corresponds to the last significant digit of the year and work week of the mold date. Rev. 1.0 Si4730/31-C40 10.3. Si4730/31 Top Mark (SSOP) 4730C40GU YYWWTTTTTT 10.4. Top Mark Explanation (SSOP) Mark Method: Line 1 Marking: Line 2 Marking: YAG Laser Part Number 4730 = Si4730; 4731 = Si4731. Die Revision C = Revision C die. Firmware Revision 40 = Firmware Revision 4.0. YY = Year WW = Work week Assigned by the Assembly House. TTTTTT = Manufacturing code Rev. 1.0 33 Si4730/31-C40 11. Package Outline: Si4730/31 QFN Figure 14 illustrates the package details for the Si4730/31. Table 16 lists the values for the dimensions shown in the illustration. Figure 14. 20-Pin Quad Flat No-Lead (QFN) Table 16. Package Dimensions Symbol Millimeters Symbol Min Nom Max A 0.50 0.55 0.60 f A1 0.00 0.02 0.05 L 0.35 0.40 0.45 b 0.20 0.25 0.30 L1 0.00 — 0.10 c 0.27 0.32 0.37 aaa — — 0.05 bbb — — 0.05 ccc — — 0.08 ddd — — 0.10 eee — — 0.10 D D2 1.65 1.70 1.75 0.50 BSC E E2 Min 3.00 BSC e 3.00 BSC 1.65 1.70 1.75 Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 34 Millimeters Rev. 1.0 Nom Max 2.53 BSC Si4730/31-C40 12. PCB Land Pattern: Si4730/31 QFN Figure 15 illustrates the PCB land pattern details for the Si4730/31-C40-GM QFN. Table 17 lists the values for the dimensions shown in the illustration. Figure 15. PCB Land Pattern Rev. 1.0 35 Si4730/31-C40 Table 17. PCB Land Pattern Dimensions Symbol Millimeters Min D D2 Symbol Max 2.71 REF 1.60 1.80 Min Max GE 2.10 — W — 0.34 — e 0.50 BSC X E 2.71 REF Y E2 f GD 1.60 1.80 2.53 BSC 2.10 Millimeters 0.28 0.61 REF ZE — 3.31 ZD — 3.31 — Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes: Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes: Stencil Design 1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 36 Rev. 1.0 Si4730/31-C40 13. Package Outline: Si4730/31 SSOP Figure 16 illustrates the package details for the Si4730/31. Table 18 lists the values for the dimensions shown in the illustration. Figure 16. 24-Pin SSOP Table 18. Package Dimensions Dimension A A1 b c D E E1 e L L2 θ aaa bbb ccc ddd Min — 0.10 0.20 0.10 Nom — — — — 8.65 BSC 6.00 BSC 3.90 BSC 0.635 BSC — 0.25 BSC — 0.20 0.18 0.10 0.10 0.40 0° Max 1.75 0.25 0.30 0.25 1.27 8° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AE. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 37 Si4730/31-C40 14. PCB Land Pattern: Si4730/31 SSOP Figure 17 illustrates the PCB land pattern details for the Si4730/31-C40-GU SSOP. Table 19 lists the values for the dimensions shown in the illustration. Figure 17. PCB Land Pattern Table 19. PCB Land Pattern Dimensions Dimension Min Max C 5.20 5.40 E 0.65 BSC X1 0.35 0.45 Y1 1.55 1.75 General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. Solder Mask Design: 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design: 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly: 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 38 Rev. 1.0 Si4730/31-C40 15. Additional Reference Resources Contact your local sales representatives for more information or to obtain copies of the following references:  EN55020 Compliance Test Certificate AN332: Si47xx Programming Guide  AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines  AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure  Rev. 1.0 39 Si4730/31-C40 DOCUMENT CHANGE LIST Revision 0.5 to Revision 0.7  Updated Table 3, “DC Characteristics,” on page 5. Updated Table 9, “FM Receiver Characteristics1,2,” on page 12.  Updated Table 15, “Selected Si473x Properties,” on page 27.  Updated Table 10.4, “Top Mark Explanation (SSOP),” on page 33.  Revision 0.7 to Revision 0.71  VIO minimum changed from 1.5 V to 1.85 V. Revision 0.71 to Revision 1.0           40 Updated patent information on page 1. Pin 22 changed from “GND” to “DBYP.” Updated Table 1 on page 4. Updated Table 3 on page 5. Updated Table 9 on page 12. Updated Table 11 on page 15. Updated "3. Typical Application Schematic (SSOP)" on page 18. Updated "4. Bill of Materials (QFN/SSOP)" on page 19. Updated "8. Pin Descriptions: Si4730/31-GU" on page 30. Updated "9. Ordering Guide" on page 31. Rev. 1.0 Si4730/31-C40 NOTES: Rev. 1.0 41 Si4730/31-C40 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 42 Rev. 1.0