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CLC1005ISO8

CLC1005ISO8

  • 厂商:

    SIPEX(迈凌)

  • 封装:

  • 描述:

    IC OPAMP VFB 1 CIRCUIT 8SOIC

  • 数据手册
  • 价格&库存
CLC1005ISO8 数据手册
CLC1005, CLC1015, CLC2005 Low Cost, +2.7V to 5.5V, 260MHz Rail-to-Rail Amplifiers FE ATU R E S ■■ 260MHz bandwidth ■■ Fully specified at +2.7V and +5V supplies ■■ Output voltage range: ❏❏ 0.036V to 4.953V; V = +5; R = 2kΩ S L ■■ Input voltage range: ❏❏ -0.3V to +3.8V; V = +5 S ■■ 145V/μs slew rate ■■ 4.2mA supply current ■■ Power down to 127μA ■■ ±55mA linear output current ■■ ±85mA short circuit current ■■ CLC2005 directly replaces AD8052/42/92 in single supply applications ■■ CLC1005 directly replaces AD8051/41/91 in single supply applications General Description The CLC1005 (single), CLC1015 (single with disable), and CLC2005 (dual) are low cost, voltage feedback amplifiers. These amplifiers are designed to operate on +2.7V to +5V, or ±2.5V supplies. The input voltage range extends 300mV below the negative rail and 1.2V below the positive rail. Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d The CLC1005, CLC1015, and CLC2005 offer superior dynamic performance with 260MHz small signal bandwidth and 145V/μs slew rate. The amplifiers consume only 4.2mA of supply current per channel and the CLC1015 offers a disable supply current of only 127μA. The combination of low power, high output current drive, and rail-to-rail performance make these amplifiers well suited for battery-powered communication/computing systems. The combination of low cost and high performance make the CLC1005, CLC1015, and CLC2005 suitable for high volume applications in both consumer and industrial applications such as interactive whiteboards, wireless phones, scanners, color copiers, and video transmission. A P P LICATION S ■■ A/D driver ■■ Active filters ■■ CCD imaging systems ■■ CD/DVD ROM ■■ Coaxial cable drivers ■■ High capacitive load driver ■■ Portable/battery-powered applications ■■ Twisted pair driver ■■ Telecom and optical terminals ■■ Video driver ■■ Interactive whiteboards Ordering Information - backpage Output Swing 2.7 2nd & 3rd Harmonic Distortion; VS = +2.7V -20 Vo = 1Vpp Rf = 1kΩ Distortion (dBc) Output Voltage (0.5V/div) -30 -50 2nd RL = 150Ω -60 2nd RL = 2kΩ -70 3rd RL = 2kΩ -80 Vs = +2.7V RL = 2kΩ G = -1 -90 0 0 5 10 15 20 Frequency (MHz) Time (0.5μs/div) © 2007-2015 Exar Corporation 3rd RL = 150Ω -40 1 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Absolute Maximum Ratings Operating Conditions Stresses beyond the limits listed below may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Supply Voltage Range....................................................2.5 to 5.5V Operating Temperature Range..................................-40°C to 85°C Junction Temperature............................................................ 150°C Storage Temperature Range....................................-65°C to 150°C Lead Temperature (Soldering, 10s).......................................260°C VS.................................................................................... 0V to +6V VIN............................................................. -VS - 0.5V to +VS +0.5V Package Thermal Resistance θJA (SOIC-8)......................................................................150°C/W θJA (MSOP-8)................................................................... 200°C/W θJA (TSOT23-5).................................................................215°C/W Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d θJA (TSOT23-6).................................................................192°C/W Package thermal resistance (θJA), JEDEC standard, multi-layer test boards, still air. ESD Protection SOIC-8 (HBM)........................................................................2.5kV ESD Rating for HBM (Human Body Model) and CDM (Charged Device Model). © 2007-2015 Exar Corporation 2 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Electrical Characteristics at +2.7V TA = 25°C, VS = +2.7V, Rf = 2kΩ, RL = 2kΩ to VS/2; G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response GBWP -3dB Gain Bandwidth Product 86 MHz UGBW Unity Gain Bandwidth(1) G = +1, VOUT = 0.05Vpp 215 MHz BWSS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 85 MHz BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 36 MHz tR, tF Rise and Fall Time (1) VOUT = 0.2V step; (10% to 90%) 3.7 ns tS Settling Time to 0.1% VOUT = 1V step 40 ns OS Overshoot VOUT = 0.2V step 9 % SR Slew Rate G = -1, 2.7V step 130 V/μs Distortion/Noise Response Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d Time Domain HD2 2nd Harmonic Distortion (1) 5MHz, VOUT = 1Vpp 79 dBc HD3 3rd Harmonic Distortion (1) 5MHz, VOUT = 1Vpp 82 dBc THD Total Harmonic Distortion 5MHz, VOUT = 1Vpp 77 dB en Input Voltage Noise >1MHz 16 nV/√Hz in Input Current Noise >1MHz 1.3 pA/√Hz XTALK Crosstalk CLC2005, 10MHz 65 dB (1) DC Performance (1) VIO Input Offset Voltage -1.6 mV dVIO Average Drift 10 μV/°C IB Input Bias Current 3 μA dIB Average Drift 7 nA/°C IOS Input Offset Current 0.1 μA PSRR Power Supply Rejection Ratio 57 dB AOL Open Loop Gain 75 dB IS Supply Current 3.9 mA 150 ns DC 52 Disable Characteristics (CLC1015) TON Turn On Time TOFF Turn Off Time OFFISO Off Isolation ISD Disable Supply Current Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio 25 ns 5MHz, RL = 100Ω 75 dB DIS tied to GND 58 DC, VCM = 0 to VS - 1.5V 100 μA 4.3 MΩ 1.8 pF -0.3 to 1.5 V 87 dB Output Characteristics RL = 10kΩ to VS / 2 VOUT Output Swing RL = 2kΩ to VS / 2 RL = 150Ω to VS / 2 IOUT Output Current ISC Short Circuit Current VS Power Supply Operating Range -40°C to +85°C VOUT = VS / 2 0.023 to 2.66 0.025 to 2.653 0.065 to 2.55 ±55 mA ±50 mA V V V ±85 2.5 2.7 mA 5.5 V Notes: 1. Rf = 1kΩ was used for optimal performance. (For G = +1, Rf = 0) © 2007-2015 Exar Corporation 3 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Electrical Characteristics at +5V TA = 25°C, VS = +5V, Rf = 2kΩ, RL = 2kΩ to VS/2; G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response GBWP -3dB Gain Bandwidth Product 90 MHz UGBW Unity Gain Bandwidth(1) G = +1, VOUT = 0.05Vpp 260 MHz BWSS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 90 MHz BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 40 MHz tR, tF Rise and Fall Time (1) VOUT = 0.2V step 3.6 ns tS Settling Time to 0.1% VOUT = 2V step 40 ns OS Overshoot VOUT = 0.2V step 7 % SR Slew Rate G = -1, 5V step 145 V/μs Distortion/Noise Response Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d Time Domain HD2 2nd Harmonic Distortion (1) 5MHz, VOUT = 2Vpp 71 dBc HD3 3rd Harmonic Distortion (1) 5MHz, VOUT = 2Vpp 78 dBc THD Total Harmonic Distortion 5MHz, VOUT = 2Vpp (1) 70 dB NTSC (3.85MHz), AC-Coupled, RL = 150Ω 0.06 % NTSC (3.85MHz), DC-Coupled, RL = 150Ω 0.08 % NTSC (3.85MHz), AC-Coupled, RL = 150Ω 0.07 ° NTSC (3.85MHz), DC-Coupled, RL = 150Ω 0.06 ° DG Differential Gain DP Differential Phase en Input Voltage Noise >1MHz 16 nV/√Hz in Input Current Noise >1MHz 1.3 pA/√Hz XTALK Crosstalk(1) CLC2005, 10MHz 62 dB DC Performance VIO Input Offset Voltage dVIO Average Drift IB Input Bias Current dIB Average Drift IOS Input Offset Current PSRR Power Supply Rejection Ratio AOL Open Loop Gain IS Supply Current DC -8 1.4 8 10 -8 3 -0.8 0.1 52 57 8 7 68 μA nA/°C 0.8 μA dB 78 4.2 mV μV/°C dB 5.2 mA Disable Characteristics (CLC1015) TON Turn On Time TOFF Turn Off Time OFFISO Off Isolation ISD Disable Supply Current 150 ns 25 ns 5MHz, RL = 100Ω 75 dB DIS tied to GND 127 170 μA Input Characteristics RIN Input Resistance 4.3 MΩ CIN Input Capacitance 1.8 pF CMIR Common Mode Input Range -0.3 to 3.8 V CMRR Common Mode Rejection Ratio 87 dB DC, VCM = 0 to VS - 1.5V © 2007-2015 Exar Corporation 4 / 19 72 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Electrical Characteristics at +5V Continued TA = 25°C, VS = +5V, Rf = 2kΩ, RL = 2kΩ to VS/2; G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Output Characteristics VOUT Output Swing RL = 10kΩ to VS / 2 0.027 to 4.97 V RL = 2kΩ to VS / 2 0.036 to 4.953 V RL = 150Ω to VS / 2 Output Current ISC Short Circuit Current VS Power Supply Operating Range Notes: 0.12 to 4.8 4.625 V ±55 mA -40°C to +85°C ±50 mA VOUT = VS / 2 ±85 mA Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d IOUT 0.3 2.5 5 5.5 V 1. Rf = 1kΩ was used for optimal performance. (For G = +1, Rf = 0) © 2007-2015 Exar Corporation 5 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 CLC1005 Pin Configurations CLC1005 Pin Assignments TSOT-5 TSOT-5 OUT 1 -Vs 2 +IN 3 5 + +Vs 4 -IN SOIC-8 Pin Name Description 1 OUT Output 2 -VS Negative supply 3 +IN Positive input 4 -IN Negative input 5 +VS Positive supply 1 -IN 2 +IN 3 + 4 Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d SOIC-8 NC -Vs Pin No. 8 NC 7 +Vs 6 OUT NC 5 Pin No. Pin Name Description 1 NC No Connect 2 -IN Negative input 3 +IN Positive input 4 -VS Negative supply 5 NC No Connect 6 OUT Output 7 +VS Positive supply 8 NC No Connect CLC1015 Pin Configurations CLC1015 Pin Assignments TSOT-6 TSOT-6 OUT 1 -Vs 2 +IN 3 + - 6 +Vs 5 DIS 4 -IN © 2007-2015 Exar Corporation Pin No. Pin Name 1 OUT Output 2 -VS Negative supply 3 +IN Positive input 4 -IN Negative input 5 DIS Disable pin. Enabled if pin is left open or tied to +VS, disabled if pin is tied to -VS (which is GND in a single supply application.) 6 +VS Positive supply 6 / 19 Description exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 CLC2005 Pin Configuration CLC2005 Pin Assignments SOIC-8 / MSOP-8 SOIC-8 / MSOP-8 OUT1 1 -IN1 2 +IN1 3 4 + + Pin Name Description 1 OUT1 8 +Vs 2 -IN1 Negative input, channel 1 7 OUT2 3 +IN1 Positive input, channel 1 4 -IN2 -VS 6 5 +IN2 Positive input, channel 2 +IN2 6 -IN2 Negative input, channel 2 7 OUT2 8 +VS 5 Output, channel 1 Negative supply Output, channel 2 Positive supply Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d -Vs - Pin No. © 2007-2015 Exar Corporation 7 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Typical Performance Characteristics TA = 25°C, VS = +5V, RL = 2kΩ to VS/2, G = +2, RF = 2kΩ; unless otherwise noted. Inverting Frequency Response VS = +5V Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne Normalized Magnitude (1dB/div) Magnitude (1dB/div) Normalized Magnitude (1dB/div) d ) an in uf th ac is tu re d Normalized Magnitude (2dB/div) Non-Inverting Frequency Response VS = +5V G=2 Rf = 1kΩ G = -10 Rf = 2kΩ G = 10 Rf = 2kΩ G=5 Rf = 2kΩ 0.1 G = -1 Rf = 2kΩ G=1 Rf = 0 1 10 0.1 100 G = -5 Rf = 2kΩ G = -2 Rf = 2kΩ 1 10 100 Frequency (MHz) Non-Inverting Frequency Response VS = +2.7V Inverting Frequency Response VS = +2.7V Normalized Magnitude (2dB/div) Frequency (MHz) G = -1 Rf = 2kΩ G=1 Rf = 0 G=2 Rf = 1kΩ G = -10 Rf = 2kΩ G = 10 Rf = 2kΩ G=5 Rf = 2kΩ 1 0.1 10 0.1 100 1 G = -5 Rf = 2kΩ G = -2 Rf = 2kΩ 10 100 Frequency (MHz) Frequency (MHz) Magnitude (1dB/div) Frequency Response vs CL Large Signal Frequency Response CL = 100pF Rs = 25Ω CL = 50pF Rs = 33Ω + - CL 1kW 0.1 1 Vo = 2Vpp CL = 20pF Rs = 20Ω Rs 1kW Vo = 1Vpp RL CL = 10pF Rs = 0Ω 10 100 0.1 Frequency (MHz) © 2007-2015 Exar Corporation 1 10 100 Frequency (MHz) 8 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Typical Performance Characteristics TA = 25°C, VS = +5V, RL = 2kΩ to VS/2, G = +2, RF = 2kΩ; unless otherwise noted. Frequency Response vs. Temperature Input Voltage Noise vs Frequency 100 Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d ei nti ( Distortion O (dBc) ng Voltage Noise (nV/√Hz) BS m one ) an d in uf th ac is tu re d Magnitude (0.5dB/div) 90 80 70 60 50 40 30 20 10 1 10 0 100 1k 2nd & 3rd Harmonic Distortion VS = +5V -20 Distortion (dBc) -30 2nd RL = 150Ω -40 -50 1M 3rd RL = 150Ω Vo = 1Vpp Rf = 1kΩ -30 3rd RL = 150Ω -40 -50 -60 2nd RL = 150Ω -60 2nd RL = 2kΩ -70 -90 2nd RL = 2kΩ -70 3rd RL = 2kΩ -80 -80 3rd RL = 2kΩ -90 0 5 10 15 0 20 5 Frequency (MHz) -20 -30 20 2.0 2.5 Rf = 1kΩ -30 -50 Distortion (dBc) 20MHz -40 10MHz -60 -70 5MHz -80 2MHz 20MHz -40 -50 10MHz -60 -70 5MHz -80 -90 2MHz -90 0.5 15 3rd Harmonic Distortion vs VO -20 Rf = 1kΩ 10 Frequency (MHz) 2nd Harmonic Distortion vs VO Distortion (dBc) 100k 2nd & 3rd Harmonic Distortion VS = +2.7V -20 Vo = 2Vpp Rf = 1kΩ 10k Frequency (Hz) Frequency (MHz) 1.0 1.5 2.0 2.5 0.5 Output Amplitude (Vpp) © 2007-2015 Exar Corporation 1.0 1.5 Output Amplitude (Vpp) 9 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Typical Performance Characteristics TA = 25°C, VS = +5V, RL = 2kΩ to VS/2, G = +2, RF = 2kΩ; unless otherwise noted. PSRR CMRR -40 0 -10 -50 CMRR (dB) PSRR (dB) -20 -30 -40 -60 -70 -50 Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d ei nti ( OB(V) ng on Output Voltage Output Voltage (0.05V/div) S) ma ed nu in fa thi ct s ur ed -80 -60 -90 -70 1k 0.01 0.1 1 10 0.01 100 0.1 Frequency (MHz) Open Loop Gain & Phase vs. Frequency 0.6 60 50 |Gain| 40 30 0 Phase -45 0.4 -20 0.01 0.1 1 10 Linear output current ±55mA 0.2 0 -0.2 Short circuit current ±85mA -0.4 -90 0 -10 -135 -0.6 -180 -0.8 -100 100 Frequency (MHz) Small Signal Pulse Response VS = +5V Output Voltage (0.05V/div) 100 Output Current Phase (degrees) Open Loop Gain (dB) 70 10 10 0.8 80 20 1.0 Frequency (MHz) Rf = 1kΩ -50 0 50 100 Output Current (mA) Small Signal Pulse Response VS = +2.7V Rf = 1kΩ Time (20ns/div) © 2007-2015 Exar Corporation Time (20ns/div) 10 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Typical Performance Characteristics TA = 25°C, VS = +5V, RL = 2kΩ to VS/2, G = +2, RF = 2kΩ; unless otherwise noted. Large Signal Pulse Response VS = +5V Output Swing Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio Output Voltage (0.5V/div) BS m ne ) an d in uf th ac is tu re d Output Voltage (0.5V/div) 2.7 Rf = 1kΩ Vs = +2.7V RL = 2kΩ G = -1 0 Time (20ns/div) Time (0.5μs/div) Channel Matching VS = +5V Magnitude (0.5dB/div) Rf = 1kΩ RL = 2kΩ G=2 Channel 1 Channel 2 0.1 1 10 100 Frequency (MHz) © 2007-2015 Exar Corporation 11 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Application Information +Vs General Description The CLC1005, CLC1015, and CLC2005 are single supply, general purpose, voltage-feedback amplifiers fabricated on a complementary bipolar process using a patented topography. They feature a rail-to-rail output stage and are unity gain stable. Both gain bandwidth and slew rate are insensitive to temperature. Input 0.1μF + Output RL 0.1μF The common mode input range extends to 300mV below ground and to 1.2V below Vs. Exceeding these values will not cause phase reversal. However, if the input voltage exceeds the rails by more than 0.5V, the input ESD devices will begin to conduct. The output will stay at the rail during this overdrive condition. 6.8μF G=1 -Vs Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne Magnitude (1dB/div) ) an d in uf th ac is tu re d Figure 3: Unity Gain Circuit +Vs The design is short circuit protected and offers “soft” saturation protection that improves recovery time. Figures 1, 2, and 3 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. Figure 4 shows the typical non-inverting gain circuit for single supply applications. +Vs 6.8μF In 6.8μF + 0.1μF + Out - Rf Rg 6.8μF Figure 4: Single Supply Non-Inverting Gain Circuit Input 0.1μF + Output - RL 0.1μF Rg 6.8μF -Vs Rf At non-inverting gains other than G = +1, keep Rg below 1kΩ to minimize peaking; thus for optimum response at a gain of +2, a feedback resistor of 1kΩ is recommended. Figure 5 illustrates the CLC1005, CLC1015 and CLC2005 frequency response with both 1kΩ and 2kΩ feedback resistors. G = 1 + (Rf/Rg) Figure 1: Typical Non-Inverting Gain Circuit +Vs R1 Input Rg G=2 RL = 2kΩ Vs = +5V Rf = 2kΩ 6.8μF Rf = 1kΩ 0.1μF + Output RL 0.1μF 6.8μF -Vs Rf 1 10 100 Frequency (MHz) G = - (Rf/Rg) Figure 5: Frequency Response vs. Rf For optimum input offset voltage set R1 = Rf || Rg Figure 2: Typical Inverting Gain Circuit © 2007-2015 Exar Corporation 12 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Overdrive Recovery For an amplifier, an overdrive condition occurs when the output and/or input ranges are exceeded. The recovery time varies based on whether the input or output is overdriven and by how much the ranges are exceeded. The CLC1005, CLC1015, and CLC2005 will typically recover in less than 20ns from an overdrive condition. Figure 6 shows the CLC2005 in an overdriven condition. needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation. Psupply = Vsupply × IRMSsupply Vsupply = VS+ - VS- RL = 2kΩ Vin =2Vpp G=5 Rf = 1kΩ Input Pload = ((Vload)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d Input Voltage (0.5V/div) Power delivered to a purely resistive load is: Output Rloadeff in Figure 3 would be calculated as: RL || (Rf + Rg) Time (20ns/div) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from Figure 6: Overdrive Recovery PD = PQuiescent + PDynamic - Pload Enable/Disable Function The CLC1015 offers an active-low disable pin that can be used to lower its supply current. Leave the pin floating to enable to part. Pull the disable pin to the negative supply (which is ground in a single supply application) to disable the output. During the disable condition, the nominal supply current will drop below 127μA and the output will be at a high impedance with about 2pF capacitance. Power Dissipation Power dissipation should not be a factor when operating under the stated 2kΩ load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it’s intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150°C. To calculate the junction temperature, the package thermal resistance value ThetaJA (θJA) is used along with the total die power dissipation. Quiescent power can be derived from the specified IS values along with known supply voltage, Vsupply. Load power can be calculated as above with the desired signal amplitudes using: (Vload)RMS = Vpeak / √2 ( Iload)RMS = ( Vload)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDynamic = (VS+ - Vload)RMS × ( Iload)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. The CLC1015 is short circuit protected. However, this may not guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. Figure 7 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available. TJunction = TAmbient + (θJA × PD) Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load © 2007-2015 Exar Corporation 13 / 19 exar.com/CLC1005 Rev 2D CLC1005, CLC1015, CLC2005 Layout Considerations Maximum Power Dissipation (W) 1.5 General layout and supply bypassing play major roles in high frequency performance. Exar has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: SOIC-8 1 TSOT-6 ■■ MSOP-8 0.5 TSOT-5 ■■ Place the 6.8µF capacitor within 0.75 inches of the power pin ■■ Place the 0.1µF capacitor within 0.1 inches of the power pin ■■ 0 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Minimize all trace lengths to reduce series inductances Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d ■■ Figure 7. Maximum Power Derating Driving Capacitive Loads Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 8. Refer to the evaluation board layouts below for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # Input + Rs Rf Rg Output CL RL Figure 8. Addition of RS for Driving Capacitive Loads Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in approximately
CLC1005ISO8 价格&库存

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