SE4150L-R

DATA SHEET SE4150L: GPS Receiver IC Preliminary Datasheet High sensitivity / low power GPS / A-GPS apps. Personal Navigation Devices (PNDs) , mobile phones, and GPS peripheral devices Features         The SE4150L features two gain control modes, to optimize the performance of the LNA and mixer for systems which either require high signal handling, or systems which need minimal supply current. tin  Single-conversion L1-band GPS radio with integrated IF filter Integrated LNA with high-gain (20 dB typ.) and low NF (0.9 dB typ.) Integrated antenna switching with active antenna current detection Low cascaded system noise figure of 1.2 dB typical 2-bit SIGN & MAG digital IF output 2.7 V - 3.6 V operation Standby current 70 uA out of the pin to allow guaranteed levels to be set. Mixer RF Input The mixer RF input, MIX_IN (pin 11), is a singleended 50 Ω input designed to interface either to ANT_SW_OUT (pin 7) or to the output of an external filter. An external active antenna can also be Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 202445B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 1, 2019 5 DATA SHEET SE4150L: GPS Receiver IC Preliminary Datasheet connected directly to MIX_IN (pin 11) in some applications. follows a classic 3rd-order response. Typical PLL Loop- Bandwidth is set to be approx. 200kHz. The image reject mixer ensures that the receiver’s full sensitivity is achieved without an external filter. For applications where additional selectivity is required, an external filter can be added between the ANT_SW_OUT (pin 7) and MIX_IN (pin 11) pins. The reference frequency for the PLL is provided by an external reference source; normally a TCXO. AGC and ADC The supply to the external TCXO can be connected to pin 13 of the SE4150L. The VCC_TCXO supply is disabled when the SE4150L is in stand-by mode. The VCC_TCXO pin can be left floating if a direct connection from VCC to the power supply of the external TCXO is desired. tin The bandpass response has a nominal bandwidth of 2.2 MHz; the nominal center frequency is preset to 4.092 MHz. These parameters ensure very low implementation loss in all frequency plan configurations. d The SE4150L includes a fully integrated Intermediate Frequency (IF) filter which provides excellent interference rejection with no additional external components. The filter has a 3rd order Butterworth bandpass response. The SE4150L can be used with an external TCXO. The TCXO should have a clipped sinewave signal output which is connected to the TCXO_IN (pin 15) input. ue IF Filter TCXO Connection on The SE4150L features a linear IF chain with 2-bit SIGN / MAG ADC. SIGN output is pin 20, and MAG output is pin 19. VCC_TCXO supply modes is c An Automatic Gain Control (AGC) system is included. This provides 50 dB of gain control range so that the output signal level is held at an optimum level at the input of the ADC. D The MAG data controls the AGC loop, such that the MAG bit is active (HIGH) for approximately 33% of the time. The SIGN (pin 20) and MAG (pin 19) signals are latched by the falling edge of the sample clock, CLK_OUT (pin 21) within the ADC. The SIGN and MAG signals, once they arrive at the GPS baseband IC, are best re-sampled on the rising edge of CLK_OUT, for optimum sample and hold. The AGC time constant is determined by a single external capacitor, connected between VAGC (pin 1), and VSSN / GND. The settling-time of the AGC is within 10ms with a 10nF capacitor. PLL and Loop Filter The entire Phase-Locked Loop (PLL) generating the local oscillator for the mixer is contained on-chip. A classic three-element RC PLL loop filter has been implemented on-chip between the output of the internal charge pump and GND / VSSN. The PLL RX_EN Logic level CLK_EN Logic level Note VCC_TCXO output ‘0’ ‘0’ - OPEN ‘0’ ‘1’ 1 VCC ‘1’ ‘1’ 1 VCC Note: (1) TCXO supply current limited to 30 mA max. Clock and Data Output Coupling The high input sensitivity achieved by the SE4150L’s internal LNA requires careful control of harmonically related sources of interference. For this reason the CLK_OUT (pin 21), SIGN (pin 20) and MAG (pin 19) outputs provide carefully controlled current and slew-rate. The data and clock outputs of the SE4150L are specified to drive up to 15pF load (N.B. the max standard CMOS input capacitance is 10pF). The output drive of the SE4150L can be adjusted with a resistor connected between VDDQ (pin 14) and RVI (pin 12), as shown in the Logic Output Current Drive Adjustment Settings section below. The output current drive is determined by a bias current ratio internal to the SE4150L and the external resistor. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 202445B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 1, 2019 6 DATA SHEET SE4150L: GPS Receiver IC Preliminary Datasheet Hardware Configuration The SE4150L supports two settings for gain and input IP3 in the on-chip LNA. LNA Mode LNA Gain LNA IIP3 Hi Gain 20 dB -6 dBm Lo Gain 17 dB -12 dBm The internal LNA can be disabled by connecting the Vcc supply connection to the LNA, VCC_LNA (pin 6) to GND. This may be desirable in some applications, and prevents the LNA from consuming any current, saving approximately 5mA. The sample clock output, CLK_OUT (pin 21) can be kept active by setting CLK_EN (pin 18) pin to logic ‘1’ (HI). This will cause all circuits required to produce the CLK_OUT signal to remain active, even when the receiver is forced into Standby mode (RX_EN (pin 5) set to Logic ‘0’). on Mixer Gain Selection The RX_EN input has a 200 kΩ pull-down resistor to GND, on-chip. This ensures that the RFIC will put itself in standby when the RX_EN controller on the baseband is tri-stated to an impedance much greater than 200 kΩ. tin Supported LNA Gain & Linearity Modes The SE4150L uses RX_EN (pin 5) to put the device into standby. In standby mode, all circuits are off and the device consumes only leakage current. d LNA Gain & Linearity Selection Power Management ue The SE4150L can be configured to change the LNA Gain/Linearity and the Mixer Gain/Linearity by means of the settings on the HW_0 (pin 16) and HW_1 (pin 17) logic inputs. The adjustment of the gain and linearity allow the SE4150L to be used in differing environments, either with significant co-located interference sources (e.g. mobile phone) or no interference sources (e.g. PND). The SE4150L supports two gain settings for the onchip mixer. Supported Mixer Gain Modes Mixer Buffer Gain Hi Gain 32 dB Lo Gain 24 dB D is c Mixer Mode The following truth table gives the settings for hardware configuration of both the LNA Gain/Linearity and also the Mixer Gain/Linearity. Hardware Configuration LNA Mode Mixer Mode Selection value (HW_) Hi Gain Hi Gain 11 Lo Gain Lo Gain 00 Logic Interfacing The SE4150L Logic Inputs can either be driven from an external baseband IC, or permanently set by connecting to either VDDN (pin 22) for Logic ‘1’, or GND for Logic ‘0’. The digital interface on the SE4150L, supplied from VDDN, has been designed to operate at the same voltage as the GPS baseband IC. The ANT_DET (pin 8) output is sourced from the antenna current detector, and is also connected to the internal antenna switch; the switch toggles the RF signal source automatically when an external active antenna is connected. The antenna current detector can be overridden by applying a low impedance source (