SL2305SI-1H

SL2305 Not Recommended for New Designs Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features 10 to 140 MHz operating frequency range Low output clock jitter: - 140 ps-max c-c-j at 66 MHz Low output-to-output skew: 150 ps-max Low product-to-product skew: 400 ps-max 3.3 V power supply range Low power dissipation: - 14 mA-max at 66MHz - 26 mA-max at 133 MHz One input drives 5 outputs organized as 4+1 SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 8-pin SOIC and TSSOP packages Available in Commercial and Industrial grades The SL2305 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. N ot fo R r N ec o ew m m D e es nd ig e ns d   Description          Applications       The SL2305 is available with two (2) drive strength versions. The -1 is the standard-drive version and -1H is the highdrive version. The SL2305 high-drive version operates up to 140MHz and the standard drive version -1 operates up to 100. The SL2305 enter into Power-Down (PD) mode if the input at CLKIN is DC (0 to VDD). In this power-down state all five (5) outputs are tri-stated and the PLL is turned off leading to less than 12μA-max of power supply current draw. Benefits   Printers and MFPs Digital Copiers PCs and Work Stations DTV Routers, Switchers and Servers Digital Embeded Systems    Up to five (5) distribution of input clock Standard and High-Drive levels to control impedance level, frequency range and EMI Low jitter and skew Low power dissipation Low cost Block Diagram PLL CLKIN CLKOUT CLK1 CLK2 CLK3 CLK4 VDD GND Rev 0.1 9/13 400 West Cesar Chavez, Austin, TX 78701 Page 1 of 11 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL2305 N ot fo R r N ec o ew m m D e es nd ig e ns d Pin Configuration CLKIN 1 8 CLKOUT CLK2 2 7 CLK4 CLK1 3 6 VDD GND 4 5 CLK3 8-Pin SOIC or TSSOP Pin Description Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input 2 CLK2 Output Buffered Clock Output Weak pull-down (250kΩ). 3 CLK1 Output Buffered Clock Output. Weak pull-down (250kΩ). 4 GND Power Power Ground. 5 CLK3 Output Buffered Clock Output. Weak pull-down (250kΩ). 6 VDD Power 3.3V Power Supply. 7 CLK4 Output Buffered Clock Output. Weak pull-down (250kΩ). 8 CLKOUT Output Buffered Clock Output, Used for Internal Feedback to PLL Input. Weak pulldown (250kΩ). Rev 0.1 9/13 Reference Frequency Clock Input. Weak pull-down (250kΩ). Page 2 of 11 SL2305 General Description The SL2305 is a low skew, low jitter Zero Delay Buffer with very low operating power supply current (IDD). The SL2305 is offered with High-Drive “-1H” and StandardDrive “-1” options. These drive options enable the users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details. N ot fo R r N ec o ew m m D e es nd ig e ns d The product includes an on-chip high performance PLL that locks into the input reference clock and produces five (5) output clock drivers tracking the input reference clock for systems requiring clock distribution. High and Low-Drive Product Options In addition to CLKOUT that is used for internal PLL feedback, there is a single bank with four (4) outputs, bringing the number of total available output clocks to five (5). Input and output Frequency Range The input and output frequency range is the same. But, the frequency range depends on the drive levels and load capacitance (CL) as given in the below Table 1. Drive CL(pF) Min(MHz) Max(MHz) HIGH (-1H) 15 10 140 HIGH (-1H) 30 10 100 STD (-1) 15 10 100 STD (-1) 30 10 66 Table 1. Input/Output Frequency Range If the input clock frequency is DC (0 to VDD), this is detected by an input detection circuitry and all five (5) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12μA-max supply current. SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL2305 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its CLKIN (reference) input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency. Skew and Zero Delay All outputs should drive the similar load to achieve outputto-output and input-to-output skew specifications given in the AC electrical tables. However, Zero delay between input and outputs can be adjusted by changing the loading of CLKOUT relative to the other clock outputs since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL2305 is designed to operate from 3.0V (Min) to 3.6V (Max), complying with VDD=3.3V+/-10% requirement. An internal on-chip voltage regulator is used to supply PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Temperature Range and Packages The SL2305 is offered with commercial temperature range of 0 to +70°C (C-Grade) and industrial temperature range of -40 to +85°C (I-Grade). The SL2305 is available in 8-pin SOIC (150-mil) and 8-pin TSSOP (173-mil) packages. SL23EP05 Refer to SL23EP05 for extended frequency operation from 10 to 220MHz and 2.5V to 3.3V power supply operation range. Absolute Maximum Ratings Description Condition Min Max Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V Ambient Operating Temperature In operation, C-Grade 0 70 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C Rev 0.1 9/13 Page 3 of 11 SL2305 Soldering Temperature – 260 °C JEDEC22-A114D -4,000 4,000 V ESD Rating (Charge Device Model) JEDEC22-C101C -1,500 1,500 V ESD Rating (Machine Model) JEDEC22-A115D -250 250 V Latch-up 125°C -200 200 mA N ot fo R r N ec o ew m m D e es nd ig e ns d ESD Rating (Human Body Model) Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Max Unit VDD 3.3V Supply Voltage 3.3V+/-10% 3.0 3.6 V TA Operating Temperature(Ambient) Commercial 0 70 °C –40 85 °C Load Capacitance 10 to 140 MHz, -1H high drive – 15 pF 10 to 100 MHz, -1H high drive – 30 pF 10 to 100MHz, -1 standard drive – 15 pF 10 to 66MHz, -1 standard drive – 30 pF – 7 pF 0.05 100 ms CLOAD Industrial CIN Input Capacitance CLKIN pin tpu Power-up Time Power-up time for all VDDs to reach minimum VDD voltage (VDD=3.0V). CLBW Closed-loop bandwidth 3.3V, (typical) 1.2 MHz ZOUT Output Impedance 3.3V (typical), -1H high drive 22 Ω 3.3V (typical), -1 standard drive 32 Ω Rev 0.1 9/13 Page 4 of 11 SL2305 DC Electrical Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Max Unit 3.0 3.6 V Supply Voltage VIL Input LOW Voltage CLKIN (Pin-1) – 0.8 V VIH Input HIGH Voltage CLKIN (Pin-1) 2.0 VDD+0.3 V IIL Input LOW Current CLKIN, 0 < VIN < 0.8V – 25 µA IIH Input HIGH Current CLKIN, VIN = VDD – 50 µA VOL Output LOW Voltage (All outputs) IOL = 8 mA (standard drive) – 0.4 V IOL = 12 mA (high drive) – 0.4 V Output HIGH Voltage (All outputs) IOH = –8 mA (standard drive) 2.4 – V IOH = –12 mA (high drive) 2.4 – V Power Down Supply Current CLKIN=0 to VDD C-Grade, Power-down if CLKIN=0 to VDD or input is floating – 12 µA I-Grade, Power-down if CLKIN=0 to VDD or input is floating – 25 µA N ot fo R r N ec o ew m m D e es nd ig e ns d VDD VOH IDDPD IDD1 Power Supply Current All Outputs CL=0, 33MHz CLKIN – 8 mA IDD2 Power Supply Current All Outputs CL=0, 66MHz CLKIN – 14 mA IDD3 Power Supply Current All Outputs CL=0, 100MHz CLKIN – 20 mA IDD4 Power Supply Current All Outputs CL=0, 133MHz CLKIN – 26 mA RPD Pull-down Resistors Pins-1/2/3/5/7/8, 250kΩ-typ 175 325 kΩ Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition FMAX1 Maximum Frequency [1] (Input=Output ) All Active PLL Modes High drive (-1H). All outputs CL=15pF 10 140 MHz High drive (-1H), All outputs CL=30pF 10 100 MHz Standard drive, (-1), All outputs CL=15pf 10 100 MHz Standard drive, (-1), All outputs CL=30pf 10 66 MHz Input Duty Cycle Measured at 1.4V, Fout=66MHz, CL=15pF 30 70 % OUTDC1 Output Duty Cycle[2] Measured at 1.4V, Fout≥50MHz, CL=15pF 40 60 % OUTDC2 Output Duty Cycle[2] Measured at 1.4V, Fout≤50MHz, CL=15pF 45 55 % tr/f Rise, Fall Time (3.3V) [2] (Measured at: 0.8 to 2.0V) High drive (-1H), CL=10pF – 1.5 ns High drive (-1H), CL=30pF – 1.8 ns Standard drive (-1), CL=10pF – 2.2 ns Standard drive (-1), CL=30pF – 2.5 ns INDC Rev 0.1 9/13 Min Max Unit Page 5 of 11 SL2305 Output-to-Output Skew[2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 150 ps t2 Product-to-Product Skew[2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 400 ps N ot fo R r N ec o ew m m D e es nd ig e ns d t1 t3 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge[2] Measured at VDD/2 tPLOCK PLL Lock Time[2] CCJ Cycle-to-cycle Jitter [2] –220 220 ps Time from 90% of VDD to valid clocks on all the output clocks – 1.0 ms Fin=Fout=66 MHz,