SL74HC165D

SL74HC165 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS The SL74HC165 is identical in pinout to the LS/ALS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device is an 8-bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/ Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2 -input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC165N Plastic SL74HC165D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16=VCC PIN 8 = GND FUNCTION TABLE Inputs Serial Shift/ Parallel Load L H H H H H H H L L X H L H X L Clock H Clock Inhibit X L L SA X L H L H X X X A -H a...h X X X X X X X n o change No Clock Internal Stages QA a L H L H QB-QG b-g QAn-QFn QAn-QFn QAn-QFn QAn-QFn n o change Output QH h QGn QGn QGn QGn Serial Shift via Clock Inhibit Inhibited Clock Asynchronous Parallel Load Serial Shift via Clock Operation X = Don’t Care QAn-QFn = Data shifted from the preceding stage SLS System Logic Semiconductor SL74HC165 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC165 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 ≤85 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 ≤125 °C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 µA µA V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT ≤ 20 µA VIN= VIL or VIH IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN=VCC or GND IOUT=0µA SLS System Logic Semiconductor SL74HC165 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 8) Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH (Figures 1 and 8) Maximum Propagation Delay , SerialShift./.Parallel Load to QH or QH (Figures 2 and 8) Maximum Propagation Delay, Input H to QH or QH (Figures 3 and 8) Maximum Output Transition Time, Any Output (Figures 1 and 8) Maximum Input Capacitance Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 6.0 30 35 150 30 26 175 35 30 150 30 26 75 15 13 10 ≤85°C 4.8 24 28 190 38 33 220 44 37 190 38 33 95 19 16 10 ≤125°C 4.0 20 24 225 45 38 265 53 45 225 45 38 110 22 19 10 Unit MHz tPLH, t PHL ns tPLH, t PHL ns tPLH, t PHL ns tTLH, t THL ns CIN pF Typical @25°C,VCC=5.0 V 85 pF SLS System Logic Semiconductor SL74HC165 TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tSU Parameter Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4) Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5) Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6) Minimum Setup Time, Clock to Clock Inhibit (Figure 7) Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4) Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5) Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6) Minimu m Recovery Time, Clock to Clock Inhibit (Figure 7) Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1) Minimum Pulse Width, Serial Shift/Parallel Load (Figure 2) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 25 °C to -55°C 100 20 17 100 20 17 100 20 17 100 20 17 5 5 5 5 5 5 5 5 5 100 20 17 80 16 14 80 16 14 1000 500 400 Guaranteed Limit ≤85°C 125 25 21 125 25 21 125 25 21 125 25 21 5 5 5 5 5 5 5 5 5 125 25 21 100 20 17 100 20 17 1000 500 400 ≤125°C 150 30 26 150 30 26 150 30 26 150 30 26 5 5 5 5 5 5 5 5 5 150 30 26 120 24 20 120 24 20 1000 500 400 Unit ns tSU ns tSU ns tSU ns th ns th ns th ns trec ns tw ns tw ns tr, tf ns SLS System Logic Semiconductor SL74HC165 SWITCHING WAVEFORMS SLS System Logic Semiconductor SL74HC165 TIMING DIAGRAM EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor