SL74LV245D

SL74LV245 OCTAL BUS TRANSCEIVER (3-State) By pinning SL74LV245 are compatible with SL74HC245 and SL74HCT245 series. Input voltage levels are compatible with standard CMOS levels. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS NS F I U FX • Supply voltage range: 2.0 to 3.2 V P A TC LSI • Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ • Output current 8 mÀ • Latch current value: not less 150 mÀ at Ò = 125 °Ñ 20 • ESD acceptable values: not less than 2000 V as per HBM and 1 DS F I U FX not less 200 V as per ÌÌ SI OC • 20 1 BLOCK DIAGRAM DIR 01 OE A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 Pin 20=VCC Pin 10 = GND 18 19 DIR ORDERING INFORMATION S L74LV245N Plastic DIP S L74LV245D SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT 01 20 19 18 17 16 02 VCC OE B0 B1 B2 B3 B4 B5 B6 B7 A0 02 A1 03 03 17 A2 04 A3 05 245 04 16 A4 06 A5 07 15 14 13 12 11 05 15 A6 08 A7 09 06 14 GND 10 07 13 08 FUNCTION TABLE 12 Inputs OE 11 L L H DIR L H X Inputs/Outputs À A=B input Z  input B=A Z 09 SLS System Logic Semiconductor SL74LV245 ABSOLUTE MAXIMUM RATINGS* Symbol VCC IIK * 1 2 Parameter Supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: Plastic DIP *4 SOIC *4 Storage temperature range Rating -0.5 to +5.0 ±20 ±50 ±35 ±70 ±70 750 500 -65 to +150 Unit V mÀ mÀ mÀ mÀ mÀ mW IOK * IO *3 ICC IGND PD Tstg * °C In absolute maximum ratings modes functioning is not guaranteed. Vpon lifting the absolute maximum ratings functioning is guaranteed at the recommended operating conditions. *1 Provided VI < -0.5 V or VI > VCC + 0.5 V. *2 Provided VO < -0.5 V or VO > VCC + 0.5 V. *3 P rovided -0.5 V < VO < VCC + 0.5 V. *4 When operating in the temperature range of 70°Ñ to 125°C power dissipation value decreases: - for Plastic DIP by 12 m W/ °C - for SOIC by 8 m W/ °C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA tLH, tHL Supply voltage Input voltage Output voltage Operating ambient temperature range. For all package types Input rise and fall times VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Parameter Min 1.2 0 0 -40 0 Max 3.6 VCC VCC 125 1000 700 500 400 Unit V V V °C ns SLS System Logic Semiconductor SL74LV245 DC CHARACTERISTICS Test Symbol Parameter conditions VCC, V 25° C min VIH HIGH level input voltage VO = VCC-0.1 V 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 3.0 1.2 2.0 3.0 3.6 3.0 3.6 3.6 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 max 0.3 0.6 0.9 1.1 0.09 0.09 0.09 0.09 0.33 ±0.1 ±0.5 Limits -40° C to 85° C min 0.9 1.4 2.1 2.5 1. 0 1.9 2.9 3.5 2.34 m ax 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0. 09 0.4 ±1.0 ±5 125° C min 0.9 1.4 2.1 2.5 1. 0 1.9 2.9 3.5 2.20 m ax 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0. 09 0.5 ±1.0 ±10 V Unit VIL LOW level output VO =0.1 V voltage V VOH HIGH level output VI = VIH or VIL voltage IO = -50 µÀ V VI = VIH or VIL IO = -8 mÀ VOL LOW level output VI = VIH or VIL voltage IO = 50 µÀ V V VI = VIH or VIL IO = 8 mÀ II IOZ Input current VI = VCC or 0 V V µÀ µÀ OFF-state current 3-state outputs VI = VIL or VIH VO =VCC or 0 V Supply current VI =VCC or 0 V IO = 0 µÀ ICC 3.6 - 8.0 - 80 - 160 µÀ SLS System Logic Semiconductor SL74LV245 AC CHARACTERISTICS(CL=50 pF, tLH = tHL = 6.0 ns) Test Symbol Parameter conditions VCC, V 25° C Limits -40° C to 85° C m ax 125 28 18 140 37 24 140 35 21 75 20 13 min 125° C m ax 140 34 21 160 43 28 160 43 26 90 24 15 pF ns Unit min max min tPHL, tPLH Propagation from An to delay Bn, from Bn to An tPHZ tPLZ 3-state output from OE, DIR enable time to An, Bn tPZH tPZL from OE to An, Bn tTHL, tTLH 3-state output disable time HIGH-to-LOW and LOW-to HIGH transition time Input capacitance Input capacitance Figure 1 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 3.0 3.0 100 23 14 120 30 20 120 28 17 60 15 10 7 20 - Figure 2 ns Figure 2 Figure 1 CI CI/Î For inputs 01,19 For inputs/ outputs 02-09, 11-18 CPD Power VI = 0 V or dissipation VCC capacitance (per one channel) 3.0 - 50 - - - - SLS System Logic Semiconductor SL74LV245 tLH 0.9 An, Bn V1 0.1 tPLH V1 tHL 0.9 VCC 0.1 tPHL GND 0.9 V1 0.1 tTLH V1 = 0.5V CC 0.9 V1 0.1 0V B Bn, An tTHL Figure 1 -Time diagram of AC parameters control tPLH, tPHL. tHL 0.9 OE, DIR V1 0.1 tPZH V1 0.1 tLH 0.9 V1 VCC GND VOH 0.9 tPHZ An, Bn 0V B tPLZ An, Bn V1 tPZL 0.1 VOL V1 = 0.5V CC VCC Figure 2 - Time diagram of tPLZ, tPHZ, tPZL, tPZH. AC parameters control SLS System Logic Semiconductor SL74LV245 2.3mm 18 19 17 16 15 14 13 12 On-chip marking 11 1.99 mm 74LV245 10 1 2 3 4 5 6 7 8 9 Drawing of the chip Pads allocation Table Pad number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 coordinates (counted from lower left corner), mm X Y 0.140 0.573 0.140 0.315 0.370 0.140 0.790 0.140 1.000 0.140 1.200 0.140 1.417 0.140 1.833 0.140 2.060 0.354 2.060 0.760 2.060 1.340 2.060 1.520 1.833 1.750 1.415 1.750 1.000 1.750 0.790 1.750 0.580 1.750 0.370 1.750 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 System Logic Semiconductor SLS SL74LV245 19 20 0.140 0.140 1.544 1.375 0.108 x 0.108 0.108 x 0.108 SLS System Logic Semiconductor