CY28408ZCT

CY28408 Clock Synthesizer with Differential CPU Outputs Features • Compatible to Intel® CK 408 Mobile Clock Synthesizer • Support Intel P4 and Brookdale CPU • Specifications • 3.3V power supply • Three differential CPU clocks • Ten copies of PCI clocks Table 1. Frequency Table[1] S2 1 1 1 1 0 0 0 0 M M S1 0 0 1 1 0 0 1 1 0 0 S0 0 1 0 1 0 1 0 1 0 1 133 MHz Hi-Z TCLK/2 66 MHz Hi-Z TCLK/4 166 MHz 66 MHz 100 MHz 66 MHz 66 MHz 66 MHz CPU(0:2) 100 MHz 133 MHz 3V66 66 MHz 66 MHz PCI_PCIF 33 MHz 33 MHz Reserved 33 MHz 33 MHz 33 MHz Reserved 33 MHz Hi-Z TCLK/8 14.318 MHz Hi-Z TCLK 48 MHz Hi-Z TCLK/2 14.318 MHz 14.318 MHz 14.318 MHz 48 MHz 48 MHz 48 MHz REF 14.318 MHz 14.318 MHz USB/DOT 48 MHz 48 MHz • Six copies of 3V66 clocks • SMBus support with read back capabilities • Spread Spectrum electromagnetic interference (EMI) reduction • Dial-A-Frequency® features • Dial-A-dB features • 56-pin TSSOP package Block Diagram XIN XOUT PLL1 CPU_STP# IREF VSSIREF S(0:2) MULT0 VTT_PWRGD# PCI_STP# PLL2 /2 Pin Configuration REF VDD XIN XOUT VSS PCIF0 PCIF1 PCIF2 VDD VSS PCI0 EPCI1/PCI1 PCI2 EPCI3/PCI3 VDD VSS PCI4 PCI5 PCI6 VDD VSS 3V66_2 3V66_3 3V66_4 3V66_5 PD# VDDA VSSA VTT_PWRGD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF S1 S0 CPU_STP# CPUT0 CPUC0 VDD CPUT1 CPUC1 VSS VDD CPUT2 CPUC2 MULT0 IREF VSSIREF S2 48M_USB 48M_DOT VDD VSS 3V66_1/VCH PCI_STP# 3V66_0 VDD VSS SCLK SDATA CPUT(0:2) CPUC(0:2) 3V66_0 3V66_1/VCH PCI(0:6) PCI_F(0:2) 48M_USB 48M_DOT CY28408 PD# SDATA SCLK VDDA WD Logic I2C Logic 3V66[2:5] Power Up Logic Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, an 0 state will be latched into the device’s internal state register. Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 18 www.SpectraLinear.com CY28408 Pin Description Pin 2 3 Name XIN XOUT PWR VDD VDD VDD VDDP VDD VDD I/O I O O O I/O PD O Description Oscillator buffer input. Connect to a crystal or to an external clock. Oscillator buffer output. Connect to a crystal. Do not connect when an external clock is applied at XIN. Differential host output clock pairs. See Table 1 for frequencies and functionality. PCI clock outputs. Synchronous to the 3V66 clock. See Table 1. Early or normal PCI clock outputs. There is an internal 250k pull-down resistor. See Table 8. 33-MHz PCI clocks, which are 2 copies of 3V66 clocks, may be free running (not stopped when PCI_STP# is asserted LOW) or may be stoppable depending on the programming of SMBus register Byte3, Bits (3:5). Buffered output copy of the device’s XIN clock. Current reference programming input for CPU buffers. A resistor is connected between this pin and VSSIREF. Qualifying input that latches S(0:2) and MULT0. When this input is at a logic low, the S(0:2) and MULT0 are latched Fixed 48-MHz USB clock outputs. Fixed 48-MHZ DOT clock outputs. 3.3V 66-MHz fixed frequency clock. 3.3V clock selectable with SMBus byte0, Bit5, when Byte5, Bit5. When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When byte0, Bit5 is a logic 0, then this is a 66-MHz output clock (default). 3.3V 66-MHz fixed frequency clock. This pin is a power-down mode pin. A logic LOW level causes the device to enter a power-down state. All internal logic is turned off except for the SMBus logic. All output buffers are stopped. Programming input selection for CPU clock current multiplier. 0 = 4 * IREF, 1 = 6 * =IREF Frequency select inputs. See Table 1 Serial data input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. Serial clock input. Conforms to the SMBus specification. 52, 51, 49, 48, CPUT(0:2), 45, 44 CPUC(0:2) 10, 12, 16, 17, 18 PCI(0,2)/(3:5) 11,13 EPCI/PCI(1,3) 5, 6, 7 PCIF (0:2) 56 42 28 39 38 33 35 REF IREF VTT_PWRGD# 48M_USB 48M_DOT 3V66_0 3V66_1/VCH VDD VDD VDD VDD48 VDD48 VDD VDD O I I O O O O 21, 22, 23, 24 25 3V66(2:5) PD# VDD VDD O I PU I PU I I/O PU I PU I T I PU 43 55, 54 29 MULT0 S(0,1) SDATA VDD VDD VDD 30 40 34 SCLK S2 PCI_STP# VDD VDD VDD 53 CPU_STP# VDD 1, 8, 14, 19, 32, 37, 46, 50 4, 9, 15, 20, 27, 31, 36, 47 41 VDD VSS VSSIREF – – – Frequency select input. See Table 1. This is a tri-level input that is driven HIGH, LOW, or driven to a intermediate level. PCI clock disable input. When asserted LOW, PCI (0:6) clocks are synchronously disabled in a LOW state. This pin does not effect PCIF (0:2) clock outputs if they are programmed to be PCIF clocks via the device’s SMBus interface. I CPU clock disable input. When asserted LOW, CPUT (0:2) clocks are PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchronously disabled in a LOW state. PWR 3.3V power supply. PWR Common ground. PWR Current reference programming input for CPU buffers. A resistor is connected between this pin and IREF. This pin should also be returned to device VSS. PWR Analog power input. Used for PLL and internal analog circuits. It is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate. 26 VDDA – Rev 1.0, November 20, 2006 Page 2 of 18 CY28408 Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Data Protocol The clock driver serial protocol accepts block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 Bits Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N –8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... ... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Description Bit 1 8:2 9 10 18:11 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Byte Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 Bits Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits Acknowledge Data bytes from slave / Acknowledge Data Bte N from slave – 8 bits NOT Acknowledge Stop Block Read Protocol Description Rev 1.0, November 20, 2006 Page 3 of 18 CY28408 Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 19 27:20 28 29 Data byte – 8 bits Acknowledge from slave Stop Description Acknowledge from slave Bit 19 20 27:21 28 29 37:30 38 39 Byte 0: CPU Clock Register[2] Bit 7 @Pup 0 Name Description Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On This is a Read and Write control bit. CPU clock Power-down Mode Select. 0 = Drive CPUT to 4 or 6 IREF and drive CPUC to low when PD# is asserted LOW. 1 = Three-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to CPU_STP#. 3V66_1/VCH CPU_STP# PCI_STP# SEL2 SEL1 SEL0 3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected This is a Read and Write control bit. Reflects the current value of the external CPU_STP#. This bit is Read-only. Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin. This is a Read and Write control bit. Frequency Select Bit 2. Reflects the value of SEL2. This bit is Read-only. Frequency Select Bit 1. Reflects the value of SEL1. This bit is Read-only. Frequency Select Bit 0. Reflects the value of SEL0. This bit is Read-only. Repeated start Slave address – 7 bits Read Acknowledge from slave Data from slave – 8 bits NOT Acknowledge Stop Byte Read Protocol Description Acknowledge from slave 6 0 5 4 3 2 1 0 0 Pin 53 Pin 34 Pin 40 Pin 55 Pin 54 Byte 1: CPU Clock Register Bit 7 @Pup Pin 43 Name Description MULT0 Value. This bit is Read-only. Controls functionality of CPUT/C outputs when CPU_STP# is asserted. 0 = Drive CPUT to 4 or 6 IREF and drive CPUC to low when CPU_STP# is asserted LOW. 1 = Tri-state all CPU outputs when CPU_STP# is asserted.This bit will override Byte0, Bit6 such that even if it is a 0, when PD# goes low the CPU outputs will be tri-stated. Controls CPU2 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. Controls CPU1 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. Controls CPUT0 functionality when CPU_STP# is asserted LOW 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW This is a Read and Write control bit. CPUT/C2 CPUT/C2 Output Control 1 = enabled, 0 = three-state CPUT/C2 This is a Read and Write control bit. 6 0 5 0 4 0 3 0 2 1 Note: 2. PU = Internal Pull-up. PD = Internal Pull-down. T = Tri-level logic input. Rev 1.0, November 20, 2006 Page 4 of 18 CY28408 Byte 1: CPU Clock Register (continued) Bit 1 @Pup 1 Name CPUT/C1 Description CPUT/C1 Output Control 1 = enabled, 0 = three-state CPUT/C1 This is a Read and Write control bit. CPUT/C0 Output Control 1 = enabled, 0 = three-state CPUT/C0 This is a Read and Write control bit. 0 1 CPUT/C0 Byte 2: PCI Clock Control Register (all bits are read- and write-functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Name REF PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Description REF Output Control. 0 = high strength, 1 = low strength PCI6 Output Control 1 = enabled, 0 = forced LOW PCI5 Output Control 1 = enabled, 0 = forced LOW PCI4 Output Control 1 = enabled, 0 = forced LOW PCI3 Output Control 1 = enabled, 0 = forced LOW PCI2 Output Control 1 = enabled, 0 = forced LOW PCI1 Output Control 1 = enabled, 0 = forced LOW PCI0 Output Control 1 = enabled, 0 = forced LOW Byte 3: PCI_F Clock and 48M Control Register (all bits are read- and write-functional) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 0 1 1 1 PCI_F2 PCI_F1 PCI_F0 Name 48M_DOT 48M_USB 48M_DOT Output Control 1 = enabled, 0 = forced LOW 48M_USB Output Control 1 = enabled, 0 = forced LOW PCI_STP#, control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_STP#, control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_STP#, control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_F2 Output Control 1 = running, 0 = forced LOW PCI_F1 Output Control 1 = running, 0 = forced LOW PCI_F0 Output Control 1 = running, 0 = forced LOW Description Rev 1.0, November 20, 2006 Page 5 of 18 CY28408 Byte 4: 3V66 Control Register (all bits are read- and write-functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 1 1 1 1 1 3V66_0 3V66_1/VCH 3V66_5 3V66_4 3V66_3 3V66_2 Name Reserved 3V66_0 Output Enabled, 1 = enabled, 0 = disabled 3V66_1/VCH Output Enable 1 = enabled, 0 = disabled 3V66_5 Output Enable 1 = enabled, 0 = disabled 3V66_4 Output Enabled 1 = enabled, 0 = disabled 3V66_3 Output Enabled 1 = enabled, 0 = disabled 3V66_2 Output Enabled 1 = enabled, 0 = disabled Description SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread) Byte 5: Spread Spectrum Control Register (all bits are read and write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 0 0 0 Name Description SS1 Spread Spectrum control bit SS0 Spread Spectrum control bit Reserved Reserved Reserved 48M_DOT edge rate control. When set to 1, the edge is slowed by 40%. Reserved USB edge rate control. When set to 1, the edge is slowed by 40%. Table 5. Spread Spectrum SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Center Center Center Center Spread% +0.00, –0.25 +0.00, –0.50 +0.00, –0.75 +0.00, –1.00 +0.13, –0.13 +0.25, –0.25 +0.37, –0.37 +0.50, –1.50 Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI reduction generated by repetitive digital signals. A clock presents the generated EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. Table 5 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Byte 6: Silicon Signature Register (all bits are read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Rev 1.0, November 20, 2006 Page 6 of 18 CY28408 Byte 7: Reserved Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 1 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved N8, MSB Description Byte 8: Dial-a-Frequency Control Register N (all bits are read and write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name N7 N6 N5 N4 N3 N2 N3 N0, LSB Description Byte 9: Dial-a-Frequency™ Control Register R (all bits are read and write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name R6 MSB R5 R4 R3 R2 R1 R0, LSB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from DAF (SMBus) registers. Description Dial-a-Frequency Feature SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. See our App Note AN-0025 for details on our Dial-a-Frequency feature. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 6. Table 6. P Value S(1:0) 00 01 10 11 P 32005333 48008000 96016000 64010667 USB and DOT 48M Phase Relationship The 48M_USB and 48M_DOT clocks are normally in phase. It is understood that the difference in edge rate will introduce some inherent offset. When 3V66_1/VCH clock is configured for VCH (48-MHz) operation it is also in phase with the USB and DOT outputs. See Figure 1. Rev 1.0, November 20, 2006 Page 7 of 18 CY28408 48MUSB 48MDOT Figure 1. 48M_USB and 48M_DOT Phase Relationship Table 7. Group Timing Relationship and Tolerances Description 3V66 to PCI 48M_USB to 48M_DOT Skew Offset 2.5 ns 0 or 10.4 ns Tolerance 1.0 ns 1.0 ns 3V66 Leads PCI Conditions 3V66 PCI PCI_F Tpci Figure 2. 3V66 to PCI and PCI_F Phase Relationship Table 8. Early PCI Select Functions[3] EPCI3 0 1 1 EPCI1 0 0 1 EPCI(3,1) 0.0 ns 0.8 ns 1.6 ns 3V66_1/VCH Clock Output The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. If Byte0, Bit 5 = ‘1’, then the output is configured as a 48-MHz non-spread spectrum output. This output is phase aligned with the other 48M outputs (USB and DOT), to within 1 ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power on. When the SMBus Bit 5 of Byte 0 is programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH output may glitch while transitioning to 48M output mode. CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# – Assertion When CPU_STP# pin is asserted, all CPUT/C outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two falling CPUT/C clock edges. The final state of the stopped CPU signals is CPUT = HIGH and CPU0C = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal will not be driven. Due to external pull-down circuitry CPUC will be LOW during this stopped state. Special Functions PCI_F and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. ANY two of the PCI_F clock outputs can be used as IOAPIC 33-MHz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event these clocks are not required, then these clocks can be used as general PCI clocks or disabled via the assertion of the PCI_STP# pin. Note: 3. 0 = 10K Pull-down resistor, 1 = 10k Pull-up resistor. Rev 1.0, November 20, 2006 Page 8 of 18 CY28408 CPU_STP# CPUT CPUC CPUT CPUC Figure 3. CPU_STP# Assertion Waveform C PU_STP# CPUT CPUC CPUT CPUC Figure 4. CPU_STP# Deassertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces when the clock resumes. The maximum latency from the deassertion to active outputs is no more than 2 CPUC clock cycles. Table 9. Cypress Clock Power Management Truth Table B0b6 0 0 0 0 0 0 0 0 1 1 1 1 B1b6 0 0 0 0 1 1 1 1 0 0 0 0 PD# 1 1 0 0 1 1 0 0 1 1 0 0 CPU_STP# Stoppable CPUT 1 0 1 0 1 0 1 0 1 0 1 0 Running Iref x6 Iref x2 Iref x2 Running Hi Z Hi Z Hi Z Running Iref x6 Hi Z Hi Z Stoppable CPUC Running Iref x6 Low Low Running Hi Z Hi Z Hi Z Running Iref x6 Hi Z Hi Z Non-Stop CPUT Non-Stop CPUC Running Running Iref x2 Iref x2 Running Running Hi Z Hi Z Running Running Hi Z Hi Z Running Running Low Low Running Running Hi Z Hi Z Running Running Hi Z Hi Z Three-state Control of CPU Clocks Clarification During CPU_STP# and PD# modes, CPU clock outputs may be set to driven or undriven (three-state) by setting the corresponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1. Rev 1.0, November 20, 2006 Page 9 of 18 CY28408 Table 9. Cypress Clock Power Management Truth Table (continued) B0b6 1 1 1 1 B1b6 1 1 1 1 PD# 1 1 0 0 CPU_STP# Stoppable CPUT 1 0 1 0 Running Hi Z Hi Z Hi Z Stoppable CPUC Running Hi Z Hi Z Hi Z Non-Stop CPUT Non-Stop CPUC Running Running Hi Z Hi Z Running Running Hi Z Hi Z PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see Figure 7). The PCI_F clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running. PCI_STP# – Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCI_F clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. Note that the PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs to the function are logically ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the devices stoppable PCI clocks are not running. PD# (Power-down) Clarification The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. PD# – Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 x Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. t setup PCI_STP# PCI_F PCI Figure 5. PCI_STP# Assertion Waveform t setup PCI_STP# PCI_F PCI Figure 6. PCI_STP# Deassertion Waveform Rev 1.0, November 20, 2006 Page 10 of 18 CY28408 PD# CPUT CPUC PCI 3V66 48M_USB REF Figure 7. Power-down Assertion Timing Waveforms PD# – Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 1.8 ms. Tstable 0.25mS VDDA = 2.0V Sample Inputs straps Wait for