SST34HF3244C-70-4E-L1PE

32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C SST34HF32x4x32Mb CSF + 4/8/16 Mb SRAM (x16) MCP ComboMemory Data Sheet FEATURES: • Flash Organization: 2M x16 or 4M x8 • Dual-Bank Architecture for Concurrent Read/Write Operation – 32 Mbit Top Sector Protection – 8 Mbit + 24 Mbit • SRAM Organization: – 4 Mbit: 256K x16 • Single 2.7-3.3V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 25 mA (typical) – Standby Current: 20 µA (typical) • Hardware Sector Protection (WP#) – Protects 8 KWord in the smaller bank by holding WP# low and unprotects by holding WP# high • Hardware Reset Pin (RST#) – Resets the internal state machine to reading data array • Byte Selection for Flash (CIOF pin) – Selects 8-bit or 16-bit mode • Sector-Erase Capability – Uniform 2 KWord sectors • Flash Chip-Erase Capability • Block-Erase Capability – Uniform 32 KWord blocks • Erase-Suspend / Erase-Resume Capabilities • Read Access Time – Flash: 70 ns – SRAM: 70 ns • Security ID Feature – SST: 128 bits – User: 256 Bytes • Latched Address and Data • Fast Erase and Program (typical): – Sector-Erase Time: 18 ms – Block-Erase Time: 18 ms – Chip-Erase Time: 35 ms – Program Time: 7 µs • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling – Ready/Busy# pin • CMOS I/O Compatibility • JEDEC Standard Command Set • Packages Available – 56-ball LFBGA (8mm x 10mm) – 62-ball LFBGA (8mm x 10mm) • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST34HF3244C ComboMemory device integrates either a 2M x16 or 4M x8 CMOS flash memory bank with a 256K x16 CMOS SRAM memory bank in a multi-chip package (MCP). These devices are fabricated using SST’s proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF3244C are ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SST34HF3244C feature dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the SRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash memory banks are partitioned into 8 Mbit + 24 Mbit with top sector protection options for storing boot code, program code, configuration/parameter data and user data. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF3244C devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Program time of 7 µsec. The entire flash memory bank can be erased and programmed word-by-word in typically 4 seconds for the SST34HF3244C, when using interface features such as Toggle Bit, Data# Polling, or RY/BY# to indicate the completion of Program operation. To protect © 2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation. CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet against inadvertent flash write, the SST34HF3244C contain on-chip hardware and software data protection schemes. The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SRAM bank enable signals, BES1# and BES2, select the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF3244C are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figure 2 for pin assignments. Concurrent Read/Write Operation Dual bank architecture of SST34HF3244C devices allows the Concurrent Read/Write operation whereby the user can read from one bank while programming or erasing in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. See Table 3 for dual-bank memory organization. Concurrent Read/Write States Flash Bank 1 Read Write Write No Operation Write No Operation Bank 2 Write Read No Operation Write No Operation Write SRAM No Operation No Operation Read Read Write Write Device Operation The SST34HF3244C uses BES1#, BES2 and BEF# to control operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the SRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low. Note: For the purposes of this table, write means to perform Block-/Sector-Erase or Program operations as applicable to the appropriate bank. Flash Read Operation The Read operation of the SST34HF3244C is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 7). ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 2 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet Flash Program Operation These devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the CIOF pin. Before programming, one must ensure that the sector being programmed is fully erased. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 µs. See Figures 8 and 9 for WE# and BEF# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored. Flash Chip-Erase Operation The SST34HF3244C provide a Chip-Erase operation, which allows the user to erase all flash sectors/blocks to the “1” state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bits or Data# Polling. See Table 6 for the command sequence, Figure 12 for timing diagram, and Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. Flash Erase-Suspend/-Resume Operations The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode no more than 10 µs after the Erase-Suspend command had been issued. (TES maximum latency equals 10 µs.) Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erasesuspended sectors/blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or BlockErase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the onebyte sequence. Flash Sector- /Block-Erase Operation These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Block- or SectorErase operation are ignored except Erase-Suspend and Erase-Resume. See Figures 13 and 14 for timing waveforms. ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 3 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet Flash Write Operation Status Detection The SST34HF3244C provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/ Busy# (RY/BY#) pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Byte/Word (CIOF) The device includes a CIOF pin to control whether the device data I/O pins operate x8 or x16. If the CIOF pin is at logic “1” (VIH) the device is in x16 data configuration: all data I/0 pins DQ0-DQ15 are active and controlled by BEF# and OE#. If the CIOF pin is at logic “0”, the device is in x8 data configuration: only data I/O pins DQ0-DQ7 are active and controlled by BEF# and OE#. The remaining data pins DQ8DQ14 are at Hi-Z, while pin DQ15 is used as the address input A-1 for the Least Significant Bit of the address bus. Flash Data# Polling (DQ7) When the devices are in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 10 for Data# Polling (DQ7) timing diagram and Figure 23 for a flowchart. Ready/Busy# (RY/BY#) The SST34HF3244C include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising edge of the final WE# pulse in the command sequence, the RY/BY# status is valid. When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress. When RY/BY# is high (Ready), the devices may be read or left in standby mode. ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 4 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of a Write operation. See Figure 11 for Toggle Bit timing diagram and Figure 23 for a flowchart. TABLE 1: Write Operation Status Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read From Erase Suspended Sector/Block Read From Non-Erase Suspended Sector/Block Program DQ7 DQ7# 0 1 DQ6 Toggle Toggle 1 DQ2 No Toggle Toggle Toggle RY/BY# 0 0 1 Data Protection The SST34HF3244C provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Hardware Block Protection The SST34HF3244C provide a hardware block protection which protects the outermost 8 KWord/16 KByte in Bank 1. The block is protected when WP# is held low. When WP# is held low and a Block-Erase command is issued to the protected block, the data in the outermost 8 KWord/16 KByte section will be protected. The rest of the block will be erased. See Table 3 for Block-Protection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Data Data Data 1 Hardware Reset (RST#) DQ7# Toggle No Toggle 0 T1.1 1282 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. The address must be in the bank where the operation is in progress in order to read the operation status. If the address is pointing to a different bank (not busy), the device will output array data. The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 19). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 18). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. See Figures 18 and 19 for timing diagrams. ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 5 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet Software Data Protection (SDP) The SST34HF3244C provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF3244C are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15DQ8 are “Don’t Care” during any SDP command sequence. Security ID The SST34HF3244C devices offer a 136-word Security ID space. The Secure ID space is divided into two segments—one 128-bit factory programmed segment and one 128-word (256-byte) user-programmed segment. The first segment is programmed and locked at SST with a unique, 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Program command. End-of-Write status is checked by reading the toggle bits. Data# Polling is not used for Security ID End-of-Write detection. Once programming is complete, the Sec ID should be locked using the User-Sec-ID-Program-Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a three-byte command sequence with QuerySec-ID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit-Sec-ID command should be executed. Refer to Table 6 for more details. Common Flash Memory Interface (CFI) These devices also contain the CFI information to describe the characteristics of the devices. In order to enter the CFI Query mode, the system must write the three-byte sequence, same as the Software ID Entry command with 98H (CFI Query command) to address BKX555H in the last byte sequence. In order to enter the CFI Query mode, the system can also use the one-byte sequence with BKX55H on Address and 98H on Data Bus. See Figure 16 for CFI Entry and Read timing diagram. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 6 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet Product Identification The Product Identification mode identifies the device SST34HF3244C and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 5 and 6 for software operation, Figure 15 for the Software ID Entry and Read timing diagram and Figure 24 for the ID Entry command sequence flowchart. TABLE 2: Product Identification ADDRESS Manufacturer’s ID Device ID SST34HF3244C Note: BK = Bank Address (A20-A18) SRAM Read The SRAM Read operation of the SST34HF3244C is controlled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the outputs. BES1# and BES2 are used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 4, for further details. SRAM Write The SRAM Write operation of the SST34HF3244C is controlled by WE# and BES1#, both have to be low, BES2 must be high for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES1#, WE#, or the falling edge of BES2 whichever occurs first. The write time is measured from the last falling edge of BES#1 or WE# or the rising edge of BES2 to the first rising edge of BES1#, or WE# or the falling edge of BES2. Refer to the Write cycle timing diagrams, Figures 5 and 6, for further details. DATA 00BFH 7353H T2.0 1282 BK0000H BK0001H Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 17 for timing waveform and Figure 24 for a flowchart. SRAM Operation With BES1# low, BES2 and BEF# high, the SST34HF3244C operates as 256K x16CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SST34HF3244C SRAM is mapped into the first 512 KWord address space. When BES1#, BEF# are high and BES2 is low, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 5 for x16 SRAM Read and Write data byte control modes of operation. ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 7 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet A20- A0 Address Buffers SuperFlash Memory (Bank 1) RST# BEF# WP# LBS# UBS# BES1# BES21 OE#2 WE#2 RY/BY# SuperFlash Memory (Bank 2) Control Logic I/O Buffers DQ15/A-1 - DQ0 Address Buffers 4 Mbit SRAM Notes: 1. For LS package only: WE# = WEF# and/or WES# OE# = OEF# and/or OES# 1282 B1.4 FIGURE 1: Functional Block Diagram ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 8 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet TABLE 3: Dual-Bank Memory Organization (1 of 2) SST34HF3244C Block BA63 BA62 BA61 BA60 BA59 BA58 BA57 Bank 1 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 Bank 2 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 Block Size 8 KW / 16 KB 24 KW / 48 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB Address Range x8 3FC000H–3FFFFFH 3F0000H–3FBFFFH 3E0000H–3EFFFFH 3D0000H–3DFFFFH 3C0000H–3CFFFFH 3B0000H–3BFFFFH 3A0000H–3AFFFFH 390000H–39FFFFH 380000H–38FFFFH 370000H–37FFFFH 360000H–36FFFFH 350000H–35FFFFH 340000H–34FFFFH 330000H–33FFFFH 320000H–32FFFFH 310000H–31FFFFH 300000H–30FFFFH 2F0000H–2FFFFFH 2E0000H–2EFFFFH 2D0000H–2DFFFFH 2C0000H–2CFFFFH 2B0000H–2BFFFFH 2A0000H—2AFFFFH 290000H—29FFFFH 280000H—28FFFFH 270000H—27FFFFH 260000H—26FFFFH 250000H—25FFFFH 240000H—24FFFFH 230000H—23FFFFH 220000H—22FFFFH 210000H—21FFFFH 200000H—20FFFFH 1F0000H—1FFFFFH 1E0000H—1EFFFFH 1D0000H—1DFFFFH 1C0000H—1CFFFFH 1B0000H—1BFFFFH 1A0000H—1AFFFFH 190000H—19FFFFH 180000H—18FFFFH 170000H—17FFFFH 160000H—16FFFFH Address Range x16 1FE000H–1FFFFFH 1F8000H–1FDFFFH 1F0000H–1F7FFFH 1E8000H–1EFFFFH 1E0000H–1E7FFFH 1D8000H–1DFFFFH 1D0000H–1D7FFFH 1C8000H–1CFFFFH 1C0000H–1C7FFFH 1B8000H–1BFFFFH 1B0000H–1B7FFFH 1A8000H–1AFFFFH 1A0000H–1A7FFFH 198000H–19FFFFH 190000H–197FFFH 188000H–18FFFFH 180000H–187FFFH 178000H–17FFFFH 170000H–177FFFH 168000H–16FFFFH 160000H–167FFFH 158000H–15FFFFH 150000H–157FFFH 148000H–14FFFFH 140000H–147FFFH 138000H–13FFFFH 130000H–137FFFH 128000H–12FFFFH 120000H–127FFFH 118000H–11FFFFH 110000H–117FFFH 108000H–10FFFFH 100000H–107FFFH 0F8000H–0FFFFFH 0F0000H–0F7FFFH 0E8000H–0EFFFFH 0E0000H–0E7FFFH 0D8000H–0DFFFFH 0D0000H–0D7FFFH 0C8000H–0CFFFFH 0C0000H–0C7FFFH 0B8000H–0BFFFFH 0B0000H–0B7FFFH ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 9 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet TABLE 3: Dual-Bank Memory Organization (Continued) (2 of 2) SST34HF3244C Block BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 Bank 2 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 Block Size 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB 32 KW / 64 KB Address Range x8 150000H—15FFFFH 140000H—14FFFFH 130000H—13FFFFH 120000H—12FFFFH 110000H—11FFFFH 100000H—10FFFFH 0F0000H—0FFFFFH 0E0000H—0EFFFFH 0D0000H—0DFFFFH 0C0000H—0CFFFFH 0B0000H—0BFFFFH 0A0000H—0AFFFFH 090000H—09FFFFH 080000H—08FFFFH 070000H—07FFFFH 060000H—06FFFFH 050000H–05FFFFH 040000H–04FFFFH 030000H–03FFFFH 020000H–02FFFFH 010000H–01FFFFH 000000H–00FFFFH Address Range x16 0A8000H–0AFFFFH 0A0000H–0A7FFFH 098000H–09FFFFH 090000H–097FFFH 088000H–08FFFFH 080000H–087FFFH 078000H–07FFFFH 070000H–077FFFH 068000H–06FFFFH 060000H–067FFFH 058000H–05FFFFH 050000H–057FFFH 048000H–04FFFFH 040000H–047FFFH 038000H–03FFFFH 030000H–037FFFH 028000H–02FFFFH 020000H–027FFFH 018000H–01FFFFH 010000H–017FFFH 008000H–00FFFFH 000000H–007FFFH T3.0 1282 ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 10 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet PIN DESCRIPTION TOP VIEW (balls facing down) 8 7 6 5 4 3 2 A7 A11 A8 A15 A12 A19 NC A13 A9 A20 NC A14 A10 A16 NC CIOF Note* VSS DQ7 DQ14 DQ6 DQ13 DQ12 DQ5 DQ4 DQ3 VDDS NC VDDF DQ11 DQ10 DQ2 DQ0 DQ8 1282 56-lfbga P1.1 WE# BES2 WP# RST# RY/BY# LBS# UBS# A18 A6 A3 A5 A2 A17 A4 A1 DQ1 VSS A0 DQ9 OE# 1 BEF# BES1# A B C D E F G H Note: F7 = DQ15/A-1 FIGURE 2: Pin Assignments for 56-ball LFBGA (8mm x 10mm) TOP VIEW (balls facing down) 8 7 6 NC A20 A16 A11 A8 A15 A10 A14 A9 A13 A12 VSSF NC NC DQ15 WES# DQ14 DQ7 DQ13 DQ6 DQ4 DQ5 WEF# RY/BY# 5 VSSS RST# DQ12 BES2 VDDS VDDF A19 DQ11 DQ9 A6 A0 A3 DQ10 DQ2 DQ8 A2 DQ0 A1 DQ3 DQ1 BES1# NC NC 1282 62-lfbga P2.1 4 WP# NC 3 LBS# UBS# OES# 2 A18 A17 A5 A7 A4 1 NC NC BEF# VSSF OEF# A B C D E F G H J K FIGURE 3: Pin Assignments for 62-ball LFBGA (8mm x 10mm) ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 11 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet TABLE 4: Pin Description Symbol Pin Name Functions To provide flash address, A20-A0. To provide SRAM address, AMSS-A0 To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high. DQ15 is used as data I/O pin when in x16 mode (CIOF = “1”) A-1 is used as the LBS address pin when in x8 mode (CIOF = “0”) To activate the Flash memory bank when BEF# is low To activate the SRAM memory bank when BES1# is low To activate the SRAM memory bank when BES2 is high To gate the data output buffers for Flash2 only To gate the data output buffers for SRAM2 only To control the Write operations for Flash2 only To control the Write operations for SRAM2 only To gate the data output buffers To control the Write operations When low, select Byte mode. When high, select Word mode. To enable DQ15-DQ8 To enable DQ7-DQ0 To protect and unprotect the bottom 8 KWord (4 sectors) from Erase or Program operation To Reset and return the device to Read mode To output the status of a Program or Erase Operation RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. Flash2 only SRAM2 only 2.7-3.3V Power Supply to Flash only 2.7-3.3V Power Supply to SRAM only Unconnected pins T4.0 1282 AMS1 to A0 Address Inputs DQ14-DQ0 Data Inputs/Outputs DQ15/A-1 BEF# BES1# BES2 OEF#2 OES#2 WEF#2 WES#2 OE# WE# CIOF UBS# LBS# WP# RST# RY/BY# Data Input/Output and LBS Address Flash Memory Bank Enable SRAM Memory Bank Enable SRAM Memory Bank Enable Output Enable Output Enable Write Enable Write Enable Output Enable Write Enable Byte Selection for Flash Upper Byte Control (SRAM) Lower Byte Control (SRAM) Write Protect Reset Ready/Busy# VSSF2 VSSS VSS 2 Ground Ground Ground Power Supply (Flash) Power Supply (SRAM) No Connection VDDF VDDS NC 1. AMSS = Most Significant Address AMSS = A17 for SST34HF3244C 2. LSE package only ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 12 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet TABLE 5: Operational Modes Selection for x16 SRAM DQ15-8 Mode Full Standby Output Disable BEF#1 VIH VIH VIL Flash Read Flash Write Flash Erase SRAM Read VIL VIL VIL VIH BES1#1,2 VIH X VIL VIL VIH X VIH X VIH X VIH X VIL BES21,2 X VIL VIH VIH X VIL X VIL X VIL X VIL VIH VIL VIH VIL VIH VIL SRAM Write VIH VIL VIH X VIL VIL VIH VIL Product Identification4 VIL VIH VIL VIL VIH X VIL VIL VIH VIL VIL VIH X DOUT HIGH-Z DOUT DIN HIGH-Z DIN DOUT DOUT HIGH-Z DIN DIN HIGH-Z DOUT DOUT HIGH-Z DIN DIN HIGH-Z VIH VIL X X X X VIH VIL X X DIN DIN VIL VIH X X DOUT DOUT DQ14-8 = HIGH-Z DQ15 = A-1 DQ14-8 = HIGH-Z DQ15 = A-1 X OE#2,3 X X VIH X VIH WE#2,3 X X VIH X VIH LBS#2 X X X VIH X UBS#2 X X X VIH X HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z DQ7-0 HIGH-Z CIOF = VIH HIGH-Z CIOF = VIL HIGH-Z Manufacturer’s ID5 Device ID5 T5.1 1282 1. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time 2. X can be VIL or VIH, but no other value. 3. OE# = OEF# and OES# WE# = WEF# and WES# for LSE package only 4. Software mode only 5. With A19-A18 = VIL; SST Manufacturer’s ID = BFH, is read with A0=0, SST34HF3244C Device ID = 7351H, is read with A0=1 ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 13 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet TABLE 6: Software Command Sequence Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID5 User-Security-IDProgram User-Security-IDProgram-Lock-out7 Software ID Entry8 CFI Query Entry CFI Query Entry Software ID Exit/ CFI Exit/ Sec ID Exit10,11 Software ID Exit/ CFI Exit/ Sec ID Exit10,11 1st Bus Write Cycle Addr1 555H 555H 555H 555H XXXXH XXXXH 555H 555H 555H 555H 555H BKX4 55H 555H 2nd Bus Write Cycle Addr1 2AAH 2AAH 2AAH 2AAH 3rd Bus Write Cycle Addr1 555H 555H 555H 555H 4th Bus Write Cycle Addr1 WA3 555H 555H 555H 5th Bus Write Cycle Addr1 2AAH 2AAH 2AAH 6th Bus Write Cycle Addr1 SAX4 BAX 4 Data2 AAH AAH AAH AAH B0H 30H AAH AAH AAH AAH AAH 98H AAH Data2 55H 55H 55H 55H Data2 A0H 80H 80H 80H Data2 Data AAH AAH AAH Data2 55H 55H 55H Data2 50H 30H 10H 555H 2AAH 2AAH 2AAH 2AAH 2AAH 55H 55H 55H 55H 55H 555H 555H 555H BKX9 555H BKX4 555H 88H A5H 85H 90H 98H SIWA6 XXH Data 0000H 2AAH 55H 555H F0H XXH F0H T6.1 1282 1. Address format A10-A0 (Hex), Addresses A20-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode. When in x8 mode, Addresses A20-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence 3. WA = Program Word/Byte address 4. SAX for Sector-Erase; uses A20-A11 address lines BAX for Block-Erase; uses A20-A15 address lines 5. For SST34HF3244C the Security ID Address Range is: (x16 mode) = 000000H to 000087H, (x8 mode) = 000000H to 00010FH SST ID is read at Address Range (x16 mode) = 000000H to 000007H (x8 mode) = 000000H to 00000FH User ID is read at Address Range (x16 mode) = 000008H to 000087H (x8 mode) = 000010H to 00010FH Lock Status is read at Address 0000FFH (x16) or 0001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. SIWA = User Security ID Program Word/Byte address For SST34HF3244C, valid Address Range is (x16 mode) = 000008H-000087H (x8 mode) = 000010H-00010FH. All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode. 7. The User-Security-ID-Program-Lock-out command must be executed in x16 mode. (CIOF = VIH) 8. The device does not remain in Software Product Identification mode if powered down. 9. A19 and A18 = VIL 10. Both Software ID Exit operations are equivalent 11. IIf users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 14 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet TABLE 7: CFI Query Identification String1 Address x16 Mode 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Address x8 Mode 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H Data2 0051H 0052H 0059H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Description Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T7.1 1282 1. Refer to CFI publication 100 for more details. 2. In x8 mode, only the lower byte of data is output. TABLE 8: System Interface Information Address x16 Mode 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Address x8 Mode 36H 38H 3AH 3CH 3EH 40H 42H 44H 46H 48H 4AH 4CH Data1 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Description VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min (00H = no VPP pin) VPP max (00H = no VPP pin) Typical time out for Program 2N µs (24 = 16 µs) Typical time out for min size buffer program 2N µs (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (26 = 64 ms) Maximum time out for Program 2N times typical (21 x 24 = 32 µs) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms) T8.0 1282 1. In x8 mode, only the lower byte of data is output. ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 15 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet TABLE 9: Device Geometry Information Address x16 Mode 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Address x8 Mode 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H Data1 0016H 0002H 0000H 0000H 0000H 0002H 003FH 0000H 0000H 0001H 00FFH 0003H 0010H 0000H Description Device size = 2N Bytes (16H = 22; 222 = 4 MByte) Flash Device Interface description; 0002H = x8/x16 asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 63 + 1 = 64 blocks (003FH = 63) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FFH = 1023) z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) T9.2 1282 1. In x8 mode, only the lower byte of data is output. ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 16 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (